1 /* 2 * Based on drivers/serial/8250.c by Russell King. 3 * 4 * Author: Nicolas Pitre 5 * Created: Feb 20, 2003 6 * Copyright: (C) 2003 Monta Vista Software, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * Note 1: This driver is made separate from the already too overloaded 14 * 8250.c because it needs some kirks of its own and that'll make it 15 * easier to add DMA support. 16 * 17 * Note 2: I'm too sick of device allocation policies for serial ports. 18 * If someone else wants to request an "official" allocation of major/minor 19 * for this driver please be my guest. And don't forget that new hardware 20 * to come from Intel might have more than 3 or 4 of those UARTs. Let's 21 * hope for a better port registration and dynamic device allocation scheme 22 * with the serial core maintainer satisfaction to appear soon. 23 */ 24 25 26 #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 27 #define SUPPORT_SYSRQ 28 #endif 29 30 #include <linux/module.h> 31 #include <linux/ioport.h> 32 #include <linux/init.h> 33 #include <linux/console.h> 34 #include <linux/sysrq.h> 35 #include <linux/serial_reg.h> 36 #include <linux/circ_buf.h> 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/platform_device.h> 40 #include <linux/tty.h> 41 #include <linux/tty_flip.h> 42 #include <linux/serial_core.h> 43 #include <linux/clk.h> 44 #include <linux/io.h> 45 #include <linux/slab.h> 46 47 struct uart_pxa_port { 48 struct uart_port port; 49 unsigned char ier; 50 unsigned char lcr; 51 unsigned char mcr; 52 unsigned int lsr_break_flag; 53 struct clk *clk; 54 char *name; 55 }; 56 57 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) 58 { 59 offset <<= 2; 60 return readl(up->port.membase + offset); 61 } 62 63 static inline void serial_out(struct uart_pxa_port *up, int offset, int value) 64 { 65 offset <<= 2; 66 writel(value, up->port.membase + offset); 67 } 68 69 static void serial_pxa_enable_ms(struct uart_port *port) 70 { 71 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 72 73 up->ier |= UART_IER_MSI; 74 serial_out(up, UART_IER, up->ier); 75 } 76 77 static void serial_pxa_stop_tx(struct uart_port *port) 78 { 79 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 80 81 if (up->ier & UART_IER_THRI) { 82 up->ier &= ~UART_IER_THRI; 83 serial_out(up, UART_IER, up->ier); 84 } 85 } 86 87 static void serial_pxa_stop_rx(struct uart_port *port) 88 { 89 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 90 91 up->ier &= ~UART_IER_RLSI; 92 up->port.read_status_mask &= ~UART_LSR_DR; 93 serial_out(up, UART_IER, up->ier); 94 } 95 96 static inline void receive_chars(struct uart_pxa_port *up, int *status) 97 { 98 struct tty_struct *tty = up->port.state->port.tty; 99 unsigned int ch, flag; 100 int max_count = 256; 101 102 do { 103 ch = serial_in(up, UART_RX); 104 flag = TTY_NORMAL; 105 up->port.icount.rx++; 106 107 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 108 UART_LSR_FE | UART_LSR_OE))) { 109 /* 110 * For statistics only 111 */ 112 if (*status & UART_LSR_BI) { 113 *status &= ~(UART_LSR_FE | UART_LSR_PE); 114 up->port.icount.brk++; 115 /* 116 * We do the SysRQ and SAK checking 117 * here because otherwise the break 118 * may get masked by ignore_status_mask 119 * or read_status_mask. 120 */ 121 if (uart_handle_break(&up->port)) 122 goto ignore_char; 123 } else if (*status & UART_LSR_PE) 124 up->port.icount.parity++; 125 else if (*status & UART_LSR_FE) 126 up->port.icount.frame++; 127 if (*status & UART_LSR_OE) 128 up->port.icount.overrun++; 129 130 /* 131 * Mask off conditions which should be ignored. 132 */ 133 *status &= up->port.read_status_mask; 134 135 #ifdef CONFIG_SERIAL_PXA_CONSOLE 136 if (up->port.line == up->port.cons->index) { 137 /* Recover the break flag from console xmit */ 138 *status |= up->lsr_break_flag; 139 up->lsr_break_flag = 0; 140 } 141 #endif 142 if (*status & UART_LSR_BI) { 143 flag = TTY_BREAK; 144 } else if (*status & UART_LSR_PE) 145 flag = TTY_PARITY; 146 else if (*status & UART_LSR_FE) 147 flag = TTY_FRAME; 148 } 149 150 if (uart_handle_sysrq_char(&up->port, ch)) 151 goto ignore_char; 152 153 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); 154 155 ignore_char: 156 *status = serial_in(up, UART_LSR); 157 } while ((*status & UART_LSR_DR) && (max_count-- > 0)); 158 tty_flip_buffer_push(tty); 159 } 160 161 static void transmit_chars(struct uart_pxa_port *up) 162 { 163 struct circ_buf *xmit = &up->port.state->xmit; 164 int count; 165 166 if (up->port.x_char) { 167 serial_out(up, UART_TX, up->port.x_char); 168 up->port.icount.tx++; 169 up->port.x_char = 0; 170 return; 171 } 172 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 173 serial_pxa_stop_tx(&up->port); 174 return; 175 } 176 177 count = up->port.fifosize / 2; 178 do { 179 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 180 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 181 up->port.icount.tx++; 182 if (uart_circ_empty(xmit)) 183 break; 184 } while (--count > 0); 185 186 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 187 uart_write_wakeup(&up->port); 188 189 190 if (uart_circ_empty(xmit)) 191 serial_pxa_stop_tx(&up->port); 192 } 193 194 static void serial_pxa_start_tx(struct uart_port *port) 195 { 196 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 197 198 if (!(up->ier & UART_IER_THRI)) { 199 up->ier |= UART_IER_THRI; 200 serial_out(up, UART_IER, up->ier); 201 } 202 } 203 204 static inline void check_modem_status(struct uart_pxa_port *up) 205 { 206 int status; 207 208 status = serial_in(up, UART_MSR); 209 210 if ((status & UART_MSR_ANY_DELTA) == 0) 211 return; 212 213 if (status & UART_MSR_TERI) 214 up->port.icount.rng++; 215 if (status & UART_MSR_DDSR) 216 up->port.icount.dsr++; 217 if (status & UART_MSR_DDCD) 218 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 219 if (status & UART_MSR_DCTS) 220 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 221 222 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 223 } 224 225 /* 226 * This handles the interrupt from one port. 227 */ 228 static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) 229 { 230 struct uart_pxa_port *up = dev_id; 231 unsigned int iir, lsr; 232 233 iir = serial_in(up, UART_IIR); 234 if (iir & UART_IIR_NO_INT) 235 return IRQ_NONE; 236 lsr = serial_in(up, UART_LSR); 237 if (lsr & UART_LSR_DR) 238 receive_chars(up, &lsr); 239 check_modem_status(up); 240 if (lsr & UART_LSR_THRE) 241 transmit_chars(up); 242 return IRQ_HANDLED; 243 } 244 245 static unsigned int serial_pxa_tx_empty(struct uart_port *port) 246 { 247 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 248 unsigned long flags; 249 unsigned int ret; 250 251 spin_lock_irqsave(&up->port.lock, flags); 252 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 253 spin_unlock_irqrestore(&up->port.lock, flags); 254 255 return ret; 256 } 257 258 static unsigned int serial_pxa_get_mctrl(struct uart_port *port) 259 { 260 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 261 unsigned char status; 262 unsigned int ret; 263 264 status = serial_in(up, UART_MSR); 265 266 ret = 0; 267 if (status & UART_MSR_DCD) 268 ret |= TIOCM_CAR; 269 if (status & UART_MSR_RI) 270 ret |= TIOCM_RNG; 271 if (status & UART_MSR_DSR) 272 ret |= TIOCM_DSR; 273 if (status & UART_MSR_CTS) 274 ret |= TIOCM_CTS; 275 return ret; 276 } 277 278 static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) 279 { 280 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 281 unsigned char mcr = 0; 282 283 if (mctrl & TIOCM_RTS) 284 mcr |= UART_MCR_RTS; 285 if (mctrl & TIOCM_DTR) 286 mcr |= UART_MCR_DTR; 287 if (mctrl & TIOCM_OUT1) 288 mcr |= UART_MCR_OUT1; 289 if (mctrl & TIOCM_OUT2) 290 mcr |= UART_MCR_OUT2; 291 if (mctrl & TIOCM_LOOP) 292 mcr |= UART_MCR_LOOP; 293 294 mcr |= up->mcr; 295 296 serial_out(up, UART_MCR, mcr); 297 } 298 299 static void serial_pxa_break_ctl(struct uart_port *port, int break_state) 300 { 301 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 302 unsigned long flags; 303 304 spin_lock_irqsave(&up->port.lock, flags); 305 if (break_state == -1) 306 up->lcr |= UART_LCR_SBC; 307 else 308 up->lcr &= ~UART_LCR_SBC; 309 serial_out(up, UART_LCR, up->lcr); 310 spin_unlock_irqrestore(&up->port.lock, flags); 311 } 312 313 #if 0 314 static void serial_pxa_dma_init(struct pxa_uart *up) 315 { 316 up->rxdma = 317 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up); 318 if (up->rxdma < 0) 319 goto out; 320 up->txdma = 321 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up); 322 if (up->txdma < 0) 323 goto err_txdma; 324 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL); 325 if (!up->dmadesc) 326 goto err_alloc; 327 328 /* ... */ 329 err_alloc: 330 pxa_free_dma(up->txdma); 331 err_rxdma: 332 pxa_free_dma(up->rxdma); 333 out: 334 return; 335 } 336 #endif 337 338 static int serial_pxa_startup(struct uart_port *port) 339 { 340 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 341 unsigned long flags; 342 int retval; 343 344 if (port->line == 3) /* HWUART */ 345 up->mcr |= UART_MCR_AFE; 346 else 347 up->mcr = 0; 348 349 up->port.uartclk = clk_get_rate(up->clk); 350 351 /* 352 * Allocate the IRQ 353 */ 354 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); 355 if (retval) 356 return retval; 357 358 /* 359 * Clear the FIFO buffers and disable them. 360 * (they will be reenabled in set_termios()) 361 */ 362 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 363 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 364 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 365 serial_out(up, UART_FCR, 0); 366 367 /* 368 * Clear the interrupt registers. 369 */ 370 (void) serial_in(up, UART_LSR); 371 (void) serial_in(up, UART_RX); 372 (void) serial_in(up, UART_IIR); 373 (void) serial_in(up, UART_MSR); 374 375 /* 376 * Now, initialize the UART 377 */ 378 serial_out(up, UART_LCR, UART_LCR_WLEN8); 379 380 spin_lock_irqsave(&up->port.lock, flags); 381 up->port.mctrl |= TIOCM_OUT2; 382 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 383 spin_unlock_irqrestore(&up->port.lock, flags); 384 385 /* 386 * Finally, enable interrupts. Note: Modem status interrupts 387 * are set via set_termios(), which will be occurring imminently 388 * anyway, so we don't enable them here. 389 */ 390 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; 391 serial_out(up, UART_IER, up->ier); 392 393 /* 394 * And clear the interrupt registers again for luck. 395 */ 396 (void) serial_in(up, UART_LSR); 397 (void) serial_in(up, UART_RX); 398 (void) serial_in(up, UART_IIR); 399 (void) serial_in(up, UART_MSR); 400 401 return 0; 402 } 403 404 static void serial_pxa_shutdown(struct uart_port *port) 405 { 406 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 407 unsigned long flags; 408 409 free_irq(up->port.irq, up); 410 411 /* 412 * Disable interrupts from this port 413 */ 414 up->ier = 0; 415 serial_out(up, UART_IER, 0); 416 417 spin_lock_irqsave(&up->port.lock, flags); 418 up->port.mctrl &= ~TIOCM_OUT2; 419 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 420 spin_unlock_irqrestore(&up->port.lock, flags); 421 422 /* 423 * Disable break condition and FIFOs 424 */ 425 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 426 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 427 UART_FCR_CLEAR_RCVR | 428 UART_FCR_CLEAR_XMIT); 429 serial_out(up, UART_FCR, 0); 430 } 431 432 static void 433 serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, 434 struct ktermios *old) 435 { 436 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 437 unsigned char cval, fcr = 0; 438 unsigned long flags; 439 unsigned int baud, quot; 440 unsigned int dll; 441 442 switch (termios->c_cflag & CSIZE) { 443 case CS5: 444 cval = UART_LCR_WLEN5; 445 break; 446 case CS6: 447 cval = UART_LCR_WLEN6; 448 break; 449 case CS7: 450 cval = UART_LCR_WLEN7; 451 break; 452 default: 453 case CS8: 454 cval = UART_LCR_WLEN8; 455 break; 456 } 457 458 if (termios->c_cflag & CSTOPB) 459 cval |= UART_LCR_STOP; 460 if (termios->c_cflag & PARENB) 461 cval |= UART_LCR_PARITY; 462 if (!(termios->c_cflag & PARODD)) 463 cval |= UART_LCR_EPAR; 464 465 /* 466 * Ask the core to calculate the divisor for us. 467 */ 468 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 469 quot = uart_get_divisor(port, baud); 470 471 if ((up->port.uartclk / quot) < (2400 * 16)) 472 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; 473 else if ((up->port.uartclk / quot) < (230400 * 16)) 474 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; 475 else 476 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; 477 478 /* 479 * Ok, we're now changing the port state. Do it with 480 * interrupts disabled. 481 */ 482 spin_lock_irqsave(&up->port.lock, flags); 483 484 /* 485 * Ensure the port will be enabled. 486 * This is required especially for serial console. 487 */ 488 up->ier |= UART_IER_UUE; 489 490 /* 491 * Update the per-port timeout. 492 */ 493 uart_update_timeout(port, termios->c_cflag, baud); 494 495 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 496 if (termios->c_iflag & INPCK) 497 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 498 if (termios->c_iflag & (BRKINT | PARMRK)) 499 up->port.read_status_mask |= UART_LSR_BI; 500 501 /* 502 * Characters to ignore 503 */ 504 up->port.ignore_status_mask = 0; 505 if (termios->c_iflag & IGNPAR) 506 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 507 if (termios->c_iflag & IGNBRK) { 508 up->port.ignore_status_mask |= UART_LSR_BI; 509 /* 510 * If we're ignoring parity and break indicators, 511 * ignore overruns too (for real raw support). 512 */ 513 if (termios->c_iflag & IGNPAR) 514 up->port.ignore_status_mask |= UART_LSR_OE; 515 } 516 517 /* 518 * ignore all characters if CREAD is not set 519 */ 520 if ((termios->c_cflag & CREAD) == 0) 521 up->port.ignore_status_mask |= UART_LSR_DR; 522 523 /* 524 * CTS flow control flag and modem status interrupts 525 */ 526 up->ier &= ~UART_IER_MSI; 527 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 528 up->ier |= UART_IER_MSI; 529 530 serial_out(up, UART_IER, up->ier); 531 532 if (termios->c_cflag & CRTSCTS) 533 up->mcr |= UART_MCR_AFE; 534 else 535 up->mcr &= ~UART_MCR_AFE; 536 537 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ 538 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ 539 540 /* 541 * work around Errata #75 according to Intel(R) PXA27x Processor Family 542 * Specification Update (Nov 2005) 543 */ 544 dll = serial_in(up, UART_DLL); 545 WARN_ON(dll != (quot & 0xff)); 546 547 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ 548 serial_out(up, UART_LCR, cval); /* reset DLAB */ 549 up->lcr = cval; /* Save LCR */ 550 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 551 serial_out(up, UART_FCR, fcr); 552 spin_unlock_irqrestore(&up->port.lock, flags); 553 } 554 555 static void 556 serial_pxa_pm(struct uart_port *port, unsigned int state, 557 unsigned int oldstate) 558 { 559 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 560 561 if (!state) 562 clk_enable(up->clk); 563 else 564 clk_disable(up->clk); 565 } 566 567 static void serial_pxa_release_port(struct uart_port *port) 568 { 569 } 570 571 static int serial_pxa_request_port(struct uart_port *port) 572 { 573 return 0; 574 } 575 576 static void serial_pxa_config_port(struct uart_port *port, int flags) 577 { 578 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 579 up->port.type = PORT_PXA; 580 } 581 582 static int 583 serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) 584 { 585 /* we don't want the core code to modify any port params */ 586 return -EINVAL; 587 } 588 589 static const char * 590 serial_pxa_type(struct uart_port *port) 591 { 592 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 593 return up->name; 594 } 595 596 static struct uart_pxa_port *serial_pxa_ports[4]; 597 static struct uart_driver serial_pxa_reg; 598 599 #ifdef CONFIG_SERIAL_PXA_CONSOLE 600 601 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 602 603 /* 604 * Wait for transmitter & holding register to empty 605 */ 606 static inline void wait_for_xmitr(struct uart_pxa_port *up) 607 { 608 unsigned int status, tmout = 10000; 609 610 /* Wait up to 10ms for the character(s) to be sent. */ 611 do { 612 status = serial_in(up, UART_LSR); 613 614 if (status & UART_LSR_BI) 615 up->lsr_break_flag = UART_LSR_BI; 616 617 if (--tmout == 0) 618 break; 619 udelay(1); 620 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 621 622 /* Wait up to 1s for flow control if necessary */ 623 if (up->port.flags & UPF_CONS_FLOW) { 624 tmout = 1000000; 625 while (--tmout && 626 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) 627 udelay(1); 628 } 629 } 630 631 static void serial_pxa_console_putchar(struct uart_port *port, int ch) 632 { 633 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 634 635 wait_for_xmitr(up); 636 serial_out(up, UART_TX, ch); 637 } 638 639 /* 640 * Print a string to the serial port trying not to disturb 641 * any possible real use of the port... 642 * 643 * The console_lock must be held when we get here. 644 */ 645 static void 646 serial_pxa_console_write(struct console *co, const char *s, unsigned int count) 647 { 648 struct uart_pxa_port *up = serial_pxa_ports[co->index]; 649 unsigned int ier; 650 651 clk_enable(up->clk); 652 653 /* 654 * First save the IER then disable the interrupts 655 */ 656 ier = serial_in(up, UART_IER); 657 serial_out(up, UART_IER, UART_IER_UUE); 658 659 uart_console_write(&up->port, s, count, serial_pxa_console_putchar); 660 661 /* 662 * Finally, wait for transmitter to become empty 663 * and restore the IER 664 */ 665 wait_for_xmitr(up); 666 serial_out(up, UART_IER, ier); 667 668 clk_disable(up->clk); 669 } 670 671 static int __init 672 serial_pxa_console_setup(struct console *co, char *options) 673 { 674 struct uart_pxa_port *up; 675 int baud = 9600; 676 int bits = 8; 677 int parity = 'n'; 678 int flow = 'n'; 679 680 if (co->index == -1 || co->index >= serial_pxa_reg.nr) 681 co->index = 0; 682 up = serial_pxa_ports[co->index]; 683 if (!up) 684 return -ENODEV; 685 686 if (options) 687 uart_parse_options(options, &baud, &parity, &bits, &flow); 688 689 return uart_set_options(&up->port, co, baud, parity, bits, flow); 690 } 691 692 static struct console serial_pxa_console = { 693 .name = "ttyS", 694 .write = serial_pxa_console_write, 695 .device = uart_console_device, 696 .setup = serial_pxa_console_setup, 697 .flags = CON_PRINTBUFFER, 698 .index = -1, 699 .data = &serial_pxa_reg, 700 }; 701 702 #define PXA_CONSOLE &serial_pxa_console 703 #else 704 #define PXA_CONSOLE NULL 705 #endif 706 707 struct uart_ops serial_pxa_pops = { 708 .tx_empty = serial_pxa_tx_empty, 709 .set_mctrl = serial_pxa_set_mctrl, 710 .get_mctrl = serial_pxa_get_mctrl, 711 .stop_tx = serial_pxa_stop_tx, 712 .start_tx = serial_pxa_start_tx, 713 .stop_rx = serial_pxa_stop_rx, 714 .enable_ms = serial_pxa_enable_ms, 715 .break_ctl = serial_pxa_break_ctl, 716 .startup = serial_pxa_startup, 717 .shutdown = serial_pxa_shutdown, 718 .set_termios = serial_pxa_set_termios, 719 .pm = serial_pxa_pm, 720 .type = serial_pxa_type, 721 .release_port = serial_pxa_release_port, 722 .request_port = serial_pxa_request_port, 723 .config_port = serial_pxa_config_port, 724 .verify_port = serial_pxa_verify_port, 725 }; 726 727 static struct uart_driver serial_pxa_reg = { 728 .owner = THIS_MODULE, 729 .driver_name = "PXA serial", 730 .dev_name = "ttyS", 731 .major = TTY_MAJOR, 732 .minor = 64, 733 .nr = 4, 734 .cons = PXA_CONSOLE, 735 }; 736 737 #ifdef CONFIG_PM 738 static int serial_pxa_suspend(struct device *dev) 739 { 740 struct uart_pxa_port *sport = dev_get_drvdata(dev); 741 742 if (sport) 743 uart_suspend_port(&serial_pxa_reg, &sport->port); 744 745 return 0; 746 } 747 748 static int serial_pxa_resume(struct device *dev) 749 { 750 struct uart_pxa_port *sport = dev_get_drvdata(dev); 751 752 if (sport) 753 uart_resume_port(&serial_pxa_reg, &sport->port); 754 755 return 0; 756 } 757 758 static const struct dev_pm_ops serial_pxa_pm_ops = { 759 .suspend = serial_pxa_suspend, 760 .resume = serial_pxa_resume, 761 }; 762 #endif 763 764 static int serial_pxa_probe(struct platform_device *dev) 765 { 766 struct uart_pxa_port *sport; 767 struct resource *mmres, *irqres; 768 int ret; 769 770 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); 771 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); 772 if (!mmres || !irqres) 773 return -ENODEV; 774 775 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); 776 if (!sport) 777 return -ENOMEM; 778 779 sport->clk = clk_get(&dev->dev, NULL); 780 if (IS_ERR(sport->clk)) { 781 ret = PTR_ERR(sport->clk); 782 goto err_free; 783 } 784 785 sport->port.type = PORT_PXA; 786 sport->port.iotype = UPIO_MEM; 787 sport->port.mapbase = mmres->start; 788 sport->port.irq = irqres->start; 789 sport->port.fifosize = 64; 790 sport->port.ops = &serial_pxa_pops; 791 sport->port.line = dev->id; 792 sport->port.dev = &dev->dev; 793 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; 794 sport->port.uartclk = clk_get_rate(sport->clk); 795 796 switch (dev->id) { 797 case 0: sport->name = "FFUART"; break; 798 case 1: sport->name = "BTUART"; break; 799 case 2: sport->name = "STUART"; break; 800 case 3: sport->name = "HWUART"; break; 801 default: 802 sport->name = "???"; 803 break; 804 } 805 806 sport->port.membase = ioremap(mmres->start, resource_size(mmres)); 807 if (!sport->port.membase) { 808 ret = -ENOMEM; 809 goto err_clk; 810 } 811 812 serial_pxa_ports[dev->id] = sport; 813 814 uart_add_one_port(&serial_pxa_reg, &sport->port); 815 platform_set_drvdata(dev, sport); 816 817 return 0; 818 819 err_clk: 820 clk_put(sport->clk); 821 err_free: 822 kfree(sport); 823 return ret; 824 } 825 826 static int serial_pxa_remove(struct platform_device *dev) 827 { 828 struct uart_pxa_port *sport = platform_get_drvdata(dev); 829 830 platform_set_drvdata(dev, NULL); 831 832 uart_remove_one_port(&serial_pxa_reg, &sport->port); 833 clk_put(sport->clk); 834 kfree(sport); 835 836 return 0; 837 } 838 839 static struct platform_driver serial_pxa_driver = { 840 .probe = serial_pxa_probe, 841 .remove = serial_pxa_remove, 842 843 .driver = { 844 .name = "pxa2xx-uart", 845 .owner = THIS_MODULE, 846 #ifdef CONFIG_PM 847 .pm = &serial_pxa_pm_ops, 848 #endif 849 }, 850 }; 851 852 int __init serial_pxa_init(void) 853 { 854 int ret; 855 856 ret = uart_register_driver(&serial_pxa_reg); 857 if (ret != 0) 858 return ret; 859 860 ret = platform_driver_register(&serial_pxa_driver); 861 if (ret != 0) 862 uart_unregister_driver(&serial_pxa_reg); 863 864 return ret; 865 } 866 867 void __exit serial_pxa_exit(void) 868 { 869 platform_driver_unregister(&serial_pxa_driver); 870 uart_unregister_driver(&serial_pxa_reg); 871 } 872 873 module_init(serial_pxa_init); 874 module_exit(serial_pxa_exit); 875 876 MODULE_LICENSE("GPL"); 877 MODULE_ALIAS("platform:pxa2xx-uart"); 878