1 /* 2 * Based on drivers/serial/8250.c by Russell King. 3 * 4 * Author: Nicolas Pitre 5 * Created: Feb 20, 2003 6 * Copyright: (C) 2003 Monta Vista Software, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * Note 1: This driver is made separate from the already too overloaded 14 * 8250.c because it needs some kirks of its own and that'll make it 15 * easier to add DMA support. 16 * 17 * Note 2: I'm too sick of device allocation policies for serial ports. 18 * If someone else wants to request an "official" allocation of major/minor 19 * for this driver please be my guest. And don't forget that new hardware 20 * to come from Intel might have more than 3 or 4 of those UARTs. Let's 21 * hope for a better port registration and dynamic device allocation scheme 22 * with the serial core maintainer satisfaction to appear soon. 23 */ 24 25 26 #if defined(CONFIG_SERIAL_PXA_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 27 #define SUPPORT_SYSRQ 28 #endif 29 30 #include <linux/module.h> 31 #include <linux/ioport.h> 32 #include <linux/init.h> 33 #include <linux/console.h> 34 #include <linux/sysrq.h> 35 #include <linux/serial_reg.h> 36 #include <linux/circ_buf.h> 37 #include <linux/delay.h> 38 #include <linux/interrupt.h> 39 #include <linux/of.h> 40 #include <linux/platform_device.h> 41 #include <linux/tty.h> 42 #include <linux/tty_flip.h> 43 #include <linux/serial_core.h> 44 #include <linux/clk.h> 45 #include <linux/io.h> 46 #include <linux/slab.h> 47 48 #define PXA_NAME_LEN 8 49 50 struct uart_pxa_port { 51 struct uart_port port; 52 unsigned char ier; 53 unsigned char lcr; 54 unsigned char mcr; 55 unsigned int lsr_break_flag; 56 struct clk *clk; 57 char name[PXA_NAME_LEN]; 58 }; 59 60 static inline unsigned int serial_in(struct uart_pxa_port *up, int offset) 61 { 62 offset <<= 2; 63 return readl(up->port.membase + offset); 64 } 65 66 static inline void serial_out(struct uart_pxa_port *up, int offset, int value) 67 { 68 offset <<= 2; 69 writel(value, up->port.membase + offset); 70 } 71 72 static void serial_pxa_enable_ms(struct uart_port *port) 73 { 74 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 75 76 up->ier |= UART_IER_MSI; 77 serial_out(up, UART_IER, up->ier); 78 } 79 80 static void serial_pxa_stop_tx(struct uart_port *port) 81 { 82 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 83 84 if (up->ier & UART_IER_THRI) { 85 up->ier &= ~UART_IER_THRI; 86 serial_out(up, UART_IER, up->ier); 87 } 88 } 89 90 static void serial_pxa_stop_rx(struct uart_port *port) 91 { 92 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 93 94 up->ier &= ~UART_IER_RLSI; 95 up->port.read_status_mask &= ~UART_LSR_DR; 96 serial_out(up, UART_IER, up->ier); 97 } 98 99 static inline void receive_chars(struct uart_pxa_port *up, int *status) 100 { 101 struct tty_struct *tty = up->port.state->port.tty; 102 unsigned int ch, flag; 103 int max_count = 256; 104 105 do { 106 /* work around Errata #20 according to 107 * Intel(R) PXA27x Processor Family 108 * Specification Update (May 2005) 109 * 110 * Step 2 111 * Disable the Reciever Time Out Interrupt via IER[RTOEI] 112 */ 113 up->ier &= ~UART_IER_RTOIE; 114 serial_out(up, UART_IER, up->ier); 115 116 ch = serial_in(up, UART_RX); 117 flag = TTY_NORMAL; 118 up->port.icount.rx++; 119 120 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE | 121 UART_LSR_FE | UART_LSR_OE))) { 122 /* 123 * For statistics only 124 */ 125 if (*status & UART_LSR_BI) { 126 *status &= ~(UART_LSR_FE | UART_LSR_PE); 127 up->port.icount.brk++; 128 /* 129 * We do the SysRQ and SAK checking 130 * here because otherwise the break 131 * may get masked by ignore_status_mask 132 * or read_status_mask. 133 */ 134 if (uart_handle_break(&up->port)) 135 goto ignore_char; 136 } else if (*status & UART_LSR_PE) 137 up->port.icount.parity++; 138 else if (*status & UART_LSR_FE) 139 up->port.icount.frame++; 140 if (*status & UART_LSR_OE) 141 up->port.icount.overrun++; 142 143 /* 144 * Mask off conditions which should be ignored. 145 */ 146 *status &= up->port.read_status_mask; 147 148 #ifdef CONFIG_SERIAL_PXA_CONSOLE 149 if (up->port.line == up->port.cons->index) { 150 /* Recover the break flag from console xmit */ 151 *status |= up->lsr_break_flag; 152 up->lsr_break_flag = 0; 153 } 154 #endif 155 if (*status & UART_LSR_BI) { 156 flag = TTY_BREAK; 157 } else if (*status & UART_LSR_PE) 158 flag = TTY_PARITY; 159 else if (*status & UART_LSR_FE) 160 flag = TTY_FRAME; 161 } 162 163 if (uart_handle_sysrq_char(&up->port, ch)) 164 goto ignore_char; 165 166 uart_insert_char(&up->port, *status, UART_LSR_OE, ch, flag); 167 168 ignore_char: 169 *status = serial_in(up, UART_LSR); 170 } while ((*status & UART_LSR_DR) && (max_count-- > 0)); 171 tty_flip_buffer_push(tty); 172 173 /* work around Errata #20 according to 174 * Intel(R) PXA27x Processor Family 175 * Specification Update (May 2005) 176 * 177 * Step 6: 178 * No more data in FIFO: Re-enable RTO interrupt via IER[RTOIE] 179 */ 180 up->ier |= UART_IER_RTOIE; 181 serial_out(up, UART_IER, up->ier); 182 } 183 184 static void transmit_chars(struct uart_pxa_port *up) 185 { 186 struct circ_buf *xmit = &up->port.state->xmit; 187 int count; 188 189 if (up->port.x_char) { 190 serial_out(up, UART_TX, up->port.x_char); 191 up->port.icount.tx++; 192 up->port.x_char = 0; 193 return; 194 } 195 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 196 serial_pxa_stop_tx(&up->port); 197 return; 198 } 199 200 count = up->port.fifosize / 2; 201 do { 202 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 203 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 204 up->port.icount.tx++; 205 if (uart_circ_empty(xmit)) 206 break; 207 } while (--count > 0); 208 209 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 210 uart_write_wakeup(&up->port); 211 212 213 if (uart_circ_empty(xmit)) 214 serial_pxa_stop_tx(&up->port); 215 } 216 217 static void serial_pxa_start_tx(struct uart_port *port) 218 { 219 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 220 221 if (!(up->ier & UART_IER_THRI)) { 222 up->ier |= UART_IER_THRI; 223 serial_out(up, UART_IER, up->ier); 224 } 225 } 226 227 static inline void check_modem_status(struct uart_pxa_port *up) 228 { 229 int status; 230 231 status = serial_in(up, UART_MSR); 232 233 if ((status & UART_MSR_ANY_DELTA) == 0) 234 return; 235 236 if (status & UART_MSR_TERI) 237 up->port.icount.rng++; 238 if (status & UART_MSR_DDSR) 239 up->port.icount.dsr++; 240 if (status & UART_MSR_DDCD) 241 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD); 242 if (status & UART_MSR_DCTS) 243 uart_handle_cts_change(&up->port, status & UART_MSR_CTS); 244 245 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 246 } 247 248 /* 249 * This handles the interrupt from one port. 250 */ 251 static inline irqreturn_t serial_pxa_irq(int irq, void *dev_id) 252 { 253 struct uart_pxa_port *up = dev_id; 254 unsigned int iir, lsr; 255 256 iir = serial_in(up, UART_IIR); 257 if (iir & UART_IIR_NO_INT) 258 return IRQ_NONE; 259 lsr = serial_in(up, UART_LSR); 260 if (lsr & UART_LSR_DR) 261 receive_chars(up, &lsr); 262 check_modem_status(up); 263 if (lsr & UART_LSR_THRE) 264 transmit_chars(up); 265 return IRQ_HANDLED; 266 } 267 268 static unsigned int serial_pxa_tx_empty(struct uart_port *port) 269 { 270 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 271 unsigned long flags; 272 unsigned int ret; 273 274 spin_lock_irqsave(&up->port.lock, flags); 275 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 276 spin_unlock_irqrestore(&up->port.lock, flags); 277 278 return ret; 279 } 280 281 static unsigned int serial_pxa_get_mctrl(struct uart_port *port) 282 { 283 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 284 unsigned char status; 285 unsigned int ret; 286 287 status = serial_in(up, UART_MSR); 288 289 ret = 0; 290 if (status & UART_MSR_DCD) 291 ret |= TIOCM_CAR; 292 if (status & UART_MSR_RI) 293 ret |= TIOCM_RNG; 294 if (status & UART_MSR_DSR) 295 ret |= TIOCM_DSR; 296 if (status & UART_MSR_CTS) 297 ret |= TIOCM_CTS; 298 return ret; 299 } 300 301 static void serial_pxa_set_mctrl(struct uart_port *port, unsigned int mctrl) 302 { 303 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 304 unsigned char mcr = 0; 305 306 if (mctrl & TIOCM_RTS) 307 mcr |= UART_MCR_RTS; 308 if (mctrl & TIOCM_DTR) 309 mcr |= UART_MCR_DTR; 310 if (mctrl & TIOCM_OUT1) 311 mcr |= UART_MCR_OUT1; 312 if (mctrl & TIOCM_OUT2) 313 mcr |= UART_MCR_OUT2; 314 if (mctrl & TIOCM_LOOP) 315 mcr |= UART_MCR_LOOP; 316 317 mcr |= up->mcr; 318 319 serial_out(up, UART_MCR, mcr); 320 } 321 322 static void serial_pxa_break_ctl(struct uart_port *port, int break_state) 323 { 324 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 325 unsigned long flags; 326 327 spin_lock_irqsave(&up->port.lock, flags); 328 if (break_state == -1) 329 up->lcr |= UART_LCR_SBC; 330 else 331 up->lcr &= ~UART_LCR_SBC; 332 serial_out(up, UART_LCR, up->lcr); 333 spin_unlock_irqrestore(&up->port.lock, flags); 334 } 335 336 #if 0 337 static void serial_pxa_dma_init(struct pxa_uart *up) 338 { 339 up->rxdma = 340 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_receive_dma, up); 341 if (up->rxdma < 0) 342 goto out; 343 up->txdma = 344 pxa_request_dma(up->name, DMA_PRIO_LOW, pxa_transmit_dma, up); 345 if (up->txdma < 0) 346 goto err_txdma; 347 up->dmadesc = kmalloc(4 * sizeof(pxa_dma_desc), GFP_KERNEL); 348 if (!up->dmadesc) 349 goto err_alloc; 350 351 /* ... */ 352 err_alloc: 353 pxa_free_dma(up->txdma); 354 err_rxdma: 355 pxa_free_dma(up->rxdma); 356 out: 357 return; 358 } 359 #endif 360 361 static int serial_pxa_startup(struct uart_port *port) 362 { 363 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 364 unsigned long flags; 365 int retval; 366 367 if (port->line == 3) /* HWUART */ 368 up->mcr |= UART_MCR_AFE; 369 else 370 up->mcr = 0; 371 372 up->port.uartclk = clk_get_rate(up->clk); 373 374 /* 375 * Allocate the IRQ 376 */ 377 retval = request_irq(up->port.irq, serial_pxa_irq, 0, up->name, up); 378 if (retval) 379 return retval; 380 381 /* 382 * Clear the FIFO buffers and disable them. 383 * (they will be reenabled in set_termios()) 384 */ 385 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 386 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 387 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 388 serial_out(up, UART_FCR, 0); 389 390 /* 391 * Clear the interrupt registers. 392 */ 393 (void) serial_in(up, UART_LSR); 394 (void) serial_in(up, UART_RX); 395 (void) serial_in(up, UART_IIR); 396 (void) serial_in(up, UART_MSR); 397 398 /* 399 * Now, initialize the UART 400 */ 401 serial_out(up, UART_LCR, UART_LCR_WLEN8); 402 403 spin_lock_irqsave(&up->port.lock, flags); 404 up->port.mctrl |= TIOCM_OUT2; 405 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 406 spin_unlock_irqrestore(&up->port.lock, flags); 407 408 /* 409 * Finally, enable interrupts. Note: Modem status interrupts 410 * are set via set_termios(), which will be occurring imminently 411 * anyway, so we don't enable them here. 412 */ 413 up->ier = UART_IER_RLSI | UART_IER_RDI | UART_IER_RTOIE | UART_IER_UUE; 414 serial_out(up, UART_IER, up->ier); 415 416 /* 417 * And clear the interrupt registers again for luck. 418 */ 419 (void) serial_in(up, UART_LSR); 420 (void) serial_in(up, UART_RX); 421 (void) serial_in(up, UART_IIR); 422 (void) serial_in(up, UART_MSR); 423 424 return 0; 425 } 426 427 static void serial_pxa_shutdown(struct uart_port *port) 428 { 429 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 430 unsigned long flags; 431 432 free_irq(up->port.irq, up); 433 434 /* 435 * Disable interrupts from this port 436 */ 437 up->ier = 0; 438 serial_out(up, UART_IER, 0); 439 440 spin_lock_irqsave(&up->port.lock, flags); 441 up->port.mctrl &= ~TIOCM_OUT2; 442 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 443 spin_unlock_irqrestore(&up->port.lock, flags); 444 445 /* 446 * Disable break condition and FIFOs 447 */ 448 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 449 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 450 UART_FCR_CLEAR_RCVR | 451 UART_FCR_CLEAR_XMIT); 452 serial_out(up, UART_FCR, 0); 453 } 454 455 static void 456 serial_pxa_set_termios(struct uart_port *port, struct ktermios *termios, 457 struct ktermios *old) 458 { 459 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 460 unsigned char cval, fcr = 0; 461 unsigned long flags; 462 unsigned int baud, quot; 463 unsigned int dll; 464 465 switch (termios->c_cflag & CSIZE) { 466 case CS5: 467 cval = UART_LCR_WLEN5; 468 break; 469 case CS6: 470 cval = UART_LCR_WLEN6; 471 break; 472 case CS7: 473 cval = UART_LCR_WLEN7; 474 break; 475 default: 476 case CS8: 477 cval = UART_LCR_WLEN8; 478 break; 479 } 480 481 if (termios->c_cflag & CSTOPB) 482 cval |= UART_LCR_STOP; 483 if (termios->c_cflag & PARENB) 484 cval |= UART_LCR_PARITY; 485 if (!(termios->c_cflag & PARODD)) 486 cval |= UART_LCR_EPAR; 487 488 /* 489 * Ask the core to calculate the divisor for us. 490 */ 491 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); 492 quot = uart_get_divisor(port, baud); 493 494 if ((up->port.uartclk / quot) < (2400 * 16)) 495 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR1; 496 else if ((up->port.uartclk / quot) < (230400 * 16)) 497 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR8; 498 else 499 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_PXAR32; 500 501 /* 502 * Ok, we're now changing the port state. Do it with 503 * interrupts disabled. 504 */ 505 spin_lock_irqsave(&up->port.lock, flags); 506 507 /* 508 * Ensure the port will be enabled. 509 * This is required especially for serial console. 510 */ 511 up->ier |= UART_IER_UUE; 512 513 /* 514 * Update the per-port timeout. 515 */ 516 uart_update_timeout(port, termios->c_cflag, baud); 517 518 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 519 if (termios->c_iflag & INPCK) 520 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 521 if (termios->c_iflag & (BRKINT | PARMRK)) 522 up->port.read_status_mask |= UART_LSR_BI; 523 524 /* 525 * Characters to ignore 526 */ 527 up->port.ignore_status_mask = 0; 528 if (termios->c_iflag & IGNPAR) 529 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 530 if (termios->c_iflag & IGNBRK) { 531 up->port.ignore_status_mask |= UART_LSR_BI; 532 /* 533 * If we're ignoring parity and break indicators, 534 * ignore overruns too (for real raw support). 535 */ 536 if (termios->c_iflag & IGNPAR) 537 up->port.ignore_status_mask |= UART_LSR_OE; 538 } 539 540 /* 541 * ignore all characters if CREAD is not set 542 */ 543 if ((termios->c_cflag & CREAD) == 0) 544 up->port.ignore_status_mask |= UART_LSR_DR; 545 546 /* 547 * CTS flow control flag and modem status interrupts 548 */ 549 up->ier &= ~UART_IER_MSI; 550 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 551 up->ier |= UART_IER_MSI; 552 553 serial_out(up, UART_IER, up->ier); 554 555 if (termios->c_cflag & CRTSCTS) 556 up->mcr |= UART_MCR_AFE; 557 else 558 up->mcr &= ~UART_MCR_AFE; 559 560 serial_out(up, UART_LCR, cval | UART_LCR_DLAB); /* set DLAB */ 561 serial_out(up, UART_DLL, quot & 0xff); /* LS of divisor */ 562 563 /* 564 * work around Errata #75 according to Intel(R) PXA27x Processor Family 565 * Specification Update (Nov 2005) 566 */ 567 dll = serial_in(up, UART_DLL); 568 WARN_ON(dll != (quot & 0xff)); 569 570 serial_out(up, UART_DLM, quot >> 8); /* MS of divisor */ 571 serial_out(up, UART_LCR, cval); /* reset DLAB */ 572 up->lcr = cval; /* Save LCR */ 573 serial_pxa_set_mctrl(&up->port, up->port.mctrl); 574 serial_out(up, UART_FCR, fcr); 575 spin_unlock_irqrestore(&up->port.lock, flags); 576 } 577 578 static void 579 serial_pxa_pm(struct uart_port *port, unsigned int state, 580 unsigned int oldstate) 581 { 582 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 583 584 if (!state) 585 clk_prepare_enable(up->clk); 586 else 587 clk_disable_unprepare(up->clk); 588 } 589 590 static void serial_pxa_release_port(struct uart_port *port) 591 { 592 } 593 594 static int serial_pxa_request_port(struct uart_port *port) 595 { 596 return 0; 597 } 598 599 static void serial_pxa_config_port(struct uart_port *port, int flags) 600 { 601 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 602 up->port.type = PORT_PXA; 603 } 604 605 static int 606 serial_pxa_verify_port(struct uart_port *port, struct serial_struct *ser) 607 { 608 /* we don't want the core code to modify any port params */ 609 return -EINVAL; 610 } 611 612 static const char * 613 serial_pxa_type(struct uart_port *port) 614 { 615 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 616 return up->name; 617 } 618 619 static struct uart_pxa_port *serial_pxa_ports[4]; 620 static struct uart_driver serial_pxa_reg; 621 622 #ifdef CONFIG_SERIAL_PXA_CONSOLE 623 624 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 625 626 /* 627 * Wait for transmitter & holding register to empty 628 */ 629 static inline void wait_for_xmitr(struct uart_pxa_port *up) 630 { 631 unsigned int status, tmout = 10000; 632 633 /* Wait up to 10ms for the character(s) to be sent. */ 634 do { 635 status = serial_in(up, UART_LSR); 636 637 if (status & UART_LSR_BI) 638 up->lsr_break_flag = UART_LSR_BI; 639 640 if (--tmout == 0) 641 break; 642 udelay(1); 643 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 644 645 /* Wait up to 1s for flow control if necessary */ 646 if (up->port.flags & UPF_CONS_FLOW) { 647 tmout = 1000000; 648 while (--tmout && 649 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0)) 650 udelay(1); 651 } 652 } 653 654 static void serial_pxa_console_putchar(struct uart_port *port, int ch) 655 { 656 struct uart_pxa_port *up = (struct uart_pxa_port *)port; 657 658 wait_for_xmitr(up); 659 serial_out(up, UART_TX, ch); 660 } 661 662 /* 663 * Print a string to the serial port trying not to disturb 664 * any possible real use of the port... 665 * 666 * The console_lock must be held when we get here. 667 */ 668 static void 669 serial_pxa_console_write(struct console *co, const char *s, unsigned int count) 670 { 671 struct uart_pxa_port *up = serial_pxa_ports[co->index]; 672 unsigned int ier; 673 674 clk_prepare_enable(up->clk); 675 676 /* 677 * First save the IER then disable the interrupts 678 */ 679 ier = serial_in(up, UART_IER); 680 serial_out(up, UART_IER, UART_IER_UUE); 681 682 uart_console_write(&up->port, s, count, serial_pxa_console_putchar); 683 684 /* 685 * Finally, wait for transmitter to become empty 686 * and restore the IER 687 */ 688 wait_for_xmitr(up); 689 serial_out(up, UART_IER, ier); 690 691 clk_disable_unprepare(up->clk); 692 } 693 694 static int __init 695 serial_pxa_console_setup(struct console *co, char *options) 696 { 697 struct uart_pxa_port *up; 698 int baud = 9600; 699 int bits = 8; 700 int parity = 'n'; 701 int flow = 'n'; 702 703 if (co->index == -1 || co->index >= serial_pxa_reg.nr) 704 co->index = 0; 705 up = serial_pxa_ports[co->index]; 706 if (!up) 707 return -ENODEV; 708 709 if (options) 710 uart_parse_options(options, &baud, &parity, &bits, &flow); 711 712 return uart_set_options(&up->port, co, baud, parity, bits, flow); 713 } 714 715 static struct console serial_pxa_console = { 716 .name = "ttyS", 717 .write = serial_pxa_console_write, 718 .device = uart_console_device, 719 .setup = serial_pxa_console_setup, 720 .flags = CON_PRINTBUFFER, 721 .index = -1, 722 .data = &serial_pxa_reg, 723 }; 724 725 #define PXA_CONSOLE &serial_pxa_console 726 #else 727 #define PXA_CONSOLE NULL 728 #endif 729 730 struct uart_ops serial_pxa_pops = { 731 .tx_empty = serial_pxa_tx_empty, 732 .set_mctrl = serial_pxa_set_mctrl, 733 .get_mctrl = serial_pxa_get_mctrl, 734 .stop_tx = serial_pxa_stop_tx, 735 .start_tx = serial_pxa_start_tx, 736 .stop_rx = serial_pxa_stop_rx, 737 .enable_ms = serial_pxa_enable_ms, 738 .break_ctl = serial_pxa_break_ctl, 739 .startup = serial_pxa_startup, 740 .shutdown = serial_pxa_shutdown, 741 .set_termios = serial_pxa_set_termios, 742 .pm = serial_pxa_pm, 743 .type = serial_pxa_type, 744 .release_port = serial_pxa_release_port, 745 .request_port = serial_pxa_request_port, 746 .config_port = serial_pxa_config_port, 747 .verify_port = serial_pxa_verify_port, 748 }; 749 750 static struct uart_driver serial_pxa_reg = { 751 .owner = THIS_MODULE, 752 .driver_name = "PXA serial", 753 .dev_name = "ttyS", 754 .major = TTY_MAJOR, 755 .minor = 64, 756 .nr = 4, 757 .cons = PXA_CONSOLE, 758 }; 759 760 #ifdef CONFIG_PM 761 static int serial_pxa_suspend(struct device *dev) 762 { 763 struct uart_pxa_port *sport = dev_get_drvdata(dev); 764 765 if (sport) 766 uart_suspend_port(&serial_pxa_reg, &sport->port); 767 768 return 0; 769 } 770 771 static int serial_pxa_resume(struct device *dev) 772 { 773 struct uart_pxa_port *sport = dev_get_drvdata(dev); 774 775 if (sport) 776 uart_resume_port(&serial_pxa_reg, &sport->port); 777 778 return 0; 779 } 780 781 static const struct dev_pm_ops serial_pxa_pm_ops = { 782 .suspend = serial_pxa_suspend, 783 .resume = serial_pxa_resume, 784 }; 785 #endif 786 787 static struct of_device_id serial_pxa_dt_ids[] = { 788 { .compatible = "mrvl,pxa-uart", }, 789 { .compatible = "mrvl,mmp-uart", }, 790 {} 791 }; 792 MODULE_DEVICE_TABLE(of, serial_pxa_dt_ids); 793 794 static int serial_pxa_probe_dt(struct platform_device *pdev, 795 struct uart_pxa_port *sport) 796 { 797 struct device_node *np = pdev->dev.of_node; 798 int ret; 799 800 if (!np) 801 return 1; 802 803 ret = of_alias_get_id(np, "serial"); 804 if (ret < 0) { 805 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret); 806 return ret; 807 } 808 sport->port.line = ret; 809 return 0; 810 } 811 812 static int serial_pxa_probe(struct platform_device *dev) 813 { 814 struct uart_pxa_port *sport; 815 struct resource *mmres, *irqres; 816 int ret; 817 818 mmres = platform_get_resource(dev, IORESOURCE_MEM, 0); 819 irqres = platform_get_resource(dev, IORESOURCE_IRQ, 0); 820 if (!mmres || !irqres) 821 return -ENODEV; 822 823 sport = kzalloc(sizeof(struct uart_pxa_port), GFP_KERNEL); 824 if (!sport) 825 return -ENOMEM; 826 827 sport->clk = clk_get(&dev->dev, NULL); 828 if (IS_ERR(sport->clk)) { 829 ret = PTR_ERR(sport->clk); 830 goto err_free; 831 } 832 833 sport->port.type = PORT_PXA; 834 sport->port.iotype = UPIO_MEM; 835 sport->port.mapbase = mmres->start; 836 sport->port.irq = irqres->start; 837 sport->port.fifosize = 64; 838 sport->port.ops = &serial_pxa_pops; 839 sport->port.dev = &dev->dev; 840 sport->port.flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF; 841 sport->port.uartclk = clk_get_rate(sport->clk); 842 843 ret = serial_pxa_probe_dt(dev, sport); 844 if (ret > 0) 845 sport->port.line = dev->id; 846 else if (ret < 0) 847 goto err_clk; 848 snprintf(sport->name, PXA_NAME_LEN - 1, "UART%d", sport->port.line + 1); 849 850 sport->port.membase = ioremap(mmres->start, resource_size(mmres)); 851 if (!sport->port.membase) { 852 ret = -ENOMEM; 853 goto err_clk; 854 } 855 856 serial_pxa_ports[sport->port.line] = sport; 857 858 uart_add_one_port(&serial_pxa_reg, &sport->port); 859 platform_set_drvdata(dev, sport); 860 861 return 0; 862 863 err_clk: 864 clk_put(sport->clk); 865 err_free: 866 kfree(sport); 867 return ret; 868 } 869 870 static int serial_pxa_remove(struct platform_device *dev) 871 { 872 struct uart_pxa_port *sport = platform_get_drvdata(dev); 873 874 platform_set_drvdata(dev, NULL); 875 876 uart_remove_one_port(&serial_pxa_reg, &sport->port); 877 clk_put(sport->clk); 878 kfree(sport); 879 880 return 0; 881 } 882 883 static struct platform_driver serial_pxa_driver = { 884 .probe = serial_pxa_probe, 885 .remove = serial_pxa_remove, 886 887 .driver = { 888 .name = "pxa2xx-uart", 889 .owner = THIS_MODULE, 890 #ifdef CONFIG_PM 891 .pm = &serial_pxa_pm_ops, 892 #endif 893 .of_match_table = serial_pxa_dt_ids, 894 }, 895 }; 896 897 int __init serial_pxa_init(void) 898 { 899 int ret; 900 901 ret = uart_register_driver(&serial_pxa_reg); 902 if (ret != 0) 903 return ret; 904 905 ret = platform_driver_register(&serial_pxa_driver); 906 if (ret != 0) 907 uart_unregister_driver(&serial_pxa_reg); 908 909 return ret; 910 } 911 912 void __exit serial_pxa_exit(void) 913 { 914 platform_driver_unregister(&serial_pxa_driver); 915 uart_unregister_driver(&serial_pxa_reg); 916 } 917 918 module_init(serial_pxa_init); 919 module_exit(serial_pxa_exit); 920 921 MODULE_LICENSE("GPL"); 922 MODULE_ALIAS("platform:pxa2xx-uart"); 923