1 /* 2 * Driver for PowerMac Z85c30 based ESCC cell found in the 3 * "macio" ASICs of various PowerMac models 4 * 5 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) 6 * 7 * Derived from drivers/macintosh/macserial.c by Paul Mackerras 8 * and drivers/serial/sunzilog.c by David S. Miller 9 * 10 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and 11 * adapted special tweaks needed for us. I don't think it's worth 12 * merging back those though. The DMA code still has to get in 13 * and once done, I expect that driver to remain fairly stable in 14 * the long term, unless we change the driver model again... 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 * 30 * 2004-08-06 Harald Welte <laforge@gnumonks.org> 31 * - Enable BREAK interrupt 32 * - Add support for sysreq 33 * 34 * TODO: - Add DMA support 35 * - Defer port shutdown to a few seconds after close 36 * - maybe put something right into uap->clk_divisor 37 */ 38 39 #undef DEBUG 40 #undef DEBUG_HARD 41 #undef USE_CTRL_O_SYSRQ 42 43 #include <linux/module.h> 44 #include <linux/tty.h> 45 46 #include <linux/tty_flip.h> 47 #include <linux/major.h> 48 #include <linux/string.h> 49 #include <linux/fcntl.h> 50 #include <linux/mm.h> 51 #include <linux/kernel.h> 52 #include <linux/delay.h> 53 #include <linux/init.h> 54 #include <linux/console.h> 55 #include <linux/adb.h> 56 #include <linux/pmu.h> 57 #include <linux/bitops.h> 58 #include <linux/sysrq.h> 59 #include <linux/mutex.h> 60 #include <asm/sections.h> 61 #include <asm/io.h> 62 #include <asm/irq.h> 63 64 #ifdef CONFIG_PPC_PMAC 65 #include <asm/prom.h> 66 #include <asm/machdep.h> 67 #include <asm/pmac_feature.h> 68 #include <asm/dbdma.h> 69 #include <asm/macio.h> 70 #else 71 #include <linux/platform_device.h> 72 #define of_machine_is_compatible(x) (0) 73 #endif 74 75 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 76 #define SUPPORT_SYSRQ 77 #endif 78 79 #include <linux/serial.h> 80 #include <linux/serial_core.h> 81 82 #include "pmac_zilog.h" 83 84 /* Not yet implemented */ 85 #undef HAS_DBDMA 86 87 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; 88 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); 89 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports."); 90 MODULE_LICENSE("GPL"); 91 92 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS 93 #define PMACZILOG_MAJOR TTY_MAJOR 94 #define PMACZILOG_MINOR 64 95 #define PMACZILOG_NAME "ttyS" 96 #else 97 #define PMACZILOG_MAJOR 204 98 #define PMACZILOG_MINOR 192 99 #define PMACZILOG_NAME "ttyPZ" 100 #endif 101 102 103 /* 104 * For the sake of early serial console, we can do a pre-probe 105 * (optional) of the ports at rather early boot time. 106 */ 107 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; 108 static int pmz_ports_count; 109 static DEFINE_MUTEX(pmz_irq_mutex); 110 111 static struct uart_driver pmz_uart_reg = { 112 .owner = THIS_MODULE, 113 .driver_name = PMACZILOG_NAME, 114 .dev_name = PMACZILOG_NAME, 115 .major = PMACZILOG_MAJOR, 116 .minor = PMACZILOG_MINOR, 117 }; 118 119 120 /* 121 * Load all registers to reprogram the port 122 * This function must only be called when the TX is not busy. The UART 123 * port lock must be held and local interrupts disabled. 124 */ 125 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) 126 { 127 int i; 128 129 if (ZS_IS_ASLEEP(uap)) 130 return; 131 132 /* Let pending transmits finish. */ 133 for (i = 0; i < 1000; i++) { 134 unsigned char stat = read_zsreg(uap, R1); 135 if (stat & ALL_SNT) 136 break; 137 udelay(100); 138 } 139 140 ZS_CLEARERR(uap); 141 zssync(uap); 142 ZS_CLEARFIFO(uap); 143 zssync(uap); 144 ZS_CLEARERR(uap); 145 146 /* Disable all interrupts. */ 147 write_zsreg(uap, R1, 148 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 149 150 /* Set parity, sync config, stop bits, and clock divisor. */ 151 write_zsreg(uap, R4, regs[R4]); 152 153 /* Set misc. TX/RX control bits. */ 154 write_zsreg(uap, R10, regs[R10]); 155 156 /* Set TX/RX controls sans the enable bits. */ 157 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); 158 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); 159 160 /* now set R7 "prime" on ESCC */ 161 write_zsreg(uap, R15, regs[R15] | EN85C30); 162 write_zsreg(uap, R7, regs[R7P]); 163 164 /* make sure we use R7 "non-prime" on ESCC */ 165 write_zsreg(uap, R15, regs[R15] & ~EN85C30); 166 167 /* Synchronous mode config. */ 168 write_zsreg(uap, R6, regs[R6]); 169 write_zsreg(uap, R7, regs[R7]); 170 171 /* Disable baud generator. */ 172 write_zsreg(uap, R14, regs[R14] & ~BRENAB); 173 174 /* Clock mode control. */ 175 write_zsreg(uap, R11, regs[R11]); 176 177 /* Lower and upper byte of baud rate generator divisor. */ 178 write_zsreg(uap, R12, regs[R12]); 179 write_zsreg(uap, R13, regs[R13]); 180 181 /* Now rewrite R14, with BRENAB (if set). */ 182 write_zsreg(uap, R14, regs[R14]); 183 184 /* Reset external status interrupts. */ 185 write_zsreg(uap, R0, RES_EXT_INT); 186 write_zsreg(uap, R0, RES_EXT_INT); 187 188 /* Rewrite R3/R5, this time without enables masked. */ 189 write_zsreg(uap, R3, regs[R3]); 190 write_zsreg(uap, R5, regs[R5]); 191 192 /* Rewrite R1, this time without IRQ enabled masked. */ 193 write_zsreg(uap, R1, regs[R1]); 194 195 /* Enable interrupts */ 196 write_zsreg(uap, R9, regs[R9]); 197 } 198 199 /* 200 * We do like sunzilog to avoid disrupting pending Tx 201 * Reprogram the Zilog channel HW registers with the copies found in the 202 * software state struct. If the transmitter is busy, we defer this update 203 * until the next TX complete interrupt. Else, we do it right now. 204 * 205 * The UART port lock must be held and local interrupts disabled. 206 */ 207 static void pmz_maybe_update_regs(struct uart_pmac_port *uap) 208 { 209 if (!ZS_REGS_HELD(uap)) { 210 if (ZS_TX_ACTIVE(uap)) { 211 uap->flags |= PMACZILOG_FLAG_REGS_HELD; 212 } else { 213 pmz_debug("pmz: maybe_update_regs: updating\n"); 214 pmz_load_zsregs(uap, uap->curregs); 215 } 216 } 217 } 218 219 static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) 220 { 221 struct tty_struct *tty = NULL; 222 unsigned char ch, r1, drop, error, flag; 223 int loops = 0; 224 225 /* The interrupt can be enabled when the port isn't open, typically 226 * that happens when using one port is open and the other closed (stale 227 * interrupt) or when one port is used as a console. 228 */ 229 if (!ZS_IS_OPEN(uap)) { 230 pmz_debug("pmz: draining input\n"); 231 /* Port is closed, drain input data */ 232 for (;;) { 233 if ((++loops) > 1000) 234 goto flood; 235 (void)read_zsreg(uap, R1); 236 write_zsreg(uap, R0, ERR_RES); 237 (void)read_zsdata(uap); 238 ch = read_zsreg(uap, R0); 239 if (!(ch & Rx_CH_AV)) 240 break; 241 } 242 return NULL; 243 } 244 245 /* Sanity check, make sure the old bug is no longer happening */ 246 if (uap->port.state == NULL || uap->port.state->port.tty == NULL) { 247 WARN_ON(1); 248 (void)read_zsdata(uap); 249 return NULL; 250 } 251 tty = uap->port.state->port.tty; 252 253 while (1) { 254 error = 0; 255 drop = 0; 256 257 r1 = read_zsreg(uap, R1); 258 ch = read_zsdata(uap); 259 260 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 261 write_zsreg(uap, R0, ERR_RES); 262 zssync(uap); 263 } 264 265 ch &= uap->parity_mask; 266 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { 267 uap->flags &= ~PMACZILOG_FLAG_BREAK; 268 } 269 270 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) 271 #ifdef USE_CTRL_O_SYSRQ 272 /* Handle the SysRq ^O Hack */ 273 if (ch == '\x0f') { 274 uap->port.sysrq = jiffies + HZ*5; 275 goto next_char; 276 } 277 #endif /* USE_CTRL_O_SYSRQ */ 278 if (uap->port.sysrq) { 279 int swallow; 280 spin_unlock(&uap->port.lock); 281 swallow = uart_handle_sysrq_char(&uap->port, ch); 282 spin_lock(&uap->port.lock); 283 if (swallow) 284 goto next_char; 285 } 286 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ 287 288 /* A real serial line, record the character and status. */ 289 if (drop) 290 goto next_char; 291 292 flag = TTY_NORMAL; 293 uap->port.icount.rx++; 294 295 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { 296 error = 1; 297 if (r1 & BRK_ABRT) { 298 pmz_debug("pmz: got break !\n"); 299 r1 &= ~(PAR_ERR | CRC_ERR); 300 uap->port.icount.brk++; 301 if (uart_handle_break(&uap->port)) 302 goto next_char; 303 } 304 else if (r1 & PAR_ERR) 305 uap->port.icount.parity++; 306 else if (r1 & CRC_ERR) 307 uap->port.icount.frame++; 308 if (r1 & Rx_OVR) 309 uap->port.icount.overrun++; 310 r1 &= uap->port.read_status_mask; 311 if (r1 & BRK_ABRT) 312 flag = TTY_BREAK; 313 else if (r1 & PAR_ERR) 314 flag = TTY_PARITY; 315 else if (r1 & CRC_ERR) 316 flag = TTY_FRAME; 317 } 318 319 if (uap->port.ignore_status_mask == 0xff || 320 (r1 & uap->port.ignore_status_mask) == 0) { 321 tty_insert_flip_char(tty, ch, flag); 322 } 323 if (r1 & Rx_OVR) 324 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 325 next_char: 326 /* We can get stuck in an infinite loop getting char 0 when the 327 * line is in a wrong HW state, we break that here. 328 * When that happens, I disable the receive side of the driver. 329 * Note that what I've been experiencing is a real irq loop where 330 * I'm getting flooded regardless of the actual port speed. 331 * Something strange is going on with the HW 332 */ 333 if ((++loops) > 1000) 334 goto flood; 335 ch = read_zsreg(uap, R0); 336 if (!(ch & Rx_CH_AV)) 337 break; 338 } 339 340 return tty; 341 flood: 342 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 343 write_zsreg(uap, R1, uap->curregs[R1]); 344 zssync(uap); 345 pmz_error("pmz: rx irq flood !\n"); 346 return tty; 347 } 348 349 static void pmz_status_handle(struct uart_pmac_port *uap) 350 { 351 unsigned char status; 352 353 status = read_zsreg(uap, R0); 354 write_zsreg(uap, R0, RES_EXT_INT); 355 zssync(uap); 356 357 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { 358 if (status & SYNC_HUNT) 359 uap->port.icount.dsr++; 360 361 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 362 * But it does not tell us which bit has changed, we have to keep 363 * track of this ourselves. 364 * The CTS input is inverted for some reason. -- paulus 365 */ 366 if ((status ^ uap->prev_status) & DCD) 367 uart_handle_dcd_change(&uap->port, 368 (status & DCD)); 369 if ((status ^ uap->prev_status) & CTS) 370 uart_handle_cts_change(&uap->port, 371 !(status & CTS)); 372 373 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 374 } 375 376 if (status & BRK_ABRT) 377 uap->flags |= PMACZILOG_FLAG_BREAK; 378 379 uap->prev_status = status; 380 } 381 382 static void pmz_transmit_chars(struct uart_pmac_port *uap) 383 { 384 struct circ_buf *xmit; 385 386 if (ZS_IS_ASLEEP(uap)) 387 return; 388 if (ZS_IS_CONS(uap)) { 389 unsigned char status = read_zsreg(uap, R0); 390 391 /* TX still busy? Just wait for the next TX done interrupt. 392 * 393 * It can occur because of how we do serial console writes. It would 394 * be nice to transmit console writes just like we normally would for 395 * a TTY line. (ie. buffered and TX interrupt driven). That is not 396 * easy because console writes cannot sleep. One solution might be 397 * to poll on enough port->xmit space becoming free. -DaveM 398 */ 399 if (!(status & Tx_BUF_EMP)) 400 return; 401 } 402 403 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; 404 405 if (ZS_REGS_HELD(uap)) { 406 pmz_load_zsregs(uap, uap->curregs); 407 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; 408 } 409 410 if (ZS_TX_STOPPED(uap)) { 411 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 412 goto ack_tx_int; 413 } 414 415 /* Under some circumstances, we see interrupts reported for 416 * a closed channel. The interrupt mask in R1 is clear, but 417 * R3 still signals the interrupts and we see them when taking 418 * an interrupt for the other channel (this could be a qemu 419 * bug but since the ESCC doc doesn't specify precsiely whether 420 * R3 interrup status bits are masked by R1 interrupt enable 421 * bits, better safe than sorry). --BenH. 422 */ 423 if (!ZS_IS_OPEN(uap)) 424 goto ack_tx_int; 425 426 if (uap->port.x_char) { 427 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 428 write_zsdata(uap, uap->port.x_char); 429 zssync(uap); 430 uap->port.icount.tx++; 431 uap->port.x_char = 0; 432 return; 433 } 434 435 if (uap->port.state == NULL) 436 goto ack_tx_int; 437 xmit = &uap->port.state->xmit; 438 if (uart_circ_empty(xmit)) { 439 uart_write_wakeup(&uap->port); 440 goto ack_tx_int; 441 } 442 if (uart_tx_stopped(&uap->port)) 443 goto ack_tx_int; 444 445 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 446 write_zsdata(uap, xmit->buf[xmit->tail]); 447 zssync(uap); 448 449 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 450 uap->port.icount.tx++; 451 452 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 453 uart_write_wakeup(&uap->port); 454 455 return; 456 457 ack_tx_int: 458 write_zsreg(uap, R0, RES_Tx_P); 459 zssync(uap); 460 } 461 462 /* Hrm... we register that twice, fixme later.... */ 463 static irqreturn_t pmz_interrupt(int irq, void *dev_id) 464 { 465 struct uart_pmac_port *uap = dev_id; 466 struct uart_pmac_port *uap_a; 467 struct uart_pmac_port *uap_b; 468 int rc = IRQ_NONE; 469 struct tty_struct *tty; 470 u8 r3; 471 472 uap_a = pmz_get_port_A(uap); 473 uap_b = uap_a->mate; 474 475 spin_lock(&uap_a->port.lock); 476 r3 = read_zsreg(uap_a, R3); 477 478 #ifdef DEBUG_HARD 479 pmz_debug("irq, r3: %x\n", r3); 480 #endif 481 /* Channel A */ 482 tty = NULL; 483 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 484 write_zsreg(uap_a, R0, RES_H_IUS); 485 zssync(uap_a); 486 if (r3 & CHAEXT) 487 pmz_status_handle(uap_a); 488 if (r3 & CHARxIP) 489 tty = pmz_receive_chars(uap_a); 490 if (r3 & CHATxIP) 491 pmz_transmit_chars(uap_a); 492 rc = IRQ_HANDLED; 493 } 494 spin_unlock(&uap_a->port.lock); 495 if (tty != NULL) 496 tty_flip_buffer_push(tty); 497 498 if (uap_b->node == NULL) 499 goto out; 500 501 spin_lock(&uap_b->port.lock); 502 tty = NULL; 503 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 504 write_zsreg(uap_b, R0, RES_H_IUS); 505 zssync(uap_b); 506 if (r3 & CHBEXT) 507 pmz_status_handle(uap_b); 508 if (r3 & CHBRxIP) 509 tty = pmz_receive_chars(uap_b); 510 if (r3 & CHBTxIP) 511 pmz_transmit_chars(uap_b); 512 rc = IRQ_HANDLED; 513 } 514 spin_unlock(&uap_b->port.lock); 515 if (tty != NULL) 516 tty_flip_buffer_push(tty); 517 518 out: 519 #ifdef DEBUG_HARD 520 pmz_debug("irq done.\n"); 521 #endif 522 return rc; 523 } 524 525 /* 526 * Peek the status register, lock not held by caller 527 */ 528 static inline u8 pmz_peek_status(struct uart_pmac_port *uap) 529 { 530 unsigned long flags; 531 u8 status; 532 533 spin_lock_irqsave(&uap->port.lock, flags); 534 status = read_zsreg(uap, R0); 535 spin_unlock_irqrestore(&uap->port.lock, flags); 536 537 return status; 538 } 539 540 /* 541 * Check if transmitter is empty 542 * The port lock is not held. 543 */ 544 static unsigned int pmz_tx_empty(struct uart_port *port) 545 { 546 struct uart_pmac_port *uap = to_pmz(port); 547 unsigned char status; 548 549 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 550 return TIOCSER_TEMT; 551 552 status = pmz_peek_status(to_pmz(port)); 553 if (status & Tx_BUF_EMP) 554 return TIOCSER_TEMT; 555 return 0; 556 } 557 558 /* 559 * Set Modem Control (RTS & DTR) bits 560 * The port lock is held and interrupts are disabled. 561 * Note: Shall we really filter out RTS on external ports or 562 * should that be dealt at higher level only ? 563 */ 564 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) 565 { 566 struct uart_pmac_port *uap = to_pmz(port); 567 unsigned char set_bits, clear_bits; 568 569 /* Do nothing for irda for now... */ 570 if (ZS_IS_IRDA(uap)) 571 return; 572 /* We get called during boot with a port not up yet */ 573 if (ZS_IS_ASLEEP(uap) || 574 !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) 575 return; 576 577 set_bits = clear_bits = 0; 578 579 if (ZS_IS_INTMODEM(uap)) { 580 if (mctrl & TIOCM_RTS) 581 set_bits |= RTS; 582 else 583 clear_bits |= RTS; 584 } 585 if (mctrl & TIOCM_DTR) 586 set_bits |= DTR; 587 else 588 clear_bits |= DTR; 589 590 /* NOTE: Not subject to 'transmitter active' rule. */ 591 uap->curregs[R5] |= set_bits; 592 uap->curregs[R5] &= ~clear_bits; 593 if (ZS_IS_ASLEEP(uap)) 594 return; 595 write_zsreg(uap, R5, uap->curregs[R5]); 596 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", 597 set_bits, clear_bits, uap->curregs[R5]); 598 zssync(uap); 599 } 600 601 /* 602 * Get Modem Control bits (only the input ones, the core will 603 * or that with a cached value of the control ones) 604 * The port lock is held and interrupts are disabled. 605 */ 606 static unsigned int pmz_get_mctrl(struct uart_port *port) 607 { 608 struct uart_pmac_port *uap = to_pmz(port); 609 unsigned char status; 610 unsigned int ret; 611 612 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 613 return 0; 614 615 status = read_zsreg(uap, R0); 616 617 ret = 0; 618 if (status & DCD) 619 ret |= TIOCM_CAR; 620 if (status & SYNC_HUNT) 621 ret |= TIOCM_DSR; 622 if (!(status & CTS)) 623 ret |= TIOCM_CTS; 624 625 return ret; 626 } 627 628 /* 629 * Stop TX side. Dealt like sunzilog at next Tx interrupt, 630 * though for DMA, we will have to do a bit more. 631 * The port lock is held and interrupts are disabled. 632 */ 633 static void pmz_stop_tx(struct uart_port *port) 634 { 635 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; 636 } 637 638 /* 639 * Kick the Tx side. 640 * The port lock is held and interrupts are disabled. 641 */ 642 static void pmz_start_tx(struct uart_port *port) 643 { 644 struct uart_pmac_port *uap = to_pmz(port); 645 unsigned char status; 646 647 pmz_debug("pmz: start_tx()\n"); 648 649 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 650 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 651 652 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 653 return; 654 655 status = read_zsreg(uap, R0); 656 657 /* TX busy? Just wait for the TX done interrupt. */ 658 if (!(status & Tx_BUF_EMP)) 659 return; 660 661 /* Send the first character to jump-start the TX done 662 * IRQ sending engine. 663 */ 664 if (port->x_char) { 665 write_zsdata(uap, port->x_char); 666 zssync(uap); 667 port->icount.tx++; 668 port->x_char = 0; 669 } else { 670 struct circ_buf *xmit = &port->state->xmit; 671 672 write_zsdata(uap, xmit->buf[xmit->tail]); 673 zssync(uap); 674 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 675 port->icount.tx++; 676 677 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 678 uart_write_wakeup(&uap->port); 679 } 680 pmz_debug("pmz: start_tx() done.\n"); 681 } 682 683 /* 684 * Stop Rx side, basically disable emitting of 685 * Rx interrupts on the port. We don't disable the rx 686 * side of the chip proper though 687 * The port lock is held. 688 */ 689 static void pmz_stop_rx(struct uart_port *port) 690 { 691 struct uart_pmac_port *uap = to_pmz(port); 692 693 if (ZS_IS_ASLEEP(uap) || uap->node == NULL) 694 return; 695 696 pmz_debug("pmz: stop_rx()()\n"); 697 698 /* Disable all RX interrupts. */ 699 uap->curregs[R1] &= ~RxINT_MASK; 700 pmz_maybe_update_regs(uap); 701 702 pmz_debug("pmz: stop_rx() done.\n"); 703 } 704 705 /* 706 * Enable modem status change interrupts 707 * The port lock is held. 708 */ 709 static void pmz_enable_ms(struct uart_port *port) 710 { 711 struct uart_pmac_port *uap = to_pmz(port); 712 unsigned char new_reg; 713 714 if (ZS_IS_IRDA(uap) || uap->node == NULL) 715 return; 716 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 717 if (new_reg != uap->curregs[R15]) { 718 uap->curregs[R15] = new_reg; 719 720 if (ZS_IS_ASLEEP(uap)) 721 return; 722 /* NOTE: Not subject to 'transmitter active' rule. */ 723 write_zsreg(uap, R15, uap->curregs[R15]); 724 } 725 } 726 727 /* 728 * Control break state emission 729 * The port lock is not held. 730 */ 731 static void pmz_break_ctl(struct uart_port *port, int break_state) 732 { 733 struct uart_pmac_port *uap = to_pmz(port); 734 unsigned char set_bits, clear_bits, new_reg; 735 unsigned long flags; 736 737 if (uap->node == NULL) 738 return; 739 set_bits = clear_bits = 0; 740 741 if (break_state) 742 set_bits |= SND_BRK; 743 else 744 clear_bits |= SND_BRK; 745 746 spin_lock_irqsave(&port->lock, flags); 747 748 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 749 if (new_reg != uap->curregs[R5]) { 750 uap->curregs[R5] = new_reg; 751 752 /* NOTE: Not subject to 'transmitter active' rule. */ 753 if (ZS_IS_ASLEEP(uap)) { 754 spin_unlock_irqrestore(&port->lock, flags); 755 return; 756 } 757 write_zsreg(uap, R5, uap->curregs[R5]); 758 } 759 760 spin_unlock_irqrestore(&port->lock, flags); 761 } 762 763 #ifdef CONFIG_PPC_PMAC 764 765 /* 766 * Turn power on or off to the SCC and associated stuff 767 * (port drivers, modem, IR port, etc.) 768 * Returns the number of milliseconds we should wait before 769 * trying to use the port. 770 */ 771 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 772 { 773 int delay = 0; 774 int rc; 775 776 if (state) { 777 rc = pmac_call_feature( 778 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); 779 pmz_debug("port power on result: %d\n", rc); 780 if (ZS_IS_INTMODEM(uap)) { 781 rc = pmac_call_feature( 782 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); 783 delay = 2500; /* wait for 2.5s before using */ 784 pmz_debug("modem power result: %d\n", rc); 785 } 786 } else { 787 /* TODO: Make that depend on a timer, don't power down 788 * immediately 789 */ 790 if (ZS_IS_INTMODEM(uap)) { 791 rc = pmac_call_feature( 792 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); 793 pmz_debug("port power off result: %d\n", rc); 794 } 795 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); 796 } 797 return delay; 798 } 799 800 #else 801 802 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 803 { 804 return 0; 805 } 806 807 #endif /* !CONFIG_PPC_PMAC */ 808 809 /* 810 * FixZeroBug....Works around a bug in the SCC receiving channel. 811 * Inspired from Darwin code, 15 Sept. 2000 -DanM 812 * 813 * The following sequence prevents a problem that is seen with O'Hare ASICs 814 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero 815 * at the input to the receiver becomes 'stuck' and locks up the receiver. 816 * This problem can occur as a result of a zero bit at the receiver input 817 * coincident with any of the following events: 818 * 819 * The SCC is initialized (hardware or software). 820 * A framing error is detected. 821 * The clocking option changes from synchronous or X1 asynchronous 822 * clocking to X16, X32, or X64 asynchronous clocking. 823 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. 824 * 825 * This workaround attempts to recover from the lockup condition by placing 826 * the SCC in synchronous loopback mode with a fast clock before programming 827 * any of the asynchronous modes. 828 */ 829 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) 830 { 831 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 832 zssync(uap); 833 udelay(10); 834 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); 835 zssync(uap); 836 837 write_zsreg(uap, 4, X1CLK | MONSYNC); 838 write_zsreg(uap, 3, Rx8); 839 write_zsreg(uap, 5, Tx8 | RTS); 840 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ 841 write_zsreg(uap, 11, RCBR | TCBR); 842 write_zsreg(uap, 12, 0); 843 write_zsreg(uap, 13, 0); 844 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); 845 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); 846 write_zsreg(uap, 3, Rx8 | RxENABLE); 847 write_zsreg(uap, 0, RES_EXT_INT); 848 write_zsreg(uap, 0, RES_EXT_INT); 849 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ 850 851 /* The channel should be OK now, but it is probably receiving 852 * loopback garbage. 853 * Switch to asynchronous mode, disable the receiver, 854 * and discard everything in the receive buffer. 855 */ 856 write_zsreg(uap, 9, NV); 857 write_zsreg(uap, 4, X16CLK | SB_MASK); 858 write_zsreg(uap, 3, Rx8); 859 860 while (read_zsreg(uap, 0) & Rx_CH_AV) { 861 (void)read_zsreg(uap, 8); 862 write_zsreg(uap, 0, RES_EXT_INT); 863 write_zsreg(uap, 0, ERR_RES); 864 } 865 } 866 867 /* 868 * Real startup routine, powers up the hardware and sets up 869 * the SCC. Returns a delay in ms where you need to wait before 870 * actually using the port, this is typically the internal modem 871 * powerup delay. This routine expect the lock to be taken. 872 */ 873 static int __pmz_startup(struct uart_pmac_port *uap) 874 { 875 int pwr_delay = 0; 876 877 memset(&uap->curregs, 0, sizeof(uap->curregs)); 878 879 /* Power up the SCC & underlying hardware (modem/irda) */ 880 pwr_delay = pmz_set_scc_power(uap, 1); 881 882 /* Nice buggy HW ... */ 883 pmz_fix_zero_bug_scc(uap); 884 885 /* Reset the channel */ 886 uap->curregs[R9] = 0; 887 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 888 zssync(uap); 889 udelay(10); 890 write_zsreg(uap, 9, 0); 891 zssync(uap); 892 893 /* Clear the interrupt registers */ 894 write_zsreg(uap, R1, 0); 895 write_zsreg(uap, R0, ERR_RES); 896 write_zsreg(uap, R0, ERR_RES); 897 write_zsreg(uap, R0, RES_H_IUS); 898 write_zsreg(uap, R0, RES_H_IUS); 899 900 /* Setup some valid baud rate */ 901 uap->curregs[R4] = X16CLK | SB1; 902 uap->curregs[R3] = Rx8; 903 uap->curregs[R5] = Tx8 | RTS; 904 if (!ZS_IS_IRDA(uap)) 905 uap->curregs[R5] |= DTR; 906 uap->curregs[R12] = 0; 907 uap->curregs[R13] = 0; 908 uap->curregs[R14] = BRENAB; 909 910 /* Clear handshaking, enable BREAK interrupts */ 911 uap->curregs[R15] = BRKIE; 912 913 /* Master interrupt enable */ 914 uap->curregs[R9] |= NV | MIE; 915 916 pmz_load_zsregs(uap, uap->curregs); 917 918 /* Enable receiver and transmitter. */ 919 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); 920 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); 921 922 /* Remember status for DCD/CTS changes */ 923 uap->prev_status = read_zsreg(uap, R0); 924 925 return pwr_delay; 926 } 927 928 static void pmz_irda_reset(struct uart_pmac_port *uap) 929 { 930 uap->curregs[R5] |= DTR; 931 write_zsreg(uap, R5, uap->curregs[R5]); 932 zssync(uap); 933 mdelay(110); 934 uap->curregs[R5] &= ~DTR; 935 write_zsreg(uap, R5, uap->curregs[R5]); 936 zssync(uap); 937 mdelay(10); 938 } 939 940 /* 941 * This is the "normal" startup routine, using the above one 942 * wrapped with the lock and doing a schedule delay 943 */ 944 static int pmz_startup(struct uart_port *port) 945 { 946 struct uart_pmac_port *uap = to_pmz(port); 947 unsigned long flags; 948 int pwr_delay = 0; 949 950 pmz_debug("pmz: startup()\n"); 951 952 if (ZS_IS_ASLEEP(uap)) 953 return -EAGAIN; 954 if (uap->node == NULL) 955 return -ENODEV; 956 957 mutex_lock(&pmz_irq_mutex); 958 959 uap->flags |= PMACZILOG_FLAG_IS_OPEN; 960 961 /* A console is never powered down. Else, power up and 962 * initialize the chip 963 */ 964 if (!ZS_IS_CONS(uap)) { 965 spin_lock_irqsave(&port->lock, flags); 966 pwr_delay = __pmz_startup(uap); 967 spin_unlock_irqrestore(&port->lock, flags); 968 } 969 970 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; 971 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, 972 "SCC", uap)) { 973 pmz_error("Unable to register zs interrupt handler.\n"); 974 pmz_set_scc_power(uap, 0); 975 mutex_unlock(&pmz_irq_mutex); 976 return -ENXIO; 977 } 978 979 mutex_unlock(&pmz_irq_mutex); 980 981 /* Right now, we deal with delay by blocking here, I'll be 982 * smarter later on 983 */ 984 if (pwr_delay != 0) { 985 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 986 msleep(pwr_delay); 987 } 988 989 /* IrDA reset is done now */ 990 if (ZS_IS_IRDA(uap)) 991 pmz_irda_reset(uap); 992 993 /* Enable interrupts emission from the chip */ 994 spin_lock_irqsave(&port->lock, flags); 995 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 996 if (!ZS_IS_EXTCLK(uap)) 997 uap->curregs[R1] |= EXT_INT_ENAB; 998 write_zsreg(uap, R1, uap->curregs[R1]); 999 spin_unlock_irqrestore(&port->lock, flags); 1000 1001 pmz_debug("pmz: startup() done.\n"); 1002 1003 return 0; 1004 } 1005 1006 static void pmz_shutdown(struct uart_port *port) 1007 { 1008 struct uart_pmac_port *uap = to_pmz(port); 1009 unsigned long flags; 1010 1011 pmz_debug("pmz: shutdown()\n"); 1012 1013 if (uap->node == NULL) 1014 return; 1015 1016 mutex_lock(&pmz_irq_mutex); 1017 1018 /* Release interrupt handler */ 1019 free_irq(uap->port.irq, uap); 1020 1021 spin_lock_irqsave(&port->lock, flags); 1022 1023 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 1024 1025 if (!ZS_IS_OPEN(uap->mate)) 1026 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; 1027 1028 /* Disable interrupts */ 1029 if (!ZS_IS_ASLEEP(uap)) { 1030 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1031 write_zsreg(uap, R1, uap->curregs[R1]); 1032 zssync(uap); 1033 } 1034 1035 if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) { 1036 spin_unlock_irqrestore(&port->lock, flags); 1037 mutex_unlock(&pmz_irq_mutex); 1038 return; 1039 } 1040 1041 /* Disable receiver and transmitter. */ 1042 uap->curregs[R3] &= ~RxENABLE; 1043 uap->curregs[R5] &= ~TxENABLE; 1044 1045 /* Disable all interrupts and BRK assertion. */ 1046 uap->curregs[R5] &= ~SND_BRK; 1047 pmz_maybe_update_regs(uap); 1048 1049 /* Shut the chip down */ 1050 pmz_set_scc_power(uap, 0); 1051 1052 spin_unlock_irqrestore(&port->lock, flags); 1053 1054 mutex_unlock(&pmz_irq_mutex); 1055 1056 pmz_debug("pmz: shutdown() done.\n"); 1057 } 1058 1059 /* Shared by TTY driver and serial console setup. The port lock is held 1060 * and local interrupts are disabled. 1061 */ 1062 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, 1063 unsigned int iflag, unsigned long baud) 1064 { 1065 int brg; 1066 1067 /* Switch to external clocking for IrDA high clock rates. That 1068 * code could be re-used for Midi interfaces with different 1069 * multipliers 1070 */ 1071 if (baud >= 115200 && ZS_IS_IRDA(uap)) { 1072 uap->curregs[R4] = X1CLK; 1073 uap->curregs[R11] = RCTRxCP | TCTRxCP; 1074 uap->curregs[R14] = 0; /* BRG off */ 1075 uap->curregs[R12] = 0; 1076 uap->curregs[R13] = 0; 1077 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; 1078 } else { 1079 switch (baud) { 1080 case ZS_CLOCK/16: /* 230400 */ 1081 uap->curregs[R4] = X16CLK; 1082 uap->curregs[R11] = 0; 1083 uap->curregs[R14] = 0; 1084 break; 1085 case ZS_CLOCK/32: /* 115200 */ 1086 uap->curregs[R4] = X32CLK; 1087 uap->curregs[R11] = 0; 1088 uap->curregs[R14] = 0; 1089 break; 1090 default: 1091 uap->curregs[R4] = X16CLK; 1092 uap->curregs[R11] = TCBR | RCBR; 1093 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); 1094 uap->curregs[R12] = (brg & 255); 1095 uap->curregs[R13] = ((brg >> 8) & 255); 1096 uap->curregs[R14] = BRENAB; 1097 } 1098 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; 1099 } 1100 1101 /* Character size, stop bits, and parity. */ 1102 uap->curregs[3] &= ~RxN_MASK; 1103 uap->curregs[5] &= ~TxN_MASK; 1104 1105 switch (cflag & CSIZE) { 1106 case CS5: 1107 uap->curregs[3] |= Rx5; 1108 uap->curregs[5] |= Tx5; 1109 uap->parity_mask = 0x1f; 1110 break; 1111 case CS6: 1112 uap->curregs[3] |= Rx6; 1113 uap->curregs[5] |= Tx6; 1114 uap->parity_mask = 0x3f; 1115 break; 1116 case CS7: 1117 uap->curregs[3] |= Rx7; 1118 uap->curregs[5] |= Tx7; 1119 uap->parity_mask = 0x7f; 1120 break; 1121 case CS8: 1122 default: 1123 uap->curregs[3] |= Rx8; 1124 uap->curregs[5] |= Tx8; 1125 uap->parity_mask = 0xff; 1126 break; 1127 }; 1128 uap->curregs[4] &= ~(SB_MASK); 1129 if (cflag & CSTOPB) 1130 uap->curregs[4] |= SB2; 1131 else 1132 uap->curregs[4] |= SB1; 1133 if (cflag & PARENB) 1134 uap->curregs[4] |= PAR_ENAB; 1135 else 1136 uap->curregs[4] &= ~PAR_ENAB; 1137 if (!(cflag & PARODD)) 1138 uap->curregs[4] |= PAR_EVEN; 1139 else 1140 uap->curregs[4] &= ~PAR_EVEN; 1141 1142 uap->port.read_status_mask = Rx_OVR; 1143 if (iflag & INPCK) 1144 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; 1145 if (iflag & (BRKINT | PARMRK)) 1146 uap->port.read_status_mask |= BRK_ABRT; 1147 1148 uap->port.ignore_status_mask = 0; 1149 if (iflag & IGNPAR) 1150 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 1151 if (iflag & IGNBRK) { 1152 uap->port.ignore_status_mask |= BRK_ABRT; 1153 if (iflag & IGNPAR) 1154 uap->port.ignore_status_mask |= Rx_OVR; 1155 } 1156 1157 if ((cflag & CREAD) == 0) 1158 uap->port.ignore_status_mask = 0xff; 1159 } 1160 1161 1162 /* 1163 * Set the irda codec on the imac to the specified baud rate. 1164 */ 1165 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) 1166 { 1167 u8 cmdbyte; 1168 int t, version; 1169 1170 switch (*baud) { 1171 /* SIR modes */ 1172 case 2400: 1173 cmdbyte = 0x53; 1174 break; 1175 case 4800: 1176 cmdbyte = 0x52; 1177 break; 1178 case 9600: 1179 cmdbyte = 0x51; 1180 break; 1181 case 19200: 1182 cmdbyte = 0x50; 1183 break; 1184 case 38400: 1185 cmdbyte = 0x4f; 1186 break; 1187 case 57600: 1188 cmdbyte = 0x4e; 1189 break; 1190 case 115200: 1191 cmdbyte = 0x4d; 1192 break; 1193 /* The FIR modes aren't really supported at this point, how 1194 * do we select the speed ? via the FCR on KeyLargo ? 1195 */ 1196 case 1152000: 1197 cmdbyte = 0; 1198 break; 1199 case 4000000: 1200 cmdbyte = 0; 1201 break; 1202 default: /* 9600 */ 1203 cmdbyte = 0x51; 1204 *baud = 9600; 1205 break; 1206 } 1207 1208 /* Wait for transmitter to drain */ 1209 t = 10000; 1210 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 1211 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { 1212 if (--t <= 0) { 1213 pmz_error("transmitter didn't drain\n"); 1214 return; 1215 } 1216 udelay(10); 1217 } 1218 1219 /* Drain the receiver too */ 1220 t = 100; 1221 (void)read_zsdata(uap); 1222 (void)read_zsdata(uap); 1223 (void)read_zsdata(uap); 1224 mdelay(10); 1225 while (read_zsreg(uap, R0) & Rx_CH_AV) { 1226 read_zsdata(uap); 1227 mdelay(10); 1228 if (--t <= 0) { 1229 pmz_error("receiver didn't drain\n"); 1230 return; 1231 } 1232 } 1233 1234 /* Switch to command mode */ 1235 uap->curregs[R5] |= DTR; 1236 write_zsreg(uap, R5, uap->curregs[R5]); 1237 zssync(uap); 1238 mdelay(1); 1239 1240 /* Switch SCC to 19200 */ 1241 pmz_convert_to_zs(uap, CS8, 0, 19200); 1242 pmz_load_zsregs(uap, uap->curregs); 1243 mdelay(1); 1244 1245 /* Write get_version command byte */ 1246 write_zsdata(uap, 1); 1247 t = 5000; 1248 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1249 if (--t <= 0) { 1250 pmz_error("irda_setup timed out on get_version byte\n"); 1251 goto out; 1252 } 1253 udelay(10); 1254 } 1255 version = read_zsdata(uap); 1256 1257 if (version < 4) { 1258 pmz_info("IrDA: dongle version %d not supported\n", version); 1259 goto out; 1260 } 1261 1262 /* Send speed mode */ 1263 write_zsdata(uap, cmdbyte); 1264 t = 5000; 1265 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1266 if (--t <= 0) { 1267 pmz_error("irda_setup timed out on speed mode byte\n"); 1268 goto out; 1269 } 1270 udelay(10); 1271 } 1272 t = read_zsdata(uap); 1273 if (t != cmdbyte) 1274 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); 1275 1276 pmz_info("IrDA setup for %ld bps, dongle version: %d\n", 1277 *baud, version); 1278 1279 (void)read_zsdata(uap); 1280 (void)read_zsdata(uap); 1281 (void)read_zsdata(uap); 1282 1283 out: 1284 /* Switch back to data mode */ 1285 uap->curregs[R5] &= ~DTR; 1286 write_zsreg(uap, R5, uap->curregs[R5]); 1287 zssync(uap); 1288 1289 (void)read_zsdata(uap); 1290 (void)read_zsdata(uap); 1291 (void)read_zsdata(uap); 1292 } 1293 1294 1295 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1296 struct ktermios *old) 1297 { 1298 struct uart_pmac_port *uap = to_pmz(port); 1299 unsigned long baud; 1300 1301 pmz_debug("pmz: set_termios()\n"); 1302 1303 if (ZS_IS_ASLEEP(uap)) 1304 return; 1305 1306 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); 1307 1308 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds 1309 * on the IR dongle. Note that the IRTTY driver currently doesn't know 1310 * about the FIR mode and high speed modes. So these are unused. For 1311 * implementing proper support for these, we should probably add some 1312 * DMA as well, at least on the Rx side, which isn't a simple thing 1313 * at this point. 1314 */ 1315 if (ZS_IS_IRDA(uap)) { 1316 /* Calc baud rate */ 1317 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); 1318 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); 1319 /* Cet the irda codec to the right rate */ 1320 pmz_irda_setup(uap, &baud); 1321 /* Set final baud rate */ 1322 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1323 pmz_load_zsregs(uap, uap->curregs); 1324 zssync(uap); 1325 } else { 1326 baud = uart_get_baud_rate(port, termios, old, 1200, 230400); 1327 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1328 /* Make sure modem status interrupts are correctly configured */ 1329 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { 1330 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; 1331 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; 1332 } else { 1333 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); 1334 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; 1335 } 1336 1337 /* Load registers to the chip */ 1338 pmz_maybe_update_regs(uap); 1339 } 1340 uart_update_timeout(port, termios->c_cflag, baud); 1341 1342 pmz_debug("pmz: set_termios() done.\n"); 1343 } 1344 1345 /* The port lock is not held. */ 1346 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1347 struct ktermios *old) 1348 { 1349 struct uart_pmac_port *uap = to_pmz(port); 1350 unsigned long flags; 1351 1352 spin_lock_irqsave(&port->lock, flags); 1353 1354 /* Disable IRQs on the port */ 1355 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1356 write_zsreg(uap, R1, uap->curregs[R1]); 1357 1358 /* Setup new port configuration */ 1359 __pmz_set_termios(port, termios, old); 1360 1361 /* Re-enable IRQs on the port */ 1362 if (ZS_IS_OPEN(uap)) { 1363 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 1364 if (!ZS_IS_EXTCLK(uap)) 1365 uap->curregs[R1] |= EXT_INT_ENAB; 1366 write_zsreg(uap, R1, uap->curregs[R1]); 1367 } 1368 spin_unlock_irqrestore(&port->lock, flags); 1369 } 1370 1371 static const char *pmz_type(struct uart_port *port) 1372 { 1373 struct uart_pmac_port *uap = to_pmz(port); 1374 1375 if (ZS_IS_IRDA(uap)) 1376 return "Z85c30 ESCC - Infrared port"; 1377 else if (ZS_IS_INTMODEM(uap)) 1378 return "Z85c30 ESCC - Internal modem"; 1379 return "Z85c30 ESCC - Serial port"; 1380 } 1381 1382 /* We do not request/release mappings of the registers here, this 1383 * happens at early serial probe time. 1384 */ 1385 static void pmz_release_port(struct uart_port *port) 1386 { 1387 } 1388 1389 static int pmz_request_port(struct uart_port *port) 1390 { 1391 return 0; 1392 } 1393 1394 /* These do not need to do anything interesting either. */ 1395 static void pmz_config_port(struct uart_port *port, int flags) 1396 { 1397 } 1398 1399 /* We do not support letting the user mess with the divisor, IRQ, etc. */ 1400 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) 1401 { 1402 return -EINVAL; 1403 } 1404 1405 #ifdef CONFIG_CONSOLE_POLL 1406 1407 static int pmz_poll_get_char(struct uart_port *port) 1408 { 1409 struct uart_pmac_port *uap = (struct uart_pmac_port *)port; 1410 1411 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) 1412 udelay(5); 1413 return read_zsdata(uap); 1414 } 1415 1416 static void pmz_poll_put_char(struct uart_port *port, unsigned char c) 1417 { 1418 struct uart_pmac_port *uap = (struct uart_pmac_port *)port; 1419 1420 /* Wait for the transmit buffer to empty. */ 1421 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1422 udelay(5); 1423 write_zsdata(uap, c); 1424 } 1425 1426 #endif /* CONFIG_CONSOLE_POLL */ 1427 1428 static struct uart_ops pmz_pops = { 1429 .tx_empty = pmz_tx_empty, 1430 .set_mctrl = pmz_set_mctrl, 1431 .get_mctrl = pmz_get_mctrl, 1432 .stop_tx = pmz_stop_tx, 1433 .start_tx = pmz_start_tx, 1434 .stop_rx = pmz_stop_rx, 1435 .enable_ms = pmz_enable_ms, 1436 .break_ctl = pmz_break_ctl, 1437 .startup = pmz_startup, 1438 .shutdown = pmz_shutdown, 1439 .set_termios = pmz_set_termios, 1440 .type = pmz_type, 1441 .release_port = pmz_release_port, 1442 .request_port = pmz_request_port, 1443 .config_port = pmz_config_port, 1444 .verify_port = pmz_verify_port, 1445 #ifdef CONFIG_CONSOLE_POLL 1446 .poll_get_char = pmz_poll_get_char, 1447 .poll_put_char = pmz_poll_put_char, 1448 #endif 1449 }; 1450 1451 #ifdef CONFIG_PPC_PMAC 1452 1453 /* 1454 * Setup one port structure after probing, HW is down at this point, 1455 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't 1456 * register our console before uart_add_one_port() is called 1457 */ 1458 static int __init pmz_init_port(struct uart_pmac_port *uap) 1459 { 1460 struct device_node *np = uap->node; 1461 const char *conn; 1462 const struct slot_names_prop { 1463 int count; 1464 char name[1]; 1465 } *slots; 1466 int len; 1467 struct resource r_ports, r_rxdma, r_txdma; 1468 1469 /* 1470 * Request & map chip registers 1471 */ 1472 if (of_address_to_resource(np, 0, &r_ports)) 1473 return -ENODEV; 1474 uap->port.mapbase = r_ports.start; 1475 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); 1476 1477 uap->control_reg = uap->port.membase; 1478 uap->data_reg = uap->control_reg + 0x10; 1479 1480 /* 1481 * Request & map DBDMA registers 1482 */ 1483 #ifdef HAS_DBDMA 1484 if (of_address_to_resource(np, 1, &r_txdma) == 0 && 1485 of_address_to_resource(np, 2, &r_rxdma) == 0) 1486 uap->flags |= PMACZILOG_FLAG_HAS_DMA; 1487 #else 1488 memset(&r_txdma, 0, sizeof(struct resource)); 1489 memset(&r_rxdma, 0, sizeof(struct resource)); 1490 #endif 1491 if (ZS_HAS_DMA(uap)) { 1492 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); 1493 if (uap->tx_dma_regs == NULL) { 1494 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1495 goto no_dma; 1496 } 1497 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); 1498 if (uap->rx_dma_regs == NULL) { 1499 iounmap(uap->tx_dma_regs); 1500 uap->tx_dma_regs = NULL; 1501 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1502 goto no_dma; 1503 } 1504 uap->tx_dma_irq = irq_of_parse_and_map(np, 1); 1505 uap->rx_dma_irq = irq_of_parse_and_map(np, 2); 1506 } 1507 no_dma: 1508 1509 /* 1510 * Detect port type 1511 */ 1512 if (of_device_is_compatible(np, "cobalt")) 1513 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1514 conn = of_get_property(np, "AAPL,connector", &len); 1515 if (conn && (strcmp(conn, "infrared") == 0)) 1516 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1517 uap->port_type = PMAC_SCC_ASYNC; 1518 /* 1999 Powerbook G3 has slot-names property instead */ 1519 slots = of_get_property(np, "slot-names", &len); 1520 if (slots && slots->count > 0) { 1521 if (strcmp(slots->name, "IrDA") == 0) 1522 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1523 else if (strcmp(slots->name, "Modem") == 0) 1524 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1525 } 1526 if (ZS_IS_IRDA(uap)) 1527 uap->port_type = PMAC_SCC_IRDA; 1528 if (ZS_IS_INTMODEM(uap)) { 1529 struct device_node* i2c_modem = 1530 of_find_node_by_name(NULL, "i2c-modem"); 1531 if (i2c_modem) { 1532 const char* mid = 1533 of_get_property(i2c_modem, "modem-id", NULL); 1534 if (mid) switch(*mid) { 1535 case 0x04 : 1536 case 0x05 : 1537 case 0x07 : 1538 case 0x08 : 1539 case 0x0b : 1540 case 0x0c : 1541 uap->port_type = PMAC_SCC_I2S1; 1542 } 1543 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", 1544 mid ? (*mid) : 0); 1545 of_node_put(i2c_modem); 1546 } else { 1547 printk(KERN_INFO "pmac_zilog: serial modem detected\n"); 1548 } 1549 } 1550 1551 /* 1552 * Init remaining bits of "port" structure 1553 */ 1554 uap->port.iotype = UPIO_MEM; 1555 uap->port.irq = irq_of_parse_and_map(np, 0); 1556 uap->port.uartclk = ZS_CLOCK; 1557 uap->port.fifosize = 1; 1558 uap->port.ops = &pmz_pops; 1559 uap->port.type = PORT_PMAC_ZILOG; 1560 uap->port.flags = 0; 1561 1562 /* 1563 * Fixup for the port on Gatwick for which the device-tree has 1564 * missing interrupts. Normally, the macio_dev would contain 1565 * fixed up interrupt info, but we use the device-tree directly 1566 * here due to early probing so we need the fixup too. 1567 */ 1568 if (uap->port.irq == NO_IRQ && 1569 np->parent && np->parent->parent && 1570 of_device_is_compatible(np->parent->parent, "gatwick")) { 1571 /* IRQs on gatwick are offset by 64 */ 1572 uap->port.irq = irq_create_mapping(NULL, 64 + 15); 1573 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); 1574 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); 1575 } 1576 1577 /* Setup some valid baud rate information in the register 1578 * shadows so we don't write crap there before baud rate is 1579 * first initialized. 1580 */ 1581 pmz_convert_to_zs(uap, CS8, 0, 9600); 1582 1583 return 0; 1584 } 1585 1586 /* 1587 * Get rid of a port on module removal 1588 */ 1589 static void pmz_dispose_port(struct uart_pmac_port *uap) 1590 { 1591 struct device_node *np; 1592 1593 np = uap->node; 1594 iounmap(uap->rx_dma_regs); 1595 iounmap(uap->tx_dma_regs); 1596 iounmap(uap->control_reg); 1597 uap->node = NULL; 1598 of_node_put(np); 1599 memset(uap, 0, sizeof(struct uart_pmac_port)); 1600 } 1601 1602 /* 1603 * Called upon match with an escc node in the device-tree. 1604 */ 1605 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) 1606 { 1607 int i; 1608 1609 /* Iterate the pmz_ports array to find a matching entry 1610 */ 1611 for (i = 0; i < MAX_ZS_PORTS; i++) 1612 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) { 1613 struct uart_pmac_port *uap = &pmz_ports[i]; 1614 1615 uap->dev = mdev; 1616 dev_set_drvdata(&mdev->ofdev.dev, uap); 1617 if (macio_request_resources(uap->dev, "pmac_zilog")) 1618 printk(KERN_WARNING "%s: Failed to request resource" 1619 ", port still active\n", 1620 uap->node->name); 1621 else 1622 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; 1623 return 0; 1624 } 1625 return -ENODEV; 1626 } 1627 1628 /* 1629 * That one should not be called, macio isn't really a hotswap device, 1630 * we don't expect one of those serial ports to go away... 1631 */ 1632 static int pmz_detach(struct macio_dev *mdev) 1633 { 1634 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1635 1636 if (!uap) 1637 return -ENODEV; 1638 1639 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { 1640 macio_release_resources(uap->dev); 1641 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; 1642 } 1643 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1644 uap->dev = NULL; 1645 1646 return 0; 1647 } 1648 1649 1650 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) 1651 { 1652 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1653 struct uart_state *state; 1654 unsigned long flags; 1655 1656 if (uap == NULL) { 1657 printk("HRM... pmz_suspend with NULL uap\n"); 1658 return 0; 1659 } 1660 1661 if (pm_state.event == mdev->ofdev.dev.power.power_state.event) 1662 return 0; 1663 1664 pmz_debug("suspend, switching to state %d\n", pm_state.event); 1665 1666 state = pmz_uart_reg.state + uap->port.line; 1667 1668 mutex_lock(&pmz_irq_mutex); 1669 mutex_lock(&state->port.mutex); 1670 1671 spin_lock_irqsave(&uap->port.lock, flags); 1672 1673 if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) { 1674 /* Disable receiver and transmitter. */ 1675 uap->curregs[R3] &= ~RxENABLE; 1676 uap->curregs[R5] &= ~TxENABLE; 1677 1678 /* Disable all interrupts and BRK assertion. */ 1679 uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 1680 uap->curregs[R5] &= ~SND_BRK; 1681 pmz_load_zsregs(uap, uap->curregs); 1682 uap->flags |= PMACZILOG_FLAG_IS_ASLEEP; 1683 mb(); 1684 } 1685 1686 spin_unlock_irqrestore(&uap->port.lock, flags); 1687 1688 if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate)) 1689 if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { 1690 pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; 1691 disable_irq(uap->port.irq); 1692 } 1693 1694 if (ZS_IS_CONS(uap)) 1695 uap->port.cons->flags &= ~CON_ENABLED; 1696 1697 /* Shut the chip down */ 1698 pmz_set_scc_power(uap, 0); 1699 1700 mutex_unlock(&state->port.mutex); 1701 mutex_unlock(&pmz_irq_mutex); 1702 1703 pmz_debug("suspend, switching complete\n"); 1704 1705 mdev->ofdev.dev.power.power_state = pm_state; 1706 1707 return 0; 1708 } 1709 1710 1711 static int pmz_resume(struct macio_dev *mdev) 1712 { 1713 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1714 struct uart_state *state; 1715 unsigned long flags; 1716 int pwr_delay = 0; 1717 1718 if (uap == NULL) 1719 return 0; 1720 1721 if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON) 1722 return 0; 1723 1724 pmz_debug("resume, switching to state 0\n"); 1725 1726 state = pmz_uart_reg.state + uap->port.line; 1727 1728 mutex_lock(&pmz_irq_mutex); 1729 mutex_lock(&state->port.mutex); 1730 1731 spin_lock_irqsave(&uap->port.lock, flags); 1732 if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) { 1733 spin_unlock_irqrestore(&uap->port.lock, flags); 1734 goto bail; 1735 } 1736 pwr_delay = __pmz_startup(uap); 1737 1738 /* Take care of config that may have changed while asleep */ 1739 __pmz_set_termios(&uap->port, &uap->termios_cache, NULL); 1740 1741 if (ZS_IS_OPEN(uap)) { 1742 /* Enable interrupts */ 1743 uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; 1744 if (!ZS_IS_EXTCLK(uap)) 1745 uap->curregs[R1] |= EXT_INT_ENAB; 1746 write_zsreg(uap, R1, uap->curregs[R1]); 1747 } 1748 1749 spin_unlock_irqrestore(&uap->port.lock, flags); 1750 1751 if (ZS_IS_CONS(uap)) 1752 uap->port.cons->flags |= CON_ENABLED; 1753 1754 /* Re-enable IRQ on the controller */ 1755 if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { 1756 pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; 1757 enable_irq(uap->port.irq); 1758 } 1759 1760 bail: 1761 mutex_unlock(&state->port.mutex); 1762 mutex_unlock(&pmz_irq_mutex); 1763 1764 /* Right now, we deal with delay by blocking here, I'll be 1765 * smarter later on 1766 */ 1767 if (pwr_delay != 0) { 1768 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 1769 msleep(pwr_delay); 1770 } 1771 1772 pmz_debug("resume, switching complete\n"); 1773 1774 mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON; 1775 1776 return 0; 1777 } 1778 1779 /* 1780 * Probe all ports in the system and build the ports array, we register 1781 * with the serial layer at this point, the macio-type probing is only 1782 * used later to "attach" to the sysfs tree so we get power management 1783 * events 1784 */ 1785 static int __init pmz_probe(void) 1786 { 1787 struct device_node *node_p, *node_a, *node_b, *np; 1788 int count = 0; 1789 int rc; 1790 1791 /* 1792 * Find all escc chips in the system 1793 */ 1794 node_p = of_find_node_by_name(NULL, "escc"); 1795 while (node_p) { 1796 /* 1797 * First get channel A/B node pointers 1798 * 1799 * TODO: Add routines with proper locking to do that... 1800 */ 1801 node_a = node_b = NULL; 1802 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { 1803 if (strncmp(np->name, "ch-a", 4) == 0) 1804 node_a = of_node_get(np); 1805 else if (strncmp(np->name, "ch-b", 4) == 0) 1806 node_b = of_node_get(np); 1807 } 1808 if (!node_a && !node_b) { 1809 of_node_put(node_a); 1810 of_node_put(node_b); 1811 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n", 1812 (!node_a) ? 'a' : 'b', node_p->full_name); 1813 goto next; 1814 } 1815 1816 /* 1817 * Fill basic fields in the port structures 1818 */ 1819 pmz_ports[count].mate = &pmz_ports[count+1]; 1820 pmz_ports[count+1].mate = &pmz_ports[count]; 1821 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1822 pmz_ports[count].node = node_a; 1823 pmz_ports[count+1].node = node_b; 1824 pmz_ports[count].port.line = count; 1825 pmz_ports[count+1].port.line = count+1; 1826 1827 /* 1828 * Setup the ports for real 1829 */ 1830 rc = pmz_init_port(&pmz_ports[count]); 1831 if (rc == 0 && node_b != NULL) 1832 rc = pmz_init_port(&pmz_ports[count+1]); 1833 if (rc != 0) { 1834 of_node_put(node_a); 1835 of_node_put(node_b); 1836 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); 1837 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); 1838 goto next; 1839 } 1840 count += 2; 1841 next: 1842 node_p = of_find_node_by_name(node_p, "escc"); 1843 } 1844 pmz_ports_count = count; 1845 1846 return 0; 1847 } 1848 1849 #else 1850 1851 extern struct platform_device scc_a_pdev, scc_b_pdev; 1852 1853 static int __init pmz_init_port(struct uart_pmac_port *uap) 1854 { 1855 struct resource *r_ports; 1856 int irq; 1857 1858 r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0); 1859 irq = platform_get_irq(uap->node, 0); 1860 if (!r_ports || !irq) 1861 return -ENODEV; 1862 1863 uap->port.mapbase = r_ports->start; 1864 uap->port.membase = (unsigned char __iomem *) r_ports->start; 1865 uap->port.iotype = UPIO_MEM; 1866 uap->port.irq = irq; 1867 uap->port.uartclk = ZS_CLOCK; 1868 uap->port.fifosize = 1; 1869 uap->port.ops = &pmz_pops; 1870 uap->port.type = PORT_PMAC_ZILOG; 1871 uap->port.flags = 0; 1872 1873 uap->control_reg = uap->port.membase; 1874 uap->data_reg = uap->control_reg + 4; 1875 uap->port_type = 0; 1876 1877 pmz_convert_to_zs(uap, CS8, 0, 9600); 1878 1879 return 0; 1880 } 1881 1882 static int __init pmz_probe(void) 1883 { 1884 int err; 1885 1886 pmz_ports_count = 0; 1887 1888 pmz_ports[0].mate = &pmz_ports[1]; 1889 pmz_ports[0].port.line = 0; 1890 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1891 pmz_ports[0].node = &scc_a_pdev; 1892 err = pmz_init_port(&pmz_ports[0]); 1893 if (err) 1894 return err; 1895 pmz_ports_count++; 1896 1897 pmz_ports[1].mate = &pmz_ports[0]; 1898 pmz_ports[1].port.line = 1; 1899 pmz_ports[1].flags = 0; 1900 pmz_ports[1].node = &scc_b_pdev; 1901 err = pmz_init_port(&pmz_ports[1]); 1902 if (err) 1903 return err; 1904 pmz_ports_count++; 1905 1906 return 0; 1907 } 1908 1909 static void pmz_dispose_port(struct uart_pmac_port *uap) 1910 { 1911 memset(uap, 0, sizeof(struct uart_pmac_port)); 1912 } 1913 1914 static int __init pmz_attach(struct platform_device *pdev) 1915 { 1916 int i; 1917 1918 for (i = 0; i < pmz_ports_count; i++) 1919 if (pmz_ports[i].node == pdev) 1920 return 0; 1921 return -ENODEV; 1922 } 1923 1924 static int __exit pmz_detach(struct platform_device *pdev) 1925 { 1926 return 0; 1927 } 1928 1929 #endif /* !CONFIG_PPC_PMAC */ 1930 1931 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1932 1933 static void pmz_console_write(struct console *con, const char *s, unsigned int count); 1934 static int __init pmz_console_setup(struct console *co, char *options); 1935 1936 static struct console pmz_console = { 1937 .name = PMACZILOG_NAME, 1938 .write = pmz_console_write, 1939 .device = uart_console_device, 1940 .setup = pmz_console_setup, 1941 .flags = CON_PRINTBUFFER, 1942 .index = -1, 1943 .data = &pmz_uart_reg, 1944 }; 1945 1946 #define PMACZILOG_CONSOLE &pmz_console 1947 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1948 #define PMACZILOG_CONSOLE (NULL) 1949 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1950 1951 /* 1952 * Register the driver, console driver and ports with the serial 1953 * core 1954 */ 1955 static int __init pmz_register(void) 1956 { 1957 int i, rc; 1958 1959 pmz_uart_reg.nr = pmz_ports_count; 1960 pmz_uart_reg.cons = PMACZILOG_CONSOLE; 1961 1962 /* 1963 * Register this driver with the serial core 1964 */ 1965 rc = uart_register_driver(&pmz_uart_reg); 1966 if (rc) 1967 return rc; 1968 1969 /* 1970 * Register each port with the serial core 1971 */ 1972 for (i = 0; i < pmz_ports_count; i++) { 1973 struct uart_pmac_port *uport = &pmz_ports[i]; 1974 /* NULL node may happen on wallstreet */ 1975 if (uport->node != NULL) 1976 rc = uart_add_one_port(&pmz_uart_reg, &uport->port); 1977 if (rc) 1978 goto err_out; 1979 } 1980 1981 return 0; 1982 err_out: 1983 while (i-- > 0) { 1984 struct uart_pmac_port *uport = &pmz_ports[i]; 1985 uart_remove_one_port(&pmz_uart_reg, &uport->port); 1986 } 1987 uart_unregister_driver(&pmz_uart_reg); 1988 return rc; 1989 } 1990 1991 #ifdef CONFIG_PPC_PMAC 1992 1993 static struct of_device_id pmz_match[] = 1994 { 1995 { 1996 .name = "ch-a", 1997 }, 1998 { 1999 .name = "ch-b", 2000 }, 2001 {}, 2002 }; 2003 MODULE_DEVICE_TABLE (of, pmz_match); 2004 2005 static struct macio_driver pmz_driver = { 2006 .driver = { 2007 .name = "pmac_zilog", 2008 .owner = THIS_MODULE, 2009 .of_match_table = pmz_match, 2010 }, 2011 .probe = pmz_attach, 2012 .remove = pmz_detach, 2013 .suspend = pmz_suspend, 2014 .resume = pmz_resume, 2015 }; 2016 2017 #else 2018 2019 static struct platform_driver pmz_driver = { 2020 .remove = __exit_p(pmz_detach), 2021 .driver = { 2022 .name = "scc", 2023 .owner = THIS_MODULE, 2024 }, 2025 }; 2026 2027 #endif /* !CONFIG_PPC_PMAC */ 2028 2029 static int __init init_pmz(void) 2030 { 2031 int rc, i; 2032 printk(KERN_INFO "%s\n", version); 2033 2034 /* 2035 * First, we need to do a direct OF-based probe pass. We 2036 * do that because we want serial console up before the 2037 * macio stuffs calls us back, and since that makes it 2038 * easier to pass the proper number of channels to 2039 * uart_register_driver() 2040 */ 2041 if (pmz_ports_count == 0) 2042 pmz_probe(); 2043 2044 /* 2045 * Bail early if no port found 2046 */ 2047 if (pmz_ports_count == 0) 2048 return -ENODEV; 2049 2050 /* 2051 * Now we register with the serial layer 2052 */ 2053 rc = pmz_register(); 2054 if (rc) { 2055 printk(KERN_ERR 2056 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" 2057 "pmac_zilog: Did another serial driver already claim the minors?\n"); 2058 /* effectively "pmz_unprobe()" */ 2059 for (i=0; i < pmz_ports_count; i++) 2060 pmz_dispose_port(&pmz_ports[i]); 2061 return rc; 2062 } 2063 2064 /* 2065 * Then we register the macio driver itself 2066 */ 2067 #ifdef CONFIG_PPC_PMAC 2068 return macio_register_driver(&pmz_driver); 2069 #else 2070 return platform_driver_probe(&pmz_driver, pmz_attach); 2071 #endif 2072 } 2073 2074 static void __exit exit_pmz(void) 2075 { 2076 int i; 2077 2078 #ifdef CONFIG_PPC_PMAC 2079 /* Get rid of macio-driver (detach from macio) */ 2080 macio_unregister_driver(&pmz_driver); 2081 #else 2082 platform_driver_unregister(&pmz_driver); 2083 #endif 2084 2085 for (i = 0; i < pmz_ports_count; i++) { 2086 struct uart_pmac_port *uport = &pmz_ports[i]; 2087 if (uport->node != NULL) { 2088 uart_remove_one_port(&pmz_uart_reg, &uport->port); 2089 pmz_dispose_port(uport); 2090 } 2091 } 2092 /* Unregister UART driver */ 2093 uart_unregister_driver(&pmz_uart_reg); 2094 } 2095 2096 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 2097 2098 static void pmz_console_putchar(struct uart_port *port, int ch) 2099 { 2100 struct uart_pmac_port *uap = (struct uart_pmac_port *)port; 2101 2102 /* Wait for the transmit buffer to empty. */ 2103 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 2104 udelay(5); 2105 write_zsdata(uap, ch); 2106 } 2107 2108 /* 2109 * Print a string to the serial port trying not to disturb 2110 * any possible real use of the port... 2111 */ 2112 static void pmz_console_write(struct console *con, const char *s, unsigned int count) 2113 { 2114 struct uart_pmac_port *uap = &pmz_ports[con->index]; 2115 unsigned long flags; 2116 2117 if (ZS_IS_ASLEEP(uap)) 2118 return; 2119 spin_lock_irqsave(&uap->port.lock, flags); 2120 2121 /* Turn of interrupts and enable the transmitter. */ 2122 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); 2123 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); 2124 2125 uart_console_write(&uap->port, s, count, pmz_console_putchar); 2126 2127 /* Restore the values in the registers. */ 2128 write_zsreg(uap, R1, uap->curregs[1]); 2129 /* Don't disable the transmitter. */ 2130 2131 spin_unlock_irqrestore(&uap->port.lock, flags); 2132 } 2133 2134 /* 2135 * Setup the serial console 2136 */ 2137 static int __init pmz_console_setup(struct console *co, char *options) 2138 { 2139 struct uart_pmac_port *uap; 2140 struct uart_port *port; 2141 int baud = 38400; 2142 int bits = 8; 2143 int parity = 'n'; 2144 int flow = 'n'; 2145 unsigned long pwr_delay; 2146 2147 /* 2148 * XServe's default to 57600 bps 2149 */ 2150 if (of_machine_is_compatible("RackMac1,1") 2151 || of_machine_is_compatible("RackMac1,2") 2152 || of_machine_is_compatible("MacRISC4")) 2153 baud = 57600; 2154 2155 /* 2156 * Check whether an invalid uart number has been specified, and 2157 * if so, search for the first available port that does have 2158 * console support. 2159 */ 2160 if (co->index >= pmz_ports_count) 2161 co->index = 0; 2162 uap = &pmz_ports[co->index]; 2163 if (uap->node == NULL) 2164 return -ENODEV; 2165 port = &uap->port; 2166 2167 /* 2168 * Mark port as beeing a console 2169 */ 2170 uap->flags |= PMACZILOG_FLAG_IS_CONS; 2171 2172 /* 2173 * Temporary fix for uart layer who didn't setup the spinlock yet 2174 */ 2175 spin_lock_init(&port->lock); 2176 2177 /* 2178 * Enable the hardware 2179 */ 2180 pwr_delay = __pmz_startup(uap); 2181 if (pwr_delay) 2182 mdelay(pwr_delay); 2183 2184 if (options) 2185 uart_parse_options(options, &baud, &parity, &bits, &flow); 2186 2187 return uart_set_options(port, co, baud, parity, bits, flow); 2188 } 2189 2190 static int __init pmz_console_init(void) 2191 { 2192 /* Probe ports */ 2193 pmz_probe(); 2194 2195 /* TODO: Autoprobe console based on OF */ 2196 /* pmz_console.index = i; */ 2197 register_console(&pmz_console); 2198 2199 return 0; 2200 2201 } 2202 console_initcall(pmz_console_init); 2203 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 2204 2205 module_init(init_pmz); 2206 module_exit(exit_pmz); 2207