1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for PowerMac Z85c30 based ESCC cell found in the 4 * "macio" ASICs of various PowerMac models 5 * 6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) 7 * 8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras 9 * and drivers/serial/sunzilog.c by David S. Miller 10 * 11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and 12 * adapted special tweaks needed for us. I don't think it's worth 13 * merging back those though. The DMA code still has to get in 14 * and once done, I expect that driver to remain fairly stable in 15 * the long term, unless we change the driver model again... 16 * 17 * 2004-08-06 Harald Welte <laforge@gnumonks.org> 18 * - Enable BREAK interrupt 19 * - Add support for sysreq 20 * 21 * TODO: - Add DMA support 22 * - Defer port shutdown to a few seconds after close 23 * - maybe put something right into uap->clk_divisor 24 */ 25 26 #undef DEBUG 27 #undef USE_CTRL_O_SYSRQ 28 29 #include <linux/module.h> 30 #include <linux/tty.h> 31 32 #include <linux/tty_flip.h> 33 #include <linux/major.h> 34 #include <linux/string.h> 35 #include <linux/fcntl.h> 36 #include <linux/mm.h> 37 #include <linux/kernel.h> 38 #include <linux/delay.h> 39 #include <linux/init.h> 40 #include <linux/console.h> 41 #include <linux/adb.h> 42 #include <linux/pmu.h> 43 #include <linux/bitops.h> 44 #include <linux/sysrq.h> 45 #include <linux/mutex.h> 46 #include <linux/of_address.h> 47 #include <linux/of_irq.h> 48 #include <asm/sections.h> 49 #include <linux/io.h> 50 #include <asm/irq.h> 51 52 #ifdef CONFIG_PPC_PMAC 53 #include <asm/machdep.h> 54 #include <asm/pmac_feature.h> 55 #include <asm/dbdma.h> 56 #include <asm/macio.h> 57 #else 58 #include <linux/platform_device.h> 59 #define of_machine_is_compatible(x) (0) 60 #endif 61 62 #include <linux/serial.h> 63 #include <linux/serial_core.h> 64 65 #include "pmac_zilog.h" 66 67 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); 68 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports."); 69 MODULE_LICENSE("GPL"); 70 71 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS 72 #define PMACZILOG_MAJOR TTY_MAJOR 73 #define PMACZILOG_MINOR 64 74 #define PMACZILOG_NAME "ttyS" 75 #else 76 #define PMACZILOG_MAJOR 204 77 #define PMACZILOG_MINOR 192 78 #define PMACZILOG_NAME "ttyPZ" 79 #endif 80 81 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg) 82 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg) 83 #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg) 84 85 /* 86 * For the sake of early serial console, we can do a pre-probe 87 * (optional) of the ports at rather early boot time. 88 */ 89 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; 90 static int pmz_ports_count; 91 92 static struct uart_driver pmz_uart_reg = { 93 .owner = THIS_MODULE, 94 .driver_name = PMACZILOG_NAME, 95 .dev_name = PMACZILOG_NAME, 96 .major = PMACZILOG_MAJOR, 97 .minor = PMACZILOG_MINOR, 98 }; 99 100 101 /* 102 * Load all registers to reprogram the port 103 * This function must only be called when the TX is not busy. The UART 104 * port lock must be held and local interrupts disabled. 105 */ 106 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) 107 { 108 int i; 109 110 /* Let pending transmits finish. */ 111 for (i = 0; i < 1000; i++) { 112 unsigned char stat = read_zsreg(uap, R1); 113 if (stat & ALL_SNT) 114 break; 115 udelay(100); 116 } 117 118 ZS_CLEARERR(uap); 119 zssync(uap); 120 ZS_CLEARFIFO(uap); 121 zssync(uap); 122 ZS_CLEARERR(uap); 123 124 /* Disable all interrupts. */ 125 write_zsreg(uap, R1, 126 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 127 128 /* Set parity, sync config, stop bits, and clock divisor. */ 129 write_zsreg(uap, R4, regs[R4]); 130 131 /* Set misc. TX/RX control bits. */ 132 write_zsreg(uap, R10, regs[R10]); 133 134 /* Set TX/RX controls sans the enable bits. */ 135 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); 136 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); 137 138 /* now set R7 "prime" on ESCC */ 139 write_zsreg(uap, R15, regs[R15] | EN85C30); 140 write_zsreg(uap, R7, regs[R7P]); 141 142 /* make sure we use R7 "non-prime" on ESCC */ 143 write_zsreg(uap, R15, regs[R15] & ~EN85C30); 144 145 /* Synchronous mode config. */ 146 write_zsreg(uap, R6, regs[R6]); 147 write_zsreg(uap, R7, regs[R7]); 148 149 /* Disable baud generator. */ 150 write_zsreg(uap, R14, regs[R14] & ~BRENAB); 151 152 /* Clock mode control. */ 153 write_zsreg(uap, R11, regs[R11]); 154 155 /* Lower and upper byte of baud rate generator divisor. */ 156 write_zsreg(uap, R12, regs[R12]); 157 write_zsreg(uap, R13, regs[R13]); 158 159 /* Now rewrite R14, with BRENAB (if set). */ 160 write_zsreg(uap, R14, regs[R14]); 161 162 /* Reset external status interrupts. */ 163 write_zsreg(uap, R0, RES_EXT_INT); 164 write_zsreg(uap, R0, RES_EXT_INT); 165 166 /* Rewrite R3/R5, this time without enables masked. */ 167 write_zsreg(uap, R3, regs[R3]); 168 write_zsreg(uap, R5, regs[R5]); 169 170 /* Rewrite R1, this time without IRQ enabled masked. */ 171 write_zsreg(uap, R1, regs[R1]); 172 173 /* Enable interrupts */ 174 write_zsreg(uap, R9, regs[R9]); 175 } 176 177 /* 178 * We do like sunzilog to avoid disrupting pending Tx 179 * Reprogram the Zilog channel HW registers with the copies found in the 180 * software state struct. If the transmitter is busy, we defer this update 181 * until the next TX complete interrupt. Else, we do it right now. 182 * 183 * The UART port lock must be held and local interrupts disabled. 184 */ 185 static void pmz_maybe_update_regs(struct uart_pmac_port *uap) 186 { 187 if (!ZS_REGS_HELD(uap)) { 188 if (ZS_TX_ACTIVE(uap)) { 189 uap->flags |= PMACZILOG_FLAG_REGS_HELD; 190 } else { 191 pmz_debug("pmz: maybe_update_regs: updating\n"); 192 pmz_load_zsregs(uap, uap->curregs); 193 } 194 } 195 } 196 197 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable) 198 { 199 if (enable) { 200 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; 201 if (!ZS_IS_EXTCLK(uap)) 202 uap->curregs[1] |= EXT_INT_ENAB; 203 } else { 204 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 205 } 206 write_zsreg(uap, R1, uap->curregs[1]); 207 } 208 209 static bool pmz_receive_chars(struct uart_pmac_port *uap) 210 __must_hold(&uap->port.lock) 211 { 212 struct tty_port *port; 213 unsigned char ch, r1, drop, flag; 214 int loops = 0; 215 216 /* Sanity check, make sure the old bug is no longer happening */ 217 if (uap->port.state == NULL) { 218 WARN_ON(1); 219 (void)read_zsdata(uap); 220 return false; 221 } 222 port = &uap->port.state->port; 223 224 while (1) { 225 drop = 0; 226 227 r1 = read_zsreg(uap, R1); 228 ch = read_zsdata(uap); 229 230 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 231 write_zsreg(uap, R0, ERR_RES); 232 zssync(uap); 233 } 234 235 ch &= uap->parity_mask; 236 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { 237 uap->flags &= ~PMACZILOG_FLAG_BREAK; 238 } 239 240 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) 241 #ifdef USE_CTRL_O_SYSRQ 242 /* Handle the SysRq ^O Hack */ 243 if (ch == '\x0f') { 244 uap->port.sysrq = jiffies + HZ*5; 245 goto next_char; 246 } 247 #endif /* USE_CTRL_O_SYSRQ */ 248 if (uap->port.sysrq) { 249 int swallow; 250 spin_unlock(&uap->port.lock); 251 swallow = uart_handle_sysrq_char(&uap->port, ch); 252 spin_lock(&uap->port.lock); 253 if (swallow) 254 goto next_char; 255 } 256 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ 257 258 /* A real serial line, record the character and status. */ 259 if (drop) 260 goto next_char; 261 262 flag = TTY_NORMAL; 263 uap->port.icount.rx++; 264 265 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { 266 if (r1 & BRK_ABRT) { 267 pmz_debug("pmz: got break !\n"); 268 r1 &= ~(PAR_ERR | CRC_ERR); 269 uap->port.icount.brk++; 270 if (uart_handle_break(&uap->port)) 271 goto next_char; 272 } 273 else if (r1 & PAR_ERR) 274 uap->port.icount.parity++; 275 else if (r1 & CRC_ERR) 276 uap->port.icount.frame++; 277 if (r1 & Rx_OVR) 278 uap->port.icount.overrun++; 279 r1 &= uap->port.read_status_mask; 280 if (r1 & BRK_ABRT) 281 flag = TTY_BREAK; 282 else if (r1 & PAR_ERR) 283 flag = TTY_PARITY; 284 else if (r1 & CRC_ERR) 285 flag = TTY_FRAME; 286 } 287 288 if (uap->port.ignore_status_mask == 0xff || 289 (r1 & uap->port.ignore_status_mask) == 0) { 290 tty_insert_flip_char(port, ch, flag); 291 } 292 if (r1 & Rx_OVR) 293 tty_insert_flip_char(port, 0, TTY_OVERRUN); 294 next_char: 295 /* We can get stuck in an infinite loop getting char 0 when the 296 * line is in a wrong HW state, we break that here. 297 * When that happens, I disable the receive side of the driver. 298 * Note that what I've been experiencing is a real irq loop where 299 * I'm getting flooded regardless of the actual port speed. 300 * Something strange is going on with the HW 301 */ 302 if ((++loops) > 1000) 303 goto flood; 304 ch = read_zsreg(uap, R0); 305 if (!(ch & Rx_CH_AV)) 306 break; 307 } 308 309 return true; 310 flood: 311 pmz_interrupt_control(uap, 0); 312 pmz_error("pmz: rx irq flood !\n"); 313 return true; 314 } 315 316 static void pmz_status_handle(struct uart_pmac_port *uap) 317 { 318 unsigned char status; 319 320 status = read_zsreg(uap, R0); 321 write_zsreg(uap, R0, RES_EXT_INT); 322 zssync(uap); 323 324 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { 325 if (status & SYNC_HUNT) 326 uap->port.icount.dsr++; 327 328 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 329 * But it does not tell us which bit has changed, we have to keep 330 * track of this ourselves. 331 * The CTS input is inverted for some reason. -- paulus 332 */ 333 if ((status ^ uap->prev_status) & DCD) 334 uart_handle_dcd_change(&uap->port, 335 (status & DCD)); 336 if ((status ^ uap->prev_status) & CTS) 337 uart_handle_cts_change(&uap->port, 338 !(status & CTS)); 339 340 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 341 } 342 343 if (status & BRK_ABRT) 344 uap->flags |= PMACZILOG_FLAG_BREAK; 345 346 uap->prev_status = status; 347 } 348 349 static void pmz_transmit_chars(struct uart_pmac_port *uap) 350 { 351 struct circ_buf *xmit; 352 353 if (ZS_IS_CONS(uap)) { 354 unsigned char status = read_zsreg(uap, R0); 355 356 /* TX still busy? Just wait for the next TX done interrupt. 357 * 358 * It can occur because of how we do serial console writes. It would 359 * be nice to transmit console writes just like we normally would for 360 * a TTY line. (ie. buffered and TX interrupt driven). That is not 361 * easy because console writes cannot sleep. One solution might be 362 * to poll on enough port->xmit space becoming free. -DaveM 363 */ 364 if (!(status & Tx_BUF_EMP)) 365 return; 366 } 367 368 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; 369 370 if (ZS_REGS_HELD(uap)) { 371 pmz_load_zsregs(uap, uap->curregs); 372 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; 373 } 374 375 if (ZS_TX_STOPPED(uap)) { 376 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 377 goto ack_tx_int; 378 } 379 380 /* Under some circumstances, we see interrupts reported for 381 * a closed channel. The interrupt mask in R1 is clear, but 382 * R3 still signals the interrupts and we see them when taking 383 * an interrupt for the other channel (this could be a qemu 384 * bug but since the ESCC doc doesn't specify precsiely whether 385 * R3 interrup status bits are masked by R1 interrupt enable 386 * bits, better safe than sorry). --BenH. 387 */ 388 if (!ZS_IS_OPEN(uap)) 389 goto ack_tx_int; 390 391 if (uap->port.x_char) { 392 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 393 write_zsdata(uap, uap->port.x_char); 394 zssync(uap); 395 uap->port.icount.tx++; 396 uap->port.x_char = 0; 397 return; 398 } 399 400 if (uap->port.state == NULL) 401 goto ack_tx_int; 402 xmit = &uap->port.state->xmit; 403 if (uart_circ_empty(xmit)) { 404 uart_write_wakeup(&uap->port); 405 goto ack_tx_int; 406 } 407 if (uart_tx_stopped(&uap->port)) 408 goto ack_tx_int; 409 410 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 411 write_zsdata(uap, xmit->buf[xmit->tail]); 412 zssync(uap); 413 414 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 415 uap->port.icount.tx++; 416 417 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 418 uart_write_wakeup(&uap->port); 419 420 return; 421 422 ack_tx_int: 423 write_zsreg(uap, R0, RES_Tx_P); 424 zssync(uap); 425 } 426 427 /* Hrm... we register that twice, fixme later.... */ 428 static irqreturn_t pmz_interrupt(int irq, void *dev_id) 429 { 430 struct uart_pmac_port *uap = dev_id; 431 struct uart_pmac_port *uap_a; 432 struct uart_pmac_port *uap_b; 433 int rc = IRQ_NONE; 434 bool push; 435 u8 r3; 436 437 uap_a = pmz_get_port_A(uap); 438 uap_b = uap_a->mate; 439 440 spin_lock(&uap_a->port.lock); 441 r3 = read_zsreg(uap_a, R3); 442 443 /* Channel A */ 444 push = false; 445 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 446 if (!ZS_IS_OPEN(uap_a)) { 447 pmz_debug("ChanA interrupt while not open !\n"); 448 goto skip_a; 449 } 450 write_zsreg(uap_a, R0, RES_H_IUS); 451 zssync(uap_a); 452 if (r3 & CHAEXT) 453 pmz_status_handle(uap_a); 454 if (r3 & CHARxIP) 455 push = pmz_receive_chars(uap_a); 456 if (r3 & CHATxIP) 457 pmz_transmit_chars(uap_a); 458 rc = IRQ_HANDLED; 459 } 460 skip_a: 461 spin_unlock(&uap_a->port.lock); 462 if (push) 463 tty_flip_buffer_push(&uap->port.state->port); 464 465 if (!uap_b) 466 goto out; 467 468 spin_lock(&uap_b->port.lock); 469 push = false; 470 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 471 if (!ZS_IS_OPEN(uap_b)) { 472 pmz_debug("ChanB interrupt while not open !\n"); 473 goto skip_b; 474 } 475 write_zsreg(uap_b, R0, RES_H_IUS); 476 zssync(uap_b); 477 if (r3 & CHBEXT) 478 pmz_status_handle(uap_b); 479 if (r3 & CHBRxIP) 480 push = pmz_receive_chars(uap_b); 481 if (r3 & CHBTxIP) 482 pmz_transmit_chars(uap_b); 483 rc = IRQ_HANDLED; 484 } 485 skip_b: 486 spin_unlock(&uap_b->port.lock); 487 if (push) 488 tty_flip_buffer_push(&uap->port.state->port); 489 490 out: 491 return rc; 492 } 493 494 /* 495 * Peek the status register, lock not held by caller 496 */ 497 static inline u8 pmz_peek_status(struct uart_pmac_port *uap) 498 { 499 unsigned long flags; 500 u8 status; 501 502 spin_lock_irqsave(&uap->port.lock, flags); 503 status = read_zsreg(uap, R0); 504 spin_unlock_irqrestore(&uap->port.lock, flags); 505 506 return status; 507 } 508 509 /* 510 * Check if transmitter is empty 511 * The port lock is not held. 512 */ 513 static unsigned int pmz_tx_empty(struct uart_port *port) 514 { 515 unsigned char status; 516 517 status = pmz_peek_status(to_pmz(port)); 518 if (status & Tx_BUF_EMP) 519 return TIOCSER_TEMT; 520 return 0; 521 } 522 523 /* 524 * Set Modem Control (RTS & DTR) bits 525 * The port lock is held and interrupts are disabled. 526 * Note: Shall we really filter out RTS on external ports or 527 * should that be dealt at higher level only ? 528 */ 529 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) 530 { 531 struct uart_pmac_port *uap = to_pmz(port); 532 unsigned char set_bits, clear_bits; 533 534 /* Do nothing for irda for now... */ 535 if (ZS_IS_IRDA(uap)) 536 return; 537 /* We get called during boot with a port not up yet */ 538 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) 539 return; 540 541 set_bits = clear_bits = 0; 542 543 if (ZS_IS_INTMODEM(uap)) { 544 if (mctrl & TIOCM_RTS) 545 set_bits |= RTS; 546 else 547 clear_bits |= RTS; 548 } 549 if (mctrl & TIOCM_DTR) 550 set_bits |= DTR; 551 else 552 clear_bits |= DTR; 553 554 /* NOTE: Not subject to 'transmitter active' rule. */ 555 uap->curregs[R5] |= set_bits; 556 uap->curregs[R5] &= ~clear_bits; 557 558 write_zsreg(uap, R5, uap->curregs[R5]); 559 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", 560 set_bits, clear_bits, uap->curregs[R5]); 561 zssync(uap); 562 } 563 564 /* 565 * Get Modem Control bits (only the input ones, the core will 566 * or that with a cached value of the control ones) 567 * The port lock is held and interrupts are disabled. 568 */ 569 static unsigned int pmz_get_mctrl(struct uart_port *port) 570 { 571 struct uart_pmac_port *uap = to_pmz(port); 572 unsigned char status; 573 unsigned int ret; 574 575 status = read_zsreg(uap, R0); 576 577 ret = 0; 578 if (status & DCD) 579 ret |= TIOCM_CAR; 580 if (status & SYNC_HUNT) 581 ret |= TIOCM_DSR; 582 if (!(status & CTS)) 583 ret |= TIOCM_CTS; 584 585 return ret; 586 } 587 588 /* 589 * Stop TX side. Dealt like sunzilog at next Tx interrupt, 590 * though for DMA, we will have to do a bit more. 591 * The port lock is held and interrupts are disabled. 592 */ 593 static void pmz_stop_tx(struct uart_port *port) 594 { 595 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; 596 } 597 598 /* 599 * Kick the Tx side. 600 * The port lock is held and interrupts are disabled. 601 */ 602 static void pmz_start_tx(struct uart_port *port) 603 { 604 struct uart_pmac_port *uap = to_pmz(port); 605 unsigned char status; 606 607 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 608 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 609 610 status = read_zsreg(uap, R0); 611 612 /* TX busy? Just wait for the TX done interrupt. */ 613 if (!(status & Tx_BUF_EMP)) 614 return; 615 616 /* Send the first character to jump-start the TX done 617 * IRQ sending engine. 618 */ 619 if (port->x_char) { 620 write_zsdata(uap, port->x_char); 621 zssync(uap); 622 port->icount.tx++; 623 port->x_char = 0; 624 } else { 625 struct circ_buf *xmit = &port->state->xmit; 626 627 if (uart_circ_empty(xmit)) 628 return; 629 write_zsdata(uap, xmit->buf[xmit->tail]); 630 zssync(uap); 631 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 632 port->icount.tx++; 633 634 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 635 uart_write_wakeup(&uap->port); 636 } 637 } 638 639 /* 640 * Stop Rx side, basically disable emitting of 641 * Rx interrupts on the port. We don't disable the rx 642 * side of the chip proper though 643 * The port lock is held. 644 */ 645 static void pmz_stop_rx(struct uart_port *port) 646 { 647 struct uart_pmac_port *uap = to_pmz(port); 648 649 /* Disable all RX interrupts. */ 650 uap->curregs[R1] &= ~RxINT_MASK; 651 pmz_maybe_update_regs(uap); 652 } 653 654 /* 655 * Enable modem status change interrupts 656 * The port lock is held. 657 */ 658 static void pmz_enable_ms(struct uart_port *port) 659 { 660 struct uart_pmac_port *uap = to_pmz(port); 661 unsigned char new_reg; 662 663 if (ZS_IS_IRDA(uap)) 664 return; 665 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 666 if (new_reg != uap->curregs[R15]) { 667 uap->curregs[R15] = new_reg; 668 669 /* NOTE: Not subject to 'transmitter active' rule. */ 670 write_zsreg(uap, R15, uap->curregs[R15]); 671 } 672 } 673 674 /* 675 * Control break state emission 676 * The port lock is not held. 677 */ 678 static void pmz_break_ctl(struct uart_port *port, int break_state) 679 { 680 struct uart_pmac_port *uap = to_pmz(port); 681 unsigned char set_bits, clear_bits, new_reg; 682 unsigned long flags; 683 684 set_bits = clear_bits = 0; 685 686 if (break_state) 687 set_bits |= SND_BRK; 688 else 689 clear_bits |= SND_BRK; 690 691 spin_lock_irqsave(&port->lock, flags); 692 693 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 694 if (new_reg != uap->curregs[R5]) { 695 uap->curregs[R5] = new_reg; 696 write_zsreg(uap, R5, uap->curregs[R5]); 697 } 698 699 spin_unlock_irqrestore(&port->lock, flags); 700 } 701 702 #ifdef CONFIG_PPC_PMAC 703 704 /* 705 * Turn power on or off to the SCC and associated stuff 706 * (port drivers, modem, IR port, etc.) 707 * Returns the number of milliseconds we should wait before 708 * trying to use the port. 709 */ 710 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 711 { 712 int delay = 0; 713 int rc; 714 715 if (state) { 716 rc = pmac_call_feature( 717 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); 718 pmz_debug("port power on result: %d\n", rc); 719 if (ZS_IS_INTMODEM(uap)) { 720 rc = pmac_call_feature( 721 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); 722 delay = 2500; /* wait for 2.5s before using */ 723 pmz_debug("modem power result: %d\n", rc); 724 } 725 } else { 726 /* TODO: Make that depend on a timer, don't power down 727 * immediately 728 */ 729 if (ZS_IS_INTMODEM(uap)) { 730 rc = pmac_call_feature( 731 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); 732 pmz_debug("port power off result: %d\n", rc); 733 } 734 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); 735 } 736 return delay; 737 } 738 739 #else 740 741 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 742 { 743 return 0; 744 } 745 746 #endif /* !CONFIG_PPC_PMAC */ 747 748 /* 749 * FixZeroBug....Works around a bug in the SCC receiving channel. 750 * Inspired from Darwin code, 15 Sept. 2000 -DanM 751 * 752 * The following sequence prevents a problem that is seen with O'Hare ASICs 753 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero 754 * at the input to the receiver becomes 'stuck' and locks up the receiver. 755 * This problem can occur as a result of a zero bit at the receiver input 756 * coincident with any of the following events: 757 * 758 * The SCC is initialized (hardware or software). 759 * A framing error is detected. 760 * The clocking option changes from synchronous or X1 asynchronous 761 * clocking to X16, X32, or X64 asynchronous clocking. 762 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. 763 * 764 * This workaround attempts to recover from the lockup condition by placing 765 * the SCC in synchronous loopback mode with a fast clock before programming 766 * any of the asynchronous modes. 767 */ 768 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) 769 { 770 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 771 zssync(uap); 772 udelay(10); 773 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); 774 zssync(uap); 775 776 write_zsreg(uap, 4, X1CLK | MONSYNC); 777 write_zsreg(uap, 3, Rx8); 778 write_zsreg(uap, 5, Tx8 | RTS); 779 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ 780 write_zsreg(uap, 11, RCBR | TCBR); 781 write_zsreg(uap, 12, 0); 782 write_zsreg(uap, 13, 0); 783 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); 784 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); 785 write_zsreg(uap, 3, Rx8 | RxENABLE); 786 write_zsreg(uap, 0, RES_EXT_INT); 787 write_zsreg(uap, 0, RES_EXT_INT); 788 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ 789 790 /* The channel should be OK now, but it is probably receiving 791 * loopback garbage. 792 * Switch to asynchronous mode, disable the receiver, 793 * and discard everything in the receive buffer. 794 */ 795 write_zsreg(uap, 9, NV); 796 write_zsreg(uap, 4, X16CLK | SB_MASK); 797 write_zsreg(uap, 3, Rx8); 798 799 while (read_zsreg(uap, 0) & Rx_CH_AV) { 800 (void)read_zsreg(uap, 8); 801 write_zsreg(uap, 0, RES_EXT_INT); 802 write_zsreg(uap, 0, ERR_RES); 803 } 804 } 805 806 /* 807 * Real startup routine, powers up the hardware and sets up 808 * the SCC. Returns a delay in ms where you need to wait before 809 * actually using the port, this is typically the internal modem 810 * powerup delay. This routine expect the lock to be taken. 811 */ 812 static int __pmz_startup(struct uart_pmac_port *uap) 813 { 814 int pwr_delay = 0; 815 816 memset(&uap->curregs, 0, sizeof(uap->curregs)); 817 818 /* Power up the SCC & underlying hardware (modem/irda) */ 819 pwr_delay = pmz_set_scc_power(uap, 1); 820 821 /* Nice buggy HW ... */ 822 pmz_fix_zero_bug_scc(uap); 823 824 /* Reset the channel */ 825 uap->curregs[R9] = 0; 826 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 827 zssync(uap); 828 udelay(10); 829 write_zsreg(uap, 9, 0); 830 zssync(uap); 831 832 /* Clear the interrupt registers */ 833 write_zsreg(uap, R1, 0); 834 write_zsreg(uap, R0, ERR_RES); 835 write_zsreg(uap, R0, ERR_RES); 836 write_zsreg(uap, R0, RES_H_IUS); 837 write_zsreg(uap, R0, RES_H_IUS); 838 839 /* Setup some valid baud rate */ 840 uap->curregs[R4] = X16CLK | SB1; 841 uap->curregs[R3] = Rx8; 842 uap->curregs[R5] = Tx8 | RTS; 843 if (!ZS_IS_IRDA(uap)) 844 uap->curregs[R5] |= DTR; 845 uap->curregs[R12] = 0; 846 uap->curregs[R13] = 0; 847 uap->curregs[R14] = BRENAB; 848 849 /* Clear handshaking, enable BREAK interrupts */ 850 uap->curregs[R15] = BRKIE; 851 852 /* Master interrupt enable */ 853 uap->curregs[R9] |= NV | MIE; 854 855 pmz_load_zsregs(uap, uap->curregs); 856 857 /* Enable receiver and transmitter. */ 858 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); 859 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); 860 861 /* Remember status for DCD/CTS changes */ 862 uap->prev_status = read_zsreg(uap, R0); 863 864 return pwr_delay; 865 } 866 867 static void pmz_irda_reset(struct uart_pmac_port *uap) 868 { 869 unsigned long flags; 870 871 spin_lock_irqsave(&uap->port.lock, flags); 872 uap->curregs[R5] |= DTR; 873 write_zsreg(uap, R5, uap->curregs[R5]); 874 zssync(uap); 875 spin_unlock_irqrestore(&uap->port.lock, flags); 876 msleep(110); 877 878 spin_lock_irqsave(&uap->port.lock, flags); 879 uap->curregs[R5] &= ~DTR; 880 write_zsreg(uap, R5, uap->curregs[R5]); 881 zssync(uap); 882 spin_unlock_irqrestore(&uap->port.lock, flags); 883 msleep(10); 884 } 885 886 /* 887 * This is the "normal" startup routine, using the above one 888 * wrapped with the lock and doing a schedule delay 889 */ 890 static int pmz_startup(struct uart_port *port) 891 { 892 struct uart_pmac_port *uap = to_pmz(port); 893 unsigned long flags; 894 int pwr_delay = 0; 895 896 uap->flags |= PMACZILOG_FLAG_IS_OPEN; 897 898 /* A console is never powered down. Else, power up and 899 * initialize the chip 900 */ 901 if (!ZS_IS_CONS(uap)) { 902 spin_lock_irqsave(&port->lock, flags); 903 pwr_delay = __pmz_startup(uap); 904 spin_unlock_irqrestore(&port->lock, flags); 905 } 906 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line); 907 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, 908 uap->irq_name, uap)) { 909 pmz_error("Unable to register zs interrupt handler.\n"); 910 pmz_set_scc_power(uap, 0); 911 return -ENXIO; 912 } 913 914 /* Right now, we deal with delay by blocking here, I'll be 915 * smarter later on 916 */ 917 if (pwr_delay != 0) { 918 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 919 msleep(pwr_delay); 920 } 921 922 /* IrDA reset is done now */ 923 if (ZS_IS_IRDA(uap)) 924 pmz_irda_reset(uap); 925 926 /* Enable interrupt requests for the channel */ 927 spin_lock_irqsave(&port->lock, flags); 928 pmz_interrupt_control(uap, 1); 929 spin_unlock_irqrestore(&port->lock, flags); 930 931 return 0; 932 } 933 934 static void pmz_shutdown(struct uart_port *port) 935 { 936 struct uart_pmac_port *uap = to_pmz(port); 937 unsigned long flags; 938 939 spin_lock_irqsave(&port->lock, flags); 940 941 /* Disable interrupt requests for the channel */ 942 pmz_interrupt_control(uap, 0); 943 944 if (!ZS_IS_CONS(uap)) { 945 /* Disable receiver and transmitter */ 946 uap->curregs[R3] &= ~RxENABLE; 947 uap->curregs[R5] &= ~TxENABLE; 948 949 /* Disable break assertion */ 950 uap->curregs[R5] &= ~SND_BRK; 951 pmz_maybe_update_regs(uap); 952 } 953 954 spin_unlock_irqrestore(&port->lock, flags); 955 956 /* Release interrupt handler */ 957 free_irq(uap->port.irq, uap); 958 959 spin_lock_irqsave(&port->lock, flags); 960 961 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 962 963 if (!ZS_IS_CONS(uap)) 964 pmz_set_scc_power(uap, 0); /* Shut the chip down */ 965 966 spin_unlock_irqrestore(&port->lock, flags); 967 } 968 969 /* Shared by TTY driver and serial console setup. The port lock is held 970 * and local interrupts are disabled. 971 */ 972 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, 973 unsigned int iflag, unsigned long baud) 974 { 975 int brg; 976 977 /* Switch to external clocking for IrDA high clock rates. That 978 * code could be re-used for Midi interfaces with different 979 * multipliers 980 */ 981 if (baud >= 115200 && ZS_IS_IRDA(uap)) { 982 uap->curregs[R4] = X1CLK; 983 uap->curregs[R11] = RCTRxCP | TCTRxCP; 984 uap->curregs[R14] = 0; /* BRG off */ 985 uap->curregs[R12] = 0; 986 uap->curregs[R13] = 0; 987 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; 988 } else { 989 switch (baud) { 990 case ZS_CLOCK/16: /* 230400 */ 991 uap->curregs[R4] = X16CLK; 992 uap->curregs[R11] = 0; 993 uap->curregs[R14] = 0; 994 break; 995 case ZS_CLOCK/32: /* 115200 */ 996 uap->curregs[R4] = X32CLK; 997 uap->curregs[R11] = 0; 998 uap->curregs[R14] = 0; 999 break; 1000 default: 1001 uap->curregs[R4] = X16CLK; 1002 uap->curregs[R11] = TCBR | RCBR; 1003 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); 1004 uap->curregs[R12] = (brg & 255); 1005 uap->curregs[R13] = ((brg >> 8) & 255); 1006 uap->curregs[R14] = BRENAB; 1007 } 1008 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; 1009 } 1010 1011 /* Character size, stop bits, and parity. */ 1012 uap->curregs[3] &= ~RxN_MASK; 1013 uap->curregs[5] &= ~TxN_MASK; 1014 1015 switch (cflag & CSIZE) { 1016 case CS5: 1017 uap->curregs[3] |= Rx5; 1018 uap->curregs[5] |= Tx5; 1019 uap->parity_mask = 0x1f; 1020 break; 1021 case CS6: 1022 uap->curregs[3] |= Rx6; 1023 uap->curregs[5] |= Tx6; 1024 uap->parity_mask = 0x3f; 1025 break; 1026 case CS7: 1027 uap->curregs[3] |= Rx7; 1028 uap->curregs[5] |= Tx7; 1029 uap->parity_mask = 0x7f; 1030 break; 1031 case CS8: 1032 default: 1033 uap->curregs[3] |= Rx8; 1034 uap->curregs[5] |= Tx8; 1035 uap->parity_mask = 0xff; 1036 break; 1037 } 1038 uap->curregs[4] &= ~(SB_MASK); 1039 if (cflag & CSTOPB) 1040 uap->curregs[4] |= SB2; 1041 else 1042 uap->curregs[4] |= SB1; 1043 if (cflag & PARENB) 1044 uap->curregs[4] |= PAR_ENAB; 1045 else 1046 uap->curregs[4] &= ~PAR_ENAB; 1047 if (!(cflag & PARODD)) 1048 uap->curregs[4] |= PAR_EVEN; 1049 else 1050 uap->curregs[4] &= ~PAR_EVEN; 1051 1052 uap->port.read_status_mask = Rx_OVR; 1053 if (iflag & INPCK) 1054 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; 1055 if (iflag & (IGNBRK | BRKINT | PARMRK)) 1056 uap->port.read_status_mask |= BRK_ABRT; 1057 1058 uap->port.ignore_status_mask = 0; 1059 if (iflag & IGNPAR) 1060 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 1061 if (iflag & IGNBRK) { 1062 uap->port.ignore_status_mask |= BRK_ABRT; 1063 if (iflag & IGNPAR) 1064 uap->port.ignore_status_mask |= Rx_OVR; 1065 } 1066 1067 if ((cflag & CREAD) == 0) 1068 uap->port.ignore_status_mask = 0xff; 1069 } 1070 1071 1072 /* 1073 * Set the irda codec on the imac to the specified baud rate. 1074 */ 1075 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) 1076 { 1077 u8 cmdbyte; 1078 int t, version; 1079 1080 switch (*baud) { 1081 /* SIR modes */ 1082 case 2400: 1083 cmdbyte = 0x53; 1084 break; 1085 case 4800: 1086 cmdbyte = 0x52; 1087 break; 1088 case 9600: 1089 cmdbyte = 0x51; 1090 break; 1091 case 19200: 1092 cmdbyte = 0x50; 1093 break; 1094 case 38400: 1095 cmdbyte = 0x4f; 1096 break; 1097 case 57600: 1098 cmdbyte = 0x4e; 1099 break; 1100 case 115200: 1101 cmdbyte = 0x4d; 1102 break; 1103 /* The FIR modes aren't really supported at this point, how 1104 * do we select the speed ? via the FCR on KeyLargo ? 1105 */ 1106 case 1152000: 1107 cmdbyte = 0; 1108 break; 1109 case 4000000: 1110 cmdbyte = 0; 1111 break; 1112 default: /* 9600 */ 1113 cmdbyte = 0x51; 1114 *baud = 9600; 1115 break; 1116 } 1117 1118 /* Wait for transmitter to drain */ 1119 t = 10000; 1120 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 1121 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { 1122 if (--t <= 0) { 1123 pmz_error("transmitter didn't drain\n"); 1124 return; 1125 } 1126 udelay(10); 1127 } 1128 1129 /* Drain the receiver too */ 1130 t = 100; 1131 (void)read_zsdata(uap); 1132 (void)read_zsdata(uap); 1133 (void)read_zsdata(uap); 1134 mdelay(10); 1135 while (read_zsreg(uap, R0) & Rx_CH_AV) { 1136 read_zsdata(uap); 1137 mdelay(10); 1138 if (--t <= 0) { 1139 pmz_error("receiver didn't drain\n"); 1140 return; 1141 } 1142 } 1143 1144 /* Switch to command mode */ 1145 uap->curregs[R5] |= DTR; 1146 write_zsreg(uap, R5, uap->curregs[R5]); 1147 zssync(uap); 1148 mdelay(1); 1149 1150 /* Switch SCC to 19200 */ 1151 pmz_convert_to_zs(uap, CS8, 0, 19200); 1152 pmz_load_zsregs(uap, uap->curregs); 1153 mdelay(1); 1154 1155 /* Write get_version command byte */ 1156 write_zsdata(uap, 1); 1157 t = 5000; 1158 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1159 if (--t <= 0) { 1160 pmz_error("irda_setup timed out on get_version byte\n"); 1161 goto out; 1162 } 1163 udelay(10); 1164 } 1165 version = read_zsdata(uap); 1166 1167 if (version < 4) { 1168 pmz_info("IrDA: dongle version %d not supported\n", version); 1169 goto out; 1170 } 1171 1172 /* Send speed mode */ 1173 write_zsdata(uap, cmdbyte); 1174 t = 5000; 1175 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1176 if (--t <= 0) { 1177 pmz_error("irda_setup timed out on speed mode byte\n"); 1178 goto out; 1179 } 1180 udelay(10); 1181 } 1182 t = read_zsdata(uap); 1183 if (t != cmdbyte) 1184 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); 1185 1186 pmz_info("IrDA setup for %ld bps, dongle version: %d\n", 1187 *baud, version); 1188 1189 (void)read_zsdata(uap); 1190 (void)read_zsdata(uap); 1191 (void)read_zsdata(uap); 1192 1193 out: 1194 /* Switch back to data mode */ 1195 uap->curregs[R5] &= ~DTR; 1196 write_zsreg(uap, R5, uap->curregs[R5]); 1197 zssync(uap); 1198 1199 (void)read_zsdata(uap); 1200 (void)read_zsdata(uap); 1201 (void)read_zsdata(uap); 1202 } 1203 1204 1205 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1206 struct ktermios *old) 1207 { 1208 struct uart_pmac_port *uap = to_pmz(port); 1209 unsigned long baud; 1210 1211 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds 1212 * on the IR dongle. Note that the IRTTY driver currently doesn't know 1213 * about the FIR mode and high speed modes. So these are unused. For 1214 * implementing proper support for these, we should probably add some 1215 * DMA as well, at least on the Rx side, which isn't a simple thing 1216 * at this point. 1217 */ 1218 if (ZS_IS_IRDA(uap)) { 1219 /* Calc baud rate */ 1220 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); 1221 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); 1222 /* Cet the irda codec to the right rate */ 1223 pmz_irda_setup(uap, &baud); 1224 /* Set final baud rate */ 1225 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1226 pmz_load_zsregs(uap, uap->curregs); 1227 zssync(uap); 1228 } else { 1229 baud = uart_get_baud_rate(port, termios, old, 1200, 230400); 1230 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1231 /* Make sure modem status interrupts are correctly configured */ 1232 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { 1233 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; 1234 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; 1235 } else { 1236 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); 1237 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; 1238 } 1239 1240 /* Load registers to the chip */ 1241 pmz_maybe_update_regs(uap); 1242 } 1243 uart_update_timeout(port, termios->c_cflag, baud); 1244 } 1245 1246 /* The port lock is not held. */ 1247 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1248 struct ktermios *old) 1249 { 1250 struct uart_pmac_port *uap = to_pmz(port); 1251 unsigned long flags; 1252 1253 spin_lock_irqsave(&port->lock, flags); 1254 1255 /* Disable IRQs on the port */ 1256 pmz_interrupt_control(uap, 0); 1257 1258 /* Setup new port configuration */ 1259 __pmz_set_termios(port, termios, old); 1260 1261 /* Re-enable IRQs on the port */ 1262 if (ZS_IS_OPEN(uap)) 1263 pmz_interrupt_control(uap, 1); 1264 1265 spin_unlock_irqrestore(&port->lock, flags); 1266 } 1267 1268 static const char *pmz_type(struct uart_port *port) 1269 { 1270 struct uart_pmac_port *uap = to_pmz(port); 1271 1272 if (ZS_IS_IRDA(uap)) 1273 return "Z85c30 ESCC - Infrared port"; 1274 else if (ZS_IS_INTMODEM(uap)) 1275 return "Z85c30 ESCC - Internal modem"; 1276 return "Z85c30 ESCC - Serial port"; 1277 } 1278 1279 /* We do not request/release mappings of the registers here, this 1280 * happens at early serial probe time. 1281 */ 1282 static void pmz_release_port(struct uart_port *port) 1283 { 1284 } 1285 1286 static int pmz_request_port(struct uart_port *port) 1287 { 1288 return 0; 1289 } 1290 1291 /* These do not need to do anything interesting either. */ 1292 static void pmz_config_port(struct uart_port *port, int flags) 1293 { 1294 } 1295 1296 /* We do not support letting the user mess with the divisor, IRQ, etc. */ 1297 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) 1298 { 1299 return -EINVAL; 1300 } 1301 1302 #ifdef CONFIG_CONSOLE_POLL 1303 1304 static int pmz_poll_get_char(struct uart_port *port) 1305 { 1306 struct uart_pmac_port *uap = 1307 container_of(port, struct uart_pmac_port, port); 1308 int tries = 2; 1309 1310 while (tries) { 1311 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0) 1312 return read_zsdata(uap); 1313 if (tries--) 1314 udelay(5); 1315 } 1316 1317 return NO_POLL_CHAR; 1318 } 1319 1320 static void pmz_poll_put_char(struct uart_port *port, unsigned char c) 1321 { 1322 struct uart_pmac_port *uap = 1323 container_of(port, struct uart_pmac_port, port); 1324 1325 /* Wait for the transmit buffer to empty. */ 1326 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1327 udelay(5); 1328 write_zsdata(uap, c); 1329 } 1330 1331 #endif /* CONFIG_CONSOLE_POLL */ 1332 1333 static const struct uart_ops pmz_pops = { 1334 .tx_empty = pmz_tx_empty, 1335 .set_mctrl = pmz_set_mctrl, 1336 .get_mctrl = pmz_get_mctrl, 1337 .stop_tx = pmz_stop_tx, 1338 .start_tx = pmz_start_tx, 1339 .stop_rx = pmz_stop_rx, 1340 .enable_ms = pmz_enable_ms, 1341 .break_ctl = pmz_break_ctl, 1342 .startup = pmz_startup, 1343 .shutdown = pmz_shutdown, 1344 .set_termios = pmz_set_termios, 1345 .type = pmz_type, 1346 .release_port = pmz_release_port, 1347 .request_port = pmz_request_port, 1348 .config_port = pmz_config_port, 1349 .verify_port = pmz_verify_port, 1350 #ifdef CONFIG_CONSOLE_POLL 1351 .poll_get_char = pmz_poll_get_char, 1352 .poll_put_char = pmz_poll_put_char, 1353 #endif 1354 }; 1355 1356 #ifdef CONFIG_PPC_PMAC 1357 1358 /* 1359 * Setup one port structure after probing, HW is down at this point, 1360 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't 1361 * register our console before uart_add_one_port() is called 1362 */ 1363 static int __init pmz_init_port(struct uart_pmac_port *uap) 1364 { 1365 struct device_node *np = uap->node; 1366 const char *conn; 1367 const struct slot_names_prop { 1368 int count; 1369 char name[1]; 1370 } *slots; 1371 int len; 1372 struct resource r_ports; 1373 1374 /* 1375 * Request & map chip registers 1376 */ 1377 if (of_address_to_resource(np, 0, &r_ports)) 1378 return -ENODEV; 1379 uap->port.mapbase = r_ports.start; 1380 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); 1381 1382 uap->control_reg = uap->port.membase; 1383 uap->data_reg = uap->control_reg + 0x10; 1384 1385 /* 1386 * Detect port type 1387 */ 1388 if (of_device_is_compatible(np, "cobalt")) 1389 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1390 conn = of_get_property(np, "AAPL,connector", &len); 1391 if (conn && (strcmp(conn, "infrared") == 0)) 1392 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1393 uap->port_type = PMAC_SCC_ASYNC; 1394 /* 1999 Powerbook G3 has slot-names property instead */ 1395 slots = of_get_property(np, "slot-names", &len); 1396 if (slots && slots->count > 0) { 1397 if (strcmp(slots->name, "IrDA") == 0) 1398 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1399 else if (strcmp(slots->name, "Modem") == 0) 1400 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1401 } 1402 if (ZS_IS_IRDA(uap)) 1403 uap->port_type = PMAC_SCC_IRDA; 1404 if (ZS_IS_INTMODEM(uap)) { 1405 struct device_node* i2c_modem = 1406 of_find_node_by_name(NULL, "i2c-modem"); 1407 if (i2c_modem) { 1408 const char* mid = 1409 of_get_property(i2c_modem, "modem-id", NULL); 1410 if (mid) switch(*mid) { 1411 case 0x04 : 1412 case 0x05 : 1413 case 0x07 : 1414 case 0x08 : 1415 case 0x0b : 1416 case 0x0c : 1417 uap->port_type = PMAC_SCC_I2S1; 1418 } 1419 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", 1420 mid ? (*mid) : 0); 1421 of_node_put(i2c_modem); 1422 } else { 1423 printk(KERN_INFO "pmac_zilog: serial modem detected\n"); 1424 } 1425 } 1426 1427 /* 1428 * Init remaining bits of "port" structure 1429 */ 1430 uap->port.iotype = UPIO_MEM; 1431 uap->port.irq = irq_of_parse_and_map(np, 0); 1432 uap->port.uartclk = ZS_CLOCK; 1433 uap->port.fifosize = 1; 1434 uap->port.ops = &pmz_pops; 1435 uap->port.type = PORT_PMAC_ZILOG; 1436 uap->port.flags = 0; 1437 1438 /* 1439 * Fixup for the port on Gatwick for which the device-tree has 1440 * missing interrupts. Normally, the macio_dev would contain 1441 * fixed up interrupt info, but we use the device-tree directly 1442 * here due to early probing so we need the fixup too. 1443 */ 1444 if (uap->port.irq == 0 && 1445 np->parent && np->parent->parent && 1446 of_device_is_compatible(np->parent->parent, "gatwick")) { 1447 /* IRQs on gatwick are offset by 64 */ 1448 uap->port.irq = irq_create_mapping(NULL, 64 + 15); 1449 } 1450 1451 /* Setup some valid baud rate information in the register 1452 * shadows so we don't write crap there before baud rate is 1453 * first initialized. 1454 */ 1455 pmz_convert_to_zs(uap, CS8, 0, 9600); 1456 1457 return 0; 1458 } 1459 1460 /* 1461 * Get rid of a port on module removal 1462 */ 1463 static void pmz_dispose_port(struct uart_pmac_port *uap) 1464 { 1465 struct device_node *np; 1466 1467 np = uap->node; 1468 iounmap(uap->control_reg); 1469 uap->node = NULL; 1470 of_node_put(np); 1471 memset(uap, 0, sizeof(struct uart_pmac_port)); 1472 } 1473 1474 /* 1475 * Called upon match with an escc node in the device-tree. 1476 */ 1477 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) 1478 { 1479 struct uart_pmac_port *uap; 1480 int i; 1481 1482 /* Iterate the pmz_ports array to find a matching entry 1483 */ 1484 for (i = 0; i < MAX_ZS_PORTS; i++) 1485 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) 1486 break; 1487 if (i >= MAX_ZS_PORTS) 1488 return -ENODEV; 1489 1490 1491 uap = &pmz_ports[i]; 1492 uap->dev = mdev; 1493 uap->port.dev = &mdev->ofdev.dev; 1494 dev_set_drvdata(&mdev->ofdev.dev, uap); 1495 1496 /* We still activate the port even when failing to request resources 1497 * to work around bugs in ancient Apple device-trees 1498 */ 1499 if (macio_request_resources(uap->dev, "pmac_zilog")) 1500 printk(KERN_WARNING "%pOFn: Failed to request resource" 1501 ", port still active\n", 1502 uap->node); 1503 else 1504 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; 1505 1506 return uart_add_one_port(&pmz_uart_reg, &uap->port); 1507 } 1508 1509 /* 1510 * That one should not be called, macio isn't really a hotswap device, 1511 * we don't expect one of those serial ports to go away... 1512 */ 1513 static int pmz_detach(struct macio_dev *mdev) 1514 { 1515 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1516 1517 if (!uap) 1518 return -ENODEV; 1519 1520 uart_remove_one_port(&pmz_uart_reg, &uap->port); 1521 1522 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { 1523 macio_release_resources(uap->dev); 1524 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; 1525 } 1526 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1527 uap->dev = NULL; 1528 uap->port.dev = NULL; 1529 1530 return 0; 1531 } 1532 1533 1534 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) 1535 { 1536 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1537 1538 if (uap == NULL) { 1539 printk("HRM... pmz_suspend with NULL uap\n"); 1540 return 0; 1541 } 1542 1543 uart_suspend_port(&pmz_uart_reg, &uap->port); 1544 1545 return 0; 1546 } 1547 1548 1549 static int pmz_resume(struct macio_dev *mdev) 1550 { 1551 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1552 1553 if (uap == NULL) 1554 return 0; 1555 1556 uart_resume_port(&pmz_uart_reg, &uap->port); 1557 1558 return 0; 1559 } 1560 1561 /* 1562 * Probe all ports in the system and build the ports array, we register 1563 * with the serial layer later, so we get a proper struct device which 1564 * allows the tty to attach properly. This is later than it used to be 1565 * but the tty layer really wants it that way. 1566 */ 1567 static int __init pmz_probe(void) 1568 { 1569 struct device_node *node_p, *node_a, *node_b, *np; 1570 int count = 0; 1571 int rc; 1572 1573 /* 1574 * Find all escc chips in the system 1575 */ 1576 for_each_node_by_name(node_p, "escc") { 1577 /* 1578 * First get channel A/B node pointers 1579 * 1580 * TODO: Add routines with proper locking to do that... 1581 */ 1582 node_a = node_b = NULL; 1583 for_each_child_of_node(node_p, np) { 1584 if (of_node_name_prefix(np, "ch-a")) 1585 node_a = of_node_get(np); 1586 else if (of_node_name_prefix(np, "ch-b")) 1587 node_b = of_node_get(np); 1588 } 1589 if (!node_a && !node_b) { 1590 of_node_put(node_a); 1591 of_node_put(node_b); 1592 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n", 1593 (!node_a) ? 'a' : 'b', node_p); 1594 continue; 1595 } 1596 1597 /* 1598 * Fill basic fields in the port structures 1599 */ 1600 if (node_b != NULL) { 1601 pmz_ports[count].mate = &pmz_ports[count+1]; 1602 pmz_ports[count+1].mate = &pmz_ports[count]; 1603 } 1604 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1605 pmz_ports[count].node = node_a; 1606 pmz_ports[count+1].node = node_b; 1607 pmz_ports[count].port.line = count; 1608 pmz_ports[count+1].port.line = count+1; 1609 1610 /* 1611 * Setup the ports for real 1612 */ 1613 rc = pmz_init_port(&pmz_ports[count]); 1614 if (rc == 0 && node_b != NULL) 1615 rc = pmz_init_port(&pmz_ports[count+1]); 1616 if (rc != 0) { 1617 of_node_put(node_a); 1618 of_node_put(node_b); 1619 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); 1620 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); 1621 continue; 1622 } 1623 count += 2; 1624 } 1625 pmz_ports_count = count; 1626 1627 return 0; 1628 } 1629 1630 #else 1631 1632 /* On PCI PowerMacs, pmz_probe() does an explicit search of the OpenFirmware 1633 * tree to obtain the device_nodes needed to start the console before the 1634 * macio driver. On Macs without OpenFirmware, global platform_devices take 1635 * the place of those device_nodes. 1636 */ 1637 extern struct platform_device scc_a_pdev, scc_b_pdev; 1638 1639 static int __init pmz_init_port(struct uart_pmac_port *uap) 1640 { 1641 struct resource *r_ports; 1642 int irq; 1643 1644 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0); 1645 if (!r_ports) 1646 return -ENODEV; 1647 1648 irq = platform_get_irq(uap->pdev, 0); 1649 if (irq < 0) 1650 return irq; 1651 1652 uap->port.mapbase = r_ports->start; 1653 uap->port.membase = (unsigned char __iomem *) r_ports->start; 1654 uap->port.iotype = UPIO_MEM; 1655 uap->port.irq = irq; 1656 uap->port.uartclk = ZS_CLOCK; 1657 uap->port.fifosize = 1; 1658 uap->port.ops = &pmz_pops; 1659 uap->port.type = PORT_PMAC_ZILOG; 1660 uap->port.flags = 0; 1661 1662 uap->control_reg = uap->port.membase; 1663 uap->data_reg = uap->control_reg + 4; 1664 uap->port_type = 0; 1665 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE); 1666 1667 pmz_convert_to_zs(uap, CS8, 0, 9600); 1668 1669 return 0; 1670 } 1671 1672 static int __init pmz_probe(void) 1673 { 1674 int err; 1675 1676 pmz_ports_count = 0; 1677 1678 pmz_ports[0].port.line = 0; 1679 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1680 pmz_ports[0].pdev = &scc_a_pdev; 1681 err = pmz_init_port(&pmz_ports[0]); 1682 if (err) 1683 return err; 1684 pmz_ports_count++; 1685 1686 pmz_ports[0].mate = &pmz_ports[1]; 1687 pmz_ports[1].mate = &pmz_ports[0]; 1688 pmz_ports[1].port.line = 1; 1689 pmz_ports[1].flags = 0; 1690 pmz_ports[1].pdev = &scc_b_pdev; 1691 err = pmz_init_port(&pmz_ports[1]); 1692 if (err) 1693 return err; 1694 pmz_ports_count++; 1695 1696 return 0; 1697 } 1698 1699 static void pmz_dispose_port(struct uart_pmac_port *uap) 1700 { 1701 memset(uap, 0, sizeof(struct uart_pmac_port)); 1702 } 1703 1704 static int __init pmz_attach(struct platform_device *pdev) 1705 { 1706 struct uart_pmac_port *uap; 1707 int i; 1708 1709 /* Iterate the pmz_ports array to find a matching entry */ 1710 for (i = 0; i < pmz_ports_count; i++) 1711 if (pmz_ports[i].pdev == pdev) 1712 break; 1713 if (i >= pmz_ports_count) 1714 return -ENODEV; 1715 1716 uap = &pmz_ports[i]; 1717 uap->port.dev = &pdev->dev; 1718 platform_set_drvdata(pdev, uap); 1719 1720 return uart_add_one_port(&pmz_uart_reg, &uap->port); 1721 } 1722 1723 static int __exit pmz_detach(struct platform_device *pdev) 1724 { 1725 struct uart_pmac_port *uap = platform_get_drvdata(pdev); 1726 1727 if (!uap) 1728 return -ENODEV; 1729 1730 uart_remove_one_port(&pmz_uart_reg, &uap->port); 1731 1732 uap->port.dev = NULL; 1733 1734 return 0; 1735 } 1736 1737 #endif /* !CONFIG_PPC_PMAC */ 1738 1739 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1740 1741 static void pmz_console_write(struct console *con, const char *s, unsigned int count); 1742 static int __init pmz_console_setup(struct console *co, char *options); 1743 1744 static struct console pmz_console = { 1745 .name = PMACZILOG_NAME, 1746 .write = pmz_console_write, 1747 .device = uart_console_device, 1748 .setup = pmz_console_setup, 1749 .flags = CON_PRINTBUFFER, 1750 .index = -1, 1751 .data = &pmz_uart_reg, 1752 }; 1753 1754 #define PMACZILOG_CONSOLE &pmz_console 1755 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1756 #define PMACZILOG_CONSOLE (NULL) 1757 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1758 1759 /* 1760 * Register the driver, console driver and ports with the serial 1761 * core 1762 */ 1763 static int __init pmz_register(void) 1764 { 1765 pmz_uart_reg.nr = pmz_ports_count; 1766 pmz_uart_reg.cons = PMACZILOG_CONSOLE; 1767 1768 /* 1769 * Register this driver with the serial core 1770 */ 1771 return uart_register_driver(&pmz_uart_reg); 1772 } 1773 1774 #ifdef CONFIG_PPC_PMAC 1775 1776 static const struct of_device_id pmz_match[] = 1777 { 1778 { 1779 .name = "ch-a", 1780 }, 1781 { 1782 .name = "ch-b", 1783 }, 1784 {}, 1785 }; 1786 MODULE_DEVICE_TABLE (of, pmz_match); 1787 1788 static struct macio_driver pmz_driver = { 1789 .driver = { 1790 .name = "pmac_zilog", 1791 .owner = THIS_MODULE, 1792 .of_match_table = pmz_match, 1793 }, 1794 .probe = pmz_attach, 1795 .remove = pmz_detach, 1796 .suspend = pmz_suspend, 1797 .resume = pmz_resume, 1798 }; 1799 1800 #else 1801 1802 static struct platform_driver pmz_driver = { 1803 .remove = __exit_p(pmz_detach), 1804 .driver = { 1805 .name = "scc", 1806 }, 1807 }; 1808 1809 #endif /* !CONFIG_PPC_PMAC */ 1810 1811 static int __init init_pmz(void) 1812 { 1813 int rc, i; 1814 1815 /* 1816 * First, we need to do a direct OF-based probe pass. We 1817 * do that because we want serial console up before the 1818 * macio stuffs calls us back, and since that makes it 1819 * easier to pass the proper number of channels to 1820 * uart_register_driver() 1821 */ 1822 if (pmz_ports_count == 0) 1823 pmz_probe(); 1824 1825 /* 1826 * Bail early if no port found 1827 */ 1828 if (pmz_ports_count == 0) 1829 return -ENODEV; 1830 1831 /* 1832 * Now we register with the serial layer 1833 */ 1834 rc = pmz_register(); 1835 if (rc) { 1836 printk(KERN_ERR 1837 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" 1838 "pmac_zilog: Did another serial driver already claim the minors?\n"); 1839 /* effectively "pmz_unprobe()" */ 1840 for (i=0; i < pmz_ports_count; i++) 1841 pmz_dispose_port(&pmz_ports[i]); 1842 return rc; 1843 } 1844 1845 /* 1846 * Then we register the macio driver itself 1847 */ 1848 #ifdef CONFIG_PPC_PMAC 1849 return macio_register_driver(&pmz_driver); 1850 #else 1851 return platform_driver_probe(&pmz_driver, pmz_attach); 1852 #endif 1853 } 1854 1855 static void __exit exit_pmz(void) 1856 { 1857 int i; 1858 1859 #ifdef CONFIG_PPC_PMAC 1860 /* Get rid of macio-driver (detach from macio) */ 1861 macio_unregister_driver(&pmz_driver); 1862 #else 1863 platform_driver_unregister(&pmz_driver); 1864 #endif 1865 1866 for (i = 0; i < pmz_ports_count; i++) { 1867 struct uart_pmac_port *uport = &pmz_ports[i]; 1868 #ifdef CONFIG_PPC_PMAC 1869 if (uport->node != NULL) 1870 pmz_dispose_port(uport); 1871 #else 1872 if (uport->pdev != NULL) 1873 pmz_dispose_port(uport); 1874 #endif 1875 } 1876 /* Unregister UART driver */ 1877 uart_unregister_driver(&pmz_uart_reg); 1878 } 1879 1880 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1881 1882 static void pmz_console_putchar(struct uart_port *port, unsigned char ch) 1883 { 1884 struct uart_pmac_port *uap = 1885 container_of(port, struct uart_pmac_port, port); 1886 1887 /* Wait for the transmit buffer to empty. */ 1888 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1889 udelay(5); 1890 write_zsdata(uap, ch); 1891 } 1892 1893 /* 1894 * Print a string to the serial port trying not to disturb 1895 * any possible real use of the port... 1896 */ 1897 static void pmz_console_write(struct console *con, const char *s, unsigned int count) 1898 { 1899 struct uart_pmac_port *uap = &pmz_ports[con->index]; 1900 unsigned long flags; 1901 1902 spin_lock_irqsave(&uap->port.lock, flags); 1903 1904 /* Turn of interrupts and enable the transmitter. */ 1905 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); 1906 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); 1907 1908 uart_console_write(&uap->port, s, count, pmz_console_putchar); 1909 1910 /* Restore the values in the registers. */ 1911 write_zsreg(uap, R1, uap->curregs[1]); 1912 /* Don't disable the transmitter. */ 1913 1914 spin_unlock_irqrestore(&uap->port.lock, flags); 1915 } 1916 1917 /* 1918 * Setup the serial console 1919 */ 1920 static int __init pmz_console_setup(struct console *co, char *options) 1921 { 1922 struct uart_pmac_port *uap; 1923 struct uart_port *port; 1924 int baud = 38400; 1925 int bits = 8; 1926 int parity = 'n'; 1927 int flow = 'n'; 1928 unsigned long pwr_delay; 1929 1930 /* 1931 * XServe's default to 57600 bps 1932 */ 1933 if (of_machine_is_compatible("RackMac1,1") 1934 || of_machine_is_compatible("RackMac1,2") 1935 || of_machine_is_compatible("MacRISC4")) 1936 baud = 57600; 1937 1938 /* 1939 * Check whether an invalid uart number has been specified, and 1940 * if so, search for the first available port that does have 1941 * console support. 1942 */ 1943 if (co->index >= pmz_ports_count) 1944 co->index = 0; 1945 uap = &pmz_ports[co->index]; 1946 #ifdef CONFIG_PPC_PMAC 1947 if (uap->node == NULL) 1948 return -ENODEV; 1949 #else 1950 if (uap->pdev == NULL) 1951 return -ENODEV; 1952 #endif 1953 port = &uap->port; 1954 1955 /* 1956 * Mark port as beeing a console 1957 */ 1958 uap->flags |= PMACZILOG_FLAG_IS_CONS; 1959 1960 /* 1961 * Temporary fix for uart layer who didn't setup the spinlock yet 1962 */ 1963 spin_lock_init(&port->lock); 1964 1965 /* 1966 * Enable the hardware 1967 */ 1968 pwr_delay = __pmz_startup(uap); 1969 if (pwr_delay) 1970 mdelay(pwr_delay); 1971 1972 if (options) 1973 uart_parse_options(options, &baud, &parity, &bits, &flow); 1974 1975 return uart_set_options(port, co, baud, parity, bits, flow); 1976 } 1977 1978 static int __init pmz_console_init(void) 1979 { 1980 /* Probe ports */ 1981 pmz_probe(); 1982 1983 if (pmz_ports_count == 0) 1984 return -ENODEV; 1985 1986 /* TODO: Autoprobe console based on OF */ 1987 /* pmz_console.index = i; */ 1988 register_console(&pmz_console); 1989 1990 return 0; 1991 1992 } 1993 console_initcall(pmz_console_init); 1994 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1995 1996 module_init(init_pmz); 1997 module_exit(exit_pmz); 1998