1 /* 2 * Driver for PowerMac Z85c30 based ESCC cell found in the 3 * "macio" ASICs of various PowerMac models 4 * 5 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) 6 * 7 * Derived from drivers/macintosh/macserial.c by Paul Mackerras 8 * and drivers/serial/sunzilog.c by David S. Miller 9 * 10 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and 11 * adapted special tweaks needed for us. I don't think it's worth 12 * merging back those though. The DMA code still has to get in 13 * and once done, I expect that driver to remain fairly stable in 14 * the long term, unless we change the driver model again... 15 * 16 * This program is free software; you can redistribute it and/or modify 17 * it under the terms of the GNU General Public License as published by 18 * the Free Software Foundation; either version 2 of the License, or 19 * (at your option) any later version. 20 * 21 * This program is distributed in the hope that it will be useful, 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * You should have received a copy of the GNU General Public License 27 * along with this program; if not, write to the Free Software 28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 29 * 30 * 2004-08-06 Harald Welte <laforge@gnumonks.org> 31 * - Enable BREAK interrupt 32 * - Add support for sysreq 33 * 34 * TODO: - Add DMA support 35 * - Defer port shutdown to a few seconds after close 36 * - maybe put something right into uap->clk_divisor 37 */ 38 39 #undef DEBUG 40 #undef DEBUG_HARD 41 #undef USE_CTRL_O_SYSRQ 42 43 #include <linux/module.h> 44 #include <linux/tty.h> 45 46 #include <linux/tty_flip.h> 47 #include <linux/major.h> 48 #include <linux/string.h> 49 #include <linux/fcntl.h> 50 #include <linux/mm.h> 51 #include <linux/kernel.h> 52 #include <linux/delay.h> 53 #include <linux/init.h> 54 #include <linux/console.h> 55 #include <linux/adb.h> 56 #include <linux/pmu.h> 57 #include <linux/bitops.h> 58 #include <linux/sysrq.h> 59 #include <linux/mutex.h> 60 #include <linux/of_address.h> 61 #include <linux/of_irq.h> 62 #include <asm/sections.h> 63 #include <asm/io.h> 64 #include <asm/irq.h> 65 66 #ifdef CONFIG_PPC_PMAC 67 #include <asm/prom.h> 68 #include <asm/machdep.h> 69 #include <asm/pmac_feature.h> 70 #include <asm/dbdma.h> 71 #include <asm/macio.h> 72 #else 73 #include <linux/platform_device.h> 74 #define of_machine_is_compatible(x) (0) 75 #endif 76 77 #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 78 #define SUPPORT_SYSRQ 79 #endif 80 81 #include <linux/serial.h> 82 #include <linux/serial_core.h> 83 84 #include "pmac_zilog.h" 85 86 /* Not yet implemented */ 87 #undef HAS_DBDMA 88 89 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; 90 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); 91 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports."); 92 MODULE_LICENSE("GPL"); 93 94 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS 95 #define PMACZILOG_MAJOR TTY_MAJOR 96 #define PMACZILOG_MINOR 64 97 #define PMACZILOG_NAME "ttyS" 98 #else 99 #define PMACZILOG_MAJOR 204 100 #define PMACZILOG_MINOR 192 101 #define PMACZILOG_NAME "ttyPZ" 102 #endif 103 104 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg) 105 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg) 106 #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg) 107 108 /* 109 * For the sake of early serial console, we can do a pre-probe 110 * (optional) of the ports at rather early boot time. 111 */ 112 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; 113 static int pmz_ports_count; 114 115 static struct uart_driver pmz_uart_reg = { 116 .owner = THIS_MODULE, 117 .driver_name = PMACZILOG_NAME, 118 .dev_name = PMACZILOG_NAME, 119 .major = PMACZILOG_MAJOR, 120 .minor = PMACZILOG_MINOR, 121 }; 122 123 124 /* 125 * Load all registers to reprogram the port 126 * This function must only be called when the TX is not busy. The UART 127 * port lock must be held and local interrupts disabled. 128 */ 129 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) 130 { 131 int i; 132 133 /* Let pending transmits finish. */ 134 for (i = 0; i < 1000; i++) { 135 unsigned char stat = read_zsreg(uap, R1); 136 if (stat & ALL_SNT) 137 break; 138 udelay(100); 139 } 140 141 ZS_CLEARERR(uap); 142 zssync(uap); 143 ZS_CLEARFIFO(uap); 144 zssync(uap); 145 ZS_CLEARERR(uap); 146 147 /* Disable all interrupts. */ 148 write_zsreg(uap, R1, 149 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 150 151 /* Set parity, sync config, stop bits, and clock divisor. */ 152 write_zsreg(uap, R4, regs[R4]); 153 154 /* Set misc. TX/RX control bits. */ 155 write_zsreg(uap, R10, regs[R10]); 156 157 /* Set TX/RX controls sans the enable bits. */ 158 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); 159 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); 160 161 /* now set R7 "prime" on ESCC */ 162 write_zsreg(uap, R15, regs[R15] | EN85C30); 163 write_zsreg(uap, R7, regs[R7P]); 164 165 /* make sure we use R7 "non-prime" on ESCC */ 166 write_zsreg(uap, R15, regs[R15] & ~EN85C30); 167 168 /* Synchronous mode config. */ 169 write_zsreg(uap, R6, regs[R6]); 170 write_zsreg(uap, R7, regs[R7]); 171 172 /* Disable baud generator. */ 173 write_zsreg(uap, R14, regs[R14] & ~BRENAB); 174 175 /* Clock mode control. */ 176 write_zsreg(uap, R11, regs[R11]); 177 178 /* Lower and upper byte of baud rate generator divisor. */ 179 write_zsreg(uap, R12, regs[R12]); 180 write_zsreg(uap, R13, regs[R13]); 181 182 /* Now rewrite R14, with BRENAB (if set). */ 183 write_zsreg(uap, R14, regs[R14]); 184 185 /* Reset external status interrupts. */ 186 write_zsreg(uap, R0, RES_EXT_INT); 187 write_zsreg(uap, R0, RES_EXT_INT); 188 189 /* Rewrite R3/R5, this time without enables masked. */ 190 write_zsreg(uap, R3, regs[R3]); 191 write_zsreg(uap, R5, regs[R5]); 192 193 /* Rewrite R1, this time without IRQ enabled masked. */ 194 write_zsreg(uap, R1, regs[R1]); 195 196 /* Enable interrupts */ 197 write_zsreg(uap, R9, regs[R9]); 198 } 199 200 /* 201 * We do like sunzilog to avoid disrupting pending Tx 202 * Reprogram the Zilog channel HW registers with the copies found in the 203 * software state struct. If the transmitter is busy, we defer this update 204 * until the next TX complete interrupt. Else, we do it right now. 205 * 206 * The UART port lock must be held and local interrupts disabled. 207 */ 208 static void pmz_maybe_update_regs(struct uart_pmac_port *uap) 209 { 210 if (!ZS_REGS_HELD(uap)) { 211 if (ZS_TX_ACTIVE(uap)) { 212 uap->flags |= PMACZILOG_FLAG_REGS_HELD; 213 } else { 214 pmz_debug("pmz: maybe_update_regs: updating\n"); 215 pmz_load_zsregs(uap, uap->curregs); 216 } 217 } 218 } 219 220 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable) 221 { 222 if (enable) { 223 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; 224 if (!ZS_IS_EXTCLK(uap)) 225 uap->curregs[1] |= EXT_INT_ENAB; 226 } else { 227 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 228 } 229 write_zsreg(uap, R1, uap->curregs[1]); 230 } 231 232 static bool pmz_receive_chars(struct uart_pmac_port *uap) 233 { 234 struct tty_port *port; 235 unsigned char ch, r1, drop, error, flag; 236 int loops = 0; 237 238 /* Sanity check, make sure the old bug is no longer happening */ 239 if (uap->port.state == NULL) { 240 WARN_ON(1); 241 (void)read_zsdata(uap); 242 return false; 243 } 244 port = &uap->port.state->port; 245 246 while (1) { 247 error = 0; 248 drop = 0; 249 250 r1 = read_zsreg(uap, R1); 251 ch = read_zsdata(uap); 252 253 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 254 write_zsreg(uap, R0, ERR_RES); 255 zssync(uap); 256 } 257 258 ch &= uap->parity_mask; 259 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { 260 uap->flags &= ~PMACZILOG_FLAG_BREAK; 261 } 262 263 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) 264 #ifdef USE_CTRL_O_SYSRQ 265 /* Handle the SysRq ^O Hack */ 266 if (ch == '\x0f') { 267 uap->port.sysrq = jiffies + HZ*5; 268 goto next_char; 269 } 270 #endif /* USE_CTRL_O_SYSRQ */ 271 if (uap->port.sysrq) { 272 int swallow; 273 spin_unlock(&uap->port.lock); 274 swallow = uart_handle_sysrq_char(&uap->port, ch); 275 spin_lock(&uap->port.lock); 276 if (swallow) 277 goto next_char; 278 } 279 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ 280 281 /* A real serial line, record the character and status. */ 282 if (drop) 283 goto next_char; 284 285 flag = TTY_NORMAL; 286 uap->port.icount.rx++; 287 288 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { 289 error = 1; 290 if (r1 & BRK_ABRT) { 291 pmz_debug("pmz: got break !\n"); 292 r1 &= ~(PAR_ERR | CRC_ERR); 293 uap->port.icount.brk++; 294 if (uart_handle_break(&uap->port)) 295 goto next_char; 296 } 297 else if (r1 & PAR_ERR) 298 uap->port.icount.parity++; 299 else if (r1 & CRC_ERR) 300 uap->port.icount.frame++; 301 if (r1 & Rx_OVR) 302 uap->port.icount.overrun++; 303 r1 &= uap->port.read_status_mask; 304 if (r1 & BRK_ABRT) 305 flag = TTY_BREAK; 306 else if (r1 & PAR_ERR) 307 flag = TTY_PARITY; 308 else if (r1 & CRC_ERR) 309 flag = TTY_FRAME; 310 } 311 312 if (uap->port.ignore_status_mask == 0xff || 313 (r1 & uap->port.ignore_status_mask) == 0) { 314 tty_insert_flip_char(port, ch, flag); 315 } 316 if (r1 & Rx_OVR) 317 tty_insert_flip_char(port, 0, TTY_OVERRUN); 318 next_char: 319 /* We can get stuck in an infinite loop getting char 0 when the 320 * line is in a wrong HW state, we break that here. 321 * When that happens, I disable the receive side of the driver. 322 * Note that what I've been experiencing is a real irq loop where 323 * I'm getting flooded regardless of the actual port speed. 324 * Something strange is going on with the HW 325 */ 326 if ((++loops) > 1000) 327 goto flood; 328 ch = read_zsreg(uap, R0); 329 if (!(ch & Rx_CH_AV)) 330 break; 331 } 332 333 return true; 334 flood: 335 pmz_interrupt_control(uap, 0); 336 pmz_error("pmz: rx irq flood !\n"); 337 return true; 338 } 339 340 static void pmz_status_handle(struct uart_pmac_port *uap) 341 { 342 unsigned char status; 343 344 status = read_zsreg(uap, R0); 345 write_zsreg(uap, R0, RES_EXT_INT); 346 zssync(uap); 347 348 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { 349 if (status & SYNC_HUNT) 350 uap->port.icount.dsr++; 351 352 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 353 * But it does not tell us which bit has changed, we have to keep 354 * track of this ourselves. 355 * The CTS input is inverted for some reason. -- paulus 356 */ 357 if ((status ^ uap->prev_status) & DCD) 358 uart_handle_dcd_change(&uap->port, 359 (status & DCD)); 360 if ((status ^ uap->prev_status) & CTS) 361 uart_handle_cts_change(&uap->port, 362 !(status & CTS)); 363 364 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 365 } 366 367 if (status & BRK_ABRT) 368 uap->flags |= PMACZILOG_FLAG_BREAK; 369 370 uap->prev_status = status; 371 } 372 373 static void pmz_transmit_chars(struct uart_pmac_port *uap) 374 { 375 struct circ_buf *xmit; 376 377 if (ZS_IS_CONS(uap)) { 378 unsigned char status = read_zsreg(uap, R0); 379 380 /* TX still busy? Just wait for the next TX done interrupt. 381 * 382 * It can occur because of how we do serial console writes. It would 383 * be nice to transmit console writes just like we normally would for 384 * a TTY line. (ie. buffered and TX interrupt driven). That is not 385 * easy because console writes cannot sleep. One solution might be 386 * to poll on enough port->xmit space becoming free. -DaveM 387 */ 388 if (!(status & Tx_BUF_EMP)) 389 return; 390 } 391 392 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; 393 394 if (ZS_REGS_HELD(uap)) { 395 pmz_load_zsregs(uap, uap->curregs); 396 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; 397 } 398 399 if (ZS_TX_STOPPED(uap)) { 400 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 401 goto ack_tx_int; 402 } 403 404 /* Under some circumstances, we see interrupts reported for 405 * a closed channel. The interrupt mask in R1 is clear, but 406 * R3 still signals the interrupts and we see them when taking 407 * an interrupt for the other channel (this could be a qemu 408 * bug but since the ESCC doc doesn't specify precsiely whether 409 * R3 interrup status bits are masked by R1 interrupt enable 410 * bits, better safe than sorry). --BenH. 411 */ 412 if (!ZS_IS_OPEN(uap)) 413 goto ack_tx_int; 414 415 if (uap->port.x_char) { 416 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 417 write_zsdata(uap, uap->port.x_char); 418 zssync(uap); 419 uap->port.icount.tx++; 420 uap->port.x_char = 0; 421 return; 422 } 423 424 if (uap->port.state == NULL) 425 goto ack_tx_int; 426 xmit = &uap->port.state->xmit; 427 if (uart_circ_empty(xmit)) { 428 uart_write_wakeup(&uap->port); 429 goto ack_tx_int; 430 } 431 if (uart_tx_stopped(&uap->port)) 432 goto ack_tx_int; 433 434 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 435 write_zsdata(uap, xmit->buf[xmit->tail]); 436 zssync(uap); 437 438 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 439 uap->port.icount.tx++; 440 441 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 442 uart_write_wakeup(&uap->port); 443 444 return; 445 446 ack_tx_int: 447 write_zsreg(uap, R0, RES_Tx_P); 448 zssync(uap); 449 } 450 451 /* Hrm... we register that twice, fixme later.... */ 452 static irqreturn_t pmz_interrupt(int irq, void *dev_id) 453 { 454 struct uart_pmac_port *uap = dev_id; 455 struct uart_pmac_port *uap_a; 456 struct uart_pmac_port *uap_b; 457 int rc = IRQ_NONE; 458 bool push; 459 u8 r3; 460 461 uap_a = pmz_get_port_A(uap); 462 uap_b = uap_a->mate; 463 464 spin_lock(&uap_a->port.lock); 465 r3 = read_zsreg(uap_a, R3); 466 467 #ifdef DEBUG_HARD 468 pmz_debug("irq, r3: %x\n", r3); 469 #endif 470 /* Channel A */ 471 push = false; 472 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 473 if (!ZS_IS_OPEN(uap_a)) { 474 pmz_debug("ChanA interrupt while not open !\n"); 475 goto skip_a; 476 } 477 write_zsreg(uap_a, R0, RES_H_IUS); 478 zssync(uap_a); 479 if (r3 & CHAEXT) 480 pmz_status_handle(uap_a); 481 if (r3 & CHARxIP) 482 push = pmz_receive_chars(uap_a); 483 if (r3 & CHATxIP) 484 pmz_transmit_chars(uap_a); 485 rc = IRQ_HANDLED; 486 } 487 skip_a: 488 spin_unlock(&uap_a->port.lock); 489 if (push) 490 tty_flip_buffer_push(&uap->port.state->port); 491 492 if (!uap_b) 493 goto out; 494 495 spin_lock(&uap_b->port.lock); 496 push = false; 497 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 498 if (!ZS_IS_OPEN(uap_b)) { 499 pmz_debug("ChanB interrupt while not open !\n"); 500 goto skip_b; 501 } 502 write_zsreg(uap_b, R0, RES_H_IUS); 503 zssync(uap_b); 504 if (r3 & CHBEXT) 505 pmz_status_handle(uap_b); 506 if (r3 & CHBRxIP) 507 push = pmz_receive_chars(uap_b); 508 if (r3 & CHBTxIP) 509 pmz_transmit_chars(uap_b); 510 rc = IRQ_HANDLED; 511 } 512 skip_b: 513 spin_unlock(&uap_b->port.lock); 514 if (push) 515 tty_flip_buffer_push(&uap->port.state->port); 516 517 out: 518 return rc; 519 } 520 521 /* 522 * Peek the status register, lock not held by caller 523 */ 524 static inline u8 pmz_peek_status(struct uart_pmac_port *uap) 525 { 526 unsigned long flags; 527 u8 status; 528 529 spin_lock_irqsave(&uap->port.lock, flags); 530 status = read_zsreg(uap, R0); 531 spin_unlock_irqrestore(&uap->port.lock, flags); 532 533 return status; 534 } 535 536 /* 537 * Check if transmitter is empty 538 * The port lock is not held. 539 */ 540 static unsigned int pmz_tx_empty(struct uart_port *port) 541 { 542 unsigned char status; 543 544 status = pmz_peek_status(to_pmz(port)); 545 if (status & Tx_BUF_EMP) 546 return TIOCSER_TEMT; 547 return 0; 548 } 549 550 /* 551 * Set Modem Control (RTS & DTR) bits 552 * The port lock is held and interrupts are disabled. 553 * Note: Shall we really filter out RTS on external ports or 554 * should that be dealt at higher level only ? 555 */ 556 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) 557 { 558 struct uart_pmac_port *uap = to_pmz(port); 559 unsigned char set_bits, clear_bits; 560 561 /* Do nothing for irda for now... */ 562 if (ZS_IS_IRDA(uap)) 563 return; 564 /* We get called during boot with a port not up yet */ 565 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) 566 return; 567 568 set_bits = clear_bits = 0; 569 570 if (ZS_IS_INTMODEM(uap)) { 571 if (mctrl & TIOCM_RTS) 572 set_bits |= RTS; 573 else 574 clear_bits |= RTS; 575 } 576 if (mctrl & TIOCM_DTR) 577 set_bits |= DTR; 578 else 579 clear_bits |= DTR; 580 581 /* NOTE: Not subject to 'transmitter active' rule. */ 582 uap->curregs[R5] |= set_bits; 583 uap->curregs[R5] &= ~clear_bits; 584 585 write_zsreg(uap, R5, uap->curregs[R5]); 586 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", 587 set_bits, clear_bits, uap->curregs[R5]); 588 zssync(uap); 589 } 590 591 /* 592 * Get Modem Control bits (only the input ones, the core will 593 * or that with a cached value of the control ones) 594 * The port lock is held and interrupts are disabled. 595 */ 596 static unsigned int pmz_get_mctrl(struct uart_port *port) 597 { 598 struct uart_pmac_port *uap = to_pmz(port); 599 unsigned char status; 600 unsigned int ret; 601 602 status = read_zsreg(uap, R0); 603 604 ret = 0; 605 if (status & DCD) 606 ret |= TIOCM_CAR; 607 if (status & SYNC_HUNT) 608 ret |= TIOCM_DSR; 609 if (!(status & CTS)) 610 ret |= TIOCM_CTS; 611 612 return ret; 613 } 614 615 /* 616 * Stop TX side. Dealt like sunzilog at next Tx interrupt, 617 * though for DMA, we will have to do a bit more. 618 * The port lock is held and interrupts are disabled. 619 */ 620 static void pmz_stop_tx(struct uart_port *port) 621 { 622 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; 623 } 624 625 /* 626 * Kick the Tx side. 627 * The port lock is held and interrupts are disabled. 628 */ 629 static void pmz_start_tx(struct uart_port *port) 630 { 631 struct uart_pmac_port *uap = to_pmz(port); 632 unsigned char status; 633 634 pmz_debug("pmz: start_tx()\n"); 635 636 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 637 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 638 639 status = read_zsreg(uap, R0); 640 641 /* TX busy? Just wait for the TX done interrupt. */ 642 if (!(status & Tx_BUF_EMP)) 643 return; 644 645 /* Send the first character to jump-start the TX done 646 * IRQ sending engine. 647 */ 648 if (port->x_char) { 649 write_zsdata(uap, port->x_char); 650 zssync(uap); 651 port->icount.tx++; 652 port->x_char = 0; 653 } else { 654 struct circ_buf *xmit = &port->state->xmit; 655 656 if (uart_circ_empty(xmit)) 657 goto out; 658 write_zsdata(uap, xmit->buf[xmit->tail]); 659 zssync(uap); 660 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 661 port->icount.tx++; 662 663 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 664 uart_write_wakeup(&uap->port); 665 } 666 out: 667 pmz_debug("pmz: start_tx() done.\n"); 668 } 669 670 /* 671 * Stop Rx side, basically disable emitting of 672 * Rx interrupts on the port. We don't disable the rx 673 * side of the chip proper though 674 * The port lock is held. 675 */ 676 static void pmz_stop_rx(struct uart_port *port) 677 { 678 struct uart_pmac_port *uap = to_pmz(port); 679 680 pmz_debug("pmz: stop_rx()()\n"); 681 682 /* Disable all RX interrupts. */ 683 uap->curregs[R1] &= ~RxINT_MASK; 684 pmz_maybe_update_regs(uap); 685 686 pmz_debug("pmz: stop_rx() done.\n"); 687 } 688 689 /* 690 * Enable modem status change interrupts 691 * The port lock is held. 692 */ 693 static void pmz_enable_ms(struct uart_port *port) 694 { 695 struct uart_pmac_port *uap = to_pmz(port); 696 unsigned char new_reg; 697 698 if (ZS_IS_IRDA(uap)) 699 return; 700 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 701 if (new_reg != uap->curregs[R15]) { 702 uap->curregs[R15] = new_reg; 703 704 /* NOTE: Not subject to 'transmitter active' rule. */ 705 write_zsreg(uap, R15, uap->curregs[R15]); 706 } 707 } 708 709 /* 710 * Control break state emission 711 * The port lock is not held. 712 */ 713 static void pmz_break_ctl(struct uart_port *port, int break_state) 714 { 715 struct uart_pmac_port *uap = to_pmz(port); 716 unsigned char set_bits, clear_bits, new_reg; 717 unsigned long flags; 718 719 set_bits = clear_bits = 0; 720 721 if (break_state) 722 set_bits |= SND_BRK; 723 else 724 clear_bits |= SND_BRK; 725 726 spin_lock_irqsave(&port->lock, flags); 727 728 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 729 if (new_reg != uap->curregs[R5]) { 730 uap->curregs[R5] = new_reg; 731 write_zsreg(uap, R5, uap->curregs[R5]); 732 } 733 734 spin_unlock_irqrestore(&port->lock, flags); 735 } 736 737 #ifdef CONFIG_PPC_PMAC 738 739 /* 740 * Turn power on or off to the SCC and associated stuff 741 * (port drivers, modem, IR port, etc.) 742 * Returns the number of milliseconds we should wait before 743 * trying to use the port. 744 */ 745 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 746 { 747 int delay = 0; 748 int rc; 749 750 if (state) { 751 rc = pmac_call_feature( 752 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); 753 pmz_debug("port power on result: %d\n", rc); 754 if (ZS_IS_INTMODEM(uap)) { 755 rc = pmac_call_feature( 756 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); 757 delay = 2500; /* wait for 2.5s before using */ 758 pmz_debug("modem power result: %d\n", rc); 759 } 760 } else { 761 /* TODO: Make that depend on a timer, don't power down 762 * immediately 763 */ 764 if (ZS_IS_INTMODEM(uap)) { 765 rc = pmac_call_feature( 766 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); 767 pmz_debug("port power off result: %d\n", rc); 768 } 769 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); 770 } 771 return delay; 772 } 773 774 #else 775 776 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 777 { 778 return 0; 779 } 780 781 #endif /* !CONFIG_PPC_PMAC */ 782 783 /* 784 * FixZeroBug....Works around a bug in the SCC receiving channel. 785 * Inspired from Darwin code, 15 Sept. 2000 -DanM 786 * 787 * The following sequence prevents a problem that is seen with O'Hare ASICs 788 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero 789 * at the input to the receiver becomes 'stuck' and locks up the receiver. 790 * This problem can occur as a result of a zero bit at the receiver input 791 * coincident with any of the following events: 792 * 793 * The SCC is initialized (hardware or software). 794 * A framing error is detected. 795 * The clocking option changes from synchronous or X1 asynchronous 796 * clocking to X16, X32, or X64 asynchronous clocking. 797 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. 798 * 799 * This workaround attempts to recover from the lockup condition by placing 800 * the SCC in synchronous loopback mode with a fast clock before programming 801 * any of the asynchronous modes. 802 */ 803 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) 804 { 805 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 806 zssync(uap); 807 udelay(10); 808 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); 809 zssync(uap); 810 811 write_zsreg(uap, 4, X1CLK | MONSYNC); 812 write_zsreg(uap, 3, Rx8); 813 write_zsreg(uap, 5, Tx8 | RTS); 814 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ 815 write_zsreg(uap, 11, RCBR | TCBR); 816 write_zsreg(uap, 12, 0); 817 write_zsreg(uap, 13, 0); 818 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); 819 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); 820 write_zsreg(uap, 3, Rx8 | RxENABLE); 821 write_zsreg(uap, 0, RES_EXT_INT); 822 write_zsreg(uap, 0, RES_EXT_INT); 823 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ 824 825 /* The channel should be OK now, but it is probably receiving 826 * loopback garbage. 827 * Switch to asynchronous mode, disable the receiver, 828 * and discard everything in the receive buffer. 829 */ 830 write_zsreg(uap, 9, NV); 831 write_zsreg(uap, 4, X16CLK | SB_MASK); 832 write_zsreg(uap, 3, Rx8); 833 834 while (read_zsreg(uap, 0) & Rx_CH_AV) { 835 (void)read_zsreg(uap, 8); 836 write_zsreg(uap, 0, RES_EXT_INT); 837 write_zsreg(uap, 0, ERR_RES); 838 } 839 } 840 841 /* 842 * Real startup routine, powers up the hardware and sets up 843 * the SCC. Returns a delay in ms where you need to wait before 844 * actually using the port, this is typically the internal modem 845 * powerup delay. This routine expect the lock to be taken. 846 */ 847 static int __pmz_startup(struct uart_pmac_port *uap) 848 { 849 int pwr_delay = 0; 850 851 memset(&uap->curregs, 0, sizeof(uap->curregs)); 852 853 /* Power up the SCC & underlying hardware (modem/irda) */ 854 pwr_delay = pmz_set_scc_power(uap, 1); 855 856 /* Nice buggy HW ... */ 857 pmz_fix_zero_bug_scc(uap); 858 859 /* Reset the channel */ 860 uap->curregs[R9] = 0; 861 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 862 zssync(uap); 863 udelay(10); 864 write_zsreg(uap, 9, 0); 865 zssync(uap); 866 867 /* Clear the interrupt registers */ 868 write_zsreg(uap, R1, 0); 869 write_zsreg(uap, R0, ERR_RES); 870 write_zsreg(uap, R0, ERR_RES); 871 write_zsreg(uap, R0, RES_H_IUS); 872 write_zsreg(uap, R0, RES_H_IUS); 873 874 /* Setup some valid baud rate */ 875 uap->curregs[R4] = X16CLK | SB1; 876 uap->curregs[R3] = Rx8; 877 uap->curregs[R5] = Tx8 | RTS; 878 if (!ZS_IS_IRDA(uap)) 879 uap->curregs[R5] |= DTR; 880 uap->curregs[R12] = 0; 881 uap->curregs[R13] = 0; 882 uap->curregs[R14] = BRENAB; 883 884 /* Clear handshaking, enable BREAK interrupts */ 885 uap->curregs[R15] = BRKIE; 886 887 /* Master interrupt enable */ 888 uap->curregs[R9] |= NV | MIE; 889 890 pmz_load_zsregs(uap, uap->curregs); 891 892 /* Enable receiver and transmitter. */ 893 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); 894 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); 895 896 /* Remember status for DCD/CTS changes */ 897 uap->prev_status = read_zsreg(uap, R0); 898 899 return pwr_delay; 900 } 901 902 static void pmz_irda_reset(struct uart_pmac_port *uap) 903 { 904 unsigned long flags; 905 906 spin_lock_irqsave(&uap->port.lock, flags); 907 uap->curregs[R5] |= DTR; 908 write_zsreg(uap, R5, uap->curregs[R5]); 909 zssync(uap); 910 spin_unlock_irqrestore(&uap->port.lock, flags); 911 msleep(110); 912 913 spin_lock_irqsave(&uap->port.lock, flags); 914 uap->curregs[R5] &= ~DTR; 915 write_zsreg(uap, R5, uap->curregs[R5]); 916 zssync(uap); 917 spin_unlock_irqrestore(&uap->port.lock, flags); 918 msleep(10); 919 } 920 921 /* 922 * This is the "normal" startup routine, using the above one 923 * wrapped with the lock and doing a schedule delay 924 */ 925 static int pmz_startup(struct uart_port *port) 926 { 927 struct uart_pmac_port *uap = to_pmz(port); 928 unsigned long flags; 929 int pwr_delay = 0; 930 931 pmz_debug("pmz: startup()\n"); 932 933 uap->flags |= PMACZILOG_FLAG_IS_OPEN; 934 935 /* A console is never powered down. Else, power up and 936 * initialize the chip 937 */ 938 if (!ZS_IS_CONS(uap)) { 939 spin_lock_irqsave(&port->lock, flags); 940 pwr_delay = __pmz_startup(uap); 941 spin_unlock_irqrestore(&port->lock, flags); 942 } 943 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line); 944 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, 945 uap->irq_name, uap)) { 946 pmz_error("Unable to register zs interrupt handler.\n"); 947 pmz_set_scc_power(uap, 0); 948 return -ENXIO; 949 } 950 951 /* Right now, we deal with delay by blocking here, I'll be 952 * smarter later on 953 */ 954 if (pwr_delay != 0) { 955 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 956 msleep(pwr_delay); 957 } 958 959 /* IrDA reset is done now */ 960 if (ZS_IS_IRDA(uap)) 961 pmz_irda_reset(uap); 962 963 /* Enable interrupt requests for the channel */ 964 spin_lock_irqsave(&port->lock, flags); 965 pmz_interrupt_control(uap, 1); 966 spin_unlock_irqrestore(&port->lock, flags); 967 968 pmz_debug("pmz: startup() done.\n"); 969 970 return 0; 971 } 972 973 static void pmz_shutdown(struct uart_port *port) 974 { 975 struct uart_pmac_port *uap = to_pmz(port); 976 unsigned long flags; 977 978 pmz_debug("pmz: shutdown()\n"); 979 980 spin_lock_irqsave(&port->lock, flags); 981 982 /* Disable interrupt requests for the channel */ 983 pmz_interrupt_control(uap, 0); 984 985 if (!ZS_IS_CONS(uap)) { 986 /* Disable receiver and transmitter */ 987 uap->curregs[R3] &= ~RxENABLE; 988 uap->curregs[R5] &= ~TxENABLE; 989 990 /* Disable break assertion */ 991 uap->curregs[R5] &= ~SND_BRK; 992 pmz_maybe_update_regs(uap); 993 } 994 995 spin_unlock_irqrestore(&port->lock, flags); 996 997 /* Release interrupt handler */ 998 free_irq(uap->port.irq, uap); 999 1000 spin_lock_irqsave(&port->lock, flags); 1001 1002 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 1003 1004 if (!ZS_IS_CONS(uap)) 1005 pmz_set_scc_power(uap, 0); /* Shut the chip down */ 1006 1007 spin_unlock_irqrestore(&port->lock, flags); 1008 1009 pmz_debug("pmz: shutdown() done.\n"); 1010 } 1011 1012 /* Shared by TTY driver and serial console setup. The port lock is held 1013 * and local interrupts are disabled. 1014 */ 1015 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, 1016 unsigned int iflag, unsigned long baud) 1017 { 1018 int brg; 1019 1020 /* Switch to external clocking for IrDA high clock rates. That 1021 * code could be re-used for Midi interfaces with different 1022 * multipliers 1023 */ 1024 if (baud >= 115200 && ZS_IS_IRDA(uap)) { 1025 uap->curregs[R4] = X1CLK; 1026 uap->curregs[R11] = RCTRxCP | TCTRxCP; 1027 uap->curregs[R14] = 0; /* BRG off */ 1028 uap->curregs[R12] = 0; 1029 uap->curregs[R13] = 0; 1030 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; 1031 } else { 1032 switch (baud) { 1033 case ZS_CLOCK/16: /* 230400 */ 1034 uap->curregs[R4] = X16CLK; 1035 uap->curregs[R11] = 0; 1036 uap->curregs[R14] = 0; 1037 break; 1038 case ZS_CLOCK/32: /* 115200 */ 1039 uap->curregs[R4] = X32CLK; 1040 uap->curregs[R11] = 0; 1041 uap->curregs[R14] = 0; 1042 break; 1043 default: 1044 uap->curregs[R4] = X16CLK; 1045 uap->curregs[R11] = TCBR | RCBR; 1046 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); 1047 uap->curregs[R12] = (brg & 255); 1048 uap->curregs[R13] = ((brg >> 8) & 255); 1049 uap->curregs[R14] = BRENAB; 1050 } 1051 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; 1052 } 1053 1054 /* Character size, stop bits, and parity. */ 1055 uap->curregs[3] &= ~RxN_MASK; 1056 uap->curregs[5] &= ~TxN_MASK; 1057 1058 switch (cflag & CSIZE) { 1059 case CS5: 1060 uap->curregs[3] |= Rx5; 1061 uap->curregs[5] |= Tx5; 1062 uap->parity_mask = 0x1f; 1063 break; 1064 case CS6: 1065 uap->curregs[3] |= Rx6; 1066 uap->curregs[5] |= Tx6; 1067 uap->parity_mask = 0x3f; 1068 break; 1069 case CS7: 1070 uap->curregs[3] |= Rx7; 1071 uap->curregs[5] |= Tx7; 1072 uap->parity_mask = 0x7f; 1073 break; 1074 case CS8: 1075 default: 1076 uap->curregs[3] |= Rx8; 1077 uap->curregs[5] |= Tx8; 1078 uap->parity_mask = 0xff; 1079 break; 1080 } 1081 uap->curregs[4] &= ~(SB_MASK); 1082 if (cflag & CSTOPB) 1083 uap->curregs[4] |= SB2; 1084 else 1085 uap->curregs[4] |= SB1; 1086 if (cflag & PARENB) 1087 uap->curregs[4] |= PAR_ENAB; 1088 else 1089 uap->curregs[4] &= ~PAR_ENAB; 1090 if (!(cflag & PARODD)) 1091 uap->curregs[4] |= PAR_EVEN; 1092 else 1093 uap->curregs[4] &= ~PAR_EVEN; 1094 1095 uap->port.read_status_mask = Rx_OVR; 1096 if (iflag & INPCK) 1097 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; 1098 if (iflag & (IGNBRK | BRKINT | PARMRK)) 1099 uap->port.read_status_mask |= BRK_ABRT; 1100 1101 uap->port.ignore_status_mask = 0; 1102 if (iflag & IGNPAR) 1103 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 1104 if (iflag & IGNBRK) { 1105 uap->port.ignore_status_mask |= BRK_ABRT; 1106 if (iflag & IGNPAR) 1107 uap->port.ignore_status_mask |= Rx_OVR; 1108 } 1109 1110 if ((cflag & CREAD) == 0) 1111 uap->port.ignore_status_mask = 0xff; 1112 } 1113 1114 1115 /* 1116 * Set the irda codec on the imac to the specified baud rate. 1117 */ 1118 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) 1119 { 1120 u8 cmdbyte; 1121 int t, version; 1122 1123 switch (*baud) { 1124 /* SIR modes */ 1125 case 2400: 1126 cmdbyte = 0x53; 1127 break; 1128 case 4800: 1129 cmdbyte = 0x52; 1130 break; 1131 case 9600: 1132 cmdbyte = 0x51; 1133 break; 1134 case 19200: 1135 cmdbyte = 0x50; 1136 break; 1137 case 38400: 1138 cmdbyte = 0x4f; 1139 break; 1140 case 57600: 1141 cmdbyte = 0x4e; 1142 break; 1143 case 115200: 1144 cmdbyte = 0x4d; 1145 break; 1146 /* The FIR modes aren't really supported at this point, how 1147 * do we select the speed ? via the FCR on KeyLargo ? 1148 */ 1149 case 1152000: 1150 cmdbyte = 0; 1151 break; 1152 case 4000000: 1153 cmdbyte = 0; 1154 break; 1155 default: /* 9600 */ 1156 cmdbyte = 0x51; 1157 *baud = 9600; 1158 break; 1159 } 1160 1161 /* Wait for transmitter to drain */ 1162 t = 10000; 1163 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 1164 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { 1165 if (--t <= 0) { 1166 pmz_error("transmitter didn't drain\n"); 1167 return; 1168 } 1169 udelay(10); 1170 } 1171 1172 /* Drain the receiver too */ 1173 t = 100; 1174 (void)read_zsdata(uap); 1175 (void)read_zsdata(uap); 1176 (void)read_zsdata(uap); 1177 mdelay(10); 1178 while (read_zsreg(uap, R0) & Rx_CH_AV) { 1179 read_zsdata(uap); 1180 mdelay(10); 1181 if (--t <= 0) { 1182 pmz_error("receiver didn't drain\n"); 1183 return; 1184 } 1185 } 1186 1187 /* Switch to command mode */ 1188 uap->curregs[R5] |= DTR; 1189 write_zsreg(uap, R5, uap->curregs[R5]); 1190 zssync(uap); 1191 mdelay(1); 1192 1193 /* Switch SCC to 19200 */ 1194 pmz_convert_to_zs(uap, CS8, 0, 19200); 1195 pmz_load_zsregs(uap, uap->curregs); 1196 mdelay(1); 1197 1198 /* Write get_version command byte */ 1199 write_zsdata(uap, 1); 1200 t = 5000; 1201 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1202 if (--t <= 0) { 1203 pmz_error("irda_setup timed out on get_version byte\n"); 1204 goto out; 1205 } 1206 udelay(10); 1207 } 1208 version = read_zsdata(uap); 1209 1210 if (version < 4) { 1211 pmz_info("IrDA: dongle version %d not supported\n", version); 1212 goto out; 1213 } 1214 1215 /* Send speed mode */ 1216 write_zsdata(uap, cmdbyte); 1217 t = 5000; 1218 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1219 if (--t <= 0) { 1220 pmz_error("irda_setup timed out on speed mode byte\n"); 1221 goto out; 1222 } 1223 udelay(10); 1224 } 1225 t = read_zsdata(uap); 1226 if (t != cmdbyte) 1227 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); 1228 1229 pmz_info("IrDA setup for %ld bps, dongle version: %d\n", 1230 *baud, version); 1231 1232 (void)read_zsdata(uap); 1233 (void)read_zsdata(uap); 1234 (void)read_zsdata(uap); 1235 1236 out: 1237 /* Switch back to data mode */ 1238 uap->curregs[R5] &= ~DTR; 1239 write_zsreg(uap, R5, uap->curregs[R5]); 1240 zssync(uap); 1241 1242 (void)read_zsdata(uap); 1243 (void)read_zsdata(uap); 1244 (void)read_zsdata(uap); 1245 } 1246 1247 1248 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1249 struct ktermios *old) 1250 { 1251 struct uart_pmac_port *uap = to_pmz(port); 1252 unsigned long baud; 1253 1254 pmz_debug("pmz: set_termios()\n"); 1255 1256 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); 1257 1258 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds 1259 * on the IR dongle. Note that the IRTTY driver currently doesn't know 1260 * about the FIR mode and high speed modes. So these are unused. For 1261 * implementing proper support for these, we should probably add some 1262 * DMA as well, at least on the Rx side, which isn't a simple thing 1263 * at this point. 1264 */ 1265 if (ZS_IS_IRDA(uap)) { 1266 /* Calc baud rate */ 1267 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); 1268 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); 1269 /* Cet the irda codec to the right rate */ 1270 pmz_irda_setup(uap, &baud); 1271 /* Set final baud rate */ 1272 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1273 pmz_load_zsregs(uap, uap->curregs); 1274 zssync(uap); 1275 } else { 1276 baud = uart_get_baud_rate(port, termios, old, 1200, 230400); 1277 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1278 /* Make sure modem status interrupts are correctly configured */ 1279 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { 1280 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; 1281 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; 1282 } else { 1283 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); 1284 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; 1285 } 1286 1287 /* Load registers to the chip */ 1288 pmz_maybe_update_regs(uap); 1289 } 1290 uart_update_timeout(port, termios->c_cflag, baud); 1291 1292 pmz_debug("pmz: set_termios() done.\n"); 1293 } 1294 1295 /* The port lock is not held. */ 1296 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1297 struct ktermios *old) 1298 { 1299 struct uart_pmac_port *uap = to_pmz(port); 1300 unsigned long flags; 1301 1302 spin_lock_irqsave(&port->lock, flags); 1303 1304 /* Disable IRQs on the port */ 1305 pmz_interrupt_control(uap, 0); 1306 1307 /* Setup new port configuration */ 1308 __pmz_set_termios(port, termios, old); 1309 1310 /* Re-enable IRQs on the port */ 1311 if (ZS_IS_OPEN(uap)) 1312 pmz_interrupt_control(uap, 1); 1313 1314 spin_unlock_irqrestore(&port->lock, flags); 1315 } 1316 1317 static const char *pmz_type(struct uart_port *port) 1318 { 1319 struct uart_pmac_port *uap = to_pmz(port); 1320 1321 if (ZS_IS_IRDA(uap)) 1322 return "Z85c30 ESCC - Infrared port"; 1323 else if (ZS_IS_INTMODEM(uap)) 1324 return "Z85c30 ESCC - Internal modem"; 1325 return "Z85c30 ESCC - Serial port"; 1326 } 1327 1328 /* We do not request/release mappings of the registers here, this 1329 * happens at early serial probe time. 1330 */ 1331 static void pmz_release_port(struct uart_port *port) 1332 { 1333 } 1334 1335 static int pmz_request_port(struct uart_port *port) 1336 { 1337 return 0; 1338 } 1339 1340 /* These do not need to do anything interesting either. */ 1341 static void pmz_config_port(struct uart_port *port, int flags) 1342 { 1343 } 1344 1345 /* We do not support letting the user mess with the divisor, IRQ, etc. */ 1346 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) 1347 { 1348 return -EINVAL; 1349 } 1350 1351 #ifdef CONFIG_CONSOLE_POLL 1352 1353 static int pmz_poll_get_char(struct uart_port *port) 1354 { 1355 struct uart_pmac_port *uap = 1356 container_of(port, struct uart_pmac_port, port); 1357 int tries = 2; 1358 1359 while (tries) { 1360 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0) 1361 return read_zsdata(uap); 1362 if (tries--) 1363 udelay(5); 1364 } 1365 1366 return NO_POLL_CHAR; 1367 } 1368 1369 static void pmz_poll_put_char(struct uart_port *port, unsigned char c) 1370 { 1371 struct uart_pmac_port *uap = 1372 container_of(port, struct uart_pmac_port, port); 1373 1374 /* Wait for the transmit buffer to empty. */ 1375 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1376 udelay(5); 1377 write_zsdata(uap, c); 1378 } 1379 1380 #endif /* CONFIG_CONSOLE_POLL */ 1381 1382 static const struct uart_ops pmz_pops = { 1383 .tx_empty = pmz_tx_empty, 1384 .set_mctrl = pmz_set_mctrl, 1385 .get_mctrl = pmz_get_mctrl, 1386 .stop_tx = pmz_stop_tx, 1387 .start_tx = pmz_start_tx, 1388 .stop_rx = pmz_stop_rx, 1389 .enable_ms = pmz_enable_ms, 1390 .break_ctl = pmz_break_ctl, 1391 .startup = pmz_startup, 1392 .shutdown = pmz_shutdown, 1393 .set_termios = pmz_set_termios, 1394 .type = pmz_type, 1395 .release_port = pmz_release_port, 1396 .request_port = pmz_request_port, 1397 .config_port = pmz_config_port, 1398 .verify_port = pmz_verify_port, 1399 #ifdef CONFIG_CONSOLE_POLL 1400 .poll_get_char = pmz_poll_get_char, 1401 .poll_put_char = pmz_poll_put_char, 1402 #endif 1403 }; 1404 1405 #ifdef CONFIG_PPC_PMAC 1406 1407 /* 1408 * Setup one port structure after probing, HW is down at this point, 1409 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't 1410 * register our console before uart_add_one_port() is called 1411 */ 1412 static int __init pmz_init_port(struct uart_pmac_port *uap) 1413 { 1414 struct device_node *np = uap->node; 1415 const char *conn; 1416 const struct slot_names_prop { 1417 int count; 1418 char name[1]; 1419 } *slots; 1420 int len; 1421 struct resource r_ports, r_rxdma, r_txdma; 1422 1423 /* 1424 * Request & map chip registers 1425 */ 1426 if (of_address_to_resource(np, 0, &r_ports)) 1427 return -ENODEV; 1428 uap->port.mapbase = r_ports.start; 1429 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); 1430 1431 uap->control_reg = uap->port.membase; 1432 uap->data_reg = uap->control_reg + 0x10; 1433 1434 /* 1435 * Request & map DBDMA registers 1436 */ 1437 #ifdef HAS_DBDMA 1438 if (of_address_to_resource(np, 1, &r_txdma) == 0 && 1439 of_address_to_resource(np, 2, &r_rxdma) == 0) 1440 uap->flags |= PMACZILOG_FLAG_HAS_DMA; 1441 #else 1442 memset(&r_txdma, 0, sizeof(struct resource)); 1443 memset(&r_rxdma, 0, sizeof(struct resource)); 1444 #endif 1445 if (ZS_HAS_DMA(uap)) { 1446 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); 1447 if (uap->tx_dma_regs == NULL) { 1448 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1449 goto no_dma; 1450 } 1451 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); 1452 if (uap->rx_dma_regs == NULL) { 1453 iounmap(uap->tx_dma_regs); 1454 uap->tx_dma_regs = NULL; 1455 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1456 goto no_dma; 1457 } 1458 uap->tx_dma_irq = irq_of_parse_and_map(np, 1); 1459 uap->rx_dma_irq = irq_of_parse_and_map(np, 2); 1460 } 1461 no_dma: 1462 1463 /* 1464 * Detect port type 1465 */ 1466 if (of_device_is_compatible(np, "cobalt")) 1467 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1468 conn = of_get_property(np, "AAPL,connector", &len); 1469 if (conn && (strcmp(conn, "infrared") == 0)) 1470 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1471 uap->port_type = PMAC_SCC_ASYNC; 1472 /* 1999 Powerbook G3 has slot-names property instead */ 1473 slots = of_get_property(np, "slot-names", &len); 1474 if (slots && slots->count > 0) { 1475 if (strcmp(slots->name, "IrDA") == 0) 1476 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1477 else if (strcmp(slots->name, "Modem") == 0) 1478 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1479 } 1480 if (ZS_IS_IRDA(uap)) 1481 uap->port_type = PMAC_SCC_IRDA; 1482 if (ZS_IS_INTMODEM(uap)) { 1483 struct device_node* i2c_modem = 1484 of_find_node_by_name(NULL, "i2c-modem"); 1485 if (i2c_modem) { 1486 const char* mid = 1487 of_get_property(i2c_modem, "modem-id", NULL); 1488 if (mid) switch(*mid) { 1489 case 0x04 : 1490 case 0x05 : 1491 case 0x07 : 1492 case 0x08 : 1493 case 0x0b : 1494 case 0x0c : 1495 uap->port_type = PMAC_SCC_I2S1; 1496 } 1497 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", 1498 mid ? (*mid) : 0); 1499 of_node_put(i2c_modem); 1500 } else { 1501 printk(KERN_INFO "pmac_zilog: serial modem detected\n"); 1502 } 1503 } 1504 1505 /* 1506 * Init remaining bits of "port" structure 1507 */ 1508 uap->port.iotype = UPIO_MEM; 1509 uap->port.irq = irq_of_parse_and_map(np, 0); 1510 uap->port.uartclk = ZS_CLOCK; 1511 uap->port.fifosize = 1; 1512 uap->port.ops = &pmz_pops; 1513 uap->port.type = PORT_PMAC_ZILOG; 1514 uap->port.flags = 0; 1515 1516 /* 1517 * Fixup for the port on Gatwick for which the device-tree has 1518 * missing interrupts. Normally, the macio_dev would contain 1519 * fixed up interrupt info, but we use the device-tree directly 1520 * here due to early probing so we need the fixup too. 1521 */ 1522 if (uap->port.irq == 0 && 1523 np->parent && np->parent->parent && 1524 of_device_is_compatible(np->parent->parent, "gatwick")) { 1525 /* IRQs on gatwick are offset by 64 */ 1526 uap->port.irq = irq_create_mapping(NULL, 64 + 15); 1527 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); 1528 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); 1529 } 1530 1531 /* Setup some valid baud rate information in the register 1532 * shadows so we don't write crap there before baud rate is 1533 * first initialized. 1534 */ 1535 pmz_convert_to_zs(uap, CS8, 0, 9600); 1536 1537 return 0; 1538 } 1539 1540 /* 1541 * Get rid of a port on module removal 1542 */ 1543 static void pmz_dispose_port(struct uart_pmac_port *uap) 1544 { 1545 struct device_node *np; 1546 1547 np = uap->node; 1548 iounmap(uap->rx_dma_regs); 1549 iounmap(uap->tx_dma_regs); 1550 iounmap(uap->control_reg); 1551 uap->node = NULL; 1552 of_node_put(np); 1553 memset(uap, 0, sizeof(struct uart_pmac_port)); 1554 } 1555 1556 /* 1557 * Called upon match with an escc node in the device-tree. 1558 */ 1559 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) 1560 { 1561 struct uart_pmac_port *uap; 1562 int i; 1563 1564 /* Iterate the pmz_ports array to find a matching entry 1565 */ 1566 for (i = 0; i < MAX_ZS_PORTS; i++) 1567 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) 1568 break; 1569 if (i >= MAX_ZS_PORTS) 1570 return -ENODEV; 1571 1572 1573 uap = &pmz_ports[i]; 1574 uap->dev = mdev; 1575 uap->port.dev = &mdev->ofdev.dev; 1576 dev_set_drvdata(&mdev->ofdev.dev, uap); 1577 1578 /* We still activate the port even when failing to request resources 1579 * to work around bugs in ancient Apple device-trees 1580 */ 1581 if (macio_request_resources(uap->dev, "pmac_zilog")) 1582 printk(KERN_WARNING "%s: Failed to request resource" 1583 ", port still active\n", 1584 uap->node->name); 1585 else 1586 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; 1587 1588 return uart_add_one_port(&pmz_uart_reg, &uap->port); 1589 } 1590 1591 /* 1592 * That one should not be called, macio isn't really a hotswap device, 1593 * we don't expect one of those serial ports to go away... 1594 */ 1595 static int pmz_detach(struct macio_dev *mdev) 1596 { 1597 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1598 1599 if (!uap) 1600 return -ENODEV; 1601 1602 uart_remove_one_port(&pmz_uart_reg, &uap->port); 1603 1604 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { 1605 macio_release_resources(uap->dev); 1606 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; 1607 } 1608 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1609 uap->dev = NULL; 1610 uap->port.dev = NULL; 1611 1612 return 0; 1613 } 1614 1615 1616 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) 1617 { 1618 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1619 1620 if (uap == NULL) { 1621 printk("HRM... pmz_suspend with NULL uap\n"); 1622 return 0; 1623 } 1624 1625 uart_suspend_port(&pmz_uart_reg, &uap->port); 1626 1627 return 0; 1628 } 1629 1630 1631 static int pmz_resume(struct macio_dev *mdev) 1632 { 1633 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1634 1635 if (uap == NULL) 1636 return 0; 1637 1638 uart_resume_port(&pmz_uart_reg, &uap->port); 1639 1640 return 0; 1641 } 1642 1643 /* 1644 * Probe all ports in the system and build the ports array, we register 1645 * with the serial layer later, so we get a proper struct device which 1646 * allows the tty to attach properly. This is later than it used to be 1647 * but the tty layer really wants it that way. 1648 */ 1649 static int __init pmz_probe(void) 1650 { 1651 struct device_node *node_p, *node_a, *node_b, *np; 1652 int count = 0; 1653 int rc; 1654 1655 /* 1656 * Find all escc chips in the system 1657 */ 1658 for_each_node_by_name(node_p, "escc") { 1659 /* 1660 * First get channel A/B node pointers 1661 * 1662 * TODO: Add routines with proper locking to do that... 1663 */ 1664 node_a = node_b = NULL; 1665 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { 1666 if (strncmp(np->name, "ch-a", 4) == 0) 1667 node_a = of_node_get(np); 1668 else if (strncmp(np->name, "ch-b", 4) == 0) 1669 node_b = of_node_get(np); 1670 } 1671 if (!node_a && !node_b) { 1672 of_node_put(node_a); 1673 of_node_put(node_b); 1674 printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n", 1675 (!node_a) ? 'a' : 'b', node_p->full_name); 1676 continue; 1677 } 1678 1679 /* 1680 * Fill basic fields in the port structures 1681 */ 1682 if (node_b != NULL) { 1683 pmz_ports[count].mate = &pmz_ports[count+1]; 1684 pmz_ports[count+1].mate = &pmz_ports[count]; 1685 } 1686 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1687 pmz_ports[count].node = node_a; 1688 pmz_ports[count+1].node = node_b; 1689 pmz_ports[count].port.line = count; 1690 pmz_ports[count+1].port.line = count+1; 1691 1692 /* 1693 * Setup the ports for real 1694 */ 1695 rc = pmz_init_port(&pmz_ports[count]); 1696 if (rc == 0 && node_b != NULL) 1697 rc = pmz_init_port(&pmz_ports[count+1]); 1698 if (rc != 0) { 1699 of_node_put(node_a); 1700 of_node_put(node_b); 1701 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); 1702 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); 1703 continue; 1704 } 1705 count += 2; 1706 } 1707 pmz_ports_count = count; 1708 1709 return 0; 1710 } 1711 1712 #else 1713 1714 extern struct platform_device scc_a_pdev, scc_b_pdev; 1715 1716 static int __init pmz_init_port(struct uart_pmac_port *uap) 1717 { 1718 struct resource *r_ports; 1719 int irq; 1720 1721 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0); 1722 irq = platform_get_irq(uap->pdev, 0); 1723 if (!r_ports || irq <= 0) 1724 return -ENODEV; 1725 1726 uap->port.mapbase = r_ports->start; 1727 uap->port.membase = (unsigned char __iomem *) r_ports->start; 1728 uap->port.iotype = UPIO_MEM; 1729 uap->port.irq = irq; 1730 uap->port.uartclk = ZS_CLOCK; 1731 uap->port.fifosize = 1; 1732 uap->port.ops = &pmz_pops; 1733 uap->port.type = PORT_PMAC_ZILOG; 1734 uap->port.flags = 0; 1735 1736 uap->control_reg = uap->port.membase; 1737 uap->data_reg = uap->control_reg + 4; 1738 uap->port_type = 0; 1739 1740 pmz_convert_to_zs(uap, CS8, 0, 9600); 1741 1742 return 0; 1743 } 1744 1745 static int __init pmz_probe(void) 1746 { 1747 int err; 1748 1749 pmz_ports_count = 0; 1750 1751 pmz_ports[0].port.line = 0; 1752 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1753 pmz_ports[0].pdev = &scc_a_pdev; 1754 err = pmz_init_port(&pmz_ports[0]); 1755 if (err) 1756 return err; 1757 pmz_ports_count++; 1758 1759 pmz_ports[0].mate = &pmz_ports[1]; 1760 pmz_ports[1].mate = &pmz_ports[0]; 1761 pmz_ports[1].port.line = 1; 1762 pmz_ports[1].flags = 0; 1763 pmz_ports[1].pdev = &scc_b_pdev; 1764 err = pmz_init_port(&pmz_ports[1]); 1765 if (err) 1766 return err; 1767 pmz_ports_count++; 1768 1769 return 0; 1770 } 1771 1772 static void pmz_dispose_port(struct uart_pmac_port *uap) 1773 { 1774 memset(uap, 0, sizeof(struct uart_pmac_port)); 1775 } 1776 1777 static int __init pmz_attach(struct platform_device *pdev) 1778 { 1779 struct uart_pmac_port *uap; 1780 int i; 1781 1782 /* Iterate the pmz_ports array to find a matching entry */ 1783 for (i = 0; i < pmz_ports_count; i++) 1784 if (pmz_ports[i].pdev == pdev) 1785 break; 1786 if (i >= pmz_ports_count) 1787 return -ENODEV; 1788 1789 uap = &pmz_ports[i]; 1790 uap->port.dev = &pdev->dev; 1791 platform_set_drvdata(pdev, uap); 1792 1793 return uart_add_one_port(&pmz_uart_reg, &uap->port); 1794 } 1795 1796 static int __exit pmz_detach(struct platform_device *pdev) 1797 { 1798 struct uart_pmac_port *uap = platform_get_drvdata(pdev); 1799 1800 if (!uap) 1801 return -ENODEV; 1802 1803 uart_remove_one_port(&pmz_uart_reg, &uap->port); 1804 1805 uap->port.dev = NULL; 1806 1807 return 0; 1808 } 1809 1810 #endif /* !CONFIG_PPC_PMAC */ 1811 1812 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1813 1814 static void pmz_console_write(struct console *con, const char *s, unsigned int count); 1815 static int __init pmz_console_setup(struct console *co, char *options); 1816 1817 static struct console pmz_console = { 1818 .name = PMACZILOG_NAME, 1819 .write = pmz_console_write, 1820 .device = uart_console_device, 1821 .setup = pmz_console_setup, 1822 .flags = CON_PRINTBUFFER, 1823 .index = -1, 1824 .data = &pmz_uart_reg, 1825 }; 1826 1827 #define PMACZILOG_CONSOLE &pmz_console 1828 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1829 #define PMACZILOG_CONSOLE (NULL) 1830 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1831 1832 /* 1833 * Register the driver, console driver and ports with the serial 1834 * core 1835 */ 1836 static int __init pmz_register(void) 1837 { 1838 pmz_uart_reg.nr = pmz_ports_count; 1839 pmz_uart_reg.cons = PMACZILOG_CONSOLE; 1840 1841 /* 1842 * Register this driver with the serial core 1843 */ 1844 return uart_register_driver(&pmz_uart_reg); 1845 } 1846 1847 #ifdef CONFIG_PPC_PMAC 1848 1849 static const struct of_device_id pmz_match[] = 1850 { 1851 { 1852 .name = "ch-a", 1853 }, 1854 { 1855 .name = "ch-b", 1856 }, 1857 {}, 1858 }; 1859 MODULE_DEVICE_TABLE (of, pmz_match); 1860 1861 static struct macio_driver pmz_driver = { 1862 .driver = { 1863 .name = "pmac_zilog", 1864 .owner = THIS_MODULE, 1865 .of_match_table = pmz_match, 1866 }, 1867 .probe = pmz_attach, 1868 .remove = pmz_detach, 1869 .suspend = pmz_suspend, 1870 .resume = pmz_resume, 1871 }; 1872 1873 #else 1874 1875 static struct platform_driver pmz_driver = { 1876 .remove = __exit_p(pmz_detach), 1877 .driver = { 1878 .name = "scc", 1879 }, 1880 }; 1881 1882 #endif /* !CONFIG_PPC_PMAC */ 1883 1884 static int __init init_pmz(void) 1885 { 1886 int rc, i; 1887 printk(KERN_INFO "%s\n", version); 1888 1889 /* 1890 * First, we need to do a direct OF-based probe pass. We 1891 * do that because we want serial console up before the 1892 * macio stuffs calls us back, and since that makes it 1893 * easier to pass the proper number of channels to 1894 * uart_register_driver() 1895 */ 1896 if (pmz_ports_count == 0) 1897 pmz_probe(); 1898 1899 /* 1900 * Bail early if no port found 1901 */ 1902 if (pmz_ports_count == 0) 1903 return -ENODEV; 1904 1905 /* 1906 * Now we register with the serial layer 1907 */ 1908 rc = pmz_register(); 1909 if (rc) { 1910 printk(KERN_ERR 1911 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" 1912 "pmac_zilog: Did another serial driver already claim the minors?\n"); 1913 /* effectively "pmz_unprobe()" */ 1914 for (i=0; i < pmz_ports_count; i++) 1915 pmz_dispose_port(&pmz_ports[i]); 1916 return rc; 1917 } 1918 1919 /* 1920 * Then we register the macio driver itself 1921 */ 1922 #ifdef CONFIG_PPC_PMAC 1923 return macio_register_driver(&pmz_driver); 1924 #else 1925 return platform_driver_probe(&pmz_driver, pmz_attach); 1926 #endif 1927 } 1928 1929 static void __exit exit_pmz(void) 1930 { 1931 int i; 1932 1933 #ifdef CONFIG_PPC_PMAC 1934 /* Get rid of macio-driver (detach from macio) */ 1935 macio_unregister_driver(&pmz_driver); 1936 #else 1937 platform_driver_unregister(&pmz_driver); 1938 #endif 1939 1940 for (i = 0; i < pmz_ports_count; i++) { 1941 struct uart_pmac_port *uport = &pmz_ports[i]; 1942 #ifdef CONFIG_PPC_PMAC 1943 if (uport->node != NULL) 1944 pmz_dispose_port(uport); 1945 #else 1946 if (uport->pdev != NULL) 1947 pmz_dispose_port(uport); 1948 #endif 1949 } 1950 /* Unregister UART driver */ 1951 uart_unregister_driver(&pmz_uart_reg); 1952 } 1953 1954 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1955 1956 static void pmz_console_putchar(struct uart_port *port, int ch) 1957 { 1958 struct uart_pmac_port *uap = 1959 container_of(port, struct uart_pmac_port, port); 1960 1961 /* Wait for the transmit buffer to empty. */ 1962 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1963 udelay(5); 1964 write_zsdata(uap, ch); 1965 } 1966 1967 /* 1968 * Print a string to the serial port trying not to disturb 1969 * any possible real use of the port... 1970 */ 1971 static void pmz_console_write(struct console *con, const char *s, unsigned int count) 1972 { 1973 struct uart_pmac_port *uap = &pmz_ports[con->index]; 1974 unsigned long flags; 1975 1976 spin_lock_irqsave(&uap->port.lock, flags); 1977 1978 /* Turn of interrupts and enable the transmitter. */ 1979 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); 1980 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); 1981 1982 uart_console_write(&uap->port, s, count, pmz_console_putchar); 1983 1984 /* Restore the values in the registers. */ 1985 write_zsreg(uap, R1, uap->curregs[1]); 1986 /* Don't disable the transmitter. */ 1987 1988 spin_unlock_irqrestore(&uap->port.lock, flags); 1989 } 1990 1991 /* 1992 * Setup the serial console 1993 */ 1994 static int __init pmz_console_setup(struct console *co, char *options) 1995 { 1996 struct uart_pmac_port *uap; 1997 struct uart_port *port; 1998 int baud = 38400; 1999 int bits = 8; 2000 int parity = 'n'; 2001 int flow = 'n'; 2002 unsigned long pwr_delay; 2003 2004 /* 2005 * XServe's default to 57600 bps 2006 */ 2007 if (of_machine_is_compatible("RackMac1,1") 2008 || of_machine_is_compatible("RackMac1,2") 2009 || of_machine_is_compatible("MacRISC4")) 2010 baud = 57600; 2011 2012 /* 2013 * Check whether an invalid uart number has been specified, and 2014 * if so, search for the first available port that does have 2015 * console support. 2016 */ 2017 if (co->index >= pmz_ports_count) 2018 co->index = 0; 2019 uap = &pmz_ports[co->index]; 2020 #ifdef CONFIG_PPC_PMAC 2021 if (uap->node == NULL) 2022 return -ENODEV; 2023 #else 2024 if (uap->pdev == NULL) 2025 return -ENODEV; 2026 #endif 2027 port = &uap->port; 2028 2029 /* 2030 * Mark port as beeing a console 2031 */ 2032 uap->flags |= PMACZILOG_FLAG_IS_CONS; 2033 2034 /* 2035 * Temporary fix for uart layer who didn't setup the spinlock yet 2036 */ 2037 spin_lock_init(&port->lock); 2038 2039 /* 2040 * Enable the hardware 2041 */ 2042 pwr_delay = __pmz_startup(uap); 2043 if (pwr_delay) 2044 mdelay(pwr_delay); 2045 2046 if (options) 2047 uart_parse_options(options, &baud, &parity, &bits, &flow); 2048 2049 return uart_set_options(port, co, baud, parity, bits, flow); 2050 } 2051 2052 static int __init pmz_console_init(void) 2053 { 2054 /* Probe ports */ 2055 pmz_probe(); 2056 2057 if (pmz_ports_count == 0) 2058 return -ENODEV; 2059 2060 /* TODO: Autoprobe console based on OF */ 2061 /* pmz_console.index = i; */ 2062 register_console(&pmz_console); 2063 2064 return 0; 2065 2066 } 2067 console_initcall(pmz_console_init); 2068 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 2069 2070 module_init(init_pmz); 2071 module_exit(exit_pmz); 2072