1 /* 2 * PIC32 Integrated Serial Driver. 3 * 4 * Copyright (C) 2015 Microchip Technology, Inc. 5 * 6 * Authors: 7 * Sorin-Andrei Pistirica <andrei.pistirica@microchip.com> 8 * 9 * Licensed under GPLv2 or later. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/platform_device.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_gpio.h> 18 #include <linux/init.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/console.h> 22 #include <linux/clk.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/serial_core.h> 26 #include <linux/delay.h> 27 28 #include <asm/mach-pic32/pic32.h> 29 #include "pic32_uart.h" 30 31 /* UART name and device definitions */ 32 #define PIC32_DEV_NAME "pic32-uart" 33 #define PIC32_MAX_UARTS 6 34 #define PIC32_SDEV_NAME "ttyPIC" 35 36 /* pic32_sport pointer for console use */ 37 static struct pic32_sport *pic32_sports[PIC32_MAX_UARTS]; 38 39 static inline void pic32_wait_deplete_txbuf(struct pic32_sport *sport) 40 { 41 /* wait for tx empty, otherwise chars will be lost or corrupted */ 42 while (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_TRMT)) 43 udelay(1); 44 } 45 46 static inline int pic32_enable_clock(struct pic32_sport *sport) 47 { 48 int ret = clk_prepare_enable(sport->clk); 49 50 if (ret) 51 return ret; 52 53 sport->ref_clk++; 54 return 0; 55 } 56 57 static inline void pic32_disable_clock(struct pic32_sport *sport) 58 { 59 sport->ref_clk--; 60 clk_disable_unprepare(sport->clk); 61 } 62 63 /* serial core request to check if uart tx buffer is empty */ 64 static unsigned int pic32_uart_tx_empty(struct uart_port *port) 65 { 66 struct pic32_sport *sport = to_pic32_sport(port); 67 u32 val = pic32_uart_readl(sport, PIC32_UART_STA); 68 69 return (val & PIC32_UART_STA_TRMT) ? 1 : 0; 70 } 71 72 /* serial core request to set UART outputs */ 73 static void pic32_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 74 { 75 struct pic32_sport *sport = to_pic32_sport(port); 76 77 /* set loopback mode */ 78 if (mctrl & TIOCM_LOOP) 79 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 80 PIC32_UART_MODE_LPBK); 81 else 82 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 83 PIC32_UART_MODE_LPBK); 84 } 85 86 /* get the state of CTS input pin for this port */ 87 static unsigned int get_cts_state(struct pic32_sport *sport) 88 { 89 /* read and invert UxCTS */ 90 if (gpio_is_valid(sport->cts_gpio)) 91 return !gpio_get_value(sport->cts_gpio); 92 93 return 1; 94 } 95 96 /* serial core request to return the state of misc UART input pins */ 97 static unsigned int pic32_uart_get_mctrl(struct uart_port *port) 98 { 99 struct pic32_sport *sport = to_pic32_sport(port); 100 unsigned int mctrl = 0; 101 102 if (!sport->hw_flow_ctrl) 103 mctrl |= TIOCM_CTS; 104 else if (get_cts_state(sport)) 105 mctrl |= TIOCM_CTS; 106 107 /* DSR and CD are not supported in PIC32, so return 1 108 * RI is not supported in PIC32, so return 0 109 */ 110 mctrl |= TIOCM_CD; 111 mctrl |= TIOCM_DSR; 112 113 return mctrl; 114 } 115 116 /* stop tx and start tx are not called in pairs, therefore a flag indicates 117 * the status of irq to control the irq-depth. 118 */ 119 static inline void pic32_uart_irqtxen(struct pic32_sport *sport, u8 en) 120 { 121 if (en && !tx_irq_enabled(sport)) { 122 enable_irq(sport->irq_tx); 123 tx_irq_enabled(sport) = 1; 124 } else if (!en && tx_irq_enabled(sport)) { 125 /* use disable_irq_nosync() and not disable_irq() to avoid self 126 * imposed deadlock by not waiting for irq handler to end, 127 * since this callback is called from interrupt context. 128 */ 129 disable_irq_nosync(sport->irq_tx); 130 tx_irq_enabled(sport) = 0; 131 } 132 } 133 134 /* serial core request to disable tx ASAP (used for flow control) */ 135 static void pic32_uart_stop_tx(struct uart_port *port) 136 { 137 struct pic32_sport *sport = to_pic32_sport(port); 138 139 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 140 return; 141 142 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 143 return; 144 145 /* wait for tx empty */ 146 pic32_wait_deplete_txbuf(sport); 147 148 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 149 PIC32_UART_STA_UTXEN); 150 pic32_uart_irqtxen(sport, 0); 151 } 152 153 /* serial core request to (re)enable tx */ 154 static void pic32_uart_start_tx(struct uart_port *port) 155 { 156 struct pic32_sport *sport = to_pic32_sport(port); 157 158 pic32_uart_irqtxen(sport, 1); 159 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 160 PIC32_UART_STA_UTXEN); 161 } 162 163 /* serial core request to stop rx, called before port shutdown */ 164 static void pic32_uart_stop_rx(struct uart_port *port) 165 { 166 struct pic32_sport *sport = to_pic32_sport(port); 167 168 /* disable rx interrupts */ 169 disable_irq(sport->irq_rx); 170 171 /* receiver Enable bit OFF */ 172 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 173 PIC32_UART_STA_URXEN); 174 } 175 176 /* serial core request to start/stop emitting break char */ 177 static void pic32_uart_break_ctl(struct uart_port *port, int ctl) 178 { 179 struct pic32_sport *sport = to_pic32_sport(port); 180 unsigned long flags; 181 182 spin_lock_irqsave(&port->lock, flags); 183 184 if (ctl) 185 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 186 PIC32_UART_STA_UTXBRK); 187 else 188 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 189 PIC32_UART_STA_UTXBRK); 190 191 spin_unlock_irqrestore(&port->lock, flags); 192 } 193 194 /* get port type in string format */ 195 static const char *pic32_uart_type(struct uart_port *port) 196 { 197 return (port->type == PORT_PIC32) ? PIC32_DEV_NAME : NULL; 198 } 199 200 /* read all chars in rx fifo and send them to core */ 201 static void pic32_uart_do_rx(struct uart_port *port) 202 { 203 struct pic32_sport *sport = to_pic32_sport(port); 204 struct tty_port *tty; 205 unsigned int max_count; 206 207 /* limit number of char read in interrupt, should not be 208 * higher than fifo size anyway since we're much faster than 209 * serial port 210 */ 211 max_count = PIC32_UART_RX_FIFO_DEPTH; 212 213 spin_lock(&port->lock); 214 215 tty = &port->state->port; 216 217 do { 218 u32 sta_reg, c; 219 char flag; 220 221 /* get overrun/fifo empty information from status register */ 222 sta_reg = pic32_uart_readl(sport, PIC32_UART_STA); 223 if (unlikely(sta_reg & PIC32_UART_STA_OERR)) { 224 225 /* fifo reset is required to clear interrupt */ 226 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 227 PIC32_UART_STA_OERR); 228 229 port->icount.overrun++; 230 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 231 } 232 233 /* Can at least one more character can be read? */ 234 if (!(sta_reg & PIC32_UART_STA_URXDA)) 235 break; 236 237 /* read the character and increment the rx counter */ 238 c = pic32_uart_readl(sport, PIC32_UART_RX); 239 240 port->icount.rx++; 241 flag = TTY_NORMAL; 242 c &= 0xff; 243 244 if (unlikely((sta_reg & PIC32_UART_STA_PERR) || 245 (sta_reg & PIC32_UART_STA_FERR))) { 246 247 /* do stats first */ 248 if (sta_reg & PIC32_UART_STA_PERR) 249 port->icount.parity++; 250 if (sta_reg & PIC32_UART_STA_FERR) 251 port->icount.frame++; 252 253 /* update flag wrt read_status_mask */ 254 sta_reg &= port->read_status_mask; 255 256 if (sta_reg & PIC32_UART_STA_FERR) 257 flag = TTY_FRAME; 258 if (sta_reg & PIC32_UART_STA_PERR) 259 flag = TTY_PARITY; 260 } 261 262 if (uart_handle_sysrq_char(port, c)) 263 continue; 264 265 if ((sta_reg & port->ignore_status_mask) == 0) 266 tty_insert_flip_char(tty, c, flag); 267 268 } while (--max_count); 269 270 spin_unlock(&port->lock); 271 272 tty_flip_buffer_push(tty); 273 } 274 275 /* fill tx fifo with chars to send, stop when fifo is about to be full 276 * or when all chars have been sent. 277 */ 278 static void pic32_uart_do_tx(struct uart_port *port) 279 { 280 struct pic32_sport *sport = to_pic32_sport(port); 281 struct circ_buf *xmit = &port->state->xmit; 282 unsigned int max_count = PIC32_UART_TX_FIFO_DEPTH; 283 284 if (port->x_char) { 285 pic32_uart_writel(sport, PIC32_UART_TX, port->x_char); 286 port->icount.tx++; 287 port->x_char = 0; 288 return; 289 } 290 291 if (uart_tx_stopped(port)) { 292 pic32_uart_stop_tx(port); 293 return; 294 } 295 296 if (uart_circ_empty(xmit)) 297 goto txq_empty; 298 299 /* keep stuffing chars into uart tx buffer 300 * 1) until uart fifo is full 301 * or 302 * 2) until the circ buffer is empty 303 * (all chars have been sent) 304 * or 305 * 3) until the max count is reached 306 * (prevents lingering here for too long in certain cases) 307 */ 308 while (!(PIC32_UART_STA_UTXBF & 309 pic32_uart_readl(sport, PIC32_UART_STA))) { 310 unsigned int c = xmit->buf[xmit->tail]; 311 312 pic32_uart_writel(sport, PIC32_UART_TX, c); 313 314 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 315 port->icount.tx++; 316 if (uart_circ_empty(xmit)) 317 break; 318 if (--max_count == 0) 319 break; 320 } 321 322 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 323 uart_write_wakeup(port); 324 325 if (uart_circ_empty(xmit)) 326 goto txq_empty; 327 328 return; 329 330 txq_empty: 331 pic32_uart_irqtxen(sport, 0); 332 } 333 334 /* RX interrupt handler */ 335 static irqreturn_t pic32_uart_rx_interrupt(int irq, void *dev_id) 336 { 337 struct uart_port *port = dev_id; 338 339 pic32_uart_do_rx(port); 340 341 return IRQ_HANDLED; 342 } 343 344 /* TX interrupt handler */ 345 static irqreturn_t pic32_uart_tx_interrupt(int irq, void *dev_id) 346 { 347 struct uart_port *port = dev_id; 348 unsigned long flags; 349 350 spin_lock_irqsave(&port->lock, flags); 351 pic32_uart_do_tx(port); 352 spin_unlock_irqrestore(&port->lock, flags); 353 354 return IRQ_HANDLED; 355 } 356 357 /* FAULT interrupt handler */ 358 static irqreturn_t pic32_uart_fault_interrupt(int irq, void *dev_id) 359 { 360 /* do nothing: pic32_uart_do_rx() handles faults. */ 361 return IRQ_HANDLED; 362 } 363 364 /* enable rx & tx operation on uart */ 365 static void pic32_uart_en_and_unmask(struct uart_port *port) 366 { 367 struct pic32_sport *sport = to_pic32_sport(port); 368 369 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_STA), 370 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 371 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 372 PIC32_UART_MODE_ON); 373 } 374 375 /* disable rx & tx operation on uart */ 376 static void pic32_uart_dsbl_and_mask(struct uart_port *port) 377 { 378 struct pic32_sport *sport = to_pic32_sport(port); 379 380 /* wait for tx empty, otherwise chars will be lost or corrupted */ 381 pic32_wait_deplete_txbuf(sport); 382 383 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 384 PIC32_UART_STA_UTXEN | PIC32_UART_STA_URXEN); 385 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 386 PIC32_UART_MODE_ON); 387 } 388 389 /* serial core request to initialize uart and start rx operation */ 390 static int pic32_uart_startup(struct uart_port *port) 391 { 392 struct pic32_sport *sport = to_pic32_sport(port); 393 u32 dflt_baud = (port->uartclk / PIC32_UART_DFLT_BRATE / 16) - 1; 394 unsigned long flags; 395 int ret; 396 397 local_irq_save(flags); 398 399 ret = pic32_enable_clock(sport); 400 if (ret) { 401 local_irq_restore(flags); 402 goto out_done; 403 } 404 405 /* clear status and mode registers */ 406 pic32_uart_writel(sport, PIC32_UART_MODE, 0); 407 pic32_uart_writel(sport, PIC32_UART_STA, 0); 408 409 /* disable uart and mask all interrupts */ 410 pic32_uart_dsbl_and_mask(port); 411 412 /* set default baud */ 413 pic32_uart_writel(sport, PIC32_UART_BRG, dflt_baud); 414 415 local_irq_restore(flags); 416 417 /* Each UART of a PIC32 has three interrupts therefore, 418 * we setup driver to register the 3 irqs for the device. 419 * 420 * For each irq request_irq() is called with interrupt disabled. 421 * And the irq is enabled as soon as we are ready to handle them. 422 */ 423 tx_irq_enabled(sport) = 0; 424 425 sport->irq_fault_name = kasprintf(GFP_KERNEL, "%s%d-fault", 426 pic32_uart_type(port), 427 sport->idx); 428 if (!sport->irq_fault_name) { 429 dev_err(port->dev, "%s: kasprintf err!", __func__); 430 ret = -ENOMEM; 431 goto out_done; 432 } 433 irq_set_status_flags(sport->irq_fault, IRQ_NOAUTOEN); 434 ret = request_irq(sport->irq_fault, pic32_uart_fault_interrupt, 435 sport->irqflags_fault, sport->irq_fault_name, port); 436 if (ret) { 437 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 438 __func__, sport->irq_fault, ret, 439 pic32_uart_type(port)); 440 goto out_f; 441 } 442 443 sport->irq_rx_name = kasprintf(GFP_KERNEL, "%s%d-rx", 444 pic32_uart_type(port), 445 sport->idx); 446 if (!sport->irq_rx_name) { 447 dev_err(port->dev, "%s: kasprintf err!", __func__); 448 kfree(sport->irq_fault_name); 449 ret = -ENOMEM; 450 goto out_f; 451 } 452 irq_set_status_flags(sport->irq_rx, IRQ_NOAUTOEN); 453 ret = request_irq(sport->irq_rx, pic32_uart_rx_interrupt, 454 sport->irqflags_rx, sport->irq_rx_name, port); 455 if (ret) { 456 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 457 __func__, sport->irq_rx, ret, 458 pic32_uart_type(port)); 459 goto out_r; 460 } 461 462 sport->irq_tx_name = kasprintf(GFP_KERNEL, "%s%d-tx", 463 pic32_uart_type(port), 464 sport->idx); 465 if (!sport->irq_tx_name) { 466 dev_err(port->dev, "%s: kasprintf err!", __func__); 467 ret = -ENOMEM; 468 goto out_r; 469 } 470 irq_set_status_flags(sport->irq_tx, IRQ_NOAUTOEN); 471 ret = request_irq(sport->irq_tx, pic32_uart_tx_interrupt, 472 sport->irqflags_tx, sport->irq_tx_name, port); 473 if (ret) { 474 dev_err(port->dev, "%s: request irq(%d) err! ret:%d name:%s\n", 475 __func__, sport->irq_tx, ret, 476 pic32_uart_type(port)); 477 goto out_t; 478 } 479 480 local_irq_save(flags); 481 482 /* set rx interrupt on first receive */ 483 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 484 PIC32_UART_STA_URXISEL1 | PIC32_UART_STA_URXISEL0); 485 486 /* set interrupt on empty */ 487 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_STA), 488 PIC32_UART_STA_UTXISEL1); 489 490 /* enable all interrupts and eanable uart */ 491 pic32_uart_en_and_unmask(port); 492 493 enable_irq(sport->irq_rx); 494 495 return 0; 496 497 out_t: 498 kfree(sport->irq_tx_name); 499 free_irq(sport->irq_tx, sport); 500 out_r: 501 kfree(sport->irq_rx_name); 502 free_irq(sport->irq_rx, sport); 503 out_f: 504 kfree(sport->irq_fault_name); 505 free_irq(sport->irq_fault, sport); 506 out_done: 507 return ret; 508 } 509 510 /* serial core request to flush & disable uart */ 511 static void pic32_uart_shutdown(struct uart_port *port) 512 { 513 struct pic32_sport *sport = to_pic32_sport(port); 514 unsigned long flags; 515 516 /* disable uart */ 517 spin_lock_irqsave(&port->lock, flags); 518 pic32_uart_dsbl_and_mask(port); 519 spin_unlock_irqrestore(&port->lock, flags); 520 pic32_disable_clock(sport); 521 522 /* free all 3 interrupts for this UART */ 523 free_irq(sport->irq_fault, port); 524 free_irq(sport->irq_tx, port); 525 free_irq(sport->irq_rx, port); 526 } 527 528 /* serial core request to change current uart setting */ 529 static void pic32_uart_set_termios(struct uart_port *port, 530 struct ktermios *new, 531 struct ktermios *old) 532 { 533 struct pic32_sport *sport = to_pic32_sport(port); 534 unsigned int baud; 535 unsigned int quot; 536 unsigned long flags; 537 538 spin_lock_irqsave(&port->lock, flags); 539 540 /* disable uart and mask all interrupts while changing speed */ 541 pic32_uart_dsbl_and_mask(port); 542 543 /* stop bit options */ 544 if (new->c_cflag & CSTOPB) 545 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 546 PIC32_UART_MODE_STSEL); 547 else 548 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 549 PIC32_UART_MODE_STSEL); 550 551 /* parity options */ 552 if (new->c_cflag & PARENB) { 553 if (new->c_cflag & PARODD) { 554 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 555 PIC32_UART_MODE_PDSEL1); 556 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 557 PIC32_UART_MODE_PDSEL0); 558 } else { 559 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 560 PIC32_UART_MODE_PDSEL0); 561 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 562 PIC32_UART_MODE_PDSEL1); 563 } 564 } else { 565 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 566 PIC32_UART_MODE_PDSEL1 | 567 PIC32_UART_MODE_PDSEL0); 568 } 569 /* if hw flow ctrl, then the pins must be specified in device tree */ 570 if ((new->c_cflag & CRTSCTS) && sport->hw_flow_ctrl) { 571 /* enable hardware flow control */ 572 pic32_uart_writel(sport, PIC32_SET(PIC32_UART_MODE), 573 PIC32_UART_MODE_UEN1); 574 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 575 PIC32_UART_MODE_UEN0); 576 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 577 PIC32_UART_MODE_RTSMD); 578 } else { 579 /* disable hardware flow control */ 580 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 581 PIC32_UART_MODE_UEN1); 582 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 583 PIC32_UART_MODE_UEN0); 584 pic32_uart_writel(sport, PIC32_CLR(PIC32_UART_MODE), 585 PIC32_UART_MODE_RTSMD); 586 } 587 588 /* Always 8-bit */ 589 new->c_cflag |= CS8; 590 591 /* Mark/Space parity is not supported */ 592 new->c_cflag &= ~CMSPAR; 593 594 /* update baud */ 595 baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); 596 quot = uart_get_divisor(port, baud) - 1; 597 pic32_uart_writel(sport, PIC32_UART_BRG, quot); 598 uart_update_timeout(port, new->c_cflag, baud); 599 600 if (tty_termios_baud_rate(new)) 601 tty_termios_encode_baud_rate(new, baud, baud); 602 603 /* enable uart */ 604 pic32_uart_en_and_unmask(port); 605 606 spin_unlock_irqrestore(&port->lock, flags); 607 } 608 609 /* serial core request to claim uart iomem */ 610 static int pic32_uart_request_port(struct uart_port *port) 611 { 612 struct platform_device *pdev = to_platform_device(port->dev); 613 struct resource *res_mem; 614 615 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 616 if (unlikely(!res_mem)) 617 return -EINVAL; 618 619 if (!request_mem_region(port->mapbase, resource_size(res_mem), 620 "pic32_uart_mem")) 621 return -EBUSY; 622 623 port->membase = devm_ioremap_nocache(port->dev, port->mapbase, 624 resource_size(res_mem)); 625 if (!port->membase) { 626 dev_err(port->dev, "Unable to map registers\n"); 627 release_mem_region(port->mapbase, resource_size(res_mem)); 628 return -ENOMEM; 629 } 630 631 return 0; 632 } 633 634 /* serial core request to release uart iomem */ 635 static void pic32_uart_release_port(struct uart_port *port) 636 { 637 struct platform_device *pdev = to_platform_device(port->dev); 638 struct resource *res_mem; 639 unsigned int res_size; 640 641 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 642 if (unlikely(!res_mem)) 643 return; 644 res_size = resource_size(res_mem); 645 646 release_mem_region(port->mapbase, res_size); 647 } 648 649 /* serial core request to do any port required auto-configuration */ 650 static void pic32_uart_config_port(struct uart_port *port, int flags) 651 { 652 if (flags & UART_CONFIG_TYPE) { 653 if (pic32_uart_request_port(port)) 654 return; 655 port->type = PORT_PIC32; 656 } 657 } 658 659 /* serial core request to check that port information in serinfo are suitable */ 660 static int pic32_uart_verify_port(struct uart_port *port, 661 struct serial_struct *serinfo) 662 { 663 if (port->type != PORT_PIC32) 664 return -EINVAL; 665 if (port->irq != serinfo->irq) 666 return -EINVAL; 667 if (port->iotype != serinfo->io_type) 668 return -EINVAL; 669 if (port->mapbase != (unsigned long)serinfo->iomem_base) 670 return -EINVAL; 671 672 return 0; 673 } 674 675 /* serial core callbacks */ 676 static const struct uart_ops pic32_uart_ops = { 677 .tx_empty = pic32_uart_tx_empty, 678 .get_mctrl = pic32_uart_get_mctrl, 679 .set_mctrl = pic32_uart_set_mctrl, 680 .start_tx = pic32_uart_start_tx, 681 .stop_tx = pic32_uart_stop_tx, 682 .stop_rx = pic32_uart_stop_rx, 683 .break_ctl = pic32_uart_break_ctl, 684 .startup = pic32_uart_startup, 685 .shutdown = pic32_uart_shutdown, 686 .set_termios = pic32_uart_set_termios, 687 .type = pic32_uart_type, 688 .release_port = pic32_uart_release_port, 689 .request_port = pic32_uart_request_port, 690 .config_port = pic32_uart_config_port, 691 .verify_port = pic32_uart_verify_port, 692 }; 693 694 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 695 /* output given char */ 696 static void pic32_console_putchar(struct uart_port *port, int ch) 697 { 698 struct pic32_sport *sport = to_pic32_sport(port); 699 700 if (!(pic32_uart_readl(sport, PIC32_UART_MODE) & PIC32_UART_MODE_ON)) 701 return; 702 703 if (!(pic32_uart_readl(sport, PIC32_UART_STA) & PIC32_UART_STA_UTXEN)) 704 return; 705 706 /* wait for tx empty */ 707 pic32_wait_deplete_txbuf(sport); 708 709 pic32_uart_writel(sport, PIC32_UART_TX, ch & 0xff); 710 } 711 712 /* console core request to output given string */ 713 static void pic32_console_write(struct console *co, const char *s, 714 unsigned int count) 715 { 716 struct pic32_sport *sport = pic32_sports[co->index]; 717 struct uart_port *port = pic32_get_port(sport); 718 719 /* call uart helper to deal with \r\n */ 720 uart_console_write(port, s, count, pic32_console_putchar); 721 } 722 723 /* console core request to setup given console, find matching uart 724 * port and setup it. 725 */ 726 static int pic32_console_setup(struct console *co, char *options) 727 { 728 struct pic32_sport *sport; 729 struct uart_port *port = NULL; 730 int baud = 115200; 731 int bits = 8; 732 int parity = 'n'; 733 int flow = 'n'; 734 int ret = 0; 735 736 if (unlikely(co->index < 0 || co->index >= PIC32_MAX_UARTS)) 737 return -ENODEV; 738 739 sport = pic32_sports[co->index]; 740 if (!sport) 741 return -ENODEV; 742 port = pic32_get_port(sport); 743 744 ret = pic32_enable_clock(sport); 745 if (ret) 746 return ret; 747 748 if (options) 749 uart_parse_options(options, &baud, &parity, &bits, &flow); 750 751 return uart_set_options(port, co, baud, parity, bits, flow); 752 } 753 754 static struct uart_driver pic32_uart_driver; 755 static struct console pic32_console = { 756 .name = PIC32_SDEV_NAME, 757 .write = pic32_console_write, 758 .device = uart_console_device, 759 .setup = pic32_console_setup, 760 .flags = CON_PRINTBUFFER, 761 .index = -1, 762 .data = &pic32_uart_driver, 763 }; 764 #define PIC32_SCONSOLE (&pic32_console) 765 766 static int __init pic32_console_init(void) 767 { 768 register_console(&pic32_console); 769 return 0; 770 } 771 console_initcall(pic32_console_init); 772 773 static inline bool is_pic32_console_port(struct uart_port *port) 774 { 775 return port->cons && port->cons->index == port->line; 776 } 777 778 /* 779 * Late console initialization. 780 */ 781 static int __init pic32_late_console_init(void) 782 { 783 if (!(pic32_console.flags & CON_ENABLED)) 784 register_console(&pic32_console); 785 786 return 0; 787 } 788 789 core_initcall(pic32_late_console_init); 790 791 #else 792 #define PIC32_SCONSOLE NULL 793 #endif 794 795 static struct uart_driver pic32_uart_driver = { 796 .owner = THIS_MODULE, 797 .driver_name = PIC32_DEV_NAME, 798 .dev_name = PIC32_SDEV_NAME, 799 .nr = PIC32_MAX_UARTS, 800 .cons = PIC32_SCONSOLE, 801 }; 802 803 static int pic32_uart_probe(struct platform_device *pdev) 804 { 805 struct device_node *np = pdev->dev.of_node; 806 struct pic32_sport *sport; 807 int uart_idx = 0; 808 struct resource *res_mem; 809 struct uart_port *port; 810 int ret; 811 812 uart_idx = of_alias_get_id(np, "serial"); 813 if (uart_idx < 0 || uart_idx >= PIC32_MAX_UARTS) 814 return -EINVAL; 815 816 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 817 if (!res_mem) 818 return -EINVAL; 819 820 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 821 if (!sport) 822 return -ENOMEM; 823 824 sport->idx = uart_idx; 825 sport->irq_fault = irq_of_parse_and_map(np, 0); 826 sport->irqflags_fault = IRQF_NO_THREAD; 827 sport->irq_rx = irq_of_parse_and_map(np, 1); 828 sport->irqflags_rx = IRQF_NO_THREAD; 829 sport->irq_tx = irq_of_parse_and_map(np, 2); 830 sport->irqflags_tx = IRQF_NO_THREAD; 831 sport->clk = devm_clk_get(&pdev->dev, NULL); 832 sport->cts_gpio = -EINVAL; 833 sport->dev = &pdev->dev; 834 835 /* Hardware flow control: gpios 836 * !Note: Basically, CTS is needed for reading the status. 837 */ 838 sport->hw_flow_ctrl = false; 839 sport->cts_gpio = of_get_named_gpio(np, "cts-gpios", 0); 840 if (gpio_is_valid(sport->cts_gpio)) { 841 sport->hw_flow_ctrl = true; 842 843 ret = devm_gpio_request(sport->dev, 844 sport->cts_gpio, "CTS"); 845 if (ret) { 846 dev_err(&pdev->dev, 847 "error requesting CTS GPIO\n"); 848 goto err; 849 } 850 851 ret = gpio_direction_input(sport->cts_gpio); 852 if (ret) { 853 dev_err(&pdev->dev, "error setting CTS GPIO\n"); 854 goto err; 855 } 856 } 857 858 pic32_sports[uart_idx] = sport; 859 port = &sport->port; 860 memset(port, 0, sizeof(*port)); 861 port->iotype = UPIO_MEM; 862 port->mapbase = res_mem->start; 863 port->ops = &pic32_uart_ops; 864 port->flags = UPF_BOOT_AUTOCONF; 865 port->dev = &pdev->dev; 866 port->fifosize = PIC32_UART_TX_FIFO_DEPTH; 867 port->uartclk = clk_get_rate(sport->clk); 868 port->line = uart_idx; 869 870 ret = uart_add_one_port(&pic32_uart_driver, port); 871 if (ret) { 872 port->membase = NULL; 873 dev_err(port->dev, "%s: uart add port error!\n", __func__); 874 goto err; 875 } 876 877 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 878 if (is_pic32_console_port(port) && 879 (pic32_console.flags & CON_ENABLED)) { 880 /* The peripheral clock has been enabled by console_setup, 881 * so disable it till the port is used. 882 */ 883 pic32_disable_clock(sport); 884 } 885 #endif 886 887 platform_set_drvdata(pdev, port); 888 889 dev_info(&pdev->dev, "%s: uart(%d) driver initialized.\n", 890 __func__, uart_idx); 891 892 return 0; 893 err: 894 /* automatic unroll of sport and gpios */ 895 return ret; 896 } 897 898 static int pic32_uart_remove(struct platform_device *pdev) 899 { 900 struct uart_port *port = platform_get_drvdata(pdev); 901 struct pic32_sport *sport = to_pic32_sport(port); 902 903 uart_remove_one_port(&pic32_uart_driver, port); 904 pic32_disable_clock(sport); 905 platform_set_drvdata(pdev, NULL); 906 pic32_sports[sport->idx] = NULL; 907 908 /* automatic unroll of sport and gpios */ 909 return 0; 910 } 911 912 static const struct of_device_id pic32_serial_dt_ids[] = { 913 { .compatible = "microchip,pic32mzda-uart" }, 914 { /* sentinel */ } 915 }; 916 MODULE_DEVICE_TABLE(of, pic32_serial_dt_ids); 917 918 static struct platform_driver pic32_uart_platform_driver = { 919 .probe = pic32_uart_probe, 920 .remove = pic32_uart_remove, 921 .driver = { 922 .name = PIC32_DEV_NAME, 923 .of_match_table = of_match_ptr(pic32_serial_dt_ids), 924 }, 925 }; 926 927 static int __init pic32_uart_init(void) 928 { 929 int ret; 930 931 ret = uart_register_driver(&pic32_uart_driver); 932 if (ret) { 933 pr_err("failed to register %s:%d\n", 934 pic32_uart_driver.driver_name, ret); 935 return ret; 936 } 937 938 ret = platform_driver_register(&pic32_uart_platform_driver); 939 if (ret) { 940 pr_err("fail to register pic32 uart\n"); 941 uart_unregister_driver(&pic32_uart_driver); 942 } 943 944 return ret; 945 } 946 arch_initcall(pic32_uart_init); 947 948 static void __exit pic32_uart_exit(void) 949 { 950 #ifdef CONFIG_SERIAL_PIC32_CONSOLE 951 unregister_console(&pic32_console); 952 #endif 953 platform_driver_unregister(&pic32_uart_platform_driver); 954 uart_unregister_driver(&pic32_uart_driver); 955 } 956 module_exit(pic32_uart_exit); 957 958 MODULE_AUTHOR("Sorin-Andrei Pistirica <andrei.pistirica@microchip.com>"); 959 MODULE_DESCRIPTION("Microchip PIC32 integrated serial port driver"); 960 MODULE_LICENSE("GPL v2"); 961