1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/serial_reg.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/dmi.h> 28 #include <linux/console.h> 29 #include <linux/nmi.h> 30 #include <linux/delay.h> 31 32 #include <linux/debugfs.h> 33 #include <linux/dmaengine.h> 34 #include <linux/pch_dma.h> 35 36 enum { 37 PCH_UART_HANDLED_RX_INT_SHIFT, 38 PCH_UART_HANDLED_TX_INT_SHIFT, 39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 41 PCH_UART_HANDLED_MS_INT_SHIFT, 42 }; 43 44 enum { 45 PCH_UART_8LINE, 46 PCH_UART_2LINE, 47 }; 48 49 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 50 51 /* Set the max number of UART port 52 * Intel EG20T PCH: 4 port 53 * LAPIS Semiconductor ML7213 IOH: 3 port 54 * LAPIS Semiconductor ML7223 IOH: 2 port 55 */ 56 #define PCH_UART_NR 4 57 58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 61 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 62 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 63 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 65 66 #define PCH_UART_RBR 0x00 67 #define PCH_UART_THR 0x00 68 69 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 70 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 71 #define PCH_UART_IER_ERBFI 0x00000001 72 #define PCH_UART_IER_ETBEI 0x00000002 73 #define PCH_UART_IER_ELSI 0x00000004 74 #define PCH_UART_IER_EDSSI 0x00000008 75 76 #define PCH_UART_IIR_IP 0x00000001 77 #define PCH_UART_IIR_IID 0x00000006 78 #define PCH_UART_IIR_MSI 0x00000000 79 #define PCH_UART_IIR_TRI 0x00000002 80 #define PCH_UART_IIR_RRI 0x00000004 81 #define PCH_UART_IIR_REI 0x00000006 82 #define PCH_UART_IIR_TOI 0x00000008 83 #define PCH_UART_IIR_FIFO256 0x00000020 84 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 85 #define PCH_UART_IIR_FE 0x000000C0 86 87 #define PCH_UART_FCR_FIFOE 0x00000001 88 #define PCH_UART_FCR_RFR 0x00000002 89 #define PCH_UART_FCR_TFR 0x00000004 90 #define PCH_UART_FCR_DMS 0x00000008 91 #define PCH_UART_FCR_FIFO256 0x00000020 92 #define PCH_UART_FCR_RFTL 0x000000C0 93 94 #define PCH_UART_FCR_RFTL1 0x00000000 95 #define PCH_UART_FCR_RFTL64 0x00000040 96 #define PCH_UART_FCR_RFTL128 0x00000080 97 #define PCH_UART_FCR_RFTL224 0x000000C0 98 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 99 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 100 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 101 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 102 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 103 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 104 #define PCH_UART_FCR_RFTL_SHIFT 6 105 106 #define PCH_UART_LCR_WLS 0x00000003 107 #define PCH_UART_LCR_STB 0x00000004 108 #define PCH_UART_LCR_PEN 0x00000008 109 #define PCH_UART_LCR_EPS 0x00000010 110 #define PCH_UART_LCR_SP 0x00000020 111 #define PCH_UART_LCR_SB 0x00000040 112 #define PCH_UART_LCR_DLAB 0x00000080 113 #define PCH_UART_LCR_NP 0x00000000 114 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 115 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 116 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 117 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 118 PCH_UART_LCR_SP) 119 120 #define PCH_UART_LCR_5BIT 0x00000000 121 #define PCH_UART_LCR_6BIT 0x00000001 122 #define PCH_UART_LCR_7BIT 0x00000002 123 #define PCH_UART_LCR_8BIT 0x00000003 124 125 #define PCH_UART_MCR_DTR 0x00000001 126 #define PCH_UART_MCR_RTS 0x00000002 127 #define PCH_UART_MCR_OUT 0x0000000C 128 #define PCH_UART_MCR_LOOP 0x00000010 129 #define PCH_UART_MCR_AFE 0x00000020 130 131 #define PCH_UART_LSR_DR 0x00000001 132 #define PCH_UART_LSR_ERR (1<<7) 133 134 #define PCH_UART_MSR_DCTS 0x00000001 135 #define PCH_UART_MSR_DDSR 0x00000002 136 #define PCH_UART_MSR_TERI 0x00000004 137 #define PCH_UART_MSR_DDCD 0x00000008 138 #define PCH_UART_MSR_CTS 0x00000010 139 #define PCH_UART_MSR_DSR 0x00000020 140 #define PCH_UART_MSR_RI 0x00000040 141 #define PCH_UART_MSR_DCD 0x00000080 142 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 143 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 144 145 #define PCH_UART_DLL 0x00 146 #define PCH_UART_DLM 0x01 147 148 #define PCH_UART_BRCSR 0x0E 149 150 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 151 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 152 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 153 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 154 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 155 156 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 157 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 158 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 159 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 160 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 161 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 162 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 163 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 164 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 165 #define PCH_UART_HAL_STB1 0 166 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 167 168 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 169 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 170 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 171 PCH_UART_HAL_CLR_RX_FIFO) 172 173 #define PCH_UART_HAL_DMA_MODE0 0 174 #define PCH_UART_HAL_FIFO_DIS 0 175 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 176 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 177 PCH_UART_FCR_FIFO256) 178 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 179 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 180 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 181 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 182 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 183 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 184 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 185 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 186 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 187 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 188 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 189 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 190 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 191 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 192 193 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 194 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 195 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 196 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 197 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 198 199 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 200 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 201 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 202 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 203 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 204 205 #define PCI_VENDOR_ID_ROHM 0x10DB 206 207 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 208 209 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 210 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 211 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 212 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 213 214 struct pch_uart_buffer { 215 unsigned char *buf; 216 int size; 217 }; 218 219 struct eg20t_port { 220 struct uart_port port; 221 int port_type; 222 void __iomem *membase; 223 resource_size_t mapbase; 224 unsigned int iobase; 225 struct pci_dev *pdev; 226 int fifo_size; 227 int uartclk; 228 int start_tx; 229 int start_rx; 230 int tx_empty; 231 int int_dis_flag; 232 int trigger; 233 int trigger_level; 234 struct pch_uart_buffer rxbuf; 235 unsigned int dmsr; 236 unsigned int fcr; 237 unsigned int mcr; 238 unsigned int use_dma; 239 unsigned int use_dma_flag; 240 struct dma_async_tx_descriptor *desc_tx; 241 struct dma_async_tx_descriptor *desc_rx; 242 struct pch_dma_slave param_tx; 243 struct pch_dma_slave param_rx; 244 struct dma_chan *chan_tx; 245 struct dma_chan *chan_rx; 246 struct scatterlist *sg_tx_p; 247 int nent; 248 struct scatterlist sg_rx; 249 int tx_dma_use; 250 void *rx_buf_virt; 251 dma_addr_t rx_buf_dma; 252 253 struct dentry *debugfs; 254 }; 255 256 /** 257 * struct pch_uart_driver_data - private data structure for UART-DMA 258 * @port_type: The number of DMA channel 259 * @line_no: UART port line number (0, 1, 2...) 260 */ 261 struct pch_uart_driver_data { 262 int port_type; 263 int line_no; 264 }; 265 266 enum pch_uart_num_t { 267 pch_et20t_uart0 = 0, 268 pch_et20t_uart1, 269 pch_et20t_uart2, 270 pch_et20t_uart3, 271 pch_ml7213_uart0, 272 pch_ml7213_uart1, 273 pch_ml7213_uart2, 274 pch_ml7223_uart0, 275 pch_ml7223_uart1, 276 pch_ml7831_uart0, 277 pch_ml7831_uart1, 278 }; 279 280 static struct pch_uart_driver_data drv_dat[] = { 281 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 282 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 283 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 284 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 285 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 286 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 287 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 288 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 289 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 290 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 291 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 292 }; 293 294 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 295 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 296 #endif 297 static unsigned int default_baud = 9600; 298 static unsigned int user_uartclk = 0; 299 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 300 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 301 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 302 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 303 304 #ifdef CONFIG_DEBUG_FS 305 306 #define PCH_REGS_BUFSIZE 1024 307 static int pch_show_regs_open(struct inode *inode, struct file *file) 308 { 309 file->private_data = inode->i_private; 310 return 0; 311 } 312 313 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 314 size_t count, loff_t *ppos) 315 { 316 struct eg20t_port *priv = file->private_data; 317 char *buf; 318 u32 len = 0; 319 ssize_t ret; 320 unsigned char lcr; 321 322 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 323 if (!buf) 324 return 0; 325 326 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 327 "PCH EG20T port[%d] regs:\n", priv->port.line); 328 329 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "=================================\n"); 331 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 332 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 333 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 334 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 335 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 336 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 337 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 338 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 339 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 340 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 341 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 342 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 343 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 344 "BRCSR: \t0x%02x\n", 345 ioread8(priv->membase + PCH_UART_BRCSR)); 346 347 lcr = ioread8(priv->membase + UART_LCR); 348 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 349 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 350 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 351 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 352 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 353 iowrite8(lcr, priv->membase + UART_LCR); 354 355 if (len > PCH_REGS_BUFSIZE) 356 len = PCH_REGS_BUFSIZE; 357 358 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 359 kfree(buf); 360 return ret; 361 } 362 363 static const struct file_operations port_regs_ops = { 364 .owner = THIS_MODULE, 365 .open = pch_show_regs_open, 366 .read = port_show_regs, 367 .llseek = default_llseek, 368 }; 369 #endif /* CONFIG_DEBUG_FS */ 370 371 /* Return UART clock, checking for board specific clocks. */ 372 static int pch_uart_get_uartclk(void) 373 { 374 const char *cmp; 375 376 if (user_uartclk) 377 return user_uartclk; 378 379 cmp = dmi_get_system_info(DMI_BOARD_NAME); 380 if (cmp && strstr(cmp, "CM-iTC")) 381 return CMITC_UARTCLK; 382 383 cmp = dmi_get_system_info(DMI_BIOS_VERSION); 384 if (cmp && strnstr(cmp, "FRI2", 4)) 385 return FRI2_64_UARTCLK; 386 387 cmp = dmi_get_system_info(DMI_PRODUCT_NAME); 388 if (cmp && strstr(cmp, "Fish River Island II")) 389 return FRI2_48_UARTCLK; 390 391 return DEFAULT_UARTCLK; 392 } 393 394 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 395 unsigned int flag) 396 { 397 u8 ier = ioread8(priv->membase + UART_IER); 398 ier |= flag & PCH_UART_IER_MASK; 399 iowrite8(ier, priv->membase + UART_IER); 400 } 401 402 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 403 unsigned int flag) 404 { 405 u8 ier = ioread8(priv->membase + UART_IER); 406 ier &= ~(flag & PCH_UART_IER_MASK); 407 iowrite8(ier, priv->membase + UART_IER); 408 } 409 410 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 411 unsigned int parity, unsigned int bits, 412 unsigned int stb) 413 { 414 unsigned int dll, dlm, lcr; 415 int div; 416 417 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 418 if (div < 0 || USHRT_MAX <= div) { 419 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 420 return -EINVAL; 421 } 422 423 dll = (unsigned int)div & 0x00FFU; 424 dlm = ((unsigned int)div >> 8) & 0x00FFU; 425 426 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 427 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 428 return -EINVAL; 429 } 430 431 if (bits & ~PCH_UART_LCR_WLS) { 432 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 433 return -EINVAL; 434 } 435 436 if (stb & ~PCH_UART_LCR_STB) { 437 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 438 return -EINVAL; 439 } 440 441 lcr = parity; 442 lcr |= bits; 443 lcr |= stb; 444 445 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 446 __func__, baud, div, lcr, jiffies); 447 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 448 iowrite8(dll, priv->membase + PCH_UART_DLL); 449 iowrite8(dlm, priv->membase + PCH_UART_DLM); 450 iowrite8(lcr, priv->membase + UART_LCR); 451 452 return 0; 453 } 454 455 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 456 unsigned int flag) 457 { 458 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 459 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 460 __func__, flag); 461 return -EINVAL; 462 } 463 464 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 465 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 466 priv->membase + UART_FCR); 467 iowrite8(priv->fcr, priv->membase + UART_FCR); 468 469 return 0; 470 } 471 472 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 473 unsigned int dmamode, 474 unsigned int fifo_size, unsigned int trigger) 475 { 476 u8 fcr; 477 478 if (dmamode & ~PCH_UART_FCR_DMS) { 479 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 480 __func__, dmamode); 481 return -EINVAL; 482 } 483 484 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 485 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 486 __func__, fifo_size); 487 return -EINVAL; 488 } 489 490 if (trigger & ~PCH_UART_FCR_RFTL) { 491 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 492 __func__, trigger); 493 return -EINVAL; 494 } 495 496 switch (priv->fifo_size) { 497 case 256: 498 priv->trigger_level = 499 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 500 break; 501 case 64: 502 priv->trigger_level = 503 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 504 break; 505 case 16: 506 priv->trigger_level = 507 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 508 break; 509 default: 510 priv->trigger_level = 511 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 512 break; 513 } 514 fcr = 515 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 516 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 517 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 518 priv->membase + UART_FCR); 519 iowrite8(fcr, priv->membase + UART_FCR); 520 priv->fcr = fcr; 521 522 return 0; 523 } 524 525 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 526 { 527 unsigned int msr = ioread8(priv->membase + UART_MSR); 528 priv->dmsr = msr & PCH_UART_MSR_DELTA; 529 return (u8)msr; 530 } 531 532 static void pch_uart_hal_write(struct eg20t_port *priv, 533 const unsigned char *buf, int tx_size) 534 { 535 int i; 536 unsigned int thr; 537 538 for (i = 0; i < tx_size;) { 539 thr = buf[i++]; 540 iowrite8(thr, priv->membase + PCH_UART_THR); 541 } 542 } 543 544 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 545 int rx_size) 546 { 547 int i; 548 u8 rbr, lsr; 549 550 lsr = ioread8(priv->membase + UART_LSR); 551 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 552 i < rx_size && lsr & UART_LSR_DR; 553 lsr = ioread8(priv->membase + UART_LSR)) { 554 rbr = ioread8(priv->membase + PCH_UART_RBR); 555 buf[i++] = rbr; 556 } 557 return i; 558 } 559 560 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv) 561 { 562 unsigned int iir; 563 int ret; 564 565 iir = ioread8(priv->membase + UART_IIR); 566 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP)); 567 return ret; 568 } 569 570 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 571 { 572 return ioread8(priv->membase + UART_LSR); 573 } 574 575 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 576 { 577 unsigned int lcr; 578 579 lcr = ioread8(priv->membase + UART_LCR); 580 if (on) 581 lcr |= PCH_UART_LCR_SB; 582 else 583 lcr &= ~PCH_UART_LCR_SB; 584 585 iowrite8(lcr, priv->membase + UART_LCR); 586 } 587 588 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 589 int size) 590 { 591 struct uart_port *port; 592 struct tty_struct *tty; 593 594 port = &priv->port; 595 tty = tty_port_tty_get(&port->state->port); 596 if (!tty) { 597 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 598 return -EBUSY; 599 } 600 601 tty_insert_flip_string(tty, buf, size); 602 tty_flip_buffer_push(tty); 603 tty_kref_put(tty); 604 605 return 0; 606 } 607 608 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 609 { 610 int ret = 0; 611 struct uart_port *port = &priv->port; 612 613 if (port->x_char) { 614 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 615 __func__, port->x_char, jiffies); 616 buf[0] = port->x_char; 617 port->x_char = 0; 618 ret = 1; 619 } 620 621 return ret; 622 } 623 624 static int dma_push_rx(struct eg20t_port *priv, int size) 625 { 626 struct tty_struct *tty; 627 int room; 628 struct uart_port *port = &priv->port; 629 630 port = &priv->port; 631 tty = tty_port_tty_get(&port->state->port); 632 if (!tty) { 633 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 634 return 0; 635 } 636 637 room = tty_buffer_request_room(tty, size); 638 639 if (room < size) 640 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 641 size - room); 642 if (!room) 643 return room; 644 645 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 646 647 port->icount.rx += room; 648 tty_kref_put(tty); 649 650 return room; 651 } 652 653 static void pch_free_dma(struct uart_port *port) 654 { 655 struct eg20t_port *priv; 656 priv = container_of(port, struct eg20t_port, port); 657 658 if (priv->chan_tx) { 659 dma_release_channel(priv->chan_tx); 660 priv->chan_tx = NULL; 661 } 662 if (priv->chan_rx) { 663 dma_release_channel(priv->chan_rx); 664 priv->chan_rx = NULL; 665 } 666 if (sg_dma_address(&priv->sg_rx)) 667 dma_free_coherent(port->dev, port->fifosize, 668 sg_virt(&priv->sg_rx), 669 sg_dma_address(&priv->sg_rx)); 670 671 return; 672 } 673 674 static bool filter(struct dma_chan *chan, void *slave) 675 { 676 struct pch_dma_slave *param = slave; 677 678 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 679 chan->device->dev)) { 680 chan->private = param; 681 return true; 682 } else { 683 return false; 684 } 685 } 686 687 static void pch_request_dma(struct uart_port *port) 688 { 689 dma_cap_mask_t mask; 690 struct dma_chan *chan; 691 struct pci_dev *dma_dev; 692 struct pch_dma_slave *param; 693 struct eg20t_port *priv = 694 container_of(port, struct eg20t_port, port); 695 dma_cap_zero(mask); 696 dma_cap_set(DMA_SLAVE, mask); 697 698 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 699 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 700 information */ 701 /* Set Tx DMA */ 702 param = &priv->param_tx; 703 param->dma_dev = &dma_dev->dev; 704 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 705 706 param->tx_reg = port->mapbase + UART_TX; 707 chan = dma_request_channel(mask, filter, param); 708 if (!chan) { 709 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 710 __func__); 711 return; 712 } 713 priv->chan_tx = chan; 714 715 /* Set Rx DMA */ 716 param = &priv->param_rx; 717 param->dma_dev = &dma_dev->dev; 718 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 719 720 param->rx_reg = port->mapbase + UART_RX; 721 chan = dma_request_channel(mask, filter, param); 722 if (!chan) { 723 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 724 __func__); 725 dma_release_channel(priv->chan_tx); 726 priv->chan_tx = NULL; 727 return; 728 } 729 730 /* Get Consistent memory for DMA */ 731 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 732 &priv->rx_buf_dma, GFP_KERNEL); 733 priv->chan_rx = chan; 734 } 735 736 static void pch_dma_rx_complete(void *arg) 737 { 738 struct eg20t_port *priv = arg; 739 struct uart_port *port = &priv->port; 740 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 741 int count; 742 743 if (!tty) { 744 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 745 return; 746 } 747 748 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 749 count = dma_push_rx(priv, priv->trigger_level); 750 if (count) 751 tty_flip_buffer_push(tty); 752 tty_kref_put(tty); 753 async_tx_ack(priv->desc_rx); 754 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 755 } 756 757 static void pch_dma_tx_complete(void *arg) 758 { 759 struct eg20t_port *priv = arg; 760 struct uart_port *port = &priv->port; 761 struct circ_buf *xmit = &port->state->xmit; 762 struct scatterlist *sg = priv->sg_tx_p; 763 int i; 764 765 for (i = 0; i < priv->nent; i++, sg++) { 766 xmit->tail += sg_dma_len(sg); 767 port->icount.tx += sg_dma_len(sg); 768 } 769 xmit->tail &= UART_XMIT_SIZE - 1; 770 async_tx_ack(priv->desc_tx); 771 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 772 priv->tx_dma_use = 0; 773 priv->nent = 0; 774 kfree(priv->sg_tx_p); 775 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 776 } 777 778 static int pop_tx(struct eg20t_port *priv, int size) 779 { 780 int count = 0; 781 struct uart_port *port = &priv->port; 782 struct circ_buf *xmit = &port->state->xmit; 783 784 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 785 goto pop_tx_end; 786 787 do { 788 int cnt_to_end = 789 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 790 int sz = min(size - count, cnt_to_end); 791 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 792 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 793 count += sz; 794 } while (!uart_circ_empty(xmit) && count < size); 795 796 pop_tx_end: 797 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 798 count, size - count, jiffies); 799 800 return count; 801 } 802 803 static int handle_rx_to(struct eg20t_port *priv) 804 { 805 struct pch_uart_buffer *buf; 806 int rx_size; 807 int ret; 808 if (!priv->start_rx) { 809 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 810 return 0; 811 } 812 buf = &priv->rxbuf; 813 do { 814 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 815 ret = push_rx(priv, buf->buf, rx_size); 816 if (ret) 817 return 0; 818 } while (rx_size == buf->size); 819 820 return PCH_UART_HANDLED_RX_INT; 821 } 822 823 static int handle_rx(struct eg20t_port *priv) 824 { 825 return handle_rx_to(priv); 826 } 827 828 static int dma_handle_rx(struct eg20t_port *priv) 829 { 830 struct uart_port *port = &priv->port; 831 struct dma_async_tx_descriptor *desc; 832 struct scatterlist *sg; 833 834 priv = container_of(port, struct eg20t_port, port); 835 sg = &priv->sg_rx; 836 837 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 838 839 sg_dma_len(sg) = priv->trigger_level; 840 841 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 842 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 843 ~PAGE_MASK); 844 845 sg_dma_address(sg) = priv->rx_buf_dma; 846 847 desc = priv->chan_rx->device->device_prep_slave_sg(priv->chan_rx, 848 sg, 1, DMA_DEV_TO_MEM, 849 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 850 851 if (!desc) 852 return 0; 853 854 priv->desc_rx = desc; 855 desc->callback = pch_dma_rx_complete; 856 desc->callback_param = priv; 857 desc->tx_submit(desc); 858 dma_async_issue_pending(priv->chan_rx); 859 860 return PCH_UART_HANDLED_RX_INT; 861 } 862 863 static unsigned int handle_tx(struct eg20t_port *priv) 864 { 865 struct uart_port *port = &priv->port; 866 struct circ_buf *xmit = &port->state->xmit; 867 int fifo_size; 868 int tx_size; 869 int size; 870 int tx_empty; 871 872 if (!priv->start_tx) { 873 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 874 __func__, jiffies); 875 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 876 priv->tx_empty = 1; 877 return 0; 878 } 879 880 fifo_size = max(priv->fifo_size, 1); 881 tx_empty = 1; 882 if (pop_tx_x(priv, xmit->buf)) { 883 pch_uart_hal_write(priv, xmit->buf, 1); 884 port->icount.tx++; 885 tx_empty = 0; 886 fifo_size--; 887 } 888 size = min(xmit->head - xmit->tail, fifo_size); 889 if (size < 0) 890 size = fifo_size; 891 892 tx_size = pop_tx(priv, size); 893 if (tx_size > 0) { 894 port->icount.tx += tx_size; 895 tx_empty = 0; 896 } 897 898 priv->tx_empty = tx_empty; 899 900 if (tx_empty) { 901 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 902 uart_write_wakeup(port); 903 } 904 905 return PCH_UART_HANDLED_TX_INT; 906 } 907 908 static unsigned int dma_handle_tx(struct eg20t_port *priv) 909 { 910 struct uart_port *port = &priv->port; 911 struct circ_buf *xmit = &port->state->xmit; 912 struct scatterlist *sg; 913 int nent; 914 int fifo_size; 915 int tx_empty; 916 struct dma_async_tx_descriptor *desc; 917 int num; 918 int i; 919 int bytes; 920 int size; 921 int rem; 922 923 if (!priv->start_tx) { 924 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 925 __func__, jiffies); 926 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 927 priv->tx_empty = 1; 928 return 0; 929 } 930 931 if (priv->tx_dma_use) { 932 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 933 __func__, jiffies); 934 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 935 priv->tx_empty = 1; 936 return 0; 937 } 938 939 fifo_size = max(priv->fifo_size, 1); 940 tx_empty = 1; 941 if (pop_tx_x(priv, xmit->buf)) { 942 pch_uart_hal_write(priv, xmit->buf, 1); 943 port->icount.tx++; 944 tx_empty = 0; 945 fifo_size--; 946 } 947 948 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 949 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 950 xmit->tail, UART_XMIT_SIZE)); 951 if (!bytes) { 952 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 953 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 954 uart_write_wakeup(port); 955 return 0; 956 } 957 958 if (bytes > fifo_size) { 959 num = bytes / fifo_size + 1; 960 size = fifo_size; 961 rem = bytes % fifo_size; 962 } else { 963 num = 1; 964 size = bytes; 965 rem = bytes; 966 } 967 968 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 969 __func__, num, size, rem); 970 971 priv->tx_dma_use = 1; 972 973 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 974 975 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 976 sg = priv->sg_tx_p; 977 978 for (i = 0; i < num; i++, sg++) { 979 if (i == (num - 1)) 980 sg_set_page(sg, virt_to_page(xmit->buf), 981 rem, fifo_size * i); 982 else 983 sg_set_page(sg, virt_to_page(xmit->buf), 984 size, fifo_size * i); 985 } 986 987 sg = priv->sg_tx_p; 988 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 989 if (!nent) { 990 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 991 return 0; 992 } 993 priv->nent = nent; 994 995 for (i = 0; i < nent; i++, sg++) { 996 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 997 fifo_size * i; 998 sg_dma_address(sg) = (sg_dma_address(sg) & 999 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1000 if (i == (nent - 1)) 1001 sg_dma_len(sg) = rem; 1002 else 1003 sg_dma_len(sg) = size; 1004 } 1005 1006 desc = priv->chan_tx->device->device_prep_slave_sg(priv->chan_tx, 1007 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1008 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1009 if (!desc) { 1010 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 1011 __func__); 1012 return 0; 1013 } 1014 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1015 priv->desc_tx = desc; 1016 desc->callback = pch_dma_tx_complete; 1017 desc->callback_param = priv; 1018 1019 desc->tx_submit(desc); 1020 1021 dma_async_issue_pending(priv->chan_tx); 1022 1023 return PCH_UART_HANDLED_TX_INT; 1024 } 1025 1026 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1027 { 1028 u8 fcr = ioread8(priv->membase + UART_FCR); 1029 1030 /* Reset FIFO */ 1031 fcr |= UART_FCR_CLEAR_RCVR; 1032 iowrite8(fcr, priv->membase + UART_FCR); 1033 1034 if (lsr & PCH_UART_LSR_ERR) 1035 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 1036 1037 if (lsr & UART_LSR_FE) 1038 dev_err(&priv->pdev->dev, "Framing Error\n"); 1039 1040 if (lsr & UART_LSR_PE) 1041 dev_err(&priv->pdev->dev, "Parity Error\n"); 1042 1043 if (lsr & UART_LSR_OE) 1044 dev_err(&priv->pdev->dev, "Overrun Error\n"); 1045 } 1046 1047 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1048 { 1049 struct eg20t_port *priv = dev_id; 1050 unsigned int handled; 1051 u8 lsr; 1052 int ret = 0; 1053 unsigned int iid; 1054 unsigned long flags; 1055 1056 spin_lock_irqsave(&priv->port.lock, flags); 1057 handled = 0; 1058 while ((iid = pch_uart_hal_get_iid(priv)) > 1) { 1059 switch (iid) { 1060 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1061 lsr = pch_uart_hal_get_line_status(priv); 1062 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1063 UART_LSR_PE | UART_LSR_OE)) { 1064 pch_uart_err_ir(priv, lsr); 1065 ret = PCH_UART_HANDLED_RX_ERR_INT; 1066 } 1067 break; 1068 case PCH_UART_IID_RDR: /* Received Data Ready */ 1069 if (priv->use_dma) { 1070 pch_uart_hal_disable_interrupt(priv, 1071 PCH_UART_HAL_RX_INT); 1072 ret = dma_handle_rx(priv); 1073 if (!ret) 1074 pch_uart_hal_enable_interrupt(priv, 1075 PCH_UART_HAL_RX_INT); 1076 } else { 1077 ret = handle_rx(priv); 1078 } 1079 break; 1080 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1081 (FIFO Timeout) */ 1082 ret = handle_rx_to(priv); 1083 break; 1084 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1085 Empty */ 1086 if (priv->use_dma) 1087 ret = dma_handle_tx(priv); 1088 else 1089 ret = handle_tx(priv); 1090 break; 1091 case PCH_UART_IID_MS: /* Modem Status */ 1092 ret = PCH_UART_HANDLED_MS_INT; 1093 break; 1094 default: /* Never junp to this label */ 1095 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__, 1096 iid, jiffies); 1097 ret = -1; 1098 break; 1099 } 1100 handled |= (unsigned int)ret; 1101 } 1102 if (handled == 0 && iid <= 1) { 1103 if (priv->int_dis_flag) 1104 priv->int_dis_flag = 0; 1105 } 1106 1107 spin_unlock_irqrestore(&priv->port.lock, flags); 1108 return IRQ_RETVAL(handled); 1109 } 1110 1111 /* This function tests whether the transmitter fifo and shifter for the port 1112 described by 'port' is empty. */ 1113 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1114 { 1115 struct eg20t_port *priv; 1116 1117 priv = container_of(port, struct eg20t_port, port); 1118 if (priv->tx_empty) 1119 return TIOCSER_TEMT; 1120 else 1121 return 0; 1122 } 1123 1124 /* Returns the current state of modem control inputs. */ 1125 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1126 { 1127 struct eg20t_port *priv; 1128 u8 modem; 1129 unsigned int ret = 0; 1130 1131 priv = container_of(port, struct eg20t_port, port); 1132 modem = pch_uart_hal_get_modem(priv); 1133 1134 if (modem & UART_MSR_DCD) 1135 ret |= TIOCM_CAR; 1136 1137 if (modem & UART_MSR_RI) 1138 ret |= TIOCM_RNG; 1139 1140 if (modem & UART_MSR_DSR) 1141 ret |= TIOCM_DSR; 1142 1143 if (modem & UART_MSR_CTS) 1144 ret |= TIOCM_CTS; 1145 1146 return ret; 1147 } 1148 1149 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1150 { 1151 u32 mcr = 0; 1152 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1153 1154 if (mctrl & TIOCM_DTR) 1155 mcr |= UART_MCR_DTR; 1156 if (mctrl & TIOCM_RTS) 1157 mcr |= UART_MCR_RTS; 1158 if (mctrl & TIOCM_LOOP) 1159 mcr |= UART_MCR_LOOP; 1160 1161 if (priv->mcr & UART_MCR_AFE) 1162 mcr |= UART_MCR_AFE; 1163 1164 if (mctrl) 1165 iowrite8(mcr, priv->membase + UART_MCR); 1166 } 1167 1168 static void pch_uart_stop_tx(struct uart_port *port) 1169 { 1170 struct eg20t_port *priv; 1171 priv = container_of(port, struct eg20t_port, port); 1172 priv->start_tx = 0; 1173 priv->tx_dma_use = 0; 1174 } 1175 1176 static void pch_uart_start_tx(struct uart_port *port) 1177 { 1178 struct eg20t_port *priv; 1179 1180 priv = container_of(port, struct eg20t_port, port); 1181 1182 if (priv->use_dma) { 1183 if (priv->tx_dma_use) { 1184 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1185 __func__); 1186 return; 1187 } 1188 } 1189 1190 priv->start_tx = 1; 1191 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1192 } 1193 1194 static void pch_uart_stop_rx(struct uart_port *port) 1195 { 1196 struct eg20t_port *priv; 1197 priv = container_of(port, struct eg20t_port, port); 1198 priv->start_rx = 0; 1199 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT); 1200 priv->int_dis_flag = 1; 1201 } 1202 1203 /* Enable the modem status interrupts. */ 1204 static void pch_uart_enable_ms(struct uart_port *port) 1205 { 1206 struct eg20t_port *priv; 1207 priv = container_of(port, struct eg20t_port, port); 1208 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1209 } 1210 1211 /* Control the transmission of a break signal. */ 1212 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1213 { 1214 struct eg20t_port *priv; 1215 unsigned long flags; 1216 1217 priv = container_of(port, struct eg20t_port, port); 1218 spin_lock_irqsave(&port->lock, flags); 1219 pch_uart_hal_set_break(priv, ctl); 1220 spin_unlock_irqrestore(&port->lock, flags); 1221 } 1222 1223 /* Grab any interrupt resources and initialise any low level driver state. */ 1224 static int pch_uart_startup(struct uart_port *port) 1225 { 1226 struct eg20t_port *priv; 1227 int ret; 1228 int fifo_size; 1229 int trigger_level; 1230 1231 priv = container_of(port, struct eg20t_port, port); 1232 priv->tx_empty = 1; 1233 1234 if (port->uartclk) 1235 priv->uartclk = port->uartclk; 1236 else 1237 port->uartclk = priv->uartclk; 1238 1239 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1240 ret = pch_uart_hal_set_line(priv, default_baud, 1241 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1242 PCH_UART_HAL_STB1); 1243 if (ret) 1244 return ret; 1245 1246 switch (priv->fifo_size) { 1247 case 256: 1248 fifo_size = PCH_UART_HAL_FIFO256; 1249 break; 1250 case 64: 1251 fifo_size = PCH_UART_HAL_FIFO64; 1252 break; 1253 case 16: 1254 fifo_size = PCH_UART_HAL_FIFO16; 1255 case 1: 1256 default: 1257 fifo_size = PCH_UART_HAL_FIFO_DIS; 1258 break; 1259 } 1260 1261 switch (priv->trigger) { 1262 case PCH_UART_HAL_TRIGGER1: 1263 trigger_level = 1; 1264 break; 1265 case PCH_UART_HAL_TRIGGER_L: 1266 trigger_level = priv->fifo_size / 4; 1267 break; 1268 case PCH_UART_HAL_TRIGGER_M: 1269 trigger_level = priv->fifo_size / 2; 1270 break; 1271 case PCH_UART_HAL_TRIGGER_H: 1272 default: 1273 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1274 break; 1275 } 1276 1277 priv->trigger_level = trigger_level; 1278 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1279 fifo_size, priv->trigger); 1280 if (ret < 0) 1281 return ret; 1282 1283 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1284 KBUILD_MODNAME, priv); 1285 if (ret < 0) 1286 return ret; 1287 1288 if (priv->use_dma) 1289 pch_request_dma(port); 1290 1291 priv->start_rx = 1; 1292 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT); 1293 uart_update_timeout(port, CS8, default_baud); 1294 1295 return 0; 1296 } 1297 1298 static void pch_uart_shutdown(struct uart_port *port) 1299 { 1300 struct eg20t_port *priv; 1301 int ret; 1302 1303 priv = container_of(port, struct eg20t_port, port); 1304 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1305 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1306 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1307 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1308 if (ret) 1309 dev_err(priv->port.dev, 1310 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1311 1312 pch_free_dma(port); 1313 1314 free_irq(priv->port.irq, priv); 1315 } 1316 1317 /* Change the port parameters, including word length, parity, stop 1318 *bits. Update read_status_mask and ignore_status_mask to indicate 1319 *the types of events we are interested in receiving. */ 1320 static void pch_uart_set_termios(struct uart_port *port, 1321 struct ktermios *termios, struct ktermios *old) 1322 { 1323 int baud; 1324 int rtn; 1325 unsigned int parity, bits, stb; 1326 struct eg20t_port *priv; 1327 unsigned long flags; 1328 1329 priv = container_of(port, struct eg20t_port, port); 1330 switch (termios->c_cflag & CSIZE) { 1331 case CS5: 1332 bits = PCH_UART_HAL_5BIT; 1333 break; 1334 case CS6: 1335 bits = PCH_UART_HAL_6BIT; 1336 break; 1337 case CS7: 1338 bits = PCH_UART_HAL_7BIT; 1339 break; 1340 default: /* CS8 */ 1341 bits = PCH_UART_HAL_8BIT; 1342 break; 1343 } 1344 if (termios->c_cflag & CSTOPB) 1345 stb = PCH_UART_HAL_STB2; 1346 else 1347 stb = PCH_UART_HAL_STB1; 1348 1349 if (termios->c_cflag & PARENB) { 1350 if (!(termios->c_cflag & PARODD)) 1351 parity = PCH_UART_HAL_PARITY_ODD; 1352 else 1353 parity = PCH_UART_HAL_PARITY_EVEN; 1354 1355 } else 1356 parity = PCH_UART_HAL_PARITY_NONE; 1357 1358 /* Only UART0 has auto hardware flow function */ 1359 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1360 priv->mcr |= UART_MCR_AFE; 1361 else 1362 priv->mcr &= ~UART_MCR_AFE; 1363 1364 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1365 1366 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1367 1368 spin_lock_irqsave(&port->lock, flags); 1369 1370 uart_update_timeout(port, termios->c_cflag, baud); 1371 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1372 if (rtn) 1373 goto out; 1374 1375 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1376 /* Don't rewrite B0 */ 1377 if (tty_termios_baud_rate(termios)) 1378 tty_termios_encode_baud_rate(termios, baud, baud); 1379 1380 out: 1381 spin_unlock_irqrestore(&port->lock, flags); 1382 } 1383 1384 static const char *pch_uart_type(struct uart_port *port) 1385 { 1386 return KBUILD_MODNAME; 1387 } 1388 1389 static void pch_uart_release_port(struct uart_port *port) 1390 { 1391 struct eg20t_port *priv; 1392 1393 priv = container_of(port, struct eg20t_port, port); 1394 pci_iounmap(priv->pdev, priv->membase); 1395 pci_release_regions(priv->pdev); 1396 } 1397 1398 static int pch_uart_request_port(struct uart_port *port) 1399 { 1400 struct eg20t_port *priv; 1401 int ret; 1402 void __iomem *membase; 1403 1404 priv = container_of(port, struct eg20t_port, port); 1405 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1406 if (ret < 0) 1407 return -EBUSY; 1408 1409 membase = pci_iomap(priv->pdev, 1, 0); 1410 if (!membase) { 1411 pci_release_regions(priv->pdev); 1412 return -EBUSY; 1413 } 1414 priv->membase = port->membase = membase; 1415 1416 return 0; 1417 } 1418 1419 static void pch_uart_config_port(struct uart_port *port, int type) 1420 { 1421 struct eg20t_port *priv; 1422 1423 priv = container_of(port, struct eg20t_port, port); 1424 if (type & UART_CONFIG_TYPE) { 1425 port->type = priv->port_type; 1426 pch_uart_request_port(port); 1427 } 1428 } 1429 1430 static int pch_uart_verify_port(struct uart_port *port, 1431 struct serial_struct *serinfo) 1432 { 1433 struct eg20t_port *priv; 1434 1435 priv = container_of(port, struct eg20t_port, port); 1436 if (serinfo->flags & UPF_LOW_LATENCY) { 1437 dev_info(priv->port.dev, 1438 "PCH UART : Use PIO Mode (without DMA)\n"); 1439 priv->use_dma = 0; 1440 serinfo->flags &= ~UPF_LOW_LATENCY; 1441 } else { 1442 #ifndef CONFIG_PCH_DMA 1443 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1444 __func__); 1445 return -EOPNOTSUPP; 1446 #endif 1447 priv->use_dma = 1; 1448 priv->use_dma_flag = 1; 1449 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1450 } 1451 1452 return 0; 1453 } 1454 1455 static struct uart_ops pch_uart_ops = { 1456 .tx_empty = pch_uart_tx_empty, 1457 .set_mctrl = pch_uart_set_mctrl, 1458 .get_mctrl = pch_uart_get_mctrl, 1459 .stop_tx = pch_uart_stop_tx, 1460 .start_tx = pch_uart_start_tx, 1461 .stop_rx = pch_uart_stop_rx, 1462 .enable_ms = pch_uart_enable_ms, 1463 .break_ctl = pch_uart_break_ctl, 1464 .startup = pch_uart_startup, 1465 .shutdown = pch_uart_shutdown, 1466 .set_termios = pch_uart_set_termios, 1467 /* .pm = pch_uart_pm, Not supported yet */ 1468 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1469 .type = pch_uart_type, 1470 .release_port = pch_uart_release_port, 1471 .request_port = pch_uart_request_port, 1472 .config_port = pch_uart_config_port, 1473 .verify_port = pch_uart_verify_port 1474 }; 1475 1476 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1477 1478 /* 1479 * Wait for transmitter & holding register to empty 1480 */ 1481 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1482 { 1483 unsigned int status, tmout = 10000; 1484 1485 /* Wait up to 10ms for the character(s) to be sent. */ 1486 for (;;) { 1487 status = ioread8(up->membase + UART_LSR); 1488 1489 if ((status & bits) == bits) 1490 break; 1491 if (--tmout == 0) 1492 break; 1493 udelay(1); 1494 } 1495 1496 /* Wait up to 1s for flow control if necessary */ 1497 if (up->port.flags & UPF_CONS_FLOW) { 1498 unsigned int tmout; 1499 for (tmout = 1000000; tmout; tmout--) { 1500 unsigned int msr = ioread8(up->membase + UART_MSR); 1501 if (msr & UART_MSR_CTS) 1502 break; 1503 udelay(1); 1504 touch_nmi_watchdog(); 1505 } 1506 } 1507 } 1508 1509 static void pch_console_putchar(struct uart_port *port, int ch) 1510 { 1511 struct eg20t_port *priv = 1512 container_of(port, struct eg20t_port, port); 1513 1514 wait_for_xmitr(priv, UART_LSR_THRE); 1515 iowrite8(ch, priv->membase + PCH_UART_THR); 1516 } 1517 1518 /* 1519 * Print a string to the serial port trying not to disturb 1520 * any possible real use of the port... 1521 * 1522 * The console_lock must be held when we get here. 1523 */ 1524 static void 1525 pch_console_write(struct console *co, const char *s, unsigned int count) 1526 { 1527 struct eg20t_port *priv; 1528 unsigned long flags; 1529 u8 ier; 1530 int locked = 1; 1531 1532 priv = pch_uart_ports[co->index]; 1533 1534 touch_nmi_watchdog(); 1535 1536 local_irq_save(flags); 1537 if (priv->port.sysrq) { 1538 /* serial8250_handle_port() already took the lock */ 1539 locked = 0; 1540 } else if (oops_in_progress) { 1541 locked = spin_trylock(&priv->port.lock); 1542 } else 1543 spin_lock(&priv->port.lock); 1544 1545 /* 1546 * First save the IER then disable the interrupts 1547 */ 1548 ier = ioread8(priv->membase + UART_IER); 1549 1550 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1551 1552 uart_console_write(&priv->port, s, count, pch_console_putchar); 1553 1554 /* 1555 * Finally, wait for transmitter to become empty 1556 * and restore the IER 1557 */ 1558 wait_for_xmitr(priv, BOTH_EMPTY); 1559 iowrite8(ier, priv->membase + UART_IER); 1560 1561 if (locked) 1562 spin_unlock(&priv->port.lock); 1563 local_irq_restore(flags); 1564 } 1565 1566 static int __init pch_console_setup(struct console *co, char *options) 1567 { 1568 struct uart_port *port; 1569 int baud = default_baud; 1570 int bits = 8; 1571 int parity = 'n'; 1572 int flow = 'n'; 1573 1574 /* 1575 * Check whether an invalid uart number has been specified, and 1576 * if so, search for the first available port that does have 1577 * console support. 1578 */ 1579 if (co->index >= PCH_UART_NR) 1580 co->index = 0; 1581 port = &pch_uart_ports[co->index]->port; 1582 1583 if (!port || (!port->iobase && !port->membase)) 1584 return -ENODEV; 1585 1586 port->uartclk = pch_uart_get_uartclk(); 1587 1588 if (options) 1589 uart_parse_options(options, &baud, &parity, &bits, &flow); 1590 1591 return uart_set_options(port, co, baud, parity, bits, flow); 1592 } 1593 1594 static struct uart_driver pch_uart_driver; 1595 1596 static struct console pch_console = { 1597 .name = PCH_UART_DRIVER_DEVICE, 1598 .write = pch_console_write, 1599 .device = uart_console_device, 1600 .setup = pch_console_setup, 1601 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1602 .index = -1, 1603 .data = &pch_uart_driver, 1604 }; 1605 1606 #define PCH_CONSOLE (&pch_console) 1607 #else 1608 #define PCH_CONSOLE NULL 1609 #endif 1610 1611 static struct uart_driver pch_uart_driver = { 1612 .owner = THIS_MODULE, 1613 .driver_name = KBUILD_MODNAME, 1614 .dev_name = PCH_UART_DRIVER_DEVICE, 1615 .major = 0, 1616 .minor = 0, 1617 .nr = PCH_UART_NR, 1618 .cons = PCH_CONSOLE, 1619 }; 1620 1621 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1622 const struct pci_device_id *id) 1623 { 1624 struct eg20t_port *priv; 1625 int ret; 1626 unsigned int iobase; 1627 unsigned int mapbase; 1628 unsigned char *rxbuf; 1629 int fifosize; 1630 int port_type; 1631 struct pch_uart_driver_data *board; 1632 char name[32]; /* for debugfs file name */ 1633 1634 board = &drv_dat[id->driver_data]; 1635 port_type = board->port_type; 1636 1637 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1638 if (priv == NULL) 1639 goto init_port_alloc_err; 1640 1641 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1642 if (!rxbuf) 1643 goto init_port_free_txbuf; 1644 1645 switch (port_type) { 1646 case PORT_UNKNOWN: 1647 fifosize = 256; /* EG20T/ML7213: UART0 */ 1648 break; 1649 case PORT_8250: 1650 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1651 break; 1652 default: 1653 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1654 goto init_port_hal_free; 1655 } 1656 1657 pci_enable_msi(pdev); 1658 1659 iobase = pci_resource_start(pdev, 0); 1660 mapbase = pci_resource_start(pdev, 1); 1661 priv->mapbase = mapbase; 1662 priv->iobase = iobase; 1663 priv->pdev = pdev; 1664 priv->tx_empty = 1; 1665 priv->rxbuf.buf = rxbuf; 1666 priv->rxbuf.size = PAGE_SIZE; 1667 1668 priv->fifo_size = fifosize; 1669 priv->uartclk = pch_uart_get_uartclk(); 1670 priv->port_type = PORT_MAX_8250 + port_type + 1; 1671 priv->port.dev = &pdev->dev; 1672 priv->port.iobase = iobase; 1673 priv->port.membase = NULL; 1674 priv->port.mapbase = mapbase; 1675 priv->port.irq = pdev->irq; 1676 priv->port.iotype = UPIO_PORT; 1677 priv->port.ops = &pch_uart_ops; 1678 priv->port.flags = UPF_BOOT_AUTOCONF; 1679 priv->port.fifosize = fifosize; 1680 priv->port.line = board->line_no; 1681 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1682 1683 spin_lock_init(&priv->port.lock); 1684 1685 pci_set_drvdata(pdev, priv); 1686 priv->trigger_level = 1; 1687 priv->fcr = 0; 1688 1689 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1690 pch_uart_ports[board->line_no] = priv; 1691 #endif 1692 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1693 if (ret < 0) 1694 goto init_port_hal_free; 1695 1696 #ifdef CONFIG_DEBUG_FS 1697 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1698 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1699 NULL, priv, &port_regs_ops); 1700 #endif 1701 1702 return priv; 1703 1704 init_port_hal_free: 1705 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1706 pch_uart_ports[board->line_no] = NULL; 1707 #endif 1708 free_page((unsigned long)rxbuf); 1709 init_port_free_txbuf: 1710 kfree(priv); 1711 init_port_alloc_err: 1712 1713 return NULL; 1714 } 1715 1716 static void pch_uart_exit_port(struct eg20t_port *priv) 1717 { 1718 1719 #ifdef CONFIG_DEBUG_FS 1720 if (priv->debugfs) 1721 debugfs_remove(priv->debugfs); 1722 #endif 1723 uart_remove_one_port(&pch_uart_driver, &priv->port); 1724 pci_set_drvdata(priv->pdev, NULL); 1725 free_page((unsigned long)priv->rxbuf.buf); 1726 } 1727 1728 static void pch_uart_pci_remove(struct pci_dev *pdev) 1729 { 1730 struct eg20t_port *priv = pci_get_drvdata(pdev); 1731 1732 pci_disable_msi(pdev); 1733 1734 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1735 pch_uart_ports[priv->port.line] = NULL; 1736 #endif 1737 pch_uart_exit_port(priv); 1738 pci_disable_device(pdev); 1739 kfree(priv); 1740 return; 1741 } 1742 #ifdef CONFIG_PM 1743 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1744 { 1745 struct eg20t_port *priv = pci_get_drvdata(pdev); 1746 1747 uart_suspend_port(&pch_uart_driver, &priv->port); 1748 1749 pci_save_state(pdev); 1750 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1751 return 0; 1752 } 1753 1754 static int pch_uart_pci_resume(struct pci_dev *pdev) 1755 { 1756 struct eg20t_port *priv = pci_get_drvdata(pdev); 1757 int ret; 1758 1759 pci_set_power_state(pdev, PCI_D0); 1760 pci_restore_state(pdev); 1761 1762 ret = pci_enable_device(pdev); 1763 if (ret) { 1764 dev_err(&pdev->dev, 1765 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1766 return ret; 1767 } 1768 1769 uart_resume_port(&pch_uart_driver, &priv->port); 1770 1771 return 0; 1772 } 1773 #else 1774 #define pch_uart_pci_suspend NULL 1775 #define pch_uart_pci_resume NULL 1776 #endif 1777 1778 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1779 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1780 .driver_data = pch_et20t_uart0}, 1781 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1782 .driver_data = pch_et20t_uart1}, 1783 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1784 .driver_data = pch_et20t_uart2}, 1785 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1786 .driver_data = pch_et20t_uart3}, 1787 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1788 .driver_data = pch_ml7213_uart0}, 1789 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1790 .driver_data = pch_ml7213_uart1}, 1791 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1792 .driver_data = pch_ml7213_uart2}, 1793 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1794 .driver_data = pch_ml7223_uart0}, 1795 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1796 .driver_data = pch_ml7223_uart1}, 1797 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1798 .driver_data = pch_ml7831_uart0}, 1799 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1800 .driver_data = pch_ml7831_uart1}, 1801 {0,}, 1802 }; 1803 1804 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, 1805 const struct pci_device_id *id) 1806 { 1807 int ret; 1808 struct eg20t_port *priv; 1809 1810 ret = pci_enable_device(pdev); 1811 if (ret < 0) 1812 goto probe_error; 1813 1814 priv = pch_uart_init_port(pdev, id); 1815 if (!priv) { 1816 ret = -EBUSY; 1817 goto probe_disable_device; 1818 } 1819 pci_set_drvdata(pdev, priv); 1820 1821 return ret; 1822 1823 probe_disable_device: 1824 pci_disable_msi(pdev); 1825 pci_disable_device(pdev); 1826 probe_error: 1827 return ret; 1828 } 1829 1830 static struct pci_driver pch_uart_pci_driver = { 1831 .name = "pch_uart", 1832 .id_table = pch_uart_pci_id, 1833 .probe = pch_uart_pci_probe, 1834 .remove = __devexit_p(pch_uart_pci_remove), 1835 .suspend = pch_uart_pci_suspend, 1836 .resume = pch_uart_pci_resume, 1837 }; 1838 1839 static int __init pch_uart_module_init(void) 1840 { 1841 int ret; 1842 1843 /* register as UART driver */ 1844 ret = uart_register_driver(&pch_uart_driver); 1845 if (ret < 0) 1846 return ret; 1847 1848 /* register as PCI driver */ 1849 ret = pci_register_driver(&pch_uart_pci_driver); 1850 if (ret < 0) 1851 uart_unregister_driver(&pch_uart_driver); 1852 1853 return ret; 1854 } 1855 module_init(pch_uart_module_init); 1856 1857 static void __exit pch_uart_module_exit(void) 1858 { 1859 pci_unregister_driver(&pch_uart_pci_driver); 1860 uart_unregister_driver(&pch_uart_driver); 1861 } 1862 module_exit(pch_uart_module_exit); 1863 1864 MODULE_LICENSE("GPL v2"); 1865 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1866 module_param(default_baud, uint, S_IRUGO); 1867 MODULE_PARM_DESC(default_baud, 1868 "Default BAUD for initial driver state and console (default 9600)"); 1869 module_param(user_uartclk, uint, S_IRUGO); 1870 MODULE_PARM_DESC(user_uartclk, 1871 "Override UART default or board specific UART clock"); 1872