1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #include <linux/kernel.h> 18 #include <linux/serial_reg.h> 19 #include <linux/slab.h> 20 #include <linux/module.h> 21 #include <linux/pci.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/interrupt.h> 26 #include <linux/io.h> 27 #include <linux/dmi.h> 28 #include <linux/console.h> 29 #include <linux/nmi.h> 30 #include <linux/delay.h> 31 32 #include <linux/debugfs.h> 33 #include <linux/dmaengine.h> 34 #include <linux/pch_dma.h> 35 36 enum { 37 PCH_UART_HANDLED_RX_INT_SHIFT, 38 PCH_UART_HANDLED_TX_INT_SHIFT, 39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 41 PCH_UART_HANDLED_MS_INT_SHIFT, 42 PCH_UART_HANDLED_LS_INT_SHIFT, 43 }; 44 45 enum { 46 PCH_UART_8LINE, 47 PCH_UART_2LINE, 48 }; 49 50 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 51 52 /* Set the max number of UART port 53 * Intel EG20T PCH: 4 port 54 * LAPIS Semiconductor ML7213 IOH: 3 port 55 * LAPIS Semiconductor ML7223 IOH: 2 port 56 */ 57 #define PCH_UART_NR 4 58 59 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 61 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 62 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 63 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 64 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 65 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 66 67 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 68 69 #define PCH_UART_RBR 0x00 70 #define PCH_UART_THR 0x00 71 72 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 73 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 74 #define PCH_UART_IER_ERBFI 0x00000001 75 #define PCH_UART_IER_ETBEI 0x00000002 76 #define PCH_UART_IER_ELSI 0x00000004 77 #define PCH_UART_IER_EDSSI 0x00000008 78 79 #define PCH_UART_IIR_IP 0x00000001 80 #define PCH_UART_IIR_IID 0x00000006 81 #define PCH_UART_IIR_MSI 0x00000000 82 #define PCH_UART_IIR_TRI 0x00000002 83 #define PCH_UART_IIR_RRI 0x00000004 84 #define PCH_UART_IIR_REI 0x00000006 85 #define PCH_UART_IIR_TOI 0x00000008 86 #define PCH_UART_IIR_FIFO256 0x00000020 87 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 88 #define PCH_UART_IIR_FE 0x000000C0 89 90 #define PCH_UART_FCR_FIFOE 0x00000001 91 #define PCH_UART_FCR_RFR 0x00000002 92 #define PCH_UART_FCR_TFR 0x00000004 93 #define PCH_UART_FCR_DMS 0x00000008 94 #define PCH_UART_FCR_FIFO256 0x00000020 95 #define PCH_UART_FCR_RFTL 0x000000C0 96 97 #define PCH_UART_FCR_RFTL1 0x00000000 98 #define PCH_UART_FCR_RFTL64 0x00000040 99 #define PCH_UART_FCR_RFTL128 0x00000080 100 #define PCH_UART_FCR_RFTL224 0x000000C0 101 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 102 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 103 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 104 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 105 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 106 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 107 #define PCH_UART_FCR_RFTL_SHIFT 6 108 109 #define PCH_UART_LCR_WLS 0x00000003 110 #define PCH_UART_LCR_STB 0x00000004 111 #define PCH_UART_LCR_PEN 0x00000008 112 #define PCH_UART_LCR_EPS 0x00000010 113 #define PCH_UART_LCR_SP 0x00000020 114 #define PCH_UART_LCR_SB 0x00000040 115 #define PCH_UART_LCR_DLAB 0x00000080 116 #define PCH_UART_LCR_NP 0x00000000 117 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 118 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 119 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 120 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 121 PCH_UART_LCR_SP) 122 123 #define PCH_UART_LCR_5BIT 0x00000000 124 #define PCH_UART_LCR_6BIT 0x00000001 125 #define PCH_UART_LCR_7BIT 0x00000002 126 #define PCH_UART_LCR_8BIT 0x00000003 127 128 #define PCH_UART_MCR_DTR 0x00000001 129 #define PCH_UART_MCR_RTS 0x00000002 130 #define PCH_UART_MCR_OUT 0x0000000C 131 #define PCH_UART_MCR_LOOP 0x00000010 132 #define PCH_UART_MCR_AFE 0x00000020 133 134 #define PCH_UART_LSR_DR 0x00000001 135 #define PCH_UART_LSR_ERR (1<<7) 136 137 #define PCH_UART_MSR_DCTS 0x00000001 138 #define PCH_UART_MSR_DDSR 0x00000002 139 #define PCH_UART_MSR_TERI 0x00000004 140 #define PCH_UART_MSR_DDCD 0x00000008 141 #define PCH_UART_MSR_CTS 0x00000010 142 #define PCH_UART_MSR_DSR 0x00000020 143 #define PCH_UART_MSR_RI 0x00000040 144 #define PCH_UART_MSR_DCD 0x00000080 145 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 146 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 147 148 #define PCH_UART_DLL 0x00 149 #define PCH_UART_DLM 0x01 150 151 #define PCH_UART_BRCSR 0x0E 152 153 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 154 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 155 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 156 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 157 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 158 159 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 160 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 161 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 162 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 163 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 164 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 165 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 166 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 167 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 168 #define PCH_UART_HAL_STB1 0 169 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 170 171 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 172 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 173 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 174 PCH_UART_HAL_CLR_RX_FIFO) 175 176 #define PCH_UART_HAL_DMA_MODE0 0 177 #define PCH_UART_HAL_FIFO_DIS 0 178 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 179 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 180 PCH_UART_FCR_FIFO256) 181 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 182 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 183 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 184 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 185 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 186 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 187 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 188 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 189 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 190 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 191 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 192 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 193 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 194 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 195 196 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 197 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 198 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 199 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 200 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 201 202 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 203 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 204 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 205 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 206 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 207 208 #define PCI_VENDOR_ID_ROHM 0x10DB 209 210 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 211 212 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 213 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 214 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 215 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 216 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 217 218 struct pch_uart_buffer { 219 unsigned char *buf; 220 int size; 221 }; 222 223 struct eg20t_port { 224 struct uart_port port; 225 int port_type; 226 void __iomem *membase; 227 resource_size_t mapbase; 228 unsigned int iobase; 229 struct pci_dev *pdev; 230 int fifo_size; 231 int uartclk; 232 int start_tx; 233 int start_rx; 234 int tx_empty; 235 int trigger; 236 int trigger_level; 237 struct pch_uart_buffer rxbuf; 238 unsigned int dmsr; 239 unsigned int fcr; 240 unsigned int mcr; 241 unsigned int use_dma; 242 struct dma_async_tx_descriptor *desc_tx; 243 struct dma_async_tx_descriptor *desc_rx; 244 struct pch_dma_slave param_tx; 245 struct pch_dma_slave param_rx; 246 struct dma_chan *chan_tx; 247 struct dma_chan *chan_rx; 248 struct scatterlist *sg_tx_p; 249 int nent; 250 struct scatterlist sg_rx; 251 int tx_dma_use; 252 void *rx_buf_virt; 253 dma_addr_t rx_buf_dma; 254 255 struct dentry *debugfs; 256 257 /* protect the eg20t_port private structure and io access to membase */ 258 spinlock_t lock; 259 }; 260 261 /** 262 * struct pch_uart_driver_data - private data structure for UART-DMA 263 * @port_type: The number of DMA channel 264 * @line_no: UART port line number (0, 1, 2...) 265 */ 266 struct pch_uart_driver_data { 267 int port_type; 268 int line_no; 269 }; 270 271 enum pch_uart_num_t { 272 pch_et20t_uart0 = 0, 273 pch_et20t_uart1, 274 pch_et20t_uart2, 275 pch_et20t_uart3, 276 pch_ml7213_uart0, 277 pch_ml7213_uart1, 278 pch_ml7213_uart2, 279 pch_ml7223_uart0, 280 pch_ml7223_uart1, 281 pch_ml7831_uart0, 282 pch_ml7831_uart1, 283 }; 284 285 static struct pch_uart_driver_data drv_dat[] = { 286 [pch_et20t_uart0] = {PCH_UART_8LINE, 0}, 287 [pch_et20t_uart1] = {PCH_UART_2LINE, 1}, 288 [pch_et20t_uart2] = {PCH_UART_2LINE, 2}, 289 [pch_et20t_uart3] = {PCH_UART_2LINE, 3}, 290 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0}, 291 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1}, 292 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2}, 293 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0}, 294 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1}, 295 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0}, 296 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1}, 297 }; 298 299 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 300 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 301 #endif 302 static unsigned int default_baud = 9600; 303 static unsigned int user_uartclk = 0; 304 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 305 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 306 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 307 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 308 309 #ifdef CONFIG_DEBUG_FS 310 311 #define PCH_REGS_BUFSIZE 1024 312 313 314 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 315 size_t count, loff_t *ppos) 316 { 317 struct eg20t_port *priv = file->private_data; 318 char *buf; 319 u32 len = 0; 320 ssize_t ret; 321 unsigned char lcr; 322 323 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 324 if (!buf) 325 return 0; 326 327 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 328 "PCH EG20T port[%d] regs:\n", priv->port.line); 329 330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 331 "=================================\n"); 332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 333 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 335 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 337 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 339 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 341 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 343 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 345 "BRCSR: \t0x%02x\n", 346 ioread8(priv->membase + PCH_UART_BRCSR)); 347 348 lcr = ioread8(priv->membase + UART_LCR); 349 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 350 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 351 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 352 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 353 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 354 iowrite8(lcr, priv->membase + UART_LCR); 355 356 if (len > PCH_REGS_BUFSIZE) 357 len = PCH_REGS_BUFSIZE; 358 359 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 360 kfree(buf); 361 return ret; 362 } 363 364 static const struct file_operations port_regs_ops = { 365 .owner = THIS_MODULE, 366 .open = simple_open, 367 .read = port_show_regs, 368 .llseek = default_llseek, 369 }; 370 #endif /* CONFIG_DEBUG_FS */ 371 372 /* Return UART clock, checking for board specific clocks. */ 373 static int pch_uart_get_uartclk(void) 374 { 375 const char *cmp; 376 377 if (user_uartclk) 378 return user_uartclk; 379 380 cmp = dmi_get_system_info(DMI_BOARD_NAME); 381 if (cmp && strstr(cmp, "CM-iTC")) 382 return CMITC_UARTCLK; 383 384 cmp = dmi_get_system_info(DMI_BIOS_VERSION); 385 if (cmp && strnstr(cmp, "FRI2", 4)) 386 return FRI2_64_UARTCLK; 387 388 cmp = dmi_get_system_info(DMI_PRODUCT_NAME); 389 if (cmp && strstr(cmp, "Fish River Island II")) 390 return FRI2_48_UARTCLK; 391 392 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */ 393 cmp = dmi_get_system_info(DMI_BOARD_NAME); 394 if (cmp && (strstr(cmp, "COMe-mTT") || 395 strstr(cmp, "nanoETXexpress-TT"))) 396 return NTC1_UARTCLK; 397 398 return DEFAULT_UARTCLK; 399 } 400 401 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 402 unsigned int flag) 403 { 404 u8 ier = ioread8(priv->membase + UART_IER); 405 ier |= flag & PCH_UART_IER_MASK; 406 iowrite8(ier, priv->membase + UART_IER); 407 } 408 409 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 410 unsigned int flag) 411 { 412 u8 ier = ioread8(priv->membase + UART_IER); 413 ier &= ~(flag & PCH_UART_IER_MASK); 414 iowrite8(ier, priv->membase + UART_IER); 415 } 416 417 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud, 418 unsigned int parity, unsigned int bits, 419 unsigned int stb) 420 { 421 unsigned int dll, dlm, lcr; 422 int div; 423 424 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 425 if (div < 0 || USHRT_MAX <= div) { 426 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 427 return -EINVAL; 428 } 429 430 dll = (unsigned int)div & 0x00FFU; 431 dlm = ((unsigned int)div >> 8) & 0x00FFU; 432 433 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 434 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 435 return -EINVAL; 436 } 437 438 if (bits & ~PCH_UART_LCR_WLS) { 439 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 440 return -EINVAL; 441 } 442 443 if (stb & ~PCH_UART_LCR_STB) { 444 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 445 return -EINVAL; 446 } 447 448 lcr = parity; 449 lcr |= bits; 450 lcr |= stb; 451 452 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n", 453 __func__, baud, div, lcr, jiffies); 454 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 455 iowrite8(dll, priv->membase + PCH_UART_DLL); 456 iowrite8(dlm, priv->membase + PCH_UART_DLM); 457 iowrite8(lcr, priv->membase + UART_LCR); 458 459 return 0; 460 } 461 462 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 463 unsigned int flag) 464 { 465 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 466 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 467 __func__, flag); 468 return -EINVAL; 469 } 470 471 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 472 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 473 priv->membase + UART_FCR); 474 iowrite8(priv->fcr, priv->membase + UART_FCR); 475 476 return 0; 477 } 478 479 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 480 unsigned int dmamode, 481 unsigned int fifo_size, unsigned int trigger) 482 { 483 u8 fcr; 484 485 if (dmamode & ~PCH_UART_FCR_DMS) { 486 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 487 __func__, dmamode); 488 return -EINVAL; 489 } 490 491 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 492 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 493 __func__, fifo_size); 494 return -EINVAL; 495 } 496 497 if (trigger & ~PCH_UART_FCR_RFTL) { 498 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 499 __func__, trigger); 500 return -EINVAL; 501 } 502 503 switch (priv->fifo_size) { 504 case 256: 505 priv->trigger_level = 506 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 507 break; 508 case 64: 509 priv->trigger_level = 510 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 511 break; 512 case 16: 513 priv->trigger_level = 514 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 515 break; 516 default: 517 priv->trigger_level = 518 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 519 break; 520 } 521 fcr = 522 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 523 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 524 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 525 priv->membase + UART_FCR); 526 iowrite8(fcr, priv->membase + UART_FCR); 527 priv->fcr = fcr; 528 529 return 0; 530 } 531 532 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 533 { 534 unsigned int msr = ioread8(priv->membase + UART_MSR); 535 priv->dmsr = msr & PCH_UART_MSR_DELTA; 536 return (u8)msr; 537 } 538 539 static void pch_uart_hal_write(struct eg20t_port *priv, 540 const unsigned char *buf, int tx_size) 541 { 542 int i; 543 unsigned int thr; 544 545 for (i = 0; i < tx_size;) { 546 thr = buf[i++]; 547 iowrite8(thr, priv->membase + PCH_UART_THR); 548 } 549 } 550 551 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 552 int rx_size) 553 { 554 int i; 555 u8 rbr, lsr; 556 557 lsr = ioread8(priv->membase + UART_LSR); 558 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 559 i < rx_size && lsr & UART_LSR_DR; 560 lsr = ioread8(priv->membase + UART_LSR)) { 561 rbr = ioread8(priv->membase + PCH_UART_RBR); 562 buf[i++] = rbr; 563 } 564 return i; 565 } 566 567 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 568 { 569 return ioread8(priv->membase + UART_IIR) &\ 570 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 571 } 572 573 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 574 { 575 return ioread8(priv->membase + UART_LSR); 576 } 577 578 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 579 { 580 unsigned int lcr; 581 582 lcr = ioread8(priv->membase + UART_LCR); 583 if (on) 584 lcr |= PCH_UART_LCR_SB; 585 else 586 lcr &= ~PCH_UART_LCR_SB; 587 588 iowrite8(lcr, priv->membase + UART_LCR); 589 } 590 591 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 592 int size) 593 { 594 struct uart_port *port; 595 struct tty_struct *tty; 596 597 port = &priv->port; 598 tty = tty_port_tty_get(&port->state->port); 599 if (!tty) { 600 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 601 return -EBUSY; 602 } 603 604 tty_insert_flip_string(tty, buf, size); 605 tty_flip_buffer_push(tty); 606 tty_kref_put(tty); 607 608 return 0; 609 } 610 611 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 612 { 613 int ret = 0; 614 struct uart_port *port = &priv->port; 615 616 if (port->x_char) { 617 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 618 __func__, port->x_char, jiffies); 619 buf[0] = port->x_char; 620 port->x_char = 0; 621 ret = 1; 622 } 623 624 return ret; 625 } 626 627 static int dma_push_rx(struct eg20t_port *priv, int size) 628 { 629 struct tty_struct *tty; 630 int room; 631 struct uart_port *port = &priv->port; 632 633 port = &priv->port; 634 tty = tty_port_tty_get(&port->state->port); 635 if (!tty) { 636 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 637 return 0; 638 } 639 640 room = tty_buffer_request_room(tty, size); 641 642 if (room < size) 643 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 644 size - room); 645 if (!room) 646 return room; 647 648 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size); 649 650 port->icount.rx += room; 651 tty_kref_put(tty); 652 653 return room; 654 } 655 656 static void pch_free_dma(struct uart_port *port) 657 { 658 struct eg20t_port *priv; 659 priv = container_of(port, struct eg20t_port, port); 660 661 if (priv->chan_tx) { 662 dma_release_channel(priv->chan_tx); 663 priv->chan_tx = NULL; 664 } 665 if (priv->chan_rx) { 666 dma_release_channel(priv->chan_rx); 667 priv->chan_rx = NULL; 668 } 669 670 if (priv->rx_buf_dma) { 671 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 672 priv->rx_buf_dma); 673 priv->rx_buf_virt = NULL; 674 priv->rx_buf_dma = 0; 675 } 676 677 return; 678 } 679 680 static bool filter(struct dma_chan *chan, void *slave) 681 { 682 struct pch_dma_slave *param = slave; 683 684 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 685 chan->device->dev)) { 686 chan->private = param; 687 return true; 688 } else { 689 return false; 690 } 691 } 692 693 static void pch_request_dma(struct uart_port *port) 694 { 695 dma_cap_mask_t mask; 696 struct dma_chan *chan; 697 struct pci_dev *dma_dev; 698 struct pch_dma_slave *param; 699 struct eg20t_port *priv = 700 container_of(port, struct eg20t_port, port); 701 dma_cap_zero(mask); 702 dma_cap_set(DMA_SLAVE, mask); 703 704 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number, 705 PCI_DEVFN(0xa, 0)); /* Get DMA's dev 706 information */ 707 /* Set Tx DMA */ 708 param = &priv->param_tx; 709 param->dma_dev = &dma_dev->dev; 710 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 711 712 param->tx_reg = port->mapbase + UART_TX; 713 chan = dma_request_channel(mask, filter, param); 714 if (!chan) { 715 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 716 __func__); 717 return; 718 } 719 priv->chan_tx = chan; 720 721 /* Set Rx DMA */ 722 param = &priv->param_rx; 723 param->dma_dev = &dma_dev->dev; 724 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 725 726 param->rx_reg = port->mapbase + UART_RX; 727 chan = dma_request_channel(mask, filter, param); 728 if (!chan) { 729 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 730 __func__); 731 dma_release_channel(priv->chan_tx); 732 priv->chan_tx = NULL; 733 return; 734 } 735 736 /* Get Consistent memory for DMA */ 737 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 738 &priv->rx_buf_dma, GFP_KERNEL); 739 priv->chan_rx = chan; 740 } 741 742 static void pch_dma_rx_complete(void *arg) 743 { 744 struct eg20t_port *priv = arg; 745 struct uart_port *port = &priv->port; 746 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 747 int count; 748 749 if (!tty) { 750 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__); 751 return; 752 } 753 754 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 755 count = dma_push_rx(priv, priv->trigger_level); 756 if (count) 757 tty_flip_buffer_push(tty); 758 tty_kref_put(tty); 759 async_tx_ack(priv->desc_rx); 760 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 761 PCH_UART_HAL_RX_ERR_INT); 762 } 763 764 static void pch_dma_tx_complete(void *arg) 765 { 766 struct eg20t_port *priv = arg; 767 struct uart_port *port = &priv->port; 768 struct circ_buf *xmit = &port->state->xmit; 769 struct scatterlist *sg = priv->sg_tx_p; 770 int i; 771 772 for (i = 0; i < priv->nent; i++, sg++) { 773 xmit->tail += sg_dma_len(sg); 774 port->icount.tx += sg_dma_len(sg); 775 } 776 xmit->tail &= UART_XMIT_SIZE - 1; 777 async_tx_ack(priv->desc_tx); 778 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 779 priv->tx_dma_use = 0; 780 priv->nent = 0; 781 kfree(priv->sg_tx_p); 782 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 783 } 784 785 static int pop_tx(struct eg20t_port *priv, int size) 786 { 787 int count = 0; 788 struct uart_port *port = &priv->port; 789 struct circ_buf *xmit = &port->state->xmit; 790 791 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 792 goto pop_tx_end; 793 794 do { 795 int cnt_to_end = 796 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 797 int sz = min(size - count, cnt_to_end); 798 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 799 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 800 count += sz; 801 } while (!uart_circ_empty(xmit) && count < size); 802 803 pop_tx_end: 804 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 805 count, size - count, jiffies); 806 807 return count; 808 } 809 810 static int handle_rx_to(struct eg20t_port *priv) 811 { 812 struct pch_uart_buffer *buf; 813 int rx_size; 814 int ret; 815 if (!priv->start_rx) { 816 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 817 PCH_UART_HAL_RX_ERR_INT); 818 return 0; 819 } 820 buf = &priv->rxbuf; 821 do { 822 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 823 ret = push_rx(priv, buf->buf, rx_size); 824 if (ret) 825 return 0; 826 } while (rx_size == buf->size); 827 828 return PCH_UART_HANDLED_RX_INT; 829 } 830 831 static int handle_rx(struct eg20t_port *priv) 832 { 833 return handle_rx_to(priv); 834 } 835 836 static int dma_handle_rx(struct eg20t_port *priv) 837 { 838 struct uart_port *port = &priv->port; 839 struct dma_async_tx_descriptor *desc; 840 struct scatterlist *sg; 841 842 priv = container_of(port, struct eg20t_port, port); 843 sg = &priv->sg_rx; 844 845 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 846 847 sg_dma_len(sg) = priv->trigger_level; 848 849 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 850 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt & 851 ~PAGE_MASK); 852 853 sg_dma_address(sg) = priv->rx_buf_dma; 854 855 desc = dmaengine_prep_slave_sg(priv->chan_rx, 856 sg, 1, DMA_DEV_TO_MEM, 857 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 858 859 if (!desc) 860 return 0; 861 862 priv->desc_rx = desc; 863 desc->callback = pch_dma_rx_complete; 864 desc->callback_param = priv; 865 desc->tx_submit(desc); 866 dma_async_issue_pending(priv->chan_rx); 867 868 return PCH_UART_HANDLED_RX_INT; 869 } 870 871 static unsigned int handle_tx(struct eg20t_port *priv) 872 { 873 struct uart_port *port = &priv->port; 874 struct circ_buf *xmit = &port->state->xmit; 875 int fifo_size; 876 int tx_size; 877 int size; 878 int tx_empty; 879 880 if (!priv->start_tx) { 881 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 882 __func__, jiffies); 883 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 884 priv->tx_empty = 1; 885 return 0; 886 } 887 888 fifo_size = max(priv->fifo_size, 1); 889 tx_empty = 1; 890 if (pop_tx_x(priv, xmit->buf)) { 891 pch_uart_hal_write(priv, xmit->buf, 1); 892 port->icount.tx++; 893 tx_empty = 0; 894 fifo_size--; 895 } 896 size = min(xmit->head - xmit->tail, fifo_size); 897 if (size < 0) 898 size = fifo_size; 899 900 tx_size = pop_tx(priv, size); 901 if (tx_size > 0) { 902 port->icount.tx += tx_size; 903 tx_empty = 0; 904 } 905 906 priv->tx_empty = tx_empty; 907 908 if (tx_empty) { 909 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 910 uart_write_wakeup(port); 911 } 912 913 return PCH_UART_HANDLED_TX_INT; 914 } 915 916 static unsigned int dma_handle_tx(struct eg20t_port *priv) 917 { 918 struct uart_port *port = &priv->port; 919 struct circ_buf *xmit = &port->state->xmit; 920 struct scatterlist *sg; 921 int nent; 922 int fifo_size; 923 int tx_empty; 924 struct dma_async_tx_descriptor *desc; 925 int num; 926 int i; 927 int bytes; 928 int size; 929 int rem; 930 931 if (!priv->start_tx) { 932 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 933 __func__, jiffies); 934 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 935 priv->tx_empty = 1; 936 return 0; 937 } 938 939 if (priv->tx_dma_use) { 940 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 941 __func__, jiffies); 942 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 943 priv->tx_empty = 1; 944 return 0; 945 } 946 947 fifo_size = max(priv->fifo_size, 1); 948 tx_empty = 1; 949 if (pop_tx_x(priv, xmit->buf)) { 950 pch_uart_hal_write(priv, xmit->buf, 1); 951 port->icount.tx++; 952 tx_empty = 0; 953 fifo_size--; 954 } 955 956 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 957 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 958 xmit->tail, UART_XMIT_SIZE)); 959 if (!bytes) { 960 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 961 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 962 uart_write_wakeup(port); 963 return 0; 964 } 965 966 if (bytes > fifo_size) { 967 num = bytes / fifo_size + 1; 968 size = fifo_size; 969 rem = bytes % fifo_size; 970 } else { 971 num = 1; 972 size = bytes; 973 rem = bytes; 974 } 975 976 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 977 __func__, num, size, rem); 978 979 priv->tx_dma_use = 1; 980 981 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 982 983 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 984 sg = priv->sg_tx_p; 985 986 for (i = 0; i < num; i++, sg++) { 987 if (i == (num - 1)) 988 sg_set_page(sg, virt_to_page(xmit->buf), 989 rem, fifo_size * i); 990 else 991 sg_set_page(sg, virt_to_page(xmit->buf), 992 size, fifo_size * i); 993 } 994 995 sg = priv->sg_tx_p; 996 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 997 if (!nent) { 998 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 999 return 0; 1000 } 1001 priv->nent = nent; 1002 1003 for (i = 0; i < nent; i++, sg++) { 1004 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 1005 fifo_size * i; 1006 sg_dma_address(sg) = (sg_dma_address(sg) & 1007 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1008 if (i == (nent - 1)) 1009 sg_dma_len(sg) = rem; 1010 else 1011 sg_dma_len(sg) = size; 1012 } 1013 1014 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1015 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1016 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1017 if (!desc) { 1018 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n", 1019 __func__); 1020 return 0; 1021 } 1022 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1023 priv->desc_tx = desc; 1024 desc->callback = pch_dma_tx_complete; 1025 desc->callback_param = priv; 1026 1027 desc->tx_submit(desc); 1028 1029 dma_async_issue_pending(priv->chan_tx); 1030 1031 return PCH_UART_HANDLED_TX_INT; 1032 } 1033 1034 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1035 { 1036 u8 fcr = ioread8(priv->membase + UART_FCR); 1037 1038 /* Reset FIFO */ 1039 fcr |= UART_FCR_CLEAR_RCVR; 1040 iowrite8(fcr, priv->membase + UART_FCR); 1041 1042 if (lsr & PCH_UART_LSR_ERR) 1043 dev_err(&priv->pdev->dev, "Error data in FIFO\n"); 1044 1045 if (lsr & UART_LSR_FE) 1046 dev_err(&priv->pdev->dev, "Framing Error\n"); 1047 1048 if (lsr & UART_LSR_PE) 1049 dev_err(&priv->pdev->dev, "Parity Error\n"); 1050 1051 if (lsr & UART_LSR_OE) 1052 dev_err(&priv->pdev->dev, "Overrun Error\n"); 1053 } 1054 1055 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1056 { 1057 struct eg20t_port *priv = dev_id; 1058 unsigned int handled; 1059 u8 lsr; 1060 int ret = 0; 1061 unsigned char iid; 1062 unsigned long flags; 1063 int next = 1; 1064 u8 msr; 1065 1066 spin_lock_irqsave(&priv->lock, flags); 1067 handled = 0; 1068 while (next) { 1069 iid = pch_uart_hal_get_iid(priv); 1070 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1071 break; 1072 switch (iid) { 1073 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1074 lsr = pch_uart_hal_get_line_status(priv); 1075 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1076 UART_LSR_PE | UART_LSR_OE)) { 1077 pch_uart_err_ir(priv, lsr); 1078 ret = PCH_UART_HANDLED_RX_ERR_INT; 1079 } else { 1080 ret = PCH_UART_HANDLED_LS_INT; 1081 } 1082 break; 1083 case PCH_UART_IID_RDR: /* Received Data Ready */ 1084 if (priv->use_dma) { 1085 pch_uart_hal_disable_interrupt(priv, 1086 PCH_UART_HAL_RX_INT | 1087 PCH_UART_HAL_RX_ERR_INT); 1088 ret = dma_handle_rx(priv); 1089 if (!ret) 1090 pch_uart_hal_enable_interrupt(priv, 1091 PCH_UART_HAL_RX_INT | 1092 PCH_UART_HAL_RX_ERR_INT); 1093 } else { 1094 ret = handle_rx(priv); 1095 } 1096 break; 1097 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1098 (FIFO Timeout) */ 1099 ret = handle_rx_to(priv); 1100 break; 1101 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1102 Empty */ 1103 if (priv->use_dma) 1104 ret = dma_handle_tx(priv); 1105 else 1106 ret = handle_tx(priv); 1107 break; 1108 case PCH_UART_IID_MS: /* Modem Status */ 1109 msr = pch_uart_hal_get_modem(priv); 1110 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1111 means final interrupt */ 1112 if ((msr & UART_MSR_ANY_DELTA) == 0) 1113 break; 1114 ret |= PCH_UART_HANDLED_MS_INT; 1115 break; 1116 default: /* Never junp to this label */ 1117 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1118 iid, jiffies); 1119 ret = -1; 1120 next = 0; 1121 break; 1122 } 1123 handled |= (unsigned int)ret; 1124 } 1125 1126 spin_unlock_irqrestore(&priv->lock, flags); 1127 return IRQ_RETVAL(handled); 1128 } 1129 1130 /* This function tests whether the transmitter fifo and shifter for the port 1131 described by 'port' is empty. */ 1132 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1133 { 1134 struct eg20t_port *priv; 1135 1136 priv = container_of(port, struct eg20t_port, port); 1137 if (priv->tx_empty) 1138 return TIOCSER_TEMT; 1139 else 1140 return 0; 1141 } 1142 1143 /* Returns the current state of modem control inputs. */ 1144 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1145 { 1146 struct eg20t_port *priv; 1147 u8 modem; 1148 unsigned int ret = 0; 1149 1150 priv = container_of(port, struct eg20t_port, port); 1151 modem = pch_uart_hal_get_modem(priv); 1152 1153 if (modem & UART_MSR_DCD) 1154 ret |= TIOCM_CAR; 1155 1156 if (modem & UART_MSR_RI) 1157 ret |= TIOCM_RNG; 1158 1159 if (modem & UART_MSR_DSR) 1160 ret |= TIOCM_DSR; 1161 1162 if (modem & UART_MSR_CTS) 1163 ret |= TIOCM_CTS; 1164 1165 return ret; 1166 } 1167 1168 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1169 { 1170 u32 mcr = 0; 1171 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1172 1173 if (mctrl & TIOCM_DTR) 1174 mcr |= UART_MCR_DTR; 1175 if (mctrl & TIOCM_RTS) 1176 mcr |= UART_MCR_RTS; 1177 if (mctrl & TIOCM_LOOP) 1178 mcr |= UART_MCR_LOOP; 1179 1180 if (priv->mcr & UART_MCR_AFE) 1181 mcr |= UART_MCR_AFE; 1182 1183 if (mctrl) 1184 iowrite8(mcr, priv->membase + UART_MCR); 1185 } 1186 1187 static void pch_uart_stop_tx(struct uart_port *port) 1188 { 1189 struct eg20t_port *priv; 1190 priv = container_of(port, struct eg20t_port, port); 1191 priv->start_tx = 0; 1192 priv->tx_dma_use = 0; 1193 } 1194 1195 static void pch_uart_start_tx(struct uart_port *port) 1196 { 1197 struct eg20t_port *priv; 1198 1199 priv = container_of(port, struct eg20t_port, port); 1200 1201 if (priv->use_dma) { 1202 if (priv->tx_dma_use) { 1203 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1204 __func__); 1205 return; 1206 } 1207 } 1208 1209 priv->start_tx = 1; 1210 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1211 } 1212 1213 static void pch_uart_stop_rx(struct uart_port *port) 1214 { 1215 struct eg20t_port *priv; 1216 priv = container_of(port, struct eg20t_port, port); 1217 priv->start_rx = 0; 1218 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1219 PCH_UART_HAL_RX_ERR_INT); 1220 } 1221 1222 /* Enable the modem status interrupts. */ 1223 static void pch_uart_enable_ms(struct uart_port *port) 1224 { 1225 struct eg20t_port *priv; 1226 priv = container_of(port, struct eg20t_port, port); 1227 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1228 } 1229 1230 /* Control the transmission of a break signal. */ 1231 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1232 { 1233 struct eg20t_port *priv; 1234 unsigned long flags; 1235 1236 priv = container_of(port, struct eg20t_port, port); 1237 spin_lock_irqsave(&priv->lock, flags); 1238 pch_uart_hal_set_break(priv, ctl); 1239 spin_unlock_irqrestore(&priv->lock, flags); 1240 } 1241 1242 /* Grab any interrupt resources and initialise any low level driver state. */ 1243 static int pch_uart_startup(struct uart_port *port) 1244 { 1245 struct eg20t_port *priv; 1246 int ret; 1247 int fifo_size; 1248 int trigger_level; 1249 1250 priv = container_of(port, struct eg20t_port, port); 1251 priv->tx_empty = 1; 1252 1253 if (port->uartclk) 1254 priv->uartclk = port->uartclk; 1255 else 1256 port->uartclk = priv->uartclk; 1257 1258 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1259 ret = pch_uart_hal_set_line(priv, default_baud, 1260 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1261 PCH_UART_HAL_STB1); 1262 if (ret) 1263 return ret; 1264 1265 switch (priv->fifo_size) { 1266 case 256: 1267 fifo_size = PCH_UART_HAL_FIFO256; 1268 break; 1269 case 64: 1270 fifo_size = PCH_UART_HAL_FIFO64; 1271 break; 1272 case 16: 1273 fifo_size = PCH_UART_HAL_FIFO16; 1274 break; 1275 case 1: 1276 default: 1277 fifo_size = PCH_UART_HAL_FIFO_DIS; 1278 break; 1279 } 1280 1281 switch (priv->trigger) { 1282 case PCH_UART_HAL_TRIGGER1: 1283 trigger_level = 1; 1284 break; 1285 case PCH_UART_HAL_TRIGGER_L: 1286 trigger_level = priv->fifo_size / 4; 1287 break; 1288 case PCH_UART_HAL_TRIGGER_M: 1289 trigger_level = priv->fifo_size / 2; 1290 break; 1291 case PCH_UART_HAL_TRIGGER_H: 1292 default: 1293 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1294 break; 1295 } 1296 1297 priv->trigger_level = trigger_level; 1298 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1299 fifo_size, priv->trigger); 1300 if (ret < 0) 1301 return ret; 1302 1303 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1304 KBUILD_MODNAME, priv); 1305 if (ret < 0) 1306 return ret; 1307 1308 if (priv->use_dma) 1309 pch_request_dma(port); 1310 1311 priv->start_rx = 1; 1312 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1313 PCH_UART_HAL_RX_ERR_INT); 1314 uart_update_timeout(port, CS8, default_baud); 1315 1316 return 0; 1317 } 1318 1319 static void pch_uart_shutdown(struct uart_port *port) 1320 { 1321 struct eg20t_port *priv; 1322 int ret; 1323 1324 priv = container_of(port, struct eg20t_port, port); 1325 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1326 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1327 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1328 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1329 if (ret) 1330 dev_err(priv->port.dev, 1331 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1332 1333 pch_free_dma(port); 1334 1335 free_irq(priv->port.irq, priv); 1336 } 1337 1338 /* Change the port parameters, including word length, parity, stop 1339 *bits. Update read_status_mask and ignore_status_mask to indicate 1340 *the types of events we are interested in receiving. */ 1341 static void pch_uart_set_termios(struct uart_port *port, 1342 struct ktermios *termios, struct ktermios *old) 1343 { 1344 int baud; 1345 int rtn; 1346 unsigned int parity, bits, stb; 1347 struct eg20t_port *priv; 1348 unsigned long flags; 1349 1350 priv = container_of(port, struct eg20t_port, port); 1351 switch (termios->c_cflag & CSIZE) { 1352 case CS5: 1353 bits = PCH_UART_HAL_5BIT; 1354 break; 1355 case CS6: 1356 bits = PCH_UART_HAL_6BIT; 1357 break; 1358 case CS7: 1359 bits = PCH_UART_HAL_7BIT; 1360 break; 1361 default: /* CS8 */ 1362 bits = PCH_UART_HAL_8BIT; 1363 break; 1364 } 1365 if (termios->c_cflag & CSTOPB) 1366 stb = PCH_UART_HAL_STB2; 1367 else 1368 stb = PCH_UART_HAL_STB1; 1369 1370 if (termios->c_cflag & PARENB) { 1371 if (termios->c_cflag & PARODD) 1372 parity = PCH_UART_HAL_PARITY_ODD; 1373 else 1374 parity = PCH_UART_HAL_PARITY_EVEN; 1375 1376 } else 1377 parity = PCH_UART_HAL_PARITY_NONE; 1378 1379 /* Only UART0 has auto hardware flow function */ 1380 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1381 priv->mcr |= UART_MCR_AFE; 1382 else 1383 priv->mcr &= ~UART_MCR_AFE; 1384 1385 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1386 1387 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1388 1389 spin_lock_irqsave(&priv->lock, flags); 1390 spin_lock(&port->lock); 1391 1392 uart_update_timeout(port, termios->c_cflag, baud); 1393 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1394 if (rtn) 1395 goto out; 1396 1397 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1398 /* Don't rewrite B0 */ 1399 if (tty_termios_baud_rate(termios)) 1400 tty_termios_encode_baud_rate(termios, baud, baud); 1401 1402 out: 1403 spin_unlock(&port->lock); 1404 spin_unlock_irqrestore(&priv->lock, flags); 1405 } 1406 1407 static const char *pch_uart_type(struct uart_port *port) 1408 { 1409 return KBUILD_MODNAME; 1410 } 1411 1412 static void pch_uart_release_port(struct uart_port *port) 1413 { 1414 struct eg20t_port *priv; 1415 1416 priv = container_of(port, struct eg20t_port, port); 1417 pci_iounmap(priv->pdev, priv->membase); 1418 pci_release_regions(priv->pdev); 1419 } 1420 1421 static int pch_uart_request_port(struct uart_port *port) 1422 { 1423 struct eg20t_port *priv; 1424 int ret; 1425 void __iomem *membase; 1426 1427 priv = container_of(port, struct eg20t_port, port); 1428 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1429 if (ret < 0) 1430 return -EBUSY; 1431 1432 membase = pci_iomap(priv->pdev, 1, 0); 1433 if (!membase) { 1434 pci_release_regions(priv->pdev); 1435 return -EBUSY; 1436 } 1437 priv->membase = port->membase = membase; 1438 1439 return 0; 1440 } 1441 1442 static void pch_uart_config_port(struct uart_port *port, int type) 1443 { 1444 struct eg20t_port *priv; 1445 1446 priv = container_of(port, struct eg20t_port, port); 1447 if (type & UART_CONFIG_TYPE) { 1448 port->type = priv->port_type; 1449 pch_uart_request_port(port); 1450 } 1451 } 1452 1453 static int pch_uart_verify_port(struct uart_port *port, 1454 struct serial_struct *serinfo) 1455 { 1456 struct eg20t_port *priv; 1457 1458 priv = container_of(port, struct eg20t_port, port); 1459 if (serinfo->flags & UPF_LOW_LATENCY) { 1460 dev_info(priv->port.dev, 1461 "PCH UART : Use PIO Mode (without DMA)\n"); 1462 priv->use_dma = 0; 1463 serinfo->flags &= ~UPF_LOW_LATENCY; 1464 } else { 1465 #ifndef CONFIG_PCH_DMA 1466 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1467 __func__); 1468 return -EOPNOTSUPP; 1469 #endif 1470 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n"); 1471 if (!priv->use_dma) 1472 pch_request_dma(port); 1473 priv->use_dma = 1; 1474 } 1475 1476 return 0; 1477 } 1478 1479 static struct uart_ops pch_uart_ops = { 1480 .tx_empty = pch_uart_tx_empty, 1481 .set_mctrl = pch_uart_set_mctrl, 1482 .get_mctrl = pch_uart_get_mctrl, 1483 .stop_tx = pch_uart_stop_tx, 1484 .start_tx = pch_uart_start_tx, 1485 .stop_rx = pch_uart_stop_rx, 1486 .enable_ms = pch_uart_enable_ms, 1487 .break_ctl = pch_uart_break_ctl, 1488 .startup = pch_uart_startup, 1489 .shutdown = pch_uart_shutdown, 1490 .set_termios = pch_uart_set_termios, 1491 /* .pm = pch_uart_pm, Not supported yet */ 1492 /* .set_wake = pch_uart_set_wake, Not supported yet */ 1493 .type = pch_uart_type, 1494 .release_port = pch_uart_release_port, 1495 .request_port = pch_uart_request_port, 1496 .config_port = pch_uart_config_port, 1497 .verify_port = pch_uart_verify_port 1498 }; 1499 1500 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1501 1502 /* 1503 * Wait for transmitter & holding register to empty 1504 */ 1505 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1506 { 1507 unsigned int status, tmout = 10000; 1508 1509 /* Wait up to 10ms for the character(s) to be sent. */ 1510 for (;;) { 1511 status = ioread8(up->membase + UART_LSR); 1512 1513 if ((status & bits) == bits) 1514 break; 1515 if (--tmout == 0) 1516 break; 1517 udelay(1); 1518 } 1519 1520 /* Wait up to 1s for flow control if necessary */ 1521 if (up->port.flags & UPF_CONS_FLOW) { 1522 unsigned int tmout; 1523 for (tmout = 1000000; tmout; tmout--) { 1524 unsigned int msr = ioread8(up->membase + UART_MSR); 1525 if (msr & UART_MSR_CTS) 1526 break; 1527 udelay(1); 1528 touch_nmi_watchdog(); 1529 } 1530 } 1531 } 1532 1533 static void pch_console_putchar(struct uart_port *port, int ch) 1534 { 1535 struct eg20t_port *priv = 1536 container_of(port, struct eg20t_port, port); 1537 1538 wait_for_xmitr(priv, UART_LSR_THRE); 1539 iowrite8(ch, priv->membase + PCH_UART_THR); 1540 } 1541 1542 /* 1543 * Print a string to the serial port trying not to disturb 1544 * any possible real use of the port... 1545 * 1546 * The console_lock must be held when we get here. 1547 */ 1548 static void 1549 pch_console_write(struct console *co, const char *s, unsigned int count) 1550 { 1551 struct eg20t_port *priv; 1552 unsigned long flags; 1553 int priv_locked = 1; 1554 int port_locked = 1; 1555 u8 ier; 1556 1557 priv = pch_uart_ports[co->index]; 1558 1559 touch_nmi_watchdog(); 1560 1561 local_irq_save(flags); 1562 if (priv->port.sysrq) { 1563 spin_lock(&priv->lock); 1564 /* serial8250_handle_port() already took the port lock */ 1565 port_locked = 0; 1566 } else if (oops_in_progress) { 1567 priv_locked = spin_trylock(&priv->lock); 1568 port_locked = spin_trylock(&priv->port.lock); 1569 } else { 1570 spin_lock(&priv->lock); 1571 spin_lock(&priv->port.lock); 1572 } 1573 1574 /* 1575 * First save the IER then disable the interrupts 1576 */ 1577 ier = ioread8(priv->membase + UART_IER); 1578 1579 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1580 1581 uart_console_write(&priv->port, s, count, pch_console_putchar); 1582 1583 /* 1584 * Finally, wait for transmitter to become empty 1585 * and restore the IER 1586 */ 1587 wait_for_xmitr(priv, BOTH_EMPTY); 1588 iowrite8(ier, priv->membase + UART_IER); 1589 1590 if (port_locked) 1591 spin_unlock(&priv->port.lock); 1592 if (priv_locked) 1593 spin_unlock(&priv->lock); 1594 local_irq_restore(flags); 1595 } 1596 1597 static int __init pch_console_setup(struct console *co, char *options) 1598 { 1599 struct uart_port *port; 1600 int baud = default_baud; 1601 int bits = 8; 1602 int parity = 'n'; 1603 int flow = 'n'; 1604 1605 /* 1606 * Check whether an invalid uart number has been specified, and 1607 * if so, search for the first available port that does have 1608 * console support. 1609 */ 1610 if (co->index >= PCH_UART_NR) 1611 co->index = 0; 1612 port = &pch_uart_ports[co->index]->port; 1613 1614 if (!port || (!port->iobase && !port->membase)) 1615 return -ENODEV; 1616 1617 port->uartclk = pch_uart_get_uartclk(); 1618 1619 if (options) 1620 uart_parse_options(options, &baud, &parity, &bits, &flow); 1621 1622 return uart_set_options(port, co, baud, parity, bits, flow); 1623 } 1624 1625 static struct uart_driver pch_uart_driver; 1626 1627 static struct console pch_console = { 1628 .name = PCH_UART_DRIVER_DEVICE, 1629 .write = pch_console_write, 1630 .device = uart_console_device, 1631 .setup = pch_console_setup, 1632 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1633 .index = -1, 1634 .data = &pch_uart_driver, 1635 }; 1636 1637 #define PCH_CONSOLE (&pch_console) 1638 #else 1639 #define PCH_CONSOLE NULL 1640 #endif 1641 1642 static struct uart_driver pch_uart_driver = { 1643 .owner = THIS_MODULE, 1644 .driver_name = KBUILD_MODNAME, 1645 .dev_name = PCH_UART_DRIVER_DEVICE, 1646 .major = 0, 1647 .minor = 0, 1648 .nr = PCH_UART_NR, 1649 .cons = PCH_CONSOLE, 1650 }; 1651 1652 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1653 const struct pci_device_id *id) 1654 { 1655 struct eg20t_port *priv; 1656 int ret; 1657 unsigned int iobase; 1658 unsigned int mapbase; 1659 unsigned char *rxbuf; 1660 int fifosize; 1661 int port_type; 1662 struct pch_uart_driver_data *board; 1663 char name[32]; /* for debugfs file name */ 1664 1665 board = &drv_dat[id->driver_data]; 1666 port_type = board->port_type; 1667 1668 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1669 if (priv == NULL) 1670 goto init_port_alloc_err; 1671 1672 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1673 if (!rxbuf) 1674 goto init_port_free_txbuf; 1675 1676 switch (port_type) { 1677 case PORT_UNKNOWN: 1678 fifosize = 256; /* EG20T/ML7213: UART0 */ 1679 break; 1680 case PORT_8250: 1681 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1682 break; 1683 default: 1684 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1685 goto init_port_hal_free; 1686 } 1687 1688 pci_enable_msi(pdev); 1689 pci_set_master(pdev); 1690 1691 spin_lock_init(&priv->lock); 1692 1693 iobase = pci_resource_start(pdev, 0); 1694 mapbase = pci_resource_start(pdev, 1); 1695 priv->mapbase = mapbase; 1696 priv->iobase = iobase; 1697 priv->pdev = pdev; 1698 priv->tx_empty = 1; 1699 priv->rxbuf.buf = rxbuf; 1700 priv->rxbuf.size = PAGE_SIZE; 1701 1702 priv->fifo_size = fifosize; 1703 priv->uartclk = pch_uart_get_uartclk(); 1704 priv->port_type = PORT_MAX_8250 + port_type + 1; 1705 priv->port.dev = &pdev->dev; 1706 priv->port.iobase = iobase; 1707 priv->port.membase = NULL; 1708 priv->port.mapbase = mapbase; 1709 priv->port.irq = pdev->irq; 1710 priv->port.iotype = UPIO_PORT; 1711 priv->port.ops = &pch_uart_ops; 1712 priv->port.flags = UPF_BOOT_AUTOCONF; 1713 priv->port.fifosize = fifosize; 1714 priv->port.line = board->line_no; 1715 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1716 1717 spin_lock_init(&priv->port.lock); 1718 1719 pci_set_drvdata(pdev, priv); 1720 priv->trigger_level = 1; 1721 priv->fcr = 0; 1722 1723 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1724 pch_uart_ports[board->line_no] = priv; 1725 #endif 1726 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1727 if (ret < 0) 1728 goto init_port_hal_free; 1729 1730 #ifdef CONFIG_DEBUG_FS 1731 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1732 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1733 NULL, priv, &port_regs_ops); 1734 #endif 1735 1736 return priv; 1737 1738 init_port_hal_free: 1739 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1740 pch_uart_ports[board->line_no] = NULL; 1741 #endif 1742 free_page((unsigned long)rxbuf); 1743 init_port_free_txbuf: 1744 kfree(priv); 1745 init_port_alloc_err: 1746 1747 return NULL; 1748 } 1749 1750 static void pch_uart_exit_port(struct eg20t_port *priv) 1751 { 1752 1753 #ifdef CONFIG_DEBUG_FS 1754 if (priv->debugfs) 1755 debugfs_remove(priv->debugfs); 1756 #endif 1757 uart_remove_one_port(&pch_uart_driver, &priv->port); 1758 pci_set_drvdata(priv->pdev, NULL); 1759 free_page((unsigned long)priv->rxbuf.buf); 1760 } 1761 1762 static void pch_uart_pci_remove(struct pci_dev *pdev) 1763 { 1764 struct eg20t_port *priv = pci_get_drvdata(pdev); 1765 1766 pci_disable_msi(pdev); 1767 1768 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1769 pch_uart_ports[priv->port.line] = NULL; 1770 #endif 1771 pch_uart_exit_port(priv); 1772 pci_disable_device(pdev); 1773 kfree(priv); 1774 return; 1775 } 1776 #ifdef CONFIG_PM 1777 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1778 { 1779 struct eg20t_port *priv = pci_get_drvdata(pdev); 1780 1781 uart_suspend_port(&pch_uart_driver, &priv->port); 1782 1783 pci_save_state(pdev); 1784 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1785 return 0; 1786 } 1787 1788 static int pch_uart_pci_resume(struct pci_dev *pdev) 1789 { 1790 struct eg20t_port *priv = pci_get_drvdata(pdev); 1791 int ret; 1792 1793 pci_set_power_state(pdev, PCI_D0); 1794 pci_restore_state(pdev); 1795 1796 ret = pci_enable_device(pdev); 1797 if (ret) { 1798 dev_err(&pdev->dev, 1799 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1800 return ret; 1801 } 1802 1803 uart_resume_port(&pch_uart_driver, &priv->port); 1804 1805 return 0; 1806 } 1807 #else 1808 #define pch_uart_pci_suspend NULL 1809 #define pch_uart_pci_resume NULL 1810 #endif 1811 1812 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = { 1813 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1814 .driver_data = pch_et20t_uart0}, 1815 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1816 .driver_data = pch_et20t_uart1}, 1817 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1818 .driver_data = pch_et20t_uart2}, 1819 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1820 .driver_data = pch_et20t_uart3}, 1821 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1822 .driver_data = pch_ml7213_uart0}, 1823 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1824 .driver_data = pch_ml7213_uart1}, 1825 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1826 .driver_data = pch_ml7213_uart2}, 1827 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1828 .driver_data = pch_ml7223_uart0}, 1829 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1830 .driver_data = pch_ml7223_uart1}, 1831 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1832 .driver_data = pch_ml7831_uart0}, 1833 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1834 .driver_data = pch_ml7831_uart1}, 1835 {0,}, 1836 }; 1837 1838 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev, 1839 const struct pci_device_id *id) 1840 { 1841 int ret; 1842 struct eg20t_port *priv; 1843 1844 ret = pci_enable_device(pdev); 1845 if (ret < 0) 1846 goto probe_error; 1847 1848 priv = pch_uart_init_port(pdev, id); 1849 if (!priv) { 1850 ret = -EBUSY; 1851 goto probe_disable_device; 1852 } 1853 pci_set_drvdata(pdev, priv); 1854 1855 return ret; 1856 1857 probe_disable_device: 1858 pci_disable_msi(pdev); 1859 pci_disable_device(pdev); 1860 probe_error: 1861 return ret; 1862 } 1863 1864 static struct pci_driver pch_uart_pci_driver = { 1865 .name = "pch_uart", 1866 .id_table = pch_uart_pci_id, 1867 .probe = pch_uart_pci_probe, 1868 .remove = __devexit_p(pch_uart_pci_remove), 1869 .suspend = pch_uart_pci_suspend, 1870 .resume = pch_uart_pci_resume, 1871 }; 1872 1873 static int __init pch_uart_module_init(void) 1874 { 1875 int ret; 1876 1877 /* register as UART driver */ 1878 ret = uart_register_driver(&pch_uart_driver); 1879 if (ret < 0) 1880 return ret; 1881 1882 /* register as PCI driver */ 1883 ret = pci_register_driver(&pch_uart_pci_driver); 1884 if (ret < 0) 1885 uart_unregister_driver(&pch_uart_driver); 1886 1887 return ret; 1888 } 1889 module_init(pch_uart_module_init); 1890 1891 static void __exit pch_uart_module_exit(void) 1892 { 1893 pci_unregister_driver(&pch_uart_pci_driver); 1894 uart_unregister_driver(&pch_uart_driver); 1895 } 1896 module_exit(pch_uart_module_exit); 1897 1898 MODULE_LICENSE("GPL v2"); 1899 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1900 module_param(default_baud, uint, S_IRUGO); 1901 MODULE_PARM_DESC(default_baud, 1902 "Default BAUD for initial driver state and console (default 9600)"); 1903 module_param(user_uartclk, uint, S_IRUGO); 1904 MODULE_PARM_DESC(user_uartclk, 1905 "Override UART default or board specific UART clock"); 1906