1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 #include <linux/kernel.h> 6 #include <linux/serial_reg.h> 7 #include <linux/slab.h> 8 #include <linux/module.h> 9 #include <linux/pci.h> 10 #include <linux/console.h> 11 #include <linux/serial_core.h> 12 #include <linux/tty.h> 13 #include <linux/tty_flip.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/dmi.h> 17 #include <linux/nmi.h> 18 #include <linux/delay.h> 19 #include <linux/of.h> 20 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/pch_dma.h> 24 25 enum { 26 PCH_UART_HANDLED_RX_INT_SHIFT, 27 PCH_UART_HANDLED_TX_INT_SHIFT, 28 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 29 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 30 PCH_UART_HANDLED_MS_INT_SHIFT, 31 PCH_UART_HANDLED_LS_INT_SHIFT, 32 }; 33 34 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 35 36 /* Set the max number of UART port 37 * Intel EG20T PCH: 4 port 38 * LAPIS Semiconductor ML7213 IOH: 3 port 39 * LAPIS Semiconductor ML7223 IOH: 2 port 40 */ 41 #define PCH_UART_NR 4 42 43 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 44 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 45 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 46 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 47 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 48 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 49 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 50 51 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 52 53 #define PCH_UART_RBR 0x00 54 #define PCH_UART_THR 0x00 55 56 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 57 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 58 #define PCH_UART_IER_ERBFI 0x00000001 59 #define PCH_UART_IER_ETBEI 0x00000002 60 #define PCH_UART_IER_ELSI 0x00000004 61 #define PCH_UART_IER_EDSSI 0x00000008 62 63 #define PCH_UART_IIR_IP 0x00000001 64 #define PCH_UART_IIR_IID 0x00000006 65 #define PCH_UART_IIR_MSI 0x00000000 66 #define PCH_UART_IIR_TRI 0x00000002 67 #define PCH_UART_IIR_RRI 0x00000004 68 #define PCH_UART_IIR_REI 0x00000006 69 #define PCH_UART_IIR_TOI 0x00000008 70 #define PCH_UART_IIR_FIFO256 0x00000020 71 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 72 #define PCH_UART_IIR_FE 0x000000C0 73 74 #define PCH_UART_FCR_FIFOE 0x00000001 75 #define PCH_UART_FCR_RFR 0x00000002 76 #define PCH_UART_FCR_TFR 0x00000004 77 #define PCH_UART_FCR_DMS 0x00000008 78 #define PCH_UART_FCR_FIFO256 0x00000020 79 #define PCH_UART_FCR_RFTL 0x000000C0 80 81 #define PCH_UART_FCR_RFTL1 0x00000000 82 #define PCH_UART_FCR_RFTL64 0x00000040 83 #define PCH_UART_FCR_RFTL128 0x00000080 84 #define PCH_UART_FCR_RFTL224 0x000000C0 85 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 86 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 87 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 88 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 89 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 90 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 91 #define PCH_UART_FCR_RFTL_SHIFT 6 92 93 #define PCH_UART_LCR_WLS 0x00000003 94 #define PCH_UART_LCR_STB 0x00000004 95 #define PCH_UART_LCR_PEN 0x00000008 96 #define PCH_UART_LCR_EPS 0x00000010 97 #define PCH_UART_LCR_SP 0x00000020 98 #define PCH_UART_LCR_SB 0x00000040 99 #define PCH_UART_LCR_DLAB 0x00000080 100 #define PCH_UART_LCR_NP 0x00000000 101 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 102 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 103 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 104 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 105 PCH_UART_LCR_SP) 106 107 #define PCH_UART_LCR_5BIT 0x00000000 108 #define PCH_UART_LCR_6BIT 0x00000001 109 #define PCH_UART_LCR_7BIT 0x00000002 110 #define PCH_UART_LCR_8BIT 0x00000003 111 112 #define PCH_UART_MCR_DTR 0x00000001 113 #define PCH_UART_MCR_RTS 0x00000002 114 #define PCH_UART_MCR_OUT 0x0000000C 115 #define PCH_UART_MCR_LOOP 0x00000010 116 #define PCH_UART_MCR_AFE 0x00000020 117 118 #define PCH_UART_LSR_DR 0x00000001 119 #define PCH_UART_LSR_ERR (1<<7) 120 121 #define PCH_UART_MSR_DCTS 0x00000001 122 #define PCH_UART_MSR_DDSR 0x00000002 123 #define PCH_UART_MSR_TERI 0x00000004 124 #define PCH_UART_MSR_DDCD 0x00000008 125 #define PCH_UART_MSR_CTS 0x00000010 126 #define PCH_UART_MSR_DSR 0x00000020 127 #define PCH_UART_MSR_RI 0x00000040 128 #define PCH_UART_MSR_DCD 0x00000080 129 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 130 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 131 132 #define PCH_UART_DLL 0x00 133 #define PCH_UART_DLM 0x01 134 135 #define PCH_UART_BRCSR 0x0E 136 137 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 138 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 139 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 140 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 141 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 142 143 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 144 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 145 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 146 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 147 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 148 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 149 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 150 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 151 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 152 #define PCH_UART_HAL_STB1 0 153 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 154 155 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 156 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 157 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 158 PCH_UART_HAL_CLR_RX_FIFO) 159 160 #define PCH_UART_HAL_DMA_MODE0 0 161 #define PCH_UART_HAL_FIFO_DIS 0 162 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 163 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 164 PCH_UART_FCR_FIFO256) 165 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 166 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 167 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 168 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 169 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 170 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 171 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 172 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 173 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 174 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 175 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 176 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 177 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 178 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 179 180 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 181 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 182 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 183 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 184 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 185 186 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 187 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 188 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 189 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 190 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 191 192 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 193 194 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 195 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 196 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 197 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 198 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 199 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ 200 201 struct pch_uart_buffer { 202 unsigned char *buf; 203 int size; 204 }; 205 206 struct eg20t_port { 207 struct uart_port port; 208 int port_type; 209 void __iomem *membase; 210 resource_size_t mapbase; 211 unsigned int iobase; 212 struct pci_dev *pdev; 213 int fifo_size; 214 unsigned int uartclk; 215 int start_tx; 216 int start_rx; 217 int tx_empty; 218 int trigger; 219 int trigger_level; 220 struct pch_uart_buffer rxbuf; 221 unsigned int dmsr; 222 unsigned int fcr; 223 unsigned int mcr; 224 unsigned int use_dma; 225 struct dma_async_tx_descriptor *desc_tx; 226 struct dma_async_tx_descriptor *desc_rx; 227 struct pch_dma_slave param_tx; 228 struct pch_dma_slave param_rx; 229 struct dma_chan *chan_tx; 230 struct dma_chan *chan_rx; 231 struct scatterlist *sg_tx_p; 232 int nent; 233 int orig_nent; 234 struct scatterlist sg_rx; 235 int tx_dma_use; 236 void *rx_buf_virt; 237 dma_addr_t rx_buf_dma; 238 239 #define IRQ_NAME_SIZE 17 240 char irq_name[IRQ_NAME_SIZE]; 241 242 /* protect the eg20t_port private structure and io access to membase */ 243 spinlock_t lock; 244 }; 245 246 /** 247 * struct pch_uart_driver_data - private data structure for UART-DMA 248 * @port_type: The type of UART port 249 * @line_no: UART port line number (0, 1, 2...) 250 */ 251 struct pch_uart_driver_data { 252 int port_type; 253 int line_no; 254 }; 255 256 enum pch_uart_num_t { 257 pch_et20t_uart0 = 0, 258 pch_et20t_uart1, 259 pch_et20t_uart2, 260 pch_et20t_uart3, 261 pch_ml7213_uart0, 262 pch_ml7213_uart1, 263 pch_ml7213_uart2, 264 pch_ml7223_uart0, 265 pch_ml7223_uart1, 266 pch_ml7831_uart0, 267 pch_ml7831_uart1, 268 }; 269 270 static struct pch_uart_driver_data drv_dat[] = { 271 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0}, 272 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1}, 273 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2}, 274 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3}, 275 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0}, 276 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1}, 277 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2}, 278 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0}, 279 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1}, 280 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0}, 281 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1}, 282 }; 283 284 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 285 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 286 #endif 287 static unsigned int default_baud = 9600; 288 static unsigned int user_uartclk = 0; 289 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 290 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 291 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 292 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 293 294 #define PCH_REGS_BUFSIZE 1024 295 296 297 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 298 size_t count, loff_t *ppos) 299 { 300 struct eg20t_port *priv = file->private_data; 301 char *buf; 302 u32 len = 0; 303 ssize_t ret; 304 unsigned char lcr; 305 306 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 307 if (!buf) 308 return 0; 309 310 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 311 "PCH EG20T port[%d] regs:\n", priv->port.line); 312 313 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 314 "=================================\n"); 315 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 316 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 317 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 318 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 319 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 320 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 321 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 322 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 323 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 324 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 325 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 326 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 327 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 328 "BRCSR: \t0x%02x\n", 329 ioread8(priv->membase + PCH_UART_BRCSR)); 330 331 lcr = ioread8(priv->membase + UART_LCR); 332 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 333 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 334 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 335 len += scnprintf(buf + len, PCH_REGS_BUFSIZE - len, 336 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 337 iowrite8(lcr, priv->membase + UART_LCR); 338 339 if (len > PCH_REGS_BUFSIZE) 340 len = PCH_REGS_BUFSIZE; 341 342 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 343 kfree(buf); 344 return ret; 345 } 346 347 static const struct file_operations port_regs_ops = { 348 .owner = THIS_MODULE, 349 .open = simple_open, 350 .read = port_show_regs, 351 .llseek = default_llseek, 352 }; 353 354 static const struct dmi_system_id pch_uart_dmi_table[] = { 355 { 356 .ident = "CM-iTC", 357 { 358 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), 359 }, 360 (void *)CMITC_UARTCLK, 361 }, 362 { 363 .ident = "FRI2", 364 { 365 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), 366 }, 367 (void *)FRI2_64_UARTCLK, 368 }, 369 { 370 .ident = "Fish River Island II", 371 { 372 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), 373 }, 374 (void *)FRI2_48_UARTCLK, 375 }, 376 { 377 .ident = "COMe-mTT", 378 { 379 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), 380 }, 381 (void *)NTC1_UARTCLK, 382 }, 383 { 384 .ident = "nanoETXexpress-TT", 385 { 386 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), 387 }, 388 (void *)NTC1_UARTCLK, 389 }, 390 { 391 .ident = "MinnowBoard", 392 { 393 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), 394 }, 395 (void *)MINNOW_UARTCLK, 396 }, 397 { } 398 }; 399 400 /* Return UART clock, checking for board specific clocks. */ 401 static unsigned int pch_uart_get_uartclk(void) 402 { 403 const struct dmi_system_id *d; 404 405 if (user_uartclk) 406 return user_uartclk; 407 408 d = dmi_first_match(pch_uart_dmi_table); 409 if (d) 410 return (unsigned long)d->driver_data; 411 412 return DEFAULT_UARTCLK; 413 } 414 415 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 416 unsigned int flag) 417 { 418 u8 ier = ioread8(priv->membase + UART_IER); 419 ier |= flag & PCH_UART_IER_MASK; 420 iowrite8(ier, priv->membase + UART_IER); 421 } 422 423 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 424 unsigned int flag) 425 { 426 u8 ier = ioread8(priv->membase + UART_IER); 427 ier &= ~(flag & PCH_UART_IER_MASK); 428 iowrite8(ier, priv->membase + UART_IER); 429 } 430 431 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, 432 unsigned int parity, unsigned int bits, 433 unsigned int stb) 434 { 435 unsigned int dll, dlm, lcr; 436 int div; 437 438 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 439 if (div < 0 || USHRT_MAX <= div) { 440 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 441 return -EINVAL; 442 } 443 444 dll = (unsigned int)div & 0x00FFU; 445 dlm = ((unsigned int)div >> 8) & 0x00FFU; 446 447 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 448 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 449 return -EINVAL; 450 } 451 452 if (bits & ~PCH_UART_LCR_WLS) { 453 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 454 return -EINVAL; 455 } 456 457 if (stb & ~PCH_UART_LCR_STB) { 458 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 459 return -EINVAL; 460 } 461 462 lcr = parity; 463 lcr |= bits; 464 lcr |= stb; 465 466 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", 467 __func__, baud, div, lcr, jiffies); 468 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 469 iowrite8(dll, priv->membase + PCH_UART_DLL); 470 iowrite8(dlm, priv->membase + PCH_UART_DLM); 471 iowrite8(lcr, priv->membase + UART_LCR); 472 473 return 0; 474 } 475 476 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 477 unsigned int flag) 478 { 479 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 480 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 481 __func__, flag); 482 return -EINVAL; 483 } 484 485 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 486 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 487 priv->membase + UART_FCR); 488 iowrite8(priv->fcr, priv->membase + UART_FCR); 489 490 return 0; 491 } 492 493 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 494 unsigned int dmamode, 495 unsigned int fifo_size, unsigned int trigger) 496 { 497 u8 fcr; 498 499 if (dmamode & ~PCH_UART_FCR_DMS) { 500 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 501 __func__, dmamode); 502 return -EINVAL; 503 } 504 505 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 506 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 507 __func__, fifo_size); 508 return -EINVAL; 509 } 510 511 if (trigger & ~PCH_UART_FCR_RFTL) { 512 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 513 __func__, trigger); 514 return -EINVAL; 515 } 516 517 switch (priv->fifo_size) { 518 case 256: 519 priv->trigger_level = 520 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 521 break; 522 case 64: 523 priv->trigger_level = 524 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 525 break; 526 case 16: 527 priv->trigger_level = 528 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 529 break; 530 default: 531 priv->trigger_level = 532 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 533 break; 534 } 535 fcr = 536 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 537 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 538 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 539 priv->membase + UART_FCR); 540 iowrite8(fcr, priv->membase + UART_FCR); 541 priv->fcr = fcr; 542 543 return 0; 544 } 545 546 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 547 { 548 unsigned int msr = ioread8(priv->membase + UART_MSR); 549 priv->dmsr = msr & PCH_UART_MSR_DELTA; 550 return (u8)msr; 551 } 552 553 static void pch_uart_hal_write(struct eg20t_port *priv, 554 const unsigned char *buf, int tx_size) 555 { 556 int i; 557 unsigned int thr; 558 559 for (i = 0; i < tx_size;) { 560 thr = buf[i++]; 561 iowrite8(thr, priv->membase + PCH_UART_THR); 562 } 563 } 564 565 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 566 int rx_size) 567 { 568 int i; 569 u8 rbr, lsr; 570 struct uart_port *port = &priv->port; 571 572 lsr = ioread8(priv->membase + UART_LSR); 573 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 574 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); 575 lsr = ioread8(priv->membase + UART_LSR)) { 576 rbr = ioread8(priv->membase + PCH_UART_RBR); 577 578 if (lsr & UART_LSR_BI) { 579 port->icount.brk++; 580 if (uart_handle_break(port)) 581 continue; 582 } 583 if (uart_handle_sysrq_char(port, rbr)) 584 continue; 585 586 buf[i++] = rbr; 587 } 588 return i; 589 } 590 591 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 592 { 593 return ioread8(priv->membase + UART_IIR) &\ 594 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 595 } 596 597 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 598 { 599 return ioread8(priv->membase + UART_LSR); 600 } 601 602 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 603 { 604 unsigned int lcr; 605 606 lcr = ioread8(priv->membase + UART_LCR); 607 if (on) 608 lcr |= PCH_UART_LCR_SB; 609 else 610 lcr &= ~PCH_UART_LCR_SB; 611 612 iowrite8(lcr, priv->membase + UART_LCR); 613 } 614 615 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 616 int size) 617 { 618 struct uart_port *port = &priv->port; 619 struct tty_port *tport = &port->state->port; 620 621 tty_insert_flip_string(tport, buf, size); 622 tty_flip_buffer_push(tport); 623 624 return 0; 625 } 626 627 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 628 { 629 int ret = 0; 630 struct uart_port *port = &priv->port; 631 632 if (port->x_char) { 633 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 634 __func__, port->x_char, jiffies); 635 buf[0] = port->x_char; 636 port->x_char = 0; 637 ret = 1; 638 } 639 640 return ret; 641 } 642 643 static int dma_push_rx(struct eg20t_port *priv, int size) 644 { 645 int room; 646 struct uart_port *port = &priv->port; 647 struct tty_port *tport = &port->state->port; 648 649 room = tty_buffer_request_room(tport, size); 650 651 if (room < size) 652 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 653 size - room); 654 if (!room) 655 return 0; 656 657 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); 658 659 port->icount.rx += room; 660 661 return room; 662 } 663 664 static void pch_free_dma(struct uart_port *port) 665 { 666 struct eg20t_port *priv; 667 priv = container_of(port, struct eg20t_port, port); 668 669 if (priv->chan_tx) { 670 dma_release_channel(priv->chan_tx); 671 priv->chan_tx = NULL; 672 } 673 if (priv->chan_rx) { 674 dma_release_channel(priv->chan_rx); 675 priv->chan_rx = NULL; 676 } 677 678 if (priv->rx_buf_dma) { 679 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 680 priv->rx_buf_dma); 681 priv->rx_buf_virt = NULL; 682 priv->rx_buf_dma = 0; 683 } 684 685 return; 686 } 687 688 static bool filter(struct dma_chan *chan, void *slave) 689 { 690 struct pch_dma_slave *param = slave; 691 692 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 693 chan->device->dev)) { 694 chan->private = param; 695 return true; 696 } else { 697 return false; 698 } 699 } 700 701 static void pch_request_dma(struct uart_port *port) 702 { 703 dma_cap_mask_t mask; 704 struct dma_chan *chan; 705 struct pci_dev *dma_dev; 706 struct pch_dma_slave *param; 707 struct eg20t_port *priv = 708 container_of(port, struct eg20t_port, port); 709 dma_cap_zero(mask); 710 dma_cap_set(DMA_SLAVE, mask); 711 712 /* Get DMA's dev information */ 713 dma_dev = pci_get_slot(priv->pdev->bus, 714 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); 715 716 /* Set Tx DMA */ 717 param = &priv->param_tx; 718 param->dma_dev = &dma_dev->dev; 719 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 720 721 param->tx_reg = port->mapbase + UART_TX; 722 chan = dma_request_channel(mask, filter, param); 723 if (!chan) { 724 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 725 __func__); 726 return; 727 } 728 priv->chan_tx = chan; 729 730 /* Set Rx DMA */ 731 param = &priv->param_rx; 732 param->dma_dev = &dma_dev->dev; 733 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 734 735 param->rx_reg = port->mapbase + UART_RX; 736 chan = dma_request_channel(mask, filter, param); 737 if (!chan) { 738 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 739 __func__); 740 dma_release_channel(priv->chan_tx); 741 priv->chan_tx = NULL; 742 return; 743 } 744 745 /* Get Consistent memory for DMA */ 746 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 747 &priv->rx_buf_dma, GFP_KERNEL); 748 priv->chan_rx = chan; 749 } 750 751 static void pch_dma_rx_complete(void *arg) 752 { 753 struct eg20t_port *priv = arg; 754 struct uart_port *port = &priv->port; 755 int count; 756 757 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 758 count = dma_push_rx(priv, priv->trigger_level); 759 if (count) 760 tty_flip_buffer_push(&port->state->port); 761 async_tx_ack(priv->desc_rx); 762 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 763 PCH_UART_HAL_RX_ERR_INT); 764 } 765 766 static void pch_dma_tx_complete(void *arg) 767 { 768 struct eg20t_port *priv = arg; 769 struct uart_port *port = &priv->port; 770 struct circ_buf *xmit = &port->state->xmit; 771 struct scatterlist *sg = priv->sg_tx_p; 772 int i; 773 774 for (i = 0; i < priv->nent; i++, sg++) { 775 xmit->tail += sg_dma_len(sg); 776 port->icount.tx += sg_dma_len(sg); 777 } 778 xmit->tail &= UART_XMIT_SIZE - 1; 779 async_tx_ack(priv->desc_tx); 780 dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE); 781 priv->tx_dma_use = 0; 782 priv->nent = 0; 783 priv->orig_nent = 0; 784 kfree(priv->sg_tx_p); 785 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 786 } 787 788 static int pop_tx(struct eg20t_port *priv, int size) 789 { 790 int count = 0; 791 struct uart_port *port = &priv->port; 792 struct circ_buf *xmit = &port->state->xmit; 793 794 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 795 goto pop_tx_end; 796 797 do { 798 int cnt_to_end = 799 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 800 int sz = min(size - count, cnt_to_end); 801 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 802 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 803 count += sz; 804 } while (!uart_circ_empty(xmit) && count < size); 805 806 pop_tx_end: 807 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 808 count, size - count, jiffies); 809 810 return count; 811 } 812 813 static int handle_rx_to(struct eg20t_port *priv) 814 { 815 struct pch_uart_buffer *buf; 816 int rx_size; 817 int ret; 818 if (!priv->start_rx) { 819 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 820 PCH_UART_HAL_RX_ERR_INT); 821 return 0; 822 } 823 buf = &priv->rxbuf; 824 do { 825 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 826 ret = push_rx(priv, buf->buf, rx_size); 827 if (ret) 828 return 0; 829 } while (rx_size == buf->size); 830 831 return PCH_UART_HANDLED_RX_INT; 832 } 833 834 static int handle_rx(struct eg20t_port *priv) 835 { 836 return handle_rx_to(priv); 837 } 838 839 static int dma_handle_rx(struct eg20t_port *priv) 840 { 841 struct uart_port *port = &priv->port; 842 struct dma_async_tx_descriptor *desc; 843 struct scatterlist *sg; 844 845 priv = container_of(port, struct eg20t_port, port); 846 sg = &priv->sg_rx; 847 848 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 849 850 sg_dma_len(sg) = priv->trigger_level; 851 852 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 853 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); 854 855 sg_dma_address(sg) = priv->rx_buf_dma; 856 857 desc = dmaengine_prep_slave_sg(priv->chan_rx, 858 sg, 1, DMA_DEV_TO_MEM, 859 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 860 861 if (!desc) 862 return 0; 863 864 priv->desc_rx = desc; 865 desc->callback = pch_dma_rx_complete; 866 desc->callback_param = priv; 867 desc->tx_submit(desc); 868 dma_async_issue_pending(priv->chan_rx); 869 870 return PCH_UART_HANDLED_RX_INT; 871 } 872 873 static unsigned int handle_tx(struct eg20t_port *priv) 874 { 875 struct uart_port *port = &priv->port; 876 struct circ_buf *xmit = &port->state->xmit; 877 int fifo_size; 878 int tx_size; 879 int size; 880 int tx_empty; 881 882 if (!priv->start_tx) { 883 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 884 __func__, jiffies); 885 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 886 priv->tx_empty = 1; 887 return 0; 888 } 889 890 fifo_size = max(priv->fifo_size, 1); 891 tx_empty = 1; 892 if (pop_tx_x(priv, xmit->buf)) { 893 pch_uart_hal_write(priv, xmit->buf, 1); 894 port->icount.tx++; 895 tx_empty = 0; 896 fifo_size--; 897 } 898 size = min(xmit->head - xmit->tail, fifo_size); 899 if (size < 0) 900 size = fifo_size; 901 902 tx_size = pop_tx(priv, size); 903 if (tx_size > 0) { 904 port->icount.tx += tx_size; 905 tx_empty = 0; 906 } 907 908 priv->tx_empty = tx_empty; 909 910 if (tx_empty) { 911 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 912 uart_write_wakeup(port); 913 } 914 915 return PCH_UART_HANDLED_TX_INT; 916 } 917 918 static unsigned int dma_handle_tx(struct eg20t_port *priv) 919 { 920 struct uart_port *port = &priv->port; 921 struct circ_buf *xmit = &port->state->xmit; 922 struct scatterlist *sg; 923 int nent; 924 int fifo_size; 925 struct dma_async_tx_descriptor *desc; 926 int num; 927 int i; 928 int bytes; 929 int size; 930 int rem; 931 932 if (!priv->start_tx) { 933 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 934 __func__, jiffies); 935 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 936 priv->tx_empty = 1; 937 return 0; 938 } 939 940 if (priv->tx_dma_use) { 941 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 942 __func__, jiffies); 943 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 944 priv->tx_empty = 1; 945 return 0; 946 } 947 948 fifo_size = max(priv->fifo_size, 1); 949 if (pop_tx_x(priv, xmit->buf)) { 950 pch_uart_hal_write(priv, xmit->buf, 1); 951 port->icount.tx++; 952 fifo_size--; 953 } 954 955 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 956 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 957 xmit->tail, UART_XMIT_SIZE)); 958 if (!bytes) { 959 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 960 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 961 uart_write_wakeup(port); 962 return 0; 963 } 964 965 if (bytes > fifo_size) { 966 num = bytes / fifo_size + 1; 967 size = fifo_size; 968 rem = bytes % fifo_size; 969 } else { 970 num = 1; 971 size = bytes; 972 rem = bytes; 973 } 974 975 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 976 __func__, num, size, rem); 977 978 priv->tx_dma_use = 1; 979 980 priv->sg_tx_p = kmalloc_array(num, sizeof(struct scatterlist), GFP_ATOMIC); 981 if (!priv->sg_tx_p) { 982 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 983 return 0; 984 } 985 986 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 987 sg = priv->sg_tx_p; 988 989 for (i = 0; i < num; i++, sg++) { 990 if (i == (num - 1)) 991 sg_set_page(sg, virt_to_page(xmit->buf), 992 rem, fifo_size * i); 993 else 994 sg_set_page(sg, virt_to_page(xmit->buf), 995 size, fifo_size * i); 996 } 997 998 sg = priv->sg_tx_p; 999 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 1000 if (!nent) { 1001 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 1002 return 0; 1003 } 1004 priv->orig_nent = num; 1005 priv->nent = nent; 1006 1007 for (i = 0; i < nent; i++, sg++) { 1008 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 1009 fifo_size * i; 1010 sg_dma_address(sg) = (sg_dma_address(sg) & 1011 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1012 if (i == (nent - 1)) 1013 sg_dma_len(sg) = rem; 1014 else 1015 sg_dma_len(sg) = size; 1016 } 1017 1018 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1019 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1020 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1021 if (!desc) { 1022 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", 1023 __func__); 1024 return 0; 1025 } 1026 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1027 priv->desc_tx = desc; 1028 desc->callback = pch_dma_tx_complete; 1029 desc->callback_param = priv; 1030 1031 desc->tx_submit(desc); 1032 1033 dma_async_issue_pending(priv->chan_tx); 1034 1035 return PCH_UART_HANDLED_TX_INT; 1036 } 1037 1038 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1039 { 1040 struct uart_port *port = &priv->port; 1041 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 1042 char *error_msg[5] = {}; 1043 int i = 0; 1044 1045 if (lsr & PCH_UART_LSR_ERR) 1046 error_msg[i++] = "Error data in FIFO\n"; 1047 1048 if (lsr & UART_LSR_FE) { 1049 port->icount.frame++; 1050 error_msg[i++] = " Framing Error\n"; 1051 } 1052 1053 if (lsr & UART_LSR_PE) { 1054 port->icount.parity++; 1055 error_msg[i++] = " Parity Error\n"; 1056 } 1057 1058 if (lsr & UART_LSR_OE) { 1059 port->icount.overrun++; 1060 error_msg[i++] = " Overrun Error\n"; 1061 } 1062 1063 if (tty == NULL) { 1064 for (i = 0; error_msg[i] != NULL; i++) 1065 dev_err(&priv->pdev->dev, error_msg[i]); 1066 } else { 1067 tty_kref_put(tty); 1068 } 1069 } 1070 1071 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1072 { 1073 struct eg20t_port *priv = dev_id; 1074 unsigned int handled; 1075 u8 lsr; 1076 int ret = 0; 1077 unsigned char iid; 1078 unsigned long flags; 1079 int next = 1; 1080 u8 msr; 1081 1082 spin_lock_irqsave(&priv->lock, flags); 1083 handled = 0; 1084 while (next) { 1085 iid = pch_uart_hal_get_iid(priv); 1086 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1087 break; 1088 switch (iid) { 1089 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1090 lsr = pch_uart_hal_get_line_status(priv); 1091 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1092 UART_LSR_PE | UART_LSR_OE)) { 1093 pch_uart_err_ir(priv, lsr); 1094 ret = PCH_UART_HANDLED_RX_ERR_INT; 1095 } else { 1096 ret = PCH_UART_HANDLED_LS_INT; 1097 } 1098 break; 1099 case PCH_UART_IID_RDR: /* Received Data Ready */ 1100 if (priv->use_dma) { 1101 pch_uart_hal_disable_interrupt(priv, 1102 PCH_UART_HAL_RX_INT | 1103 PCH_UART_HAL_RX_ERR_INT); 1104 ret = dma_handle_rx(priv); 1105 if (!ret) 1106 pch_uart_hal_enable_interrupt(priv, 1107 PCH_UART_HAL_RX_INT | 1108 PCH_UART_HAL_RX_ERR_INT); 1109 } else { 1110 ret = handle_rx(priv); 1111 } 1112 break; 1113 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1114 (FIFO Timeout) */ 1115 ret = handle_rx_to(priv); 1116 break; 1117 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1118 Empty */ 1119 if (priv->use_dma) 1120 ret = dma_handle_tx(priv); 1121 else 1122 ret = handle_tx(priv); 1123 break; 1124 case PCH_UART_IID_MS: /* Modem Status */ 1125 msr = pch_uart_hal_get_modem(priv); 1126 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1127 means final interrupt */ 1128 if ((msr & UART_MSR_ANY_DELTA) == 0) 1129 break; 1130 ret |= PCH_UART_HANDLED_MS_INT; 1131 break; 1132 default: /* Never junp to this label */ 1133 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1134 iid, jiffies); 1135 ret = -1; 1136 next = 0; 1137 break; 1138 } 1139 handled |= (unsigned int)ret; 1140 } 1141 1142 spin_unlock_irqrestore(&priv->lock, flags); 1143 return IRQ_RETVAL(handled); 1144 } 1145 1146 /* This function tests whether the transmitter fifo and shifter for the port 1147 described by 'port' is empty. */ 1148 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1149 { 1150 struct eg20t_port *priv; 1151 1152 priv = container_of(port, struct eg20t_port, port); 1153 if (priv->tx_empty) 1154 return TIOCSER_TEMT; 1155 else 1156 return 0; 1157 } 1158 1159 /* Returns the current state of modem control inputs. */ 1160 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1161 { 1162 struct eg20t_port *priv; 1163 u8 modem; 1164 unsigned int ret = 0; 1165 1166 priv = container_of(port, struct eg20t_port, port); 1167 modem = pch_uart_hal_get_modem(priv); 1168 1169 if (modem & UART_MSR_DCD) 1170 ret |= TIOCM_CAR; 1171 1172 if (modem & UART_MSR_RI) 1173 ret |= TIOCM_RNG; 1174 1175 if (modem & UART_MSR_DSR) 1176 ret |= TIOCM_DSR; 1177 1178 if (modem & UART_MSR_CTS) 1179 ret |= TIOCM_CTS; 1180 1181 return ret; 1182 } 1183 1184 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1185 { 1186 u32 mcr = 0; 1187 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1188 1189 if (mctrl & TIOCM_DTR) 1190 mcr |= UART_MCR_DTR; 1191 if (mctrl & TIOCM_RTS) 1192 mcr |= UART_MCR_RTS; 1193 if (mctrl & TIOCM_LOOP) 1194 mcr |= UART_MCR_LOOP; 1195 1196 if (priv->mcr & UART_MCR_AFE) 1197 mcr |= UART_MCR_AFE; 1198 1199 if (mctrl) 1200 iowrite8(mcr, priv->membase + UART_MCR); 1201 } 1202 1203 static void pch_uart_stop_tx(struct uart_port *port) 1204 { 1205 struct eg20t_port *priv; 1206 priv = container_of(port, struct eg20t_port, port); 1207 priv->start_tx = 0; 1208 priv->tx_dma_use = 0; 1209 } 1210 1211 static void pch_uart_start_tx(struct uart_port *port) 1212 { 1213 struct eg20t_port *priv; 1214 1215 priv = container_of(port, struct eg20t_port, port); 1216 1217 if (priv->use_dma) { 1218 if (priv->tx_dma_use) { 1219 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1220 __func__); 1221 return; 1222 } 1223 } 1224 1225 priv->start_tx = 1; 1226 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1227 } 1228 1229 static void pch_uart_stop_rx(struct uart_port *port) 1230 { 1231 struct eg20t_port *priv; 1232 priv = container_of(port, struct eg20t_port, port); 1233 priv->start_rx = 0; 1234 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1235 PCH_UART_HAL_RX_ERR_INT); 1236 } 1237 1238 /* Enable the modem status interrupts. */ 1239 static void pch_uart_enable_ms(struct uart_port *port) 1240 { 1241 struct eg20t_port *priv; 1242 priv = container_of(port, struct eg20t_port, port); 1243 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1244 } 1245 1246 /* Control the transmission of a break signal. */ 1247 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1248 { 1249 struct eg20t_port *priv; 1250 unsigned long flags; 1251 1252 priv = container_of(port, struct eg20t_port, port); 1253 spin_lock_irqsave(&priv->lock, flags); 1254 pch_uart_hal_set_break(priv, ctl); 1255 spin_unlock_irqrestore(&priv->lock, flags); 1256 } 1257 1258 /* Grab any interrupt resources and initialise any low level driver state. */ 1259 static int pch_uart_startup(struct uart_port *port) 1260 { 1261 struct eg20t_port *priv; 1262 int ret; 1263 int fifo_size; 1264 int trigger_level; 1265 1266 priv = container_of(port, struct eg20t_port, port); 1267 priv->tx_empty = 1; 1268 1269 if (port->uartclk) 1270 priv->uartclk = port->uartclk; 1271 else 1272 port->uartclk = priv->uartclk; 1273 1274 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1275 ret = pch_uart_hal_set_line(priv, default_baud, 1276 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1277 PCH_UART_HAL_STB1); 1278 if (ret) 1279 return ret; 1280 1281 switch (priv->fifo_size) { 1282 case 256: 1283 fifo_size = PCH_UART_HAL_FIFO256; 1284 break; 1285 case 64: 1286 fifo_size = PCH_UART_HAL_FIFO64; 1287 break; 1288 case 16: 1289 fifo_size = PCH_UART_HAL_FIFO16; 1290 break; 1291 case 1: 1292 default: 1293 fifo_size = PCH_UART_HAL_FIFO_DIS; 1294 break; 1295 } 1296 1297 switch (priv->trigger) { 1298 case PCH_UART_HAL_TRIGGER1: 1299 trigger_level = 1; 1300 break; 1301 case PCH_UART_HAL_TRIGGER_L: 1302 trigger_level = priv->fifo_size / 4; 1303 break; 1304 case PCH_UART_HAL_TRIGGER_M: 1305 trigger_level = priv->fifo_size / 2; 1306 break; 1307 case PCH_UART_HAL_TRIGGER_H: 1308 default: 1309 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1310 break; 1311 } 1312 1313 priv->trigger_level = trigger_level; 1314 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1315 fifo_size, priv->trigger); 1316 if (ret < 0) 1317 return ret; 1318 1319 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1320 priv->irq_name, priv); 1321 if (ret < 0) 1322 return ret; 1323 1324 if (priv->use_dma) 1325 pch_request_dma(port); 1326 1327 priv->start_rx = 1; 1328 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1329 PCH_UART_HAL_RX_ERR_INT); 1330 uart_update_timeout(port, CS8, default_baud); 1331 1332 return 0; 1333 } 1334 1335 static void pch_uart_shutdown(struct uart_port *port) 1336 { 1337 struct eg20t_port *priv; 1338 int ret; 1339 1340 priv = container_of(port, struct eg20t_port, port); 1341 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1342 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1343 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1344 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1345 if (ret) 1346 dev_err(priv->port.dev, 1347 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1348 1349 pch_free_dma(port); 1350 1351 free_irq(priv->port.irq, priv); 1352 } 1353 1354 /* Change the port parameters, including word length, parity, stop 1355 *bits. Update read_status_mask and ignore_status_mask to indicate 1356 *the types of events we are interested in receiving. */ 1357 static void pch_uart_set_termios(struct uart_port *port, 1358 struct ktermios *termios, struct ktermios *old) 1359 { 1360 int rtn; 1361 unsigned int baud, parity, bits, stb; 1362 struct eg20t_port *priv; 1363 unsigned long flags; 1364 1365 priv = container_of(port, struct eg20t_port, port); 1366 switch (termios->c_cflag & CSIZE) { 1367 case CS5: 1368 bits = PCH_UART_HAL_5BIT; 1369 break; 1370 case CS6: 1371 bits = PCH_UART_HAL_6BIT; 1372 break; 1373 case CS7: 1374 bits = PCH_UART_HAL_7BIT; 1375 break; 1376 default: /* CS8 */ 1377 bits = PCH_UART_HAL_8BIT; 1378 break; 1379 } 1380 if (termios->c_cflag & CSTOPB) 1381 stb = PCH_UART_HAL_STB2; 1382 else 1383 stb = PCH_UART_HAL_STB1; 1384 1385 if (termios->c_cflag & PARENB) { 1386 if (termios->c_cflag & PARODD) 1387 parity = PCH_UART_HAL_PARITY_ODD; 1388 else 1389 parity = PCH_UART_HAL_PARITY_EVEN; 1390 1391 } else 1392 parity = PCH_UART_HAL_PARITY_NONE; 1393 1394 /* Only UART0 has auto hardware flow function */ 1395 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1396 priv->mcr |= UART_MCR_AFE; 1397 else 1398 priv->mcr &= ~UART_MCR_AFE; 1399 1400 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1401 1402 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1403 1404 spin_lock_irqsave(&priv->lock, flags); 1405 spin_lock(&port->lock); 1406 1407 uart_update_timeout(port, termios->c_cflag, baud); 1408 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1409 if (rtn) 1410 goto out; 1411 1412 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1413 /* Don't rewrite B0 */ 1414 if (tty_termios_baud_rate(termios)) 1415 tty_termios_encode_baud_rate(termios, baud, baud); 1416 1417 out: 1418 spin_unlock(&port->lock); 1419 spin_unlock_irqrestore(&priv->lock, flags); 1420 } 1421 1422 static const char *pch_uart_type(struct uart_port *port) 1423 { 1424 return KBUILD_MODNAME; 1425 } 1426 1427 static void pch_uart_release_port(struct uart_port *port) 1428 { 1429 struct eg20t_port *priv; 1430 1431 priv = container_of(port, struct eg20t_port, port); 1432 pci_iounmap(priv->pdev, priv->membase); 1433 pci_release_regions(priv->pdev); 1434 } 1435 1436 static int pch_uart_request_port(struct uart_port *port) 1437 { 1438 struct eg20t_port *priv; 1439 int ret; 1440 void __iomem *membase; 1441 1442 priv = container_of(port, struct eg20t_port, port); 1443 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1444 if (ret < 0) 1445 return -EBUSY; 1446 1447 membase = pci_iomap(priv->pdev, 1, 0); 1448 if (!membase) { 1449 pci_release_regions(priv->pdev); 1450 return -EBUSY; 1451 } 1452 priv->membase = port->membase = membase; 1453 1454 return 0; 1455 } 1456 1457 static void pch_uart_config_port(struct uart_port *port, int type) 1458 { 1459 struct eg20t_port *priv; 1460 1461 priv = container_of(port, struct eg20t_port, port); 1462 if (type & UART_CONFIG_TYPE) { 1463 port->type = priv->port_type; 1464 pch_uart_request_port(port); 1465 } 1466 } 1467 1468 static int pch_uart_verify_port(struct uart_port *port, 1469 struct serial_struct *serinfo) 1470 { 1471 struct eg20t_port *priv; 1472 1473 priv = container_of(port, struct eg20t_port, port); 1474 if (serinfo->flags & UPF_LOW_LATENCY) { 1475 dev_info(priv->port.dev, 1476 "PCH UART : Use PIO Mode (without DMA)\n"); 1477 priv->use_dma = 0; 1478 serinfo->flags &= ~UPF_LOW_LATENCY; 1479 } else { 1480 #ifndef CONFIG_PCH_DMA 1481 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1482 __func__); 1483 return -EOPNOTSUPP; 1484 #endif 1485 if (!priv->use_dma) { 1486 pch_request_dma(port); 1487 if (priv->chan_rx) 1488 priv->use_dma = 1; 1489 } 1490 dev_info(priv->port.dev, "PCH UART: %s\n", 1491 priv->use_dma ? 1492 "Use DMA Mode" : "No DMA"); 1493 } 1494 1495 return 0; 1496 } 1497 1498 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE) 1499 /* 1500 * Wait for transmitter & holding register to empty 1501 */ 1502 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1503 { 1504 unsigned int status, tmout = 10000; 1505 1506 /* Wait up to 10ms for the character(s) to be sent. */ 1507 for (;;) { 1508 status = ioread8(up->membase + UART_LSR); 1509 1510 if ((status & bits) == bits) 1511 break; 1512 if (--tmout == 0) 1513 break; 1514 udelay(1); 1515 } 1516 1517 /* Wait up to 1s for flow control if necessary */ 1518 if (up->port.flags & UPF_CONS_FLOW) { 1519 unsigned int tmout; 1520 for (tmout = 1000000; tmout; tmout--) { 1521 unsigned int msr = ioread8(up->membase + UART_MSR); 1522 if (msr & UART_MSR_CTS) 1523 break; 1524 udelay(1); 1525 touch_nmi_watchdog(); 1526 } 1527 } 1528 } 1529 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */ 1530 1531 #ifdef CONFIG_CONSOLE_POLL 1532 /* 1533 * Console polling routines for communicate via uart while 1534 * in an interrupt or debug context. 1535 */ 1536 static int pch_uart_get_poll_char(struct uart_port *port) 1537 { 1538 struct eg20t_port *priv = 1539 container_of(port, struct eg20t_port, port); 1540 u8 lsr = ioread8(priv->membase + UART_LSR); 1541 1542 if (!(lsr & UART_LSR_DR)) 1543 return NO_POLL_CHAR; 1544 1545 return ioread8(priv->membase + PCH_UART_RBR); 1546 } 1547 1548 1549 static void pch_uart_put_poll_char(struct uart_port *port, 1550 unsigned char c) 1551 { 1552 unsigned int ier; 1553 struct eg20t_port *priv = 1554 container_of(port, struct eg20t_port, port); 1555 1556 /* 1557 * First save the IER then disable the interrupts 1558 */ 1559 ier = ioread8(priv->membase + UART_IER); 1560 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1561 1562 wait_for_xmitr(priv, UART_LSR_THRE); 1563 /* 1564 * Send the character out. 1565 */ 1566 iowrite8(c, priv->membase + PCH_UART_THR); 1567 1568 /* 1569 * Finally, wait for transmitter to become empty 1570 * and restore the IER 1571 */ 1572 wait_for_xmitr(priv, BOTH_EMPTY); 1573 iowrite8(ier, priv->membase + UART_IER); 1574 } 1575 #endif /* CONFIG_CONSOLE_POLL */ 1576 1577 static const struct uart_ops pch_uart_ops = { 1578 .tx_empty = pch_uart_tx_empty, 1579 .set_mctrl = pch_uart_set_mctrl, 1580 .get_mctrl = pch_uart_get_mctrl, 1581 .stop_tx = pch_uart_stop_tx, 1582 .start_tx = pch_uart_start_tx, 1583 .stop_rx = pch_uart_stop_rx, 1584 .enable_ms = pch_uart_enable_ms, 1585 .break_ctl = pch_uart_break_ctl, 1586 .startup = pch_uart_startup, 1587 .shutdown = pch_uart_shutdown, 1588 .set_termios = pch_uart_set_termios, 1589 /* .pm = pch_uart_pm, Not supported yet */ 1590 .type = pch_uart_type, 1591 .release_port = pch_uart_release_port, 1592 .request_port = pch_uart_request_port, 1593 .config_port = pch_uart_config_port, 1594 .verify_port = pch_uart_verify_port, 1595 #ifdef CONFIG_CONSOLE_POLL 1596 .poll_get_char = pch_uart_get_poll_char, 1597 .poll_put_char = pch_uart_put_poll_char, 1598 #endif 1599 }; 1600 1601 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1602 1603 static void pch_console_putchar(struct uart_port *port, int ch) 1604 { 1605 struct eg20t_port *priv = 1606 container_of(port, struct eg20t_port, port); 1607 1608 wait_for_xmitr(priv, UART_LSR_THRE); 1609 iowrite8(ch, priv->membase + PCH_UART_THR); 1610 } 1611 1612 /* 1613 * Print a string to the serial port trying not to disturb 1614 * any possible real use of the port... 1615 * 1616 * The console_lock must be held when we get here. 1617 */ 1618 static void 1619 pch_console_write(struct console *co, const char *s, unsigned int count) 1620 { 1621 struct eg20t_port *priv; 1622 unsigned long flags; 1623 int priv_locked = 1; 1624 int port_locked = 1; 1625 u8 ier; 1626 1627 priv = pch_uart_ports[co->index]; 1628 1629 touch_nmi_watchdog(); 1630 1631 local_irq_save(flags); 1632 if (priv->port.sysrq) { 1633 /* call to uart_handle_sysrq_char already took the priv lock */ 1634 priv_locked = 0; 1635 /* serial8250_handle_port() already took the port lock */ 1636 port_locked = 0; 1637 } else if (oops_in_progress) { 1638 priv_locked = spin_trylock(&priv->lock); 1639 port_locked = spin_trylock(&priv->port.lock); 1640 } else { 1641 spin_lock(&priv->lock); 1642 spin_lock(&priv->port.lock); 1643 } 1644 1645 /* 1646 * First save the IER then disable the interrupts 1647 */ 1648 ier = ioread8(priv->membase + UART_IER); 1649 1650 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1651 1652 uart_console_write(&priv->port, s, count, pch_console_putchar); 1653 1654 /* 1655 * Finally, wait for transmitter to become empty 1656 * and restore the IER 1657 */ 1658 wait_for_xmitr(priv, BOTH_EMPTY); 1659 iowrite8(ier, priv->membase + UART_IER); 1660 1661 if (port_locked) 1662 spin_unlock(&priv->port.lock); 1663 if (priv_locked) 1664 spin_unlock(&priv->lock); 1665 local_irq_restore(flags); 1666 } 1667 1668 static int __init pch_console_setup(struct console *co, char *options) 1669 { 1670 struct uart_port *port; 1671 int baud = default_baud; 1672 int bits = 8; 1673 int parity = 'n'; 1674 int flow = 'n'; 1675 1676 /* 1677 * Check whether an invalid uart number has been specified, and 1678 * if so, search for the first available port that does have 1679 * console support. 1680 */ 1681 if (co->index >= PCH_UART_NR) 1682 co->index = 0; 1683 port = &pch_uart_ports[co->index]->port; 1684 1685 if (!port || (!port->iobase && !port->membase)) 1686 return -ENODEV; 1687 1688 port->uartclk = pch_uart_get_uartclk(); 1689 1690 if (options) 1691 uart_parse_options(options, &baud, &parity, &bits, &flow); 1692 1693 return uart_set_options(port, co, baud, parity, bits, flow); 1694 } 1695 1696 static struct uart_driver pch_uart_driver; 1697 1698 static struct console pch_console = { 1699 .name = PCH_UART_DRIVER_DEVICE, 1700 .write = pch_console_write, 1701 .device = uart_console_device, 1702 .setup = pch_console_setup, 1703 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1704 .index = -1, 1705 .data = &pch_uart_driver, 1706 }; 1707 1708 #define PCH_CONSOLE (&pch_console) 1709 #else 1710 #define PCH_CONSOLE NULL 1711 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ 1712 1713 static struct uart_driver pch_uart_driver = { 1714 .owner = THIS_MODULE, 1715 .driver_name = KBUILD_MODNAME, 1716 .dev_name = PCH_UART_DRIVER_DEVICE, 1717 .major = 0, 1718 .minor = 0, 1719 .nr = PCH_UART_NR, 1720 .cons = PCH_CONSOLE, 1721 }; 1722 1723 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1724 const struct pci_device_id *id) 1725 { 1726 struct eg20t_port *priv; 1727 int ret; 1728 unsigned int iobase; 1729 unsigned int mapbase; 1730 unsigned char *rxbuf; 1731 int fifosize; 1732 int port_type; 1733 struct pch_uart_driver_data *board; 1734 char name[32]; 1735 1736 board = &drv_dat[id->driver_data]; 1737 port_type = board->port_type; 1738 1739 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1740 if (priv == NULL) 1741 goto init_port_alloc_err; 1742 1743 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1744 if (!rxbuf) 1745 goto init_port_free_txbuf; 1746 1747 switch (port_type) { 1748 case PORT_PCH_8LINE: 1749 fifosize = 256; /* EG20T/ML7213: UART0 */ 1750 break; 1751 case PORT_PCH_2LINE: 1752 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1753 break; 1754 default: 1755 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1756 goto init_port_hal_free; 1757 } 1758 1759 pci_enable_msi(pdev); 1760 pci_set_master(pdev); 1761 1762 spin_lock_init(&priv->lock); 1763 1764 iobase = pci_resource_start(pdev, 0); 1765 mapbase = pci_resource_start(pdev, 1); 1766 priv->mapbase = mapbase; 1767 priv->iobase = iobase; 1768 priv->pdev = pdev; 1769 priv->tx_empty = 1; 1770 priv->rxbuf.buf = rxbuf; 1771 priv->rxbuf.size = PAGE_SIZE; 1772 1773 priv->fifo_size = fifosize; 1774 priv->uartclk = pch_uart_get_uartclk(); 1775 priv->port_type = port_type; 1776 priv->port.dev = &pdev->dev; 1777 priv->port.iobase = iobase; 1778 priv->port.membase = NULL; 1779 priv->port.mapbase = mapbase; 1780 priv->port.irq = pdev->irq; 1781 priv->port.iotype = UPIO_PORT; 1782 priv->port.ops = &pch_uart_ops; 1783 priv->port.flags = UPF_BOOT_AUTOCONF; 1784 priv->port.fifosize = fifosize; 1785 priv->port.line = board->line_no; 1786 priv->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PCH_UART_CONSOLE); 1787 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1788 1789 snprintf(priv->irq_name, IRQ_NAME_SIZE, 1790 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d", 1791 priv->port.line); 1792 1793 spin_lock_init(&priv->port.lock); 1794 1795 pci_set_drvdata(pdev, priv); 1796 priv->trigger_level = 1; 1797 priv->fcr = 0; 1798 1799 if (pdev->dev.of_node) 1800 of_property_read_u32(pdev->dev.of_node, "clock-frequency" 1801 , &user_uartclk); 1802 1803 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1804 pch_uart_ports[board->line_no] = priv; 1805 #endif 1806 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1807 if (ret < 0) 1808 goto init_port_hal_free; 1809 1810 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1811 debugfs_create_file(name, S_IFREG | S_IRUGO, NULL, priv, 1812 &port_regs_ops); 1813 1814 return priv; 1815 1816 init_port_hal_free: 1817 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1818 pch_uart_ports[board->line_no] = NULL; 1819 #endif 1820 free_page((unsigned long)rxbuf); 1821 init_port_free_txbuf: 1822 kfree(priv); 1823 init_port_alloc_err: 1824 1825 return NULL; 1826 } 1827 1828 static void pch_uart_exit_port(struct eg20t_port *priv) 1829 { 1830 char name[32]; 1831 1832 snprintf(name, sizeof(name), "uart%d_regs", priv->port.line); 1833 debugfs_remove(debugfs_lookup(name, NULL)); 1834 uart_remove_one_port(&pch_uart_driver, &priv->port); 1835 free_page((unsigned long)priv->rxbuf.buf); 1836 } 1837 1838 static void pch_uart_pci_remove(struct pci_dev *pdev) 1839 { 1840 struct eg20t_port *priv = pci_get_drvdata(pdev); 1841 1842 pci_disable_msi(pdev); 1843 1844 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1845 pch_uart_ports[priv->port.line] = NULL; 1846 #endif 1847 pch_uart_exit_port(priv); 1848 pci_disable_device(pdev); 1849 kfree(priv); 1850 return; 1851 } 1852 1853 static int __maybe_unused pch_uart_pci_suspend(struct device *dev) 1854 { 1855 struct eg20t_port *priv = dev_get_drvdata(dev); 1856 1857 uart_suspend_port(&pch_uart_driver, &priv->port); 1858 1859 return 0; 1860 } 1861 1862 static int __maybe_unused pch_uart_pci_resume(struct device *dev) 1863 { 1864 struct eg20t_port *priv = dev_get_drvdata(dev); 1865 1866 uart_resume_port(&pch_uart_driver, &priv->port); 1867 1868 return 0; 1869 } 1870 1871 static const struct pci_device_id pch_uart_pci_id[] = { 1872 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1873 .driver_data = pch_et20t_uart0}, 1874 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1875 .driver_data = pch_et20t_uart1}, 1876 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1877 .driver_data = pch_et20t_uart2}, 1878 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1879 .driver_data = pch_et20t_uart3}, 1880 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1881 .driver_data = pch_ml7213_uart0}, 1882 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1883 .driver_data = pch_ml7213_uart1}, 1884 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1885 .driver_data = pch_ml7213_uart2}, 1886 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1887 .driver_data = pch_ml7223_uart0}, 1888 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1889 .driver_data = pch_ml7223_uart1}, 1890 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1891 .driver_data = pch_ml7831_uart0}, 1892 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1893 .driver_data = pch_ml7831_uart1}, 1894 {0,}, 1895 }; 1896 1897 static int pch_uart_pci_probe(struct pci_dev *pdev, 1898 const struct pci_device_id *id) 1899 { 1900 int ret; 1901 struct eg20t_port *priv; 1902 1903 ret = pci_enable_device(pdev); 1904 if (ret < 0) 1905 goto probe_error; 1906 1907 priv = pch_uart_init_port(pdev, id); 1908 if (!priv) { 1909 ret = -EBUSY; 1910 goto probe_disable_device; 1911 } 1912 pci_set_drvdata(pdev, priv); 1913 1914 return ret; 1915 1916 probe_disable_device: 1917 pci_disable_msi(pdev); 1918 pci_disable_device(pdev); 1919 probe_error: 1920 return ret; 1921 } 1922 1923 static SIMPLE_DEV_PM_OPS(pch_uart_pci_pm_ops, 1924 pch_uart_pci_suspend, 1925 pch_uart_pci_resume); 1926 1927 static struct pci_driver pch_uart_pci_driver = { 1928 .name = "pch_uart", 1929 .id_table = pch_uart_pci_id, 1930 .probe = pch_uart_pci_probe, 1931 .remove = pch_uart_pci_remove, 1932 .driver.pm = &pch_uart_pci_pm_ops, 1933 }; 1934 1935 static int __init pch_uart_module_init(void) 1936 { 1937 int ret; 1938 1939 /* register as UART driver */ 1940 ret = uart_register_driver(&pch_uart_driver); 1941 if (ret < 0) 1942 return ret; 1943 1944 /* register as PCI driver */ 1945 ret = pci_register_driver(&pch_uart_pci_driver); 1946 if (ret < 0) 1947 uart_unregister_driver(&pch_uart_driver); 1948 1949 return ret; 1950 } 1951 module_init(pch_uart_module_init); 1952 1953 static void __exit pch_uart_module_exit(void) 1954 { 1955 pci_unregister_driver(&pch_uart_pci_driver); 1956 uart_unregister_driver(&pch_uart_driver); 1957 } 1958 module_exit(pch_uart_module_exit); 1959 1960 MODULE_LICENSE("GPL v2"); 1961 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 1962 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id); 1963 1964 module_param(default_baud, uint, S_IRUGO); 1965 MODULE_PARM_DESC(default_baud, 1966 "Default BAUD for initial driver state and console (default 9600)"); 1967 module_param(user_uartclk, uint, S_IRUGO); 1968 MODULE_PARM_DESC(user_uartclk, 1969 "Override UART default or board specific UART clock"); 1970