1 /* 2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 3 * 4 *This program is free software; you can redistribute it and/or modify 5 *it under the terms of the GNU General Public License as published by 6 *the Free Software Foundation; version 2 of the License. 7 * 8 *This program is distributed in the hope that it will be useful, 9 *but WITHOUT ANY WARRANTY; without even the implied warranty of 10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 *GNU General Public License for more details. 12 * 13 *You should have received a copy of the GNU General Public License 14 *along with this program; if not, write to the Free Software 15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 16 */ 17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18 #define SUPPORT_SYSRQ 19 #endif 20 #include <linux/kernel.h> 21 #include <linux/serial_reg.h> 22 #include <linux/slab.h> 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/console.h> 26 #include <linux/serial_core.h> 27 #include <linux/tty.h> 28 #include <linux/tty_flip.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/dmi.h> 32 #include <linux/nmi.h> 33 #include <linux/delay.h> 34 #include <linux/of.h> 35 36 #include <linux/debugfs.h> 37 #include <linux/dmaengine.h> 38 #include <linux/pch_dma.h> 39 40 enum { 41 PCH_UART_HANDLED_RX_INT_SHIFT, 42 PCH_UART_HANDLED_TX_INT_SHIFT, 43 PCH_UART_HANDLED_RX_ERR_INT_SHIFT, 44 PCH_UART_HANDLED_RX_TRG_INT_SHIFT, 45 PCH_UART_HANDLED_MS_INT_SHIFT, 46 PCH_UART_HANDLED_LS_INT_SHIFT, 47 }; 48 49 #define PCH_UART_DRIVER_DEVICE "ttyPCH" 50 51 /* Set the max number of UART port 52 * Intel EG20T PCH: 4 port 53 * LAPIS Semiconductor ML7213 IOH: 3 port 54 * LAPIS Semiconductor ML7223 IOH: 2 port 55 */ 56 #define PCH_UART_NR 4 57 58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1)) 59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1)) 60 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\ 61 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1)) 62 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\ 63 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1)) 64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1)) 65 66 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1)) 67 68 #define PCH_UART_RBR 0x00 69 #define PCH_UART_THR 0x00 70 71 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\ 72 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI) 73 #define PCH_UART_IER_ERBFI 0x00000001 74 #define PCH_UART_IER_ETBEI 0x00000002 75 #define PCH_UART_IER_ELSI 0x00000004 76 #define PCH_UART_IER_EDSSI 0x00000008 77 78 #define PCH_UART_IIR_IP 0x00000001 79 #define PCH_UART_IIR_IID 0x00000006 80 #define PCH_UART_IIR_MSI 0x00000000 81 #define PCH_UART_IIR_TRI 0x00000002 82 #define PCH_UART_IIR_RRI 0x00000004 83 #define PCH_UART_IIR_REI 0x00000006 84 #define PCH_UART_IIR_TOI 0x00000008 85 #define PCH_UART_IIR_FIFO256 0x00000020 86 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256 87 #define PCH_UART_IIR_FE 0x000000C0 88 89 #define PCH_UART_FCR_FIFOE 0x00000001 90 #define PCH_UART_FCR_RFR 0x00000002 91 #define PCH_UART_FCR_TFR 0x00000004 92 #define PCH_UART_FCR_DMS 0x00000008 93 #define PCH_UART_FCR_FIFO256 0x00000020 94 #define PCH_UART_FCR_RFTL 0x000000C0 95 96 #define PCH_UART_FCR_RFTL1 0x00000000 97 #define PCH_UART_FCR_RFTL64 0x00000040 98 #define PCH_UART_FCR_RFTL128 0x00000080 99 #define PCH_UART_FCR_RFTL224 0x000000C0 100 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64 101 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128 102 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224 103 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64 104 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128 105 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224 106 #define PCH_UART_FCR_RFTL_SHIFT 6 107 108 #define PCH_UART_LCR_WLS 0x00000003 109 #define PCH_UART_LCR_STB 0x00000004 110 #define PCH_UART_LCR_PEN 0x00000008 111 #define PCH_UART_LCR_EPS 0x00000010 112 #define PCH_UART_LCR_SP 0x00000020 113 #define PCH_UART_LCR_SB 0x00000040 114 #define PCH_UART_LCR_DLAB 0x00000080 115 #define PCH_UART_LCR_NP 0x00000000 116 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN 117 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS) 118 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP) 119 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\ 120 PCH_UART_LCR_SP) 121 122 #define PCH_UART_LCR_5BIT 0x00000000 123 #define PCH_UART_LCR_6BIT 0x00000001 124 #define PCH_UART_LCR_7BIT 0x00000002 125 #define PCH_UART_LCR_8BIT 0x00000003 126 127 #define PCH_UART_MCR_DTR 0x00000001 128 #define PCH_UART_MCR_RTS 0x00000002 129 #define PCH_UART_MCR_OUT 0x0000000C 130 #define PCH_UART_MCR_LOOP 0x00000010 131 #define PCH_UART_MCR_AFE 0x00000020 132 133 #define PCH_UART_LSR_DR 0x00000001 134 #define PCH_UART_LSR_ERR (1<<7) 135 136 #define PCH_UART_MSR_DCTS 0x00000001 137 #define PCH_UART_MSR_DDSR 0x00000002 138 #define PCH_UART_MSR_TERI 0x00000004 139 #define PCH_UART_MSR_DDCD 0x00000008 140 #define PCH_UART_MSR_CTS 0x00000010 141 #define PCH_UART_MSR_DSR 0x00000020 142 #define PCH_UART_MSR_RI 0x00000040 143 #define PCH_UART_MSR_DCD 0x00000080 144 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\ 145 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD) 146 147 #define PCH_UART_DLL 0x00 148 #define PCH_UART_DLM 0x01 149 150 #define PCH_UART_BRCSR 0x0E 151 152 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI) 153 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI) 154 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI) 155 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI) 156 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI) 157 158 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP) 159 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP) 160 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP) 161 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P) 162 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P) 163 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT) 164 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT) 165 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT) 166 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT) 167 #define PCH_UART_HAL_STB1 0 168 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB) 169 170 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR) 171 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR) 172 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \ 173 PCH_UART_HAL_CLR_RX_FIFO) 174 175 #define PCH_UART_HAL_DMA_MODE0 0 176 #define PCH_UART_HAL_FIFO_DIS 0 177 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE) 178 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \ 179 PCH_UART_FCR_FIFO256) 180 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256) 181 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1) 182 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64) 183 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128) 184 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224) 185 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16) 186 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32) 187 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56) 188 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4) 189 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8) 190 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14) 191 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64) 192 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128) 193 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224) 194 195 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI) 196 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI) 197 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI) 198 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI) 199 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK) 200 201 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR) 202 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS) 203 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT) 204 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP) 205 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE) 206 207 #define PCI_VENDOR_ID_ROHM 0x10DB 208 209 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 210 211 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */ 212 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */ 213 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */ 214 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */ 215 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */ 216 #define MINNOW_UARTCLK 50000000 /* 50.0000 MHz */ 217 218 struct pch_uart_buffer { 219 unsigned char *buf; 220 int size; 221 }; 222 223 struct eg20t_port { 224 struct uart_port port; 225 int port_type; 226 void __iomem *membase; 227 resource_size_t mapbase; 228 unsigned int iobase; 229 struct pci_dev *pdev; 230 int fifo_size; 231 unsigned int uartclk; 232 int start_tx; 233 int start_rx; 234 int tx_empty; 235 int trigger; 236 int trigger_level; 237 struct pch_uart_buffer rxbuf; 238 unsigned int dmsr; 239 unsigned int fcr; 240 unsigned int mcr; 241 unsigned int use_dma; 242 struct dma_async_tx_descriptor *desc_tx; 243 struct dma_async_tx_descriptor *desc_rx; 244 struct pch_dma_slave param_tx; 245 struct pch_dma_slave param_rx; 246 struct dma_chan *chan_tx; 247 struct dma_chan *chan_rx; 248 struct scatterlist *sg_tx_p; 249 int nent; 250 struct scatterlist sg_rx; 251 int tx_dma_use; 252 void *rx_buf_virt; 253 dma_addr_t rx_buf_dma; 254 255 struct dentry *debugfs; 256 #define IRQ_NAME_SIZE 17 257 char irq_name[IRQ_NAME_SIZE]; 258 259 /* protect the eg20t_port private structure and io access to membase */ 260 spinlock_t lock; 261 }; 262 263 /** 264 * struct pch_uart_driver_data - private data structure for UART-DMA 265 * @port_type: The type of UART port 266 * @line_no: UART port line number (0, 1, 2...) 267 */ 268 struct pch_uart_driver_data { 269 int port_type; 270 int line_no; 271 }; 272 273 enum pch_uart_num_t { 274 pch_et20t_uart0 = 0, 275 pch_et20t_uart1, 276 pch_et20t_uart2, 277 pch_et20t_uart3, 278 pch_ml7213_uart0, 279 pch_ml7213_uart1, 280 pch_ml7213_uart2, 281 pch_ml7223_uart0, 282 pch_ml7223_uart1, 283 pch_ml7831_uart0, 284 pch_ml7831_uart1, 285 }; 286 287 static struct pch_uart_driver_data drv_dat[] = { 288 [pch_et20t_uart0] = {PORT_PCH_8LINE, 0}, 289 [pch_et20t_uart1] = {PORT_PCH_2LINE, 1}, 290 [pch_et20t_uart2] = {PORT_PCH_2LINE, 2}, 291 [pch_et20t_uart3] = {PORT_PCH_2LINE, 3}, 292 [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0}, 293 [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1}, 294 [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2}, 295 [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0}, 296 [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1}, 297 [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0}, 298 [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1}, 299 }; 300 301 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 302 static struct eg20t_port *pch_uart_ports[PCH_UART_NR]; 303 #endif 304 static unsigned int default_baud = 9600; 305 static unsigned int user_uartclk = 0; 306 static const int trigger_level_256[4] = { 1, 64, 128, 224 }; 307 static const int trigger_level_64[4] = { 1, 16, 32, 56 }; 308 static const int trigger_level_16[4] = { 1, 4, 8, 14 }; 309 static const int trigger_level_1[4] = { 1, 1, 1, 1 }; 310 311 #ifdef CONFIG_DEBUG_FS 312 313 #define PCH_REGS_BUFSIZE 1024 314 315 316 static ssize_t port_show_regs(struct file *file, char __user *user_buf, 317 size_t count, loff_t *ppos) 318 { 319 struct eg20t_port *priv = file->private_data; 320 char *buf; 321 u32 len = 0; 322 ssize_t ret; 323 unsigned char lcr; 324 325 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL); 326 if (!buf) 327 return 0; 328 329 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 330 "PCH EG20T port[%d] regs:\n", priv->port.line); 331 332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 333 "=================================\n"); 334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 335 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER)); 336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 337 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR)); 338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 339 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR)); 340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 341 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR)); 342 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 343 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR)); 344 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 345 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR)); 346 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 347 "BRCSR: \t0x%02x\n", 348 ioread8(priv->membase + PCH_UART_BRCSR)); 349 350 lcr = ioread8(priv->membase + UART_LCR); 351 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 352 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 353 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL)); 354 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len, 355 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM)); 356 iowrite8(lcr, priv->membase + UART_LCR); 357 358 if (len > PCH_REGS_BUFSIZE) 359 len = PCH_REGS_BUFSIZE; 360 361 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len); 362 kfree(buf); 363 return ret; 364 } 365 366 static const struct file_operations port_regs_ops = { 367 .owner = THIS_MODULE, 368 .open = simple_open, 369 .read = port_show_regs, 370 .llseek = default_llseek, 371 }; 372 #endif /* CONFIG_DEBUG_FS */ 373 374 static const struct dmi_system_id pch_uart_dmi_table[] = { 375 { 376 .ident = "CM-iTC", 377 { 378 DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"), 379 }, 380 (void *)CMITC_UARTCLK, 381 }, 382 { 383 .ident = "FRI2", 384 { 385 DMI_MATCH(DMI_BIOS_VERSION, "FRI2"), 386 }, 387 (void *)FRI2_64_UARTCLK, 388 }, 389 { 390 .ident = "Fish River Island II", 391 { 392 DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"), 393 }, 394 (void *)FRI2_48_UARTCLK, 395 }, 396 { 397 .ident = "COMe-mTT", 398 { 399 DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"), 400 }, 401 (void *)NTC1_UARTCLK, 402 }, 403 { 404 .ident = "nanoETXexpress-TT", 405 { 406 DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"), 407 }, 408 (void *)NTC1_UARTCLK, 409 }, 410 { 411 .ident = "MinnowBoard", 412 { 413 DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"), 414 }, 415 (void *)MINNOW_UARTCLK, 416 }, 417 { } 418 }; 419 420 /* Return UART clock, checking for board specific clocks. */ 421 static unsigned int pch_uart_get_uartclk(void) 422 { 423 const struct dmi_system_id *d; 424 425 if (user_uartclk) 426 return user_uartclk; 427 428 d = dmi_first_match(pch_uart_dmi_table); 429 if (d) 430 return (unsigned long)d->driver_data; 431 432 return DEFAULT_UARTCLK; 433 } 434 435 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv, 436 unsigned int flag) 437 { 438 u8 ier = ioread8(priv->membase + UART_IER); 439 ier |= flag & PCH_UART_IER_MASK; 440 iowrite8(ier, priv->membase + UART_IER); 441 } 442 443 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv, 444 unsigned int flag) 445 { 446 u8 ier = ioread8(priv->membase + UART_IER); 447 ier &= ~(flag & PCH_UART_IER_MASK); 448 iowrite8(ier, priv->membase + UART_IER); 449 } 450 451 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud, 452 unsigned int parity, unsigned int bits, 453 unsigned int stb) 454 { 455 unsigned int dll, dlm, lcr; 456 int div; 457 458 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud); 459 if (div < 0 || USHRT_MAX <= div) { 460 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div); 461 return -EINVAL; 462 } 463 464 dll = (unsigned int)div & 0x00FFU; 465 dlm = ((unsigned int)div >> 8) & 0x00FFU; 466 467 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) { 468 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity); 469 return -EINVAL; 470 } 471 472 if (bits & ~PCH_UART_LCR_WLS) { 473 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits); 474 return -EINVAL; 475 } 476 477 if (stb & ~PCH_UART_LCR_STB) { 478 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb); 479 return -EINVAL; 480 } 481 482 lcr = parity; 483 lcr |= bits; 484 lcr |= stb; 485 486 dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n", 487 __func__, baud, div, lcr, jiffies); 488 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR); 489 iowrite8(dll, priv->membase + PCH_UART_DLL); 490 iowrite8(dlm, priv->membase + PCH_UART_DLM); 491 iowrite8(lcr, priv->membase + UART_LCR); 492 493 return 0; 494 } 495 496 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv, 497 unsigned int flag) 498 { 499 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) { 500 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n", 501 __func__, flag); 502 return -EINVAL; 503 } 504 505 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR); 506 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag, 507 priv->membase + UART_FCR); 508 iowrite8(priv->fcr, priv->membase + UART_FCR); 509 510 return 0; 511 } 512 513 static int pch_uart_hal_set_fifo(struct eg20t_port *priv, 514 unsigned int dmamode, 515 unsigned int fifo_size, unsigned int trigger) 516 { 517 u8 fcr; 518 519 if (dmamode & ~PCH_UART_FCR_DMS) { 520 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n", 521 __func__, dmamode); 522 return -EINVAL; 523 } 524 525 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) { 526 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n", 527 __func__, fifo_size); 528 return -EINVAL; 529 } 530 531 if (trigger & ~PCH_UART_FCR_RFTL) { 532 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n", 533 __func__, trigger); 534 return -EINVAL; 535 } 536 537 switch (priv->fifo_size) { 538 case 256: 539 priv->trigger_level = 540 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 541 break; 542 case 64: 543 priv->trigger_level = 544 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 545 break; 546 case 16: 547 priv->trigger_level = 548 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 549 break; 550 default: 551 priv->trigger_level = 552 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT]; 553 break; 554 } 555 fcr = 556 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR; 557 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR); 558 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR, 559 priv->membase + UART_FCR); 560 iowrite8(fcr, priv->membase + UART_FCR); 561 priv->fcr = fcr; 562 563 return 0; 564 } 565 566 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv) 567 { 568 unsigned int msr = ioread8(priv->membase + UART_MSR); 569 priv->dmsr = msr & PCH_UART_MSR_DELTA; 570 return (u8)msr; 571 } 572 573 static void pch_uart_hal_write(struct eg20t_port *priv, 574 const unsigned char *buf, int tx_size) 575 { 576 int i; 577 unsigned int thr; 578 579 for (i = 0; i < tx_size;) { 580 thr = buf[i++]; 581 iowrite8(thr, priv->membase + PCH_UART_THR); 582 } 583 } 584 585 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf, 586 int rx_size) 587 { 588 int i; 589 u8 rbr, lsr; 590 struct uart_port *port = &priv->port; 591 592 lsr = ioread8(priv->membase + UART_LSR); 593 for (i = 0, lsr = ioread8(priv->membase + UART_LSR); 594 i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI); 595 lsr = ioread8(priv->membase + UART_LSR)) { 596 rbr = ioread8(priv->membase + PCH_UART_RBR); 597 598 if (lsr & UART_LSR_BI) { 599 port->icount.brk++; 600 if (uart_handle_break(port)) 601 continue; 602 } 603 #ifdef SUPPORT_SYSRQ 604 if (port->sysrq) { 605 if (uart_handle_sysrq_char(port, rbr)) 606 continue; 607 } 608 #endif 609 610 buf[i++] = rbr; 611 } 612 return i; 613 } 614 615 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv) 616 { 617 return ioread8(priv->membase + UART_IIR) &\ 618 (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP); 619 } 620 621 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv) 622 { 623 return ioread8(priv->membase + UART_LSR); 624 } 625 626 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on) 627 { 628 unsigned int lcr; 629 630 lcr = ioread8(priv->membase + UART_LCR); 631 if (on) 632 lcr |= PCH_UART_LCR_SB; 633 else 634 lcr &= ~PCH_UART_LCR_SB; 635 636 iowrite8(lcr, priv->membase + UART_LCR); 637 } 638 639 static int push_rx(struct eg20t_port *priv, const unsigned char *buf, 640 int size) 641 { 642 struct uart_port *port = &priv->port; 643 struct tty_port *tport = &port->state->port; 644 645 tty_insert_flip_string(tport, buf, size); 646 tty_flip_buffer_push(tport); 647 648 return 0; 649 } 650 651 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf) 652 { 653 int ret = 0; 654 struct uart_port *port = &priv->port; 655 656 if (port->x_char) { 657 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n", 658 __func__, port->x_char, jiffies); 659 buf[0] = port->x_char; 660 port->x_char = 0; 661 ret = 1; 662 } 663 664 return ret; 665 } 666 667 static int dma_push_rx(struct eg20t_port *priv, int size) 668 { 669 int room; 670 struct uart_port *port = &priv->port; 671 struct tty_port *tport = &port->state->port; 672 673 room = tty_buffer_request_room(tport, size); 674 675 if (room < size) 676 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n", 677 size - room); 678 if (!room) 679 return 0; 680 681 tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size); 682 683 port->icount.rx += room; 684 685 return room; 686 } 687 688 static void pch_free_dma(struct uart_port *port) 689 { 690 struct eg20t_port *priv; 691 priv = container_of(port, struct eg20t_port, port); 692 693 if (priv->chan_tx) { 694 dma_release_channel(priv->chan_tx); 695 priv->chan_tx = NULL; 696 } 697 if (priv->chan_rx) { 698 dma_release_channel(priv->chan_rx); 699 priv->chan_rx = NULL; 700 } 701 702 if (priv->rx_buf_dma) { 703 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt, 704 priv->rx_buf_dma); 705 priv->rx_buf_virt = NULL; 706 priv->rx_buf_dma = 0; 707 } 708 709 return; 710 } 711 712 static bool filter(struct dma_chan *chan, void *slave) 713 { 714 struct pch_dma_slave *param = slave; 715 716 if ((chan->chan_id == param->chan_id) && (param->dma_dev == 717 chan->device->dev)) { 718 chan->private = param; 719 return true; 720 } else { 721 return false; 722 } 723 } 724 725 static void pch_request_dma(struct uart_port *port) 726 { 727 dma_cap_mask_t mask; 728 struct dma_chan *chan; 729 struct pci_dev *dma_dev; 730 struct pch_dma_slave *param; 731 struct eg20t_port *priv = 732 container_of(port, struct eg20t_port, port); 733 dma_cap_zero(mask); 734 dma_cap_set(DMA_SLAVE, mask); 735 736 /* Get DMA's dev information */ 737 dma_dev = pci_get_slot(priv->pdev->bus, 738 PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0)); 739 740 /* Set Tx DMA */ 741 param = &priv->param_tx; 742 param->dma_dev = &dma_dev->dev; 743 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */ 744 745 param->tx_reg = port->mapbase + UART_TX; 746 chan = dma_request_channel(mask, filter, param); 747 if (!chan) { 748 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n", 749 __func__); 750 return; 751 } 752 priv->chan_tx = chan; 753 754 /* Set Rx DMA */ 755 param = &priv->param_rx; 756 param->dma_dev = &dma_dev->dev; 757 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */ 758 759 param->rx_reg = port->mapbase + UART_RX; 760 chan = dma_request_channel(mask, filter, param); 761 if (!chan) { 762 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n", 763 __func__); 764 dma_release_channel(priv->chan_tx); 765 priv->chan_tx = NULL; 766 return; 767 } 768 769 /* Get Consistent memory for DMA */ 770 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize, 771 &priv->rx_buf_dma, GFP_KERNEL); 772 priv->chan_rx = chan; 773 } 774 775 static void pch_dma_rx_complete(void *arg) 776 { 777 struct eg20t_port *priv = arg; 778 struct uart_port *port = &priv->port; 779 int count; 780 781 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE); 782 count = dma_push_rx(priv, priv->trigger_level); 783 if (count) 784 tty_flip_buffer_push(&port->state->port); 785 async_tx_ack(priv->desc_rx); 786 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 787 PCH_UART_HAL_RX_ERR_INT); 788 } 789 790 static void pch_dma_tx_complete(void *arg) 791 { 792 struct eg20t_port *priv = arg; 793 struct uart_port *port = &priv->port; 794 struct circ_buf *xmit = &port->state->xmit; 795 struct scatterlist *sg = priv->sg_tx_p; 796 int i; 797 798 for (i = 0; i < priv->nent; i++, sg++) { 799 xmit->tail += sg_dma_len(sg); 800 port->icount.tx += sg_dma_len(sg); 801 } 802 xmit->tail &= UART_XMIT_SIZE - 1; 803 async_tx_ack(priv->desc_tx); 804 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE); 805 priv->tx_dma_use = 0; 806 priv->nent = 0; 807 kfree(priv->sg_tx_p); 808 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 809 } 810 811 static int pop_tx(struct eg20t_port *priv, int size) 812 { 813 int count = 0; 814 struct uart_port *port = &priv->port; 815 struct circ_buf *xmit = &port->state->xmit; 816 817 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size) 818 goto pop_tx_end; 819 820 do { 821 int cnt_to_end = 822 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 823 int sz = min(size - count, cnt_to_end); 824 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz); 825 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1); 826 count += sz; 827 } while (!uart_circ_empty(xmit) && count < size); 828 829 pop_tx_end: 830 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n", 831 count, size - count, jiffies); 832 833 return count; 834 } 835 836 static int handle_rx_to(struct eg20t_port *priv) 837 { 838 struct pch_uart_buffer *buf; 839 int rx_size; 840 int ret; 841 if (!priv->start_rx) { 842 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 843 PCH_UART_HAL_RX_ERR_INT); 844 return 0; 845 } 846 buf = &priv->rxbuf; 847 do { 848 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size); 849 ret = push_rx(priv, buf->buf, rx_size); 850 if (ret) 851 return 0; 852 } while (rx_size == buf->size); 853 854 return PCH_UART_HANDLED_RX_INT; 855 } 856 857 static int handle_rx(struct eg20t_port *priv) 858 { 859 return handle_rx_to(priv); 860 } 861 862 static int dma_handle_rx(struct eg20t_port *priv) 863 { 864 struct uart_port *port = &priv->port; 865 struct dma_async_tx_descriptor *desc; 866 struct scatterlist *sg; 867 868 priv = container_of(port, struct eg20t_port, port); 869 sg = &priv->sg_rx; 870 871 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */ 872 873 sg_dma_len(sg) = priv->trigger_level; 874 875 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt), 876 sg_dma_len(sg), offset_in_page(priv->rx_buf_virt)); 877 878 sg_dma_address(sg) = priv->rx_buf_dma; 879 880 desc = dmaengine_prep_slave_sg(priv->chan_rx, 881 sg, 1, DMA_DEV_TO_MEM, 882 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 883 884 if (!desc) 885 return 0; 886 887 priv->desc_rx = desc; 888 desc->callback = pch_dma_rx_complete; 889 desc->callback_param = priv; 890 desc->tx_submit(desc); 891 dma_async_issue_pending(priv->chan_rx); 892 893 return PCH_UART_HANDLED_RX_INT; 894 } 895 896 static unsigned int handle_tx(struct eg20t_port *priv) 897 { 898 struct uart_port *port = &priv->port; 899 struct circ_buf *xmit = &port->state->xmit; 900 int fifo_size; 901 int tx_size; 902 int size; 903 int tx_empty; 904 905 if (!priv->start_tx) { 906 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 907 __func__, jiffies); 908 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 909 priv->tx_empty = 1; 910 return 0; 911 } 912 913 fifo_size = max(priv->fifo_size, 1); 914 tx_empty = 1; 915 if (pop_tx_x(priv, xmit->buf)) { 916 pch_uart_hal_write(priv, xmit->buf, 1); 917 port->icount.tx++; 918 tx_empty = 0; 919 fifo_size--; 920 } 921 size = min(xmit->head - xmit->tail, fifo_size); 922 if (size < 0) 923 size = fifo_size; 924 925 tx_size = pop_tx(priv, size); 926 if (tx_size > 0) { 927 port->icount.tx += tx_size; 928 tx_empty = 0; 929 } 930 931 priv->tx_empty = tx_empty; 932 933 if (tx_empty) { 934 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 935 uart_write_wakeup(port); 936 } 937 938 return PCH_UART_HANDLED_TX_INT; 939 } 940 941 static unsigned int dma_handle_tx(struct eg20t_port *priv) 942 { 943 struct uart_port *port = &priv->port; 944 struct circ_buf *xmit = &port->state->xmit; 945 struct scatterlist *sg; 946 int nent; 947 int fifo_size; 948 int tx_empty; 949 struct dma_async_tx_descriptor *desc; 950 int num; 951 int i; 952 int bytes; 953 int size; 954 int rem; 955 956 if (!priv->start_tx) { 957 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n", 958 __func__, jiffies); 959 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 960 priv->tx_empty = 1; 961 return 0; 962 } 963 964 if (priv->tx_dma_use) { 965 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n", 966 __func__, jiffies); 967 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 968 priv->tx_empty = 1; 969 return 0; 970 } 971 972 fifo_size = max(priv->fifo_size, 1); 973 tx_empty = 1; 974 if (pop_tx_x(priv, xmit->buf)) { 975 pch_uart_hal_write(priv, xmit->buf, 1); 976 port->icount.tx++; 977 tx_empty = 0; 978 fifo_size--; 979 } 980 981 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail, 982 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head, 983 xmit->tail, UART_XMIT_SIZE)); 984 if (!bytes) { 985 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__); 986 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT); 987 uart_write_wakeup(port); 988 return 0; 989 } 990 991 if (bytes > fifo_size) { 992 num = bytes / fifo_size + 1; 993 size = fifo_size; 994 rem = bytes % fifo_size; 995 } else { 996 num = 1; 997 size = bytes; 998 rem = bytes; 999 } 1000 1001 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n", 1002 __func__, num, size, rem); 1003 1004 priv->tx_dma_use = 1; 1005 1006 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); 1007 if (!priv->sg_tx_p) { 1008 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__); 1009 return 0; 1010 } 1011 1012 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */ 1013 sg = priv->sg_tx_p; 1014 1015 for (i = 0; i < num; i++, sg++) { 1016 if (i == (num - 1)) 1017 sg_set_page(sg, virt_to_page(xmit->buf), 1018 rem, fifo_size * i); 1019 else 1020 sg_set_page(sg, virt_to_page(xmit->buf), 1021 size, fifo_size * i); 1022 } 1023 1024 sg = priv->sg_tx_p; 1025 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE); 1026 if (!nent) { 1027 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__); 1028 return 0; 1029 } 1030 priv->nent = nent; 1031 1032 for (i = 0; i < nent; i++, sg++) { 1033 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) + 1034 fifo_size * i; 1035 sg_dma_address(sg) = (sg_dma_address(sg) & 1036 ~(UART_XMIT_SIZE - 1)) + sg->offset; 1037 if (i == (nent - 1)) 1038 sg_dma_len(sg) = rem; 1039 else 1040 sg_dma_len(sg) = size; 1041 } 1042 1043 desc = dmaengine_prep_slave_sg(priv->chan_tx, 1044 priv->sg_tx_p, nent, DMA_MEM_TO_DEV, 1045 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1046 if (!desc) { 1047 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n", 1048 __func__); 1049 return 0; 1050 } 1051 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE); 1052 priv->desc_tx = desc; 1053 desc->callback = pch_dma_tx_complete; 1054 desc->callback_param = priv; 1055 1056 desc->tx_submit(desc); 1057 1058 dma_async_issue_pending(priv->chan_tx); 1059 1060 return PCH_UART_HANDLED_TX_INT; 1061 } 1062 1063 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr) 1064 { 1065 struct uart_port *port = &priv->port; 1066 struct tty_struct *tty = tty_port_tty_get(&port->state->port); 1067 char *error_msg[5] = {}; 1068 int i = 0; 1069 1070 if (lsr & PCH_UART_LSR_ERR) 1071 error_msg[i++] = "Error data in FIFO\n"; 1072 1073 if (lsr & UART_LSR_FE) { 1074 port->icount.frame++; 1075 error_msg[i++] = " Framing Error\n"; 1076 } 1077 1078 if (lsr & UART_LSR_PE) { 1079 port->icount.parity++; 1080 error_msg[i++] = " Parity Error\n"; 1081 } 1082 1083 if (lsr & UART_LSR_OE) { 1084 port->icount.overrun++; 1085 error_msg[i++] = " Overrun Error\n"; 1086 } 1087 1088 if (tty == NULL) { 1089 for (i = 0; error_msg[i] != NULL; i++) 1090 dev_err(&priv->pdev->dev, error_msg[i]); 1091 } else { 1092 tty_kref_put(tty); 1093 } 1094 } 1095 1096 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id) 1097 { 1098 struct eg20t_port *priv = dev_id; 1099 unsigned int handled; 1100 u8 lsr; 1101 int ret = 0; 1102 unsigned char iid; 1103 unsigned long flags; 1104 int next = 1; 1105 u8 msr; 1106 1107 spin_lock_irqsave(&priv->lock, flags); 1108 handled = 0; 1109 while (next) { 1110 iid = pch_uart_hal_get_iid(priv); 1111 if (iid & PCH_UART_IIR_IP) /* No Interrupt */ 1112 break; 1113 switch (iid) { 1114 case PCH_UART_IID_RLS: /* Receiver Line Status */ 1115 lsr = pch_uart_hal_get_line_status(priv); 1116 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE | 1117 UART_LSR_PE | UART_LSR_OE)) { 1118 pch_uart_err_ir(priv, lsr); 1119 ret = PCH_UART_HANDLED_RX_ERR_INT; 1120 } else { 1121 ret = PCH_UART_HANDLED_LS_INT; 1122 } 1123 break; 1124 case PCH_UART_IID_RDR: /* Received Data Ready */ 1125 if (priv->use_dma) { 1126 pch_uart_hal_disable_interrupt(priv, 1127 PCH_UART_HAL_RX_INT | 1128 PCH_UART_HAL_RX_ERR_INT); 1129 ret = dma_handle_rx(priv); 1130 if (!ret) 1131 pch_uart_hal_enable_interrupt(priv, 1132 PCH_UART_HAL_RX_INT | 1133 PCH_UART_HAL_RX_ERR_INT); 1134 } else { 1135 ret = handle_rx(priv); 1136 } 1137 break; 1138 case PCH_UART_IID_RDR_TO: /* Received Data Ready 1139 (FIFO Timeout) */ 1140 ret = handle_rx_to(priv); 1141 break; 1142 case PCH_UART_IID_THRE: /* Transmitter Holding Register 1143 Empty */ 1144 if (priv->use_dma) 1145 ret = dma_handle_tx(priv); 1146 else 1147 ret = handle_tx(priv); 1148 break; 1149 case PCH_UART_IID_MS: /* Modem Status */ 1150 msr = pch_uart_hal_get_modem(priv); 1151 next = 0; /* MS ir prioirty is the lowest. So, MS ir 1152 means final interrupt */ 1153 if ((msr & UART_MSR_ANY_DELTA) == 0) 1154 break; 1155 ret |= PCH_UART_HANDLED_MS_INT; 1156 break; 1157 default: /* Never junp to this label */ 1158 dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__, 1159 iid, jiffies); 1160 ret = -1; 1161 next = 0; 1162 break; 1163 } 1164 handled |= (unsigned int)ret; 1165 } 1166 1167 spin_unlock_irqrestore(&priv->lock, flags); 1168 return IRQ_RETVAL(handled); 1169 } 1170 1171 /* This function tests whether the transmitter fifo and shifter for the port 1172 described by 'port' is empty. */ 1173 static unsigned int pch_uart_tx_empty(struct uart_port *port) 1174 { 1175 struct eg20t_port *priv; 1176 1177 priv = container_of(port, struct eg20t_port, port); 1178 if (priv->tx_empty) 1179 return TIOCSER_TEMT; 1180 else 1181 return 0; 1182 } 1183 1184 /* Returns the current state of modem control inputs. */ 1185 static unsigned int pch_uart_get_mctrl(struct uart_port *port) 1186 { 1187 struct eg20t_port *priv; 1188 u8 modem; 1189 unsigned int ret = 0; 1190 1191 priv = container_of(port, struct eg20t_port, port); 1192 modem = pch_uart_hal_get_modem(priv); 1193 1194 if (modem & UART_MSR_DCD) 1195 ret |= TIOCM_CAR; 1196 1197 if (modem & UART_MSR_RI) 1198 ret |= TIOCM_RNG; 1199 1200 if (modem & UART_MSR_DSR) 1201 ret |= TIOCM_DSR; 1202 1203 if (modem & UART_MSR_CTS) 1204 ret |= TIOCM_CTS; 1205 1206 return ret; 1207 } 1208 1209 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1210 { 1211 u32 mcr = 0; 1212 struct eg20t_port *priv = container_of(port, struct eg20t_port, port); 1213 1214 if (mctrl & TIOCM_DTR) 1215 mcr |= UART_MCR_DTR; 1216 if (mctrl & TIOCM_RTS) 1217 mcr |= UART_MCR_RTS; 1218 if (mctrl & TIOCM_LOOP) 1219 mcr |= UART_MCR_LOOP; 1220 1221 if (priv->mcr & UART_MCR_AFE) 1222 mcr |= UART_MCR_AFE; 1223 1224 if (mctrl) 1225 iowrite8(mcr, priv->membase + UART_MCR); 1226 } 1227 1228 static void pch_uart_stop_tx(struct uart_port *port) 1229 { 1230 struct eg20t_port *priv; 1231 priv = container_of(port, struct eg20t_port, port); 1232 priv->start_tx = 0; 1233 priv->tx_dma_use = 0; 1234 } 1235 1236 static void pch_uart_start_tx(struct uart_port *port) 1237 { 1238 struct eg20t_port *priv; 1239 1240 priv = container_of(port, struct eg20t_port, port); 1241 1242 if (priv->use_dma) { 1243 if (priv->tx_dma_use) { 1244 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n", 1245 __func__); 1246 return; 1247 } 1248 } 1249 1250 priv->start_tx = 1; 1251 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT); 1252 } 1253 1254 static void pch_uart_stop_rx(struct uart_port *port) 1255 { 1256 struct eg20t_port *priv; 1257 priv = container_of(port, struct eg20t_port, port); 1258 priv->start_rx = 0; 1259 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT | 1260 PCH_UART_HAL_RX_ERR_INT); 1261 } 1262 1263 /* Enable the modem status interrupts. */ 1264 static void pch_uart_enable_ms(struct uart_port *port) 1265 { 1266 struct eg20t_port *priv; 1267 priv = container_of(port, struct eg20t_port, port); 1268 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT); 1269 } 1270 1271 /* Control the transmission of a break signal. */ 1272 static void pch_uart_break_ctl(struct uart_port *port, int ctl) 1273 { 1274 struct eg20t_port *priv; 1275 unsigned long flags; 1276 1277 priv = container_of(port, struct eg20t_port, port); 1278 spin_lock_irqsave(&priv->lock, flags); 1279 pch_uart_hal_set_break(priv, ctl); 1280 spin_unlock_irqrestore(&priv->lock, flags); 1281 } 1282 1283 /* Grab any interrupt resources and initialise any low level driver state. */ 1284 static int pch_uart_startup(struct uart_port *port) 1285 { 1286 struct eg20t_port *priv; 1287 int ret; 1288 int fifo_size; 1289 int trigger_level; 1290 1291 priv = container_of(port, struct eg20t_port, port); 1292 priv->tx_empty = 1; 1293 1294 if (port->uartclk) 1295 priv->uartclk = port->uartclk; 1296 else 1297 port->uartclk = priv->uartclk; 1298 1299 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1300 ret = pch_uart_hal_set_line(priv, default_baud, 1301 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT, 1302 PCH_UART_HAL_STB1); 1303 if (ret) 1304 return ret; 1305 1306 switch (priv->fifo_size) { 1307 case 256: 1308 fifo_size = PCH_UART_HAL_FIFO256; 1309 break; 1310 case 64: 1311 fifo_size = PCH_UART_HAL_FIFO64; 1312 break; 1313 case 16: 1314 fifo_size = PCH_UART_HAL_FIFO16; 1315 break; 1316 case 1: 1317 default: 1318 fifo_size = PCH_UART_HAL_FIFO_DIS; 1319 break; 1320 } 1321 1322 switch (priv->trigger) { 1323 case PCH_UART_HAL_TRIGGER1: 1324 trigger_level = 1; 1325 break; 1326 case PCH_UART_HAL_TRIGGER_L: 1327 trigger_level = priv->fifo_size / 4; 1328 break; 1329 case PCH_UART_HAL_TRIGGER_M: 1330 trigger_level = priv->fifo_size / 2; 1331 break; 1332 case PCH_UART_HAL_TRIGGER_H: 1333 default: 1334 trigger_level = priv->fifo_size - (priv->fifo_size / 8); 1335 break; 1336 } 1337 1338 priv->trigger_level = trigger_level; 1339 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1340 fifo_size, priv->trigger); 1341 if (ret < 0) 1342 return ret; 1343 1344 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED, 1345 priv->irq_name, priv); 1346 if (ret < 0) 1347 return ret; 1348 1349 if (priv->use_dma) 1350 pch_request_dma(port); 1351 1352 priv->start_rx = 1; 1353 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT | 1354 PCH_UART_HAL_RX_ERR_INT); 1355 uart_update_timeout(port, CS8, default_baud); 1356 1357 return 0; 1358 } 1359 1360 static void pch_uart_shutdown(struct uart_port *port) 1361 { 1362 struct eg20t_port *priv; 1363 int ret; 1364 1365 priv = container_of(port, struct eg20t_port, port); 1366 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1367 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO); 1368 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0, 1369 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1); 1370 if (ret) 1371 dev_err(priv->port.dev, 1372 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret); 1373 1374 pch_free_dma(port); 1375 1376 free_irq(priv->port.irq, priv); 1377 } 1378 1379 /* Change the port parameters, including word length, parity, stop 1380 *bits. Update read_status_mask and ignore_status_mask to indicate 1381 *the types of events we are interested in receiving. */ 1382 static void pch_uart_set_termios(struct uart_port *port, 1383 struct ktermios *termios, struct ktermios *old) 1384 { 1385 int rtn; 1386 unsigned int baud, parity, bits, stb; 1387 struct eg20t_port *priv; 1388 unsigned long flags; 1389 1390 priv = container_of(port, struct eg20t_port, port); 1391 switch (termios->c_cflag & CSIZE) { 1392 case CS5: 1393 bits = PCH_UART_HAL_5BIT; 1394 break; 1395 case CS6: 1396 bits = PCH_UART_HAL_6BIT; 1397 break; 1398 case CS7: 1399 bits = PCH_UART_HAL_7BIT; 1400 break; 1401 default: /* CS8 */ 1402 bits = PCH_UART_HAL_8BIT; 1403 break; 1404 } 1405 if (termios->c_cflag & CSTOPB) 1406 stb = PCH_UART_HAL_STB2; 1407 else 1408 stb = PCH_UART_HAL_STB1; 1409 1410 if (termios->c_cflag & PARENB) { 1411 if (termios->c_cflag & PARODD) 1412 parity = PCH_UART_HAL_PARITY_ODD; 1413 else 1414 parity = PCH_UART_HAL_PARITY_EVEN; 1415 1416 } else 1417 parity = PCH_UART_HAL_PARITY_NONE; 1418 1419 /* Only UART0 has auto hardware flow function */ 1420 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256)) 1421 priv->mcr |= UART_MCR_AFE; 1422 else 1423 priv->mcr &= ~UART_MCR_AFE; 1424 1425 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 1426 1427 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); 1428 1429 spin_lock_irqsave(&priv->lock, flags); 1430 spin_lock(&port->lock); 1431 1432 uart_update_timeout(port, termios->c_cflag, baud); 1433 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb); 1434 if (rtn) 1435 goto out; 1436 1437 pch_uart_set_mctrl(&priv->port, priv->port.mctrl); 1438 /* Don't rewrite B0 */ 1439 if (tty_termios_baud_rate(termios)) 1440 tty_termios_encode_baud_rate(termios, baud, baud); 1441 1442 out: 1443 spin_unlock(&port->lock); 1444 spin_unlock_irqrestore(&priv->lock, flags); 1445 } 1446 1447 static const char *pch_uart_type(struct uart_port *port) 1448 { 1449 return KBUILD_MODNAME; 1450 } 1451 1452 static void pch_uart_release_port(struct uart_port *port) 1453 { 1454 struct eg20t_port *priv; 1455 1456 priv = container_of(port, struct eg20t_port, port); 1457 pci_iounmap(priv->pdev, priv->membase); 1458 pci_release_regions(priv->pdev); 1459 } 1460 1461 static int pch_uart_request_port(struct uart_port *port) 1462 { 1463 struct eg20t_port *priv; 1464 int ret; 1465 void __iomem *membase; 1466 1467 priv = container_of(port, struct eg20t_port, port); 1468 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME); 1469 if (ret < 0) 1470 return -EBUSY; 1471 1472 membase = pci_iomap(priv->pdev, 1, 0); 1473 if (!membase) { 1474 pci_release_regions(priv->pdev); 1475 return -EBUSY; 1476 } 1477 priv->membase = port->membase = membase; 1478 1479 return 0; 1480 } 1481 1482 static void pch_uart_config_port(struct uart_port *port, int type) 1483 { 1484 struct eg20t_port *priv; 1485 1486 priv = container_of(port, struct eg20t_port, port); 1487 if (type & UART_CONFIG_TYPE) { 1488 port->type = priv->port_type; 1489 pch_uart_request_port(port); 1490 } 1491 } 1492 1493 static int pch_uart_verify_port(struct uart_port *port, 1494 struct serial_struct *serinfo) 1495 { 1496 struct eg20t_port *priv; 1497 1498 priv = container_of(port, struct eg20t_port, port); 1499 if (serinfo->flags & UPF_LOW_LATENCY) { 1500 dev_info(priv->port.dev, 1501 "PCH UART : Use PIO Mode (without DMA)\n"); 1502 priv->use_dma = 0; 1503 serinfo->flags &= ~UPF_LOW_LATENCY; 1504 } else { 1505 #ifndef CONFIG_PCH_DMA 1506 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n", 1507 __func__); 1508 return -EOPNOTSUPP; 1509 #endif 1510 if (!priv->use_dma) { 1511 pch_request_dma(port); 1512 if (priv->chan_rx) 1513 priv->use_dma = 1; 1514 } 1515 dev_info(priv->port.dev, "PCH UART: %s\n", 1516 priv->use_dma ? 1517 "Use DMA Mode" : "No DMA"); 1518 } 1519 1520 return 0; 1521 } 1522 1523 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE) 1524 /* 1525 * Wait for transmitter & holding register to empty 1526 */ 1527 static void wait_for_xmitr(struct eg20t_port *up, int bits) 1528 { 1529 unsigned int status, tmout = 10000; 1530 1531 /* Wait up to 10ms for the character(s) to be sent. */ 1532 for (;;) { 1533 status = ioread8(up->membase + UART_LSR); 1534 1535 if ((status & bits) == bits) 1536 break; 1537 if (--tmout == 0) 1538 break; 1539 udelay(1); 1540 } 1541 1542 /* Wait up to 1s for flow control if necessary */ 1543 if (up->port.flags & UPF_CONS_FLOW) { 1544 unsigned int tmout; 1545 for (tmout = 1000000; tmout; tmout--) { 1546 unsigned int msr = ioread8(up->membase + UART_MSR); 1547 if (msr & UART_MSR_CTS) 1548 break; 1549 udelay(1); 1550 touch_nmi_watchdog(); 1551 } 1552 } 1553 } 1554 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */ 1555 1556 #ifdef CONFIG_CONSOLE_POLL 1557 /* 1558 * Console polling routines for communicate via uart while 1559 * in an interrupt or debug context. 1560 */ 1561 static int pch_uart_get_poll_char(struct uart_port *port) 1562 { 1563 struct eg20t_port *priv = 1564 container_of(port, struct eg20t_port, port); 1565 u8 lsr = ioread8(priv->membase + UART_LSR); 1566 1567 if (!(lsr & UART_LSR_DR)) 1568 return NO_POLL_CHAR; 1569 1570 return ioread8(priv->membase + PCH_UART_RBR); 1571 } 1572 1573 1574 static void pch_uart_put_poll_char(struct uart_port *port, 1575 unsigned char c) 1576 { 1577 unsigned int ier; 1578 struct eg20t_port *priv = 1579 container_of(port, struct eg20t_port, port); 1580 1581 /* 1582 * First save the IER then disable the interrupts 1583 */ 1584 ier = ioread8(priv->membase + UART_IER); 1585 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1586 1587 wait_for_xmitr(priv, UART_LSR_THRE); 1588 /* 1589 * Send the character out. 1590 */ 1591 iowrite8(c, priv->membase + PCH_UART_THR); 1592 1593 /* 1594 * Finally, wait for transmitter to become empty 1595 * and restore the IER 1596 */ 1597 wait_for_xmitr(priv, BOTH_EMPTY); 1598 iowrite8(ier, priv->membase + UART_IER); 1599 } 1600 #endif /* CONFIG_CONSOLE_POLL */ 1601 1602 static const struct uart_ops pch_uart_ops = { 1603 .tx_empty = pch_uart_tx_empty, 1604 .set_mctrl = pch_uart_set_mctrl, 1605 .get_mctrl = pch_uart_get_mctrl, 1606 .stop_tx = pch_uart_stop_tx, 1607 .start_tx = pch_uart_start_tx, 1608 .stop_rx = pch_uart_stop_rx, 1609 .enable_ms = pch_uart_enable_ms, 1610 .break_ctl = pch_uart_break_ctl, 1611 .startup = pch_uart_startup, 1612 .shutdown = pch_uart_shutdown, 1613 .set_termios = pch_uart_set_termios, 1614 /* .pm = pch_uart_pm, Not supported yet */ 1615 .type = pch_uart_type, 1616 .release_port = pch_uart_release_port, 1617 .request_port = pch_uart_request_port, 1618 .config_port = pch_uart_config_port, 1619 .verify_port = pch_uart_verify_port, 1620 #ifdef CONFIG_CONSOLE_POLL 1621 .poll_get_char = pch_uart_get_poll_char, 1622 .poll_put_char = pch_uart_put_poll_char, 1623 #endif 1624 }; 1625 1626 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1627 1628 static void pch_console_putchar(struct uart_port *port, int ch) 1629 { 1630 struct eg20t_port *priv = 1631 container_of(port, struct eg20t_port, port); 1632 1633 wait_for_xmitr(priv, UART_LSR_THRE); 1634 iowrite8(ch, priv->membase + PCH_UART_THR); 1635 } 1636 1637 /* 1638 * Print a string to the serial port trying not to disturb 1639 * any possible real use of the port... 1640 * 1641 * The console_lock must be held when we get here. 1642 */ 1643 static void 1644 pch_console_write(struct console *co, const char *s, unsigned int count) 1645 { 1646 struct eg20t_port *priv; 1647 unsigned long flags; 1648 int priv_locked = 1; 1649 int port_locked = 1; 1650 u8 ier; 1651 1652 priv = pch_uart_ports[co->index]; 1653 1654 touch_nmi_watchdog(); 1655 1656 local_irq_save(flags); 1657 if (priv->port.sysrq) { 1658 /* call to uart_handle_sysrq_char already took the priv lock */ 1659 priv_locked = 0; 1660 /* serial8250_handle_port() already took the port lock */ 1661 port_locked = 0; 1662 } else if (oops_in_progress) { 1663 priv_locked = spin_trylock(&priv->lock); 1664 port_locked = spin_trylock(&priv->port.lock); 1665 } else { 1666 spin_lock(&priv->lock); 1667 spin_lock(&priv->port.lock); 1668 } 1669 1670 /* 1671 * First save the IER then disable the interrupts 1672 */ 1673 ier = ioread8(priv->membase + UART_IER); 1674 1675 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT); 1676 1677 uart_console_write(&priv->port, s, count, pch_console_putchar); 1678 1679 /* 1680 * Finally, wait for transmitter to become empty 1681 * and restore the IER 1682 */ 1683 wait_for_xmitr(priv, BOTH_EMPTY); 1684 iowrite8(ier, priv->membase + UART_IER); 1685 1686 if (port_locked) 1687 spin_unlock(&priv->port.lock); 1688 if (priv_locked) 1689 spin_unlock(&priv->lock); 1690 local_irq_restore(flags); 1691 } 1692 1693 static int __init pch_console_setup(struct console *co, char *options) 1694 { 1695 struct uart_port *port; 1696 int baud = default_baud; 1697 int bits = 8; 1698 int parity = 'n'; 1699 int flow = 'n'; 1700 1701 /* 1702 * Check whether an invalid uart number has been specified, and 1703 * if so, search for the first available port that does have 1704 * console support. 1705 */ 1706 if (co->index >= PCH_UART_NR) 1707 co->index = 0; 1708 port = &pch_uart_ports[co->index]->port; 1709 1710 if (!port || (!port->iobase && !port->membase)) 1711 return -ENODEV; 1712 1713 port->uartclk = pch_uart_get_uartclk(); 1714 1715 if (options) 1716 uart_parse_options(options, &baud, &parity, &bits, &flow); 1717 1718 return uart_set_options(port, co, baud, parity, bits, flow); 1719 } 1720 1721 static struct uart_driver pch_uart_driver; 1722 1723 static struct console pch_console = { 1724 .name = PCH_UART_DRIVER_DEVICE, 1725 .write = pch_console_write, 1726 .device = uart_console_device, 1727 .setup = pch_console_setup, 1728 .flags = CON_PRINTBUFFER | CON_ANYTIME, 1729 .index = -1, 1730 .data = &pch_uart_driver, 1731 }; 1732 1733 #define PCH_CONSOLE (&pch_console) 1734 #else 1735 #define PCH_CONSOLE NULL 1736 #endif /* CONFIG_SERIAL_PCH_UART_CONSOLE */ 1737 1738 static struct uart_driver pch_uart_driver = { 1739 .owner = THIS_MODULE, 1740 .driver_name = KBUILD_MODNAME, 1741 .dev_name = PCH_UART_DRIVER_DEVICE, 1742 .major = 0, 1743 .minor = 0, 1744 .nr = PCH_UART_NR, 1745 .cons = PCH_CONSOLE, 1746 }; 1747 1748 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev, 1749 const struct pci_device_id *id) 1750 { 1751 struct eg20t_port *priv; 1752 int ret; 1753 unsigned int iobase; 1754 unsigned int mapbase; 1755 unsigned char *rxbuf; 1756 int fifosize; 1757 int port_type; 1758 struct pch_uart_driver_data *board; 1759 #ifdef CONFIG_DEBUG_FS 1760 char name[32]; /* for debugfs file name */ 1761 #endif 1762 1763 board = &drv_dat[id->driver_data]; 1764 port_type = board->port_type; 1765 1766 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL); 1767 if (priv == NULL) 1768 goto init_port_alloc_err; 1769 1770 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 1771 if (!rxbuf) 1772 goto init_port_free_txbuf; 1773 1774 switch (port_type) { 1775 case PORT_PCH_8LINE: 1776 fifosize = 256; /* EG20T/ML7213: UART0 */ 1777 break; 1778 case PORT_PCH_2LINE: 1779 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/ 1780 break; 1781 default: 1782 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type); 1783 goto init_port_hal_free; 1784 } 1785 1786 pci_enable_msi(pdev); 1787 pci_set_master(pdev); 1788 1789 spin_lock_init(&priv->lock); 1790 1791 iobase = pci_resource_start(pdev, 0); 1792 mapbase = pci_resource_start(pdev, 1); 1793 priv->mapbase = mapbase; 1794 priv->iobase = iobase; 1795 priv->pdev = pdev; 1796 priv->tx_empty = 1; 1797 priv->rxbuf.buf = rxbuf; 1798 priv->rxbuf.size = PAGE_SIZE; 1799 1800 priv->fifo_size = fifosize; 1801 priv->uartclk = pch_uart_get_uartclk(); 1802 priv->port_type = port_type; 1803 priv->port.dev = &pdev->dev; 1804 priv->port.iobase = iobase; 1805 priv->port.membase = NULL; 1806 priv->port.mapbase = mapbase; 1807 priv->port.irq = pdev->irq; 1808 priv->port.iotype = UPIO_PORT; 1809 priv->port.ops = &pch_uart_ops; 1810 priv->port.flags = UPF_BOOT_AUTOCONF; 1811 priv->port.fifosize = fifosize; 1812 priv->port.line = board->line_no; 1813 priv->trigger = PCH_UART_HAL_TRIGGER_M; 1814 1815 snprintf(priv->irq_name, IRQ_NAME_SIZE, 1816 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d", 1817 priv->port.line); 1818 1819 spin_lock_init(&priv->port.lock); 1820 1821 pci_set_drvdata(pdev, priv); 1822 priv->trigger_level = 1; 1823 priv->fcr = 0; 1824 1825 if (pdev->dev.of_node) 1826 of_property_read_u32(pdev->dev.of_node, "clock-frequency" 1827 , &user_uartclk); 1828 1829 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1830 pch_uart_ports[board->line_no] = priv; 1831 #endif 1832 ret = uart_add_one_port(&pch_uart_driver, &priv->port); 1833 if (ret < 0) 1834 goto init_port_hal_free; 1835 1836 #ifdef CONFIG_DEBUG_FS 1837 snprintf(name, sizeof(name), "uart%d_regs", board->line_no); 1838 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO, 1839 NULL, priv, &port_regs_ops); 1840 #endif 1841 1842 return priv; 1843 1844 init_port_hal_free: 1845 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1846 pch_uart_ports[board->line_no] = NULL; 1847 #endif 1848 free_page((unsigned long)rxbuf); 1849 init_port_free_txbuf: 1850 kfree(priv); 1851 init_port_alloc_err: 1852 1853 return NULL; 1854 } 1855 1856 static void pch_uart_exit_port(struct eg20t_port *priv) 1857 { 1858 1859 #ifdef CONFIG_DEBUG_FS 1860 debugfs_remove(priv->debugfs); 1861 #endif 1862 uart_remove_one_port(&pch_uart_driver, &priv->port); 1863 free_page((unsigned long)priv->rxbuf.buf); 1864 } 1865 1866 static void pch_uart_pci_remove(struct pci_dev *pdev) 1867 { 1868 struct eg20t_port *priv = pci_get_drvdata(pdev); 1869 1870 pci_disable_msi(pdev); 1871 1872 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE 1873 pch_uart_ports[priv->port.line] = NULL; 1874 #endif 1875 pch_uart_exit_port(priv); 1876 pci_disable_device(pdev); 1877 kfree(priv); 1878 return; 1879 } 1880 #ifdef CONFIG_PM 1881 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1882 { 1883 struct eg20t_port *priv = pci_get_drvdata(pdev); 1884 1885 uart_suspend_port(&pch_uart_driver, &priv->port); 1886 1887 pci_save_state(pdev); 1888 pci_set_power_state(pdev, pci_choose_state(pdev, state)); 1889 return 0; 1890 } 1891 1892 static int pch_uart_pci_resume(struct pci_dev *pdev) 1893 { 1894 struct eg20t_port *priv = pci_get_drvdata(pdev); 1895 int ret; 1896 1897 pci_set_power_state(pdev, PCI_D0); 1898 pci_restore_state(pdev); 1899 1900 ret = pci_enable_device(pdev); 1901 if (ret) { 1902 dev_err(&pdev->dev, 1903 "%s-pci_enable_device failed(ret=%d) ", __func__, ret); 1904 return ret; 1905 } 1906 1907 uart_resume_port(&pch_uart_driver, &priv->port); 1908 1909 return 0; 1910 } 1911 #else 1912 #define pch_uart_pci_suspend NULL 1913 #define pch_uart_pci_resume NULL 1914 #endif 1915 1916 static const struct pci_device_id pch_uart_pci_id[] = { 1917 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811), 1918 .driver_data = pch_et20t_uart0}, 1919 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812), 1920 .driver_data = pch_et20t_uart1}, 1921 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813), 1922 .driver_data = pch_et20t_uart2}, 1923 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814), 1924 .driver_data = pch_et20t_uart3}, 1925 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027), 1926 .driver_data = pch_ml7213_uart0}, 1927 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028), 1928 .driver_data = pch_ml7213_uart1}, 1929 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029), 1930 .driver_data = pch_ml7213_uart2}, 1931 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C), 1932 .driver_data = pch_ml7223_uart0}, 1933 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D), 1934 .driver_data = pch_ml7223_uart1}, 1935 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811), 1936 .driver_data = pch_ml7831_uart0}, 1937 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812), 1938 .driver_data = pch_ml7831_uart1}, 1939 {0,}, 1940 }; 1941 1942 static int pch_uart_pci_probe(struct pci_dev *pdev, 1943 const struct pci_device_id *id) 1944 { 1945 int ret; 1946 struct eg20t_port *priv; 1947 1948 ret = pci_enable_device(pdev); 1949 if (ret < 0) 1950 goto probe_error; 1951 1952 priv = pch_uart_init_port(pdev, id); 1953 if (!priv) { 1954 ret = -EBUSY; 1955 goto probe_disable_device; 1956 } 1957 pci_set_drvdata(pdev, priv); 1958 1959 return ret; 1960 1961 probe_disable_device: 1962 pci_disable_msi(pdev); 1963 pci_disable_device(pdev); 1964 probe_error: 1965 return ret; 1966 } 1967 1968 static struct pci_driver pch_uart_pci_driver = { 1969 .name = "pch_uart", 1970 .id_table = pch_uart_pci_id, 1971 .probe = pch_uart_pci_probe, 1972 .remove = pch_uart_pci_remove, 1973 .suspend = pch_uart_pci_suspend, 1974 .resume = pch_uart_pci_resume, 1975 }; 1976 1977 static int __init pch_uart_module_init(void) 1978 { 1979 int ret; 1980 1981 /* register as UART driver */ 1982 ret = uart_register_driver(&pch_uart_driver); 1983 if (ret < 0) 1984 return ret; 1985 1986 /* register as PCI driver */ 1987 ret = pci_register_driver(&pch_uart_pci_driver); 1988 if (ret < 0) 1989 uart_unregister_driver(&pch_uart_driver); 1990 1991 return ret; 1992 } 1993 module_init(pch_uart_module_init); 1994 1995 static void __exit pch_uart_module_exit(void) 1996 { 1997 pci_unregister_driver(&pch_uart_pci_driver); 1998 uart_unregister_driver(&pch_uart_driver); 1999 } 2000 module_exit(pch_uart_module_exit); 2001 2002 MODULE_LICENSE("GPL v2"); 2003 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver"); 2004 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id); 2005 2006 module_param(default_baud, uint, S_IRUGO); 2007 MODULE_PARM_DESC(default_baud, 2008 "Default BAUD for initial driver state and console (default 9600)"); 2009 module_param(user_uartclk, uint, S_IRUGO); 2010 MODULE_PARM_DESC(user_uartclk, 2011 "Override UART default or board specific UART clock"); 2012