xref: /openbmc/linux/drivers/tty/serial/pch_uart.c (revision 4da722ca)
1 /*
2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3  *
4  *This program is free software; you can redistribute it and/or modify
5  *it under the terms of the GNU General Public License as published by
6  *the Free Software Foundation; version 2 of the License.
7  *
8  *This program is distributed in the hope that it will be useful,
9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  *GNU General Public License for more details.
12  *
13  *You should have received a copy of the GNU General Public License
14  *along with this program; if not, write to the Free Software
15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
16  */
17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18 #define SUPPORT_SYSRQ
19 #endif
20 #include <linux/kernel.h>
21 #include <linux/serial_reg.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/pci.h>
25 #include <linux/console.h>
26 #include <linux/serial_core.h>
27 #include <linux/tty.h>
28 #include <linux/tty_flip.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/dmi.h>
32 #include <linux/nmi.h>
33 #include <linux/delay.h>
34 #include <linux/of.h>
35 
36 #include <linux/debugfs.h>
37 #include <linux/dmaengine.h>
38 #include <linux/pch_dma.h>
39 
40 enum {
41 	PCH_UART_HANDLED_RX_INT_SHIFT,
42 	PCH_UART_HANDLED_TX_INT_SHIFT,
43 	PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
44 	PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
45 	PCH_UART_HANDLED_MS_INT_SHIFT,
46 	PCH_UART_HANDLED_LS_INT_SHIFT,
47 };
48 
49 enum {
50 	PCH_UART_8LINE,
51 	PCH_UART_2LINE,
52 };
53 
54 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
55 
56 /* Set the max number of UART port
57  * Intel EG20T PCH: 4 port
58  * LAPIS Semiconductor ML7213 IOH: 3 port
59  * LAPIS Semiconductor ML7223 IOH: 2 port
60 */
61 #define PCH_UART_NR	4
62 
63 #define PCH_UART_HANDLED_RX_INT	(1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_TX_INT	(1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
65 #define PCH_UART_HANDLED_RX_ERR_INT	(1<<((\
66 					PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
67 #define PCH_UART_HANDLED_RX_TRG_INT	(1<<((\
68 					PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
69 #define PCH_UART_HANDLED_MS_INT	(1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
70 
71 #define PCH_UART_HANDLED_LS_INT	(1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
72 
73 #define PCH_UART_RBR		0x00
74 #define PCH_UART_THR		0x00
75 
76 #define PCH_UART_IER_MASK	(PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
77 				PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
78 #define PCH_UART_IER_ERBFI	0x00000001
79 #define PCH_UART_IER_ETBEI	0x00000002
80 #define PCH_UART_IER_ELSI	0x00000004
81 #define PCH_UART_IER_EDSSI	0x00000008
82 
83 #define PCH_UART_IIR_IP			0x00000001
84 #define PCH_UART_IIR_IID		0x00000006
85 #define PCH_UART_IIR_MSI		0x00000000
86 #define PCH_UART_IIR_TRI		0x00000002
87 #define PCH_UART_IIR_RRI		0x00000004
88 #define PCH_UART_IIR_REI		0x00000006
89 #define PCH_UART_IIR_TOI		0x00000008
90 #define PCH_UART_IIR_FIFO256		0x00000020
91 #define PCH_UART_IIR_FIFO64		PCH_UART_IIR_FIFO256
92 #define PCH_UART_IIR_FE			0x000000C0
93 
94 #define PCH_UART_FCR_FIFOE		0x00000001
95 #define PCH_UART_FCR_RFR		0x00000002
96 #define PCH_UART_FCR_TFR		0x00000004
97 #define PCH_UART_FCR_DMS		0x00000008
98 #define PCH_UART_FCR_FIFO256		0x00000020
99 #define PCH_UART_FCR_RFTL		0x000000C0
100 
101 #define PCH_UART_FCR_RFTL1		0x00000000
102 #define PCH_UART_FCR_RFTL64		0x00000040
103 #define PCH_UART_FCR_RFTL128		0x00000080
104 #define PCH_UART_FCR_RFTL224		0x000000C0
105 #define PCH_UART_FCR_RFTL16		PCH_UART_FCR_RFTL64
106 #define PCH_UART_FCR_RFTL32		PCH_UART_FCR_RFTL128
107 #define PCH_UART_FCR_RFTL56		PCH_UART_FCR_RFTL224
108 #define PCH_UART_FCR_RFTL4		PCH_UART_FCR_RFTL64
109 #define PCH_UART_FCR_RFTL8		PCH_UART_FCR_RFTL128
110 #define PCH_UART_FCR_RFTL14		PCH_UART_FCR_RFTL224
111 #define PCH_UART_FCR_RFTL_SHIFT		6
112 
113 #define PCH_UART_LCR_WLS	0x00000003
114 #define PCH_UART_LCR_STB	0x00000004
115 #define PCH_UART_LCR_PEN	0x00000008
116 #define PCH_UART_LCR_EPS	0x00000010
117 #define PCH_UART_LCR_SP		0x00000020
118 #define PCH_UART_LCR_SB		0x00000040
119 #define PCH_UART_LCR_DLAB	0x00000080
120 #define PCH_UART_LCR_NP		0x00000000
121 #define PCH_UART_LCR_OP		PCH_UART_LCR_PEN
122 #define PCH_UART_LCR_EP		(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
123 #define PCH_UART_LCR_1P		(PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
124 #define PCH_UART_LCR_0P		(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
125 				PCH_UART_LCR_SP)
126 
127 #define PCH_UART_LCR_5BIT	0x00000000
128 #define PCH_UART_LCR_6BIT	0x00000001
129 #define PCH_UART_LCR_7BIT	0x00000002
130 #define PCH_UART_LCR_8BIT	0x00000003
131 
132 #define PCH_UART_MCR_DTR	0x00000001
133 #define PCH_UART_MCR_RTS	0x00000002
134 #define PCH_UART_MCR_OUT	0x0000000C
135 #define PCH_UART_MCR_LOOP	0x00000010
136 #define PCH_UART_MCR_AFE	0x00000020
137 
138 #define PCH_UART_LSR_DR		0x00000001
139 #define PCH_UART_LSR_ERR	(1<<7)
140 
141 #define PCH_UART_MSR_DCTS	0x00000001
142 #define PCH_UART_MSR_DDSR	0x00000002
143 #define PCH_UART_MSR_TERI	0x00000004
144 #define PCH_UART_MSR_DDCD	0x00000008
145 #define PCH_UART_MSR_CTS	0x00000010
146 #define PCH_UART_MSR_DSR	0x00000020
147 #define PCH_UART_MSR_RI		0x00000040
148 #define PCH_UART_MSR_DCD	0x00000080
149 #define PCH_UART_MSR_DELTA	(PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
150 				PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
151 
152 #define PCH_UART_DLL		0x00
153 #define PCH_UART_DLM		0x01
154 
155 #define PCH_UART_BRCSR		0x0E
156 
157 #define PCH_UART_IID_RLS	(PCH_UART_IIR_REI)
158 #define PCH_UART_IID_RDR	(PCH_UART_IIR_RRI)
159 #define PCH_UART_IID_RDR_TO	(PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
160 #define PCH_UART_IID_THRE	(PCH_UART_IIR_TRI)
161 #define PCH_UART_IID_MS		(PCH_UART_IIR_MSI)
162 
163 #define PCH_UART_HAL_PARITY_NONE	(PCH_UART_LCR_NP)
164 #define PCH_UART_HAL_PARITY_ODD		(PCH_UART_LCR_OP)
165 #define PCH_UART_HAL_PARITY_EVEN	(PCH_UART_LCR_EP)
166 #define PCH_UART_HAL_PARITY_FIX1	(PCH_UART_LCR_1P)
167 #define PCH_UART_HAL_PARITY_FIX0	(PCH_UART_LCR_0P)
168 #define PCH_UART_HAL_5BIT		(PCH_UART_LCR_5BIT)
169 #define PCH_UART_HAL_6BIT		(PCH_UART_LCR_6BIT)
170 #define PCH_UART_HAL_7BIT		(PCH_UART_LCR_7BIT)
171 #define PCH_UART_HAL_8BIT		(PCH_UART_LCR_8BIT)
172 #define PCH_UART_HAL_STB1		0
173 #define PCH_UART_HAL_STB2		(PCH_UART_LCR_STB)
174 
175 #define PCH_UART_HAL_CLR_TX_FIFO	(PCH_UART_FCR_TFR)
176 #define PCH_UART_HAL_CLR_RX_FIFO	(PCH_UART_FCR_RFR)
177 #define PCH_UART_HAL_CLR_ALL_FIFO	(PCH_UART_HAL_CLR_TX_FIFO | \
178 					PCH_UART_HAL_CLR_RX_FIFO)
179 
180 #define PCH_UART_HAL_DMA_MODE0		0
181 #define PCH_UART_HAL_FIFO_DIS		0
182 #define PCH_UART_HAL_FIFO16		(PCH_UART_FCR_FIFOE)
183 #define PCH_UART_HAL_FIFO256		(PCH_UART_FCR_FIFOE | \
184 					PCH_UART_FCR_FIFO256)
185 #define PCH_UART_HAL_FIFO64		(PCH_UART_HAL_FIFO256)
186 #define PCH_UART_HAL_TRIGGER1		(PCH_UART_FCR_RFTL1)
187 #define PCH_UART_HAL_TRIGGER64		(PCH_UART_FCR_RFTL64)
188 #define PCH_UART_HAL_TRIGGER128		(PCH_UART_FCR_RFTL128)
189 #define PCH_UART_HAL_TRIGGER224		(PCH_UART_FCR_RFTL224)
190 #define PCH_UART_HAL_TRIGGER16		(PCH_UART_FCR_RFTL16)
191 #define PCH_UART_HAL_TRIGGER32		(PCH_UART_FCR_RFTL32)
192 #define PCH_UART_HAL_TRIGGER56		(PCH_UART_FCR_RFTL56)
193 #define PCH_UART_HAL_TRIGGER4		(PCH_UART_FCR_RFTL4)
194 #define PCH_UART_HAL_TRIGGER8		(PCH_UART_FCR_RFTL8)
195 #define PCH_UART_HAL_TRIGGER14		(PCH_UART_FCR_RFTL14)
196 #define PCH_UART_HAL_TRIGGER_L		(PCH_UART_FCR_RFTL64)
197 #define PCH_UART_HAL_TRIGGER_M		(PCH_UART_FCR_RFTL128)
198 #define PCH_UART_HAL_TRIGGER_H		(PCH_UART_FCR_RFTL224)
199 
200 #define PCH_UART_HAL_RX_INT		(PCH_UART_IER_ERBFI)
201 #define PCH_UART_HAL_TX_INT		(PCH_UART_IER_ETBEI)
202 #define PCH_UART_HAL_RX_ERR_INT		(PCH_UART_IER_ELSI)
203 #define PCH_UART_HAL_MS_INT		(PCH_UART_IER_EDSSI)
204 #define PCH_UART_HAL_ALL_INT		(PCH_UART_IER_MASK)
205 
206 #define PCH_UART_HAL_DTR		(PCH_UART_MCR_DTR)
207 #define PCH_UART_HAL_RTS		(PCH_UART_MCR_RTS)
208 #define PCH_UART_HAL_OUT		(PCH_UART_MCR_OUT)
209 #define PCH_UART_HAL_LOOP		(PCH_UART_MCR_LOOP)
210 #define PCH_UART_HAL_AFE		(PCH_UART_MCR_AFE)
211 
212 #define PCI_VENDOR_ID_ROHM		0x10DB
213 
214 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
215 
216 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
217 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
218 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
219 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
220 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
221 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
222 
223 struct pch_uart_buffer {
224 	unsigned char *buf;
225 	int size;
226 };
227 
228 struct eg20t_port {
229 	struct uart_port port;
230 	int port_type;
231 	void __iomem *membase;
232 	resource_size_t mapbase;
233 	unsigned int iobase;
234 	struct pci_dev *pdev;
235 	int fifo_size;
236 	unsigned int uartclk;
237 	int start_tx;
238 	int start_rx;
239 	int tx_empty;
240 	int trigger;
241 	int trigger_level;
242 	struct pch_uart_buffer rxbuf;
243 	unsigned int dmsr;
244 	unsigned int fcr;
245 	unsigned int mcr;
246 	unsigned int use_dma;
247 	struct dma_async_tx_descriptor	*desc_tx;
248 	struct dma_async_tx_descriptor	*desc_rx;
249 	struct pch_dma_slave		param_tx;
250 	struct pch_dma_slave		param_rx;
251 	struct dma_chan			*chan_tx;
252 	struct dma_chan			*chan_rx;
253 	struct scatterlist		*sg_tx_p;
254 	int				nent;
255 	struct scatterlist		sg_rx;
256 	int				tx_dma_use;
257 	void				*rx_buf_virt;
258 	dma_addr_t			rx_buf_dma;
259 
260 	struct dentry	*debugfs;
261 #define IRQ_NAME_SIZE 17
262 	char				irq_name[IRQ_NAME_SIZE];
263 
264 	/* protect the eg20t_port private structure and io access to membase */
265 	spinlock_t lock;
266 };
267 
268 /**
269  * struct pch_uart_driver_data - private data structure for UART-DMA
270  * @port_type:			The number of DMA channel
271  * @line_no:			UART port line number (0, 1, 2...)
272  */
273 struct pch_uart_driver_data {
274 	int port_type;
275 	int line_no;
276 };
277 
278 enum pch_uart_num_t {
279 	pch_et20t_uart0 = 0,
280 	pch_et20t_uart1,
281 	pch_et20t_uart2,
282 	pch_et20t_uart3,
283 	pch_ml7213_uart0,
284 	pch_ml7213_uart1,
285 	pch_ml7213_uart2,
286 	pch_ml7223_uart0,
287 	pch_ml7223_uart1,
288 	pch_ml7831_uart0,
289 	pch_ml7831_uart1,
290 };
291 
292 static struct pch_uart_driver_data drv_dat[] = {
293 	[pch_et20t_uart0] = {PCH_UART_8LINE, 0},
294 	[pch_et20t_uart1] = {PCH_UART_2LINE, 1},
295 	[pch_et20t_uart2] = {PCH_UART_2LINE, 2},
296 	[pch_et20t_uart3] = {PCH_UART_2LINE, 3},
297 	[pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
298 	[pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
299 	[pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
300 	[pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
301 	[pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
302 	[pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
303 	[pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
304 };
305 
306 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
307 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
308 #endif
309 static unsigned int default_baud = 9600;
310 static unsigned int user_uartclk = 0;
311 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
312 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
313 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
314 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
315 
316 #ifdef CONFIG_DEBUG_FS
317 
318 #define PCH_REGS_BUFSIZE	1024
319 
320 
321 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
322 				size_t count, loff_t *ppos)
323 {
324 	struct eg20t_port *priv = file->private_data;
325 	char *buf;
326 	u32 len = 0;
327 	ssize_t ret;
328 	unsigned char lcr;
329 
330 	buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
331 	if (!buf)
332 		return 0;
333 
334 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 			"PCH EG20T port[%d] regs:\n", priv->port.line);
336 
337 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
338 			"=================================\n");
339 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
340 			"IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
341 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
342 			"IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
343 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
344 			"LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
345 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
346 			"MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
347 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
348 			"LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
349 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
350 			"MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
351 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
352 			"BRCSR: \t0x%02x\n",
353 			ioread8(priv->membase + PCH_UART_BRCSR));
354 
355 	lcr = ioread8(priv->membase + UART_LCR);
356 	iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
357 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
358 			"DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
359 	len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
360 			"DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
361 	iowrite8(lcr, priv->membase + UART_LCR);
362 
363 	if (len > PCH_REGS_BUFSIZE)
364 		len = PCH_REGS_BUFSIZE;
365 
366 	ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
367 	kfree(buf);
368 	return ret;
369 }
370 
371 static const struct file_operations port_regs_ops = {
372 	.owner		= THIS_MODULE,
373 	.open		= simple_open,
374 	.read		= port_show_regs,
375 	.llseek		= default_llseek,
376 };
377 #endif	/* CONFIG_DEBUG_FS */
378 
379 static struct dmi_system_id pch_uart_dmi_table[] = {
380 	{
381 		.ident = "CM-iTC",
382 		{
383 			DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
384 		},
385 		(void *)CMITC_UARTCLK,
386 	},
387 	{
388 		.ident = "FRI2",
389 		{
390 			DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
391 		},
392 		(void *)FRI2_64_UARTCLK,
393 	},
394 	{
395 		.ident = "Fish River Island II",
396 		{
397 			DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
398 		},
399 		(void *)FRI2_48_UARTCLK,
400 	},
401 	{
402 		.ident = "COMe-mTT",
403 		{
404 			DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
405 		},
406 		(void *)NTC1_UARTCLK,
407 	},
408 	{
409 		.ident = "nanoETXexpress-TT",
410 		{
411 			DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
412 		},
413 		(void *)NTC1_UARTCLK,
414 	},
415 	{
416 		.ident = "MinnowBoard",
417 		{
418 			DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
419 		},
420 		(void *)MINNOW_UARTCLK,
421 	},
422 	{ }
423 };
424 
425 /* Return UART clock, checking for board specific clocks. */
426 static unsigned int pch_uart_get_uartclk(void)
427 {
428 	const struct dmi_system_id *d;
429 
430 	if (user_uartclk)
431 		return user_uartclk;
432 
433 	d = dmi_first_match(pch_uart_dmi_table);
434 	if (d)
435 		return (unsigned long)d->driver_data;
436 
437 	return DEFAULT_UARTCLK;
438 }
439 
440 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
441 					  unsigned int flag)
442 {
443 	u8 ier = ioread8(priv->membase + UART_IER);
444 	ier |= flag & PCH_UART_IER_MASK;
445 	iowrite8(ier, priv->membase + UART_IER);
446 }
447 
448 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
449 					   unsigned int flag)
450 {
451 	u8 ier = ioread8(priv->membase + UART_IER);
452 	ier &= ~(flag & PCH_UART_IER_MASK);
453 	iowrite8(ier, priv->membase + UART_IER);
454 }
455 
456 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
457 				 unsigned int parity, unsigned int bits,
458 				 unsigned int stb)
459 {
460 	unsigned int dll, dlm, lcr;
461 	int div;
462 
463 	div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
464 	if (div < 0 || USHRT_MAX <= div) {
465 		dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
466 		return -EINVAL;
467 	}
468 
469 	dll = (unsigned int)div & 0x00FFU;
470 	dlm = ((unsigned int)div >> 8) & 0x00FFU;
471 
472 	if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
473 		dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
474 		return -EINVAL;
475 	}
476 
477 	if (bits & ~PCH_UART_LCR_WLS) {
478 		dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
479 		return -EINVAL;
480 	}
481 
482 	if (stb & ~PCH_UART_LCR_STB) {
483 		dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
484 		return -EINVAL;
485 	}
486 
487 	lcr = parity;
488 	lcr |= bits;
489 	lcr |= stb;
490 
491 	dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
492 		 __func__, baud, div, lcr, jiffies);
493 	iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
494 	iowrite8(dll, priv->membase + PCH_UART_DLL);
495 	iowrite8(dlm, priv->membase + PCH_UART_DLM);
496 	iowrite8(lcr, priv->membase + UART_LCR);
497 
498 	return 0;
499 }
500 
501 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
502 				    unsigned int flag)
503 {
504 	if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
505 		dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
506 			__func__, flag);
507 		return -EINVAL;
508 	}
509 
510 	iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
511 	iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
512 		 priv->membase + UART_FCR);
513 	iowrite8(priv->fcr, priv->membase + UART_FCR);
514 
515 	return 0;
516 }
517 
518 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
519 				 unsigned int dmamode,
520 				 unsigned int fifo_size, unsigned int trigger)
521 {
522 	u8 fcr;
523 
524 	if (dmamode & ~PCH_UART_FCR_DMS) {
525 		dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
526 			__func__, dmamode);
527 		return -EINVAL;
528 	}
529 
530 	if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
531 		dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
532 			__func__, fifo_size);
533 		return -EINVAL;
534 	}
535 
536 	if (trigger & ~PCH_UART_FCR_RFTL) {
537 		dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
538 			__func__, trigger);
539 		return -EINVAL;
540 	}
541 
542 	switch (priv->fifo_size) {
543 	case 256:
544 		priv->trigger_level =
545 		    trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
546 		break;
547 	case 64:
548 		priv->trigger_level =
549 		    trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
550 		break;
551 	case 16:
552 		priv->trigger_level =
553 		    trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
554 		break;
555 	default:
556 		priv->trigger_level =
557 		    trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
558 		break;
559 	}
560 	fcr =
561 	    dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
562 	iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
563 	iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
564 		 priv->membase + UART_FCR);
565 	iowrite8(fcr, priv->membase + UART_FCR);
566 	priv->fcr = fcr;
567 
568 	return 0;
569 }
570 
571 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
572 {
573 	unsigned int msr = ioread8(priv->membase + UART_MSR);
574 	priv->dmsr = msr & PCH_UART_MSR_DELTA;
575 	return (u8)msr;
576 }
577 
578 static void pch_uart_hal_write(struct eg20t_port *priv,
579 			      const unsigned char *buf, int tx_size)
580 {
581 	int i;
582 	unsigned int thr;
583 
584 	for (i = 0; i < tx_size;) {
585 		thr = buf[i++];
586 		iowrite8(thr, priv->membase + PCH_UART_THR);
587 	}
588 }
589 
590 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
591 			     int rx_size)
592 {
593 	int i;
594 	u8 rbr, lsr;
595 	struct uart_port *port = &priv->port;
596 
597 	lsr = ioread8(priv->membase + UART_LSR);
598 	for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
599 	     i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
600 	     lsr = ioread8(priv->membase + UART_LSR)) {
601 		rbr = ioread8(priv->membase + PCH_UART_RBR);
602 
603 		if (lsr & UART_LSR_BI) {
604 			port->icount.brk++;
605 			if (uart_handle_break(port))
606 				continue;
607 		}
608 #ifdef SUPPORT_SYSRQ
609 		if (port->sysrq) {
610 			if (uart_handle_sysrq_char(port, rbr))
611 				continue;
612 		}
613 #endif
614 
615 		buf[i++] = rbr;
616 	}
617 	return i;
618 }
619 
620 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
621 {
622 	return ioread8(priv->membase + UART_IIR) &\
623 		      (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
624 }
625 
626 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
627 {
628 	return ioread8(priv->membase + UART_LSR);
629 }
630 
631 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
632 {
633 	unsigned int lcr;
634 
635 	lcr = ioread8(priv->membase + UART_LCR);
636 	if (on)
637 		lcr |= PCH_UART_LCR_SB;
638 	else
639 		lcr &= ~PCH_UART_LCR_SB;
640 
641 	iowrite8(lcr, priv->membase + UART_LCR);
642 }
643 
644 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
645 		   int size)
646 {
647 	struct uart_port *port = &priv->port;
648 	struct tty_port *tport = &port->state->port;
649 
650 	tty_insert_flip_string(tport, buf, size);
651 	tty_flip_buffer_push(tport);
652 
653 	return 0;
654 }
655 
656 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
657 {
658 	int ret = 0;
659 	struct uart_port *port = &priv->port;
660 
661 	if (port->x_char) {
662 		dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
663 			__func__, port->x_char, jiffies);
664 		buf[0] = port->x_char;
665 		port->x_char = 0;
666 		ret = 1;
667 	}
668 
669 	return ret;
670 }
671 
672 static int dma_push_rx(struct eg20t_port *priv, int size)
673 {
674 	int room;
675 	struct uart_port *port = &priv->port;
676 	struct tty_port *tport = &port->state->port;
677 
678 	room = tty_buffer_request_room(tport, size);
679 
680 	if (room < size)
681 		dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
682 			 size - room);
683 	if (!room)
684 		return 0;
685 
686 	tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
687 
688 	port->icount.rx += room;
689 
690 	return room;
691 }
692 
693 static void pch_free_dma(struct uart_port *port)
694 {
695 	struct eg20t_port *priv;
696 	priv = container_of(port, struct eg20t_port, port);
697 
698 	if (priv->chan_tx) {
699 		dma_release_channel(priv->chan_tx);
700 		priv->chan_tx = NULL;
701 	}
702 	if (priv->chan_rx) {
703 		dma_release_channel(priv->chan_rx);
704 		priv->chan_rx = NULL;
705 	}
706 
707 	if (priv->rx_buf_dma) {
708 		dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
709 				  priv->rx_buf_dma);
710 		priv->rx_buf_virt = NULL;
711 		priv->rx_buf_dma = 0;
712 	}
713 
714 	return;
715 }
716 
717 static bool filter(struct dma_chan *chan, void *slave)
718 {
719 	struct pch_dma_slave *param = slave;
720 
721 	if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
722 						  chan->device->dev)) {
723 		chan->private = param;
724 		return true;
725 	} else {
726 		return false;
727 	}
728 }
729 
730 static void pch_request_dma(struct uart_port *port)
731 {
732 	dma_cap_mask_t mask;
733 	struct dma_chan *chan;
734 	struct pci_dev *dma_dev;
735 	struct pch_dma_slave *param;
736 	struct eg20t_port *priv =
737 				container_of(port, struct eg20t_port, port);
738 	dma_cap_zero(mask);
739 	dma_cap_set(DMA_SLAVE, mask);
740 
741 	/* Get DMA's dev information */
742 	dma_dev = pci_get_slot(priv->pdev->bus,
743 			PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
744 
745 	/* Set Tx DMA */
746 	param = &priv->param_tx;
747 	param->dma_dev = &dma_dev->dev;
748 	param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
749 
750 	param->tx_reg = port->mapbase + UART_TX;
751 	chan = dma_request_channel(mask, filter, param);
752 	if (!chan) {
753 		dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
754 			__func__);
755 		return;
756 	}
757 	priv->chan_tx = chan;
758 
759 	/* Set Rx DMA */
760 	param = &priv->param_rx;
761 	param->dma_dev = &dma_dev->dev;
762 	param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
763 
764 	param->rx_reg = port->mapbase + UART_RX;
765 	chan = dma_request_channel(mask, filter, param);
766 	if (!chan) {
767 		dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
768 			__func__);
769 		dma_release_channel(priv->chan_tx);
770 		priv->chan_tx = NULL;
771 		return;
772 	}
773 
774 	/* Get Consistent memory for DMA */
775 	priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
776 				    &priv->rx_buf_dma, GFP_KERNEL);
777 	priv->chan_rx = chan;
778 }
779 
780 static void pch_dma_rx_complete(void *arg)
781 {
782 	struct eg20t_port *priv = arg;
783 	struct uart_port *port = &priv->port;
784 	int count;
785 
786 	dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
787 	count = dma_push_rx(priv, priv->trigger_level);
788 	if (count)
789 		tty_flip_buffer_push(&port->state->port);
790 	async_tx_ack(priv->desc_rx);
791 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
792 					    PCH_UART_HAL_RX_ERR_INT);
793 }
794 
795 static void pch_dma_tx_complete(void *arg)
796 {
797 	struct eg20t_port *priv = arg;
798 	struct uart_port *port = &priv->port;
799 	struct circ_buf *xmit = &port->state->xmit;
800 	struct scatterlist *sg = priv->sg_tx_p;
801 	int i;
802 
803 	for (i = 0; i < priv->nent; i++, sg++) {
804 		xmit->tail += sg_dma_len(sg);
805 		port->icount.tx += sg_dma_len(sg);
806 	}
807 	xmit->tail &= UART_XMIT_SIZE - 1;
808 	async_tx_ack(priv->desc_tx);
809 	dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
810 	priv->tx_dma_use = 0;
811 	priv->nent = 0;
812 	kfree(priv->sg_tx_p);
813 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
814 }
815 
816 static int pop_tx(struct eg20t_port *priv, int size)
817 {
818 	int count = 0;
819 	struct uart_port *port = &priv->port;
820 	struct circ_buf *xmit = &port->state->xmit;
821 
822 	if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
823 		goto pop_tx_end;
824 
825 	do {
826 		int cnt_to_end =
827 		    CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
828 		int sz = min(size - count, cnt_to_end);
829 		pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
830 		xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
831 		count += sz;
832 	} while (!uart_circ_empty(xmit) && count < size);
833 
834 pop_tx_end:
835 	dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
836 		 count, size - count, jiffies);
837 
838 	return count;
839 }
840 
841 static int handle_rx_to(struct eg20t_port *priv)
842 {
843 	struct pch_uart_buffer *buf;
844 	int rx_size;
845 	int ret;
846 	if (!priv->start_rx) {
847 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
848 						     PCH_UART_HAL_RX_ERR_INT);
849 		return 0;
850 	}
851 	buf = &priv->rxbuf;
852 	do {
853 		rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
854 		ret = push_rx(priv, buf->buf, rx_size);
855 		if (ret)
856 			return 0;
857 	} while (rx_size == buf->size);
858 
859 	return PCH_UART_HANDLED_RX_INT;
860 }
861 
862 static int handle_rx(struct eg20t_port *priv)
863 {
864 	return handle_rx_to(priv);
865 }
866 
867 static int dma_handle_rx(struct eg20t_port *priv)
868 {
869 	struct uart_port *port = &priv->port;
870 	struct dma_async_tx_descriptor *desc;
871 	struct scatterlist *sg;
872 
873 	priv = container_of(port, struct eg20t_port, port);
874 	sg = &priv->sg_rx;
875 
876 	sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
877 
878 	sg_dma_len(sg) = priv->trigger_level;
879 
880 	sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
881 		     sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
882 
883 	sg_dma_address(sg) = priv->rx_buf_dma;
884 
885 	desc = dmaengine_prep_slave_sg(priv->chan_rx,
886 			sg, 1, DMA_DEV_TO_MEM,
887 			DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
888 
889 	if (!desc)
890 		return 0;
891 
892 	priv->desc_rx = desc;
893 	desc->callback = pch_dma_rx_complete;
894 	desc->callback_param = priv;
895 	desc->tx_submit(desc);
896 	dma_async_issue_pending(priv->chan_rx);
897 
898 	return PCH_UART_HANDLED_RX_INT;
899 }
900 
901 static unsigned int handle_tx(struct eg20t_port *priv)
902 {
903 	struct uart_port *port = &priv->port;
904 	struct circ_buf *xmit = &port->state->xmit;
905 	int fifo_size;
906 	int tx_size;
907 	int size;
908 	int tx_empty;
909 
910 	if (!priv->start_tx) {
911 		dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
912 			__func__, jiffies);
913 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
914 		priv->tx_empty = 1;
915 		return 0;
916 	}
917 
918 	fifo_size = max(priv->fifo_size, 1);
919 	tx_empty = 1;
920 	if (pop_tx_x(priv, xmit->buf)) {
921 		pch_uart_hal_write(priv, xmit->buf, 1);
922 		port->icount.tx++;
923 		tx_empty = 0;
924 		fifo_size--;
925 	}
926 	size = min(xmit->head - xmit->tail, fifo_size);
927 	if (size < 0)
928 		size = fifo_size;
929 
930 	tx_size = pop_tx(priv, size);
931 	if (tx_size > 0) {
932 		port->icount.tx += tx_size;
933 		tx_empty = 0;
934 	}
935 
936 	priv->tx_empty = tx_empty;
937 
938 	if (tx_empty) {
939 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
940 		uart_write_wakeup(port);
941 	}
942 
943 	return PCH_UART_HANDLED_TX_INT;
944 }
945 
946 static unsigned int dma_handle_tx(struct eg20t_port *priv)
947 {
948 	struct uart_port *port = &priv->port;
949 	struct circ_buf *xmit = &port->state->xmit;
950 	struct scatterlist *sg;
951 	int nent;
952 	int fifo_size;
953 	int tx_empty;
954 	struct dma_async_tx_descriptor *desc;
955 	int num;
956 	int i;
957 	int bytes;
958 	int size;
959 	int rem;
960 
961 	if (!priv->start_tx) {
962 		dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
963 			__func__, jiffies);
964 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
965 		priv->tx_empty = 1;
966 		return 0;
967 	}
968 
969 	if (priv->tx_dma_use) {
970 		dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
971 			__func__, jiffies);
972 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
973 		priv->tx_empty = 1;
974 		return 0;
975 	}
976 
977 	fifo_size = max(priv->fifo_size, 1);
978 	tx_empty = 1;
979 	if (pop_tx_x(priv, xmit->buf)) {
980 		pch_uart_hal_write(priv, xmit->buf, 1);
981 		port->icount.tx++;
982 		tx_empty = 0;
983 		fifo_size--;
984 	}
985 
986 	bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
987 			     UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
988 			     xmit->tail, UART_XMIT_SIZE));
989 	if (!bytes) {
990 		dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
991 		pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
992 		uart_write_wakeup(port);
993 		return 0;
994 	}
995 
996 	if (bytes > fifo_size) {
997 		num = bytes / fifo_size + 1;
998 		size = fifo_size;
999 		rem = bytes % fifo_size;
1000 	} else {
1001 		num = 1;
1002 		size = bytes;
1003 		rem = bytes;
1004 	}
1005 
1006 	dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1007 		__func__, num, size, rem);
1008 
1009 	priv->tx_dma_use = 1;
1010 
1011 	priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1012 	if (!priv->sg_tx_p) {
1013 		dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1014 		return 0;
1015 	}
1016 
1017 	sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1018 	sg = priv->sg_tx_p;
1019 
1020 	for (i = 0; i < num; i++, sg++) {
1021 		if (i == (num - 1))
1022 			sg_set_page(sg, virt_to_page(xmit->buf),
1023 				    rem, fifo_size * i);
1024 		else
1025 			sg_set_page(sg, virt_to_page(xmit->buf),
1026 				    size, fifo_size * i);
1027 	}
1028 
1029 	sg = priv->sg_tx_p;
1030 	nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1031 	if (!nent) {
1032 		dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1033 		return 0;
1034 	}
1035 	priv->nent = nent;
1036 
1037 	for (i = 0; i < nent; i++, sg++) {
1038 		sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1039 			      fifo_size * i;
1040 		sg_dma_address(sg) = (sg_dma_address(sg) &
1041 				    ~(UART_XMIT_SIZE - 1)) + sg->offset;
1042 		if (i == (nent - 1))
1043 			sg_dma_len(sg) = rem;
1044 		else
1045 			sg_dma_len(sg) = size;
1046 	}
1047 
1048 	desc = dmaengine_prep_slave_sg(priv->chan_tx,
1049 					priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1050 					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1051 	if (!desc) {
1052 		dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1053 			__func__);
1054 		return 0;
1055 	}
1056 	dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1057 	priv->desc_tx = desc;
1058 	desc->callback = pch_dma_tx_complete;
1059 	desc->callback_param = priv;
1060 
1061 	desc->tx_submit(desc);
1062 
1063 	dma_async_issue_pending(priv->chan_tx);
1064 
1065 	return PCH_UART_HANDLED_TX_INT;
1066 }
1067 
1068 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1069 {
1070 	struct uart_port *port = &priv->port;
1071 	struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1072 	char   *error_msg[5] = {};
1073 	int    i = 0;
1074 
1075 	if (lsr & PCH_UART_LSR_ERR)
1076 		error_msg[i++] = "Error data in FIFO\n";
1077 
1078 	if (lsr & UART_LSR_FE) {
1079 		port->icount.frame++;
1080 		error_msg[i++] = "  Framing Error\n";
1081 	}
1082 
1083 	if (lsr & UART_LSR_PE) {
1084 		port->icount.parity++;
1085 		error_msg[i++] = "  Parity Error\n";
1086 	}
1087 
1088 	if (lsr & UART_LSR_OE) {
1089 		port->icount.overrun++;
1090 		error_msg[i++] = "  Overrun Error\n";
1091 	}
1092 
1093 	if (tty == NULL) {
1094 		for (i = 0; error_msg[i] != NULL; i++)
1095 			dev_err(&priv->pdev->dev, error_msg[i]);
1096 	} else {
1097 		tty_kref_put(tty);
1098 	}
1099 }
1100 
1101 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1102 {
1103 	struct eg20t_port *priv = dev_id;
1104 	unsigned int handled;
1105 	u8 lsr;
1106 	int ret = 0;
1107 	unsigned char iid;
1108 	unsigned long flags;
1109 	int next = 1;
1110 	u8 msr;
1111 
1112 	spin_lock_irqsave(&priv->lock, flags);
1113 	handled = 0;
1114 	while (next) {
1115 		iid = pch_uart_hal_get_iid(priv);
1116 		if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1117 			break;
1118 		switch (iid) {
1119 		case PCH_UART_IID_RLS:	/* Receiver Line Status */
1120 			lsr = pch_uart_hal_get_line_status(priv);
1121 			if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1122 						UART_LSR_PE | UART_LSR_OE)) {
1123 				pch_uart_err_ir(priv, lsr);
1124 				ret = PCH_UART_HANDLED_RX_ERR_INT;
1125 			} else {
1126 				ret = PCH_UART_HANDLED_LS_INT;
1127 			}
1128 			break;
1129 		case PCH_UART_IID_RDR:	/* Received Data Ready */
1130 			if (priv->use_dma) {
1131 				pch_uart_hal_disable_interrupt(priv,
1132 						PCH_UART_HAL_RX_INT |
1133 						PCH_UART_HAL_RX_ERR_INT);
1134 				ret = dma_handle_rx(priv);
1135 				if (!ret)
1136 					pch_uart_hal_enable_interrupt(priv,
1137 						PCH_UART_HAL_RX_INT |
1138 						PCH_UART_HAL_RX_ERR_INT);
1139 			} else {
1140 				ret = handle_rx(priv);
1141 			}
1142 			break;
1143 		case PCH_UART_IID_RDR_TO:	/* Received Data Ready
1144 						   (FIFO Timeout) */
1145 			ret = handle_rx_to(priv);
1146 			break;
1147 		case PCH_UART_IID_THRE:	/* Transmitter Holding Register
1148 						   Empty */
1149 			if (priv->use_dma)
1150 				ret = dma_handle_tx(priv);
1151 			else
1152 				ret = handle_tx(priv);
1153 			break;
1154 		case PCH_UART_IID_MS:	/* Modem Status */
1155 			msr = pch_uart_hal_get_modem(priv);
1156 			next = 0; /* MS ir prioirty is the lowest. So, MS ir
1157 				     means final interrupt */
1158 			if ((msr & UART_MSR_ANY_DELTA) == 0)
1159 				break;
1160 			ret |= PCH_UART_HANDLED_MS_INT;
1161 			break;
1162 		default:	/* Never junp to this label */
1163 			dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1164 				iid, jiffies);
1165 			ret = -1;
1166 			next = 0;
1167 			break;
1168 		}
1169 		handled |= (unsigned int)ret;
1170 	}
1171 
1172 	spin_unlock_irqrestore(&priv->lock, flags);
1173 	return IRQ_RETVAL(handled);
1174 }
1175 
1176 /* This function tests whether the transmitter fifo and shifter for the port
1177 						described by 'port' is empty. */
1178 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1179 {
1180 	struct eg20t_port *priv;
1181 
1182 	priv = container_of(port, struct eg20t_port, port);
1183 	if (priv->tx_empty)
1184 		return TIOCSER_TEMT;
1185 	else
1186 		return 0;
1187 }
1188 
1189 /* Returns the current state of modem control inputs. */
1190 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1191 {
1192 	struct eg20t_port *priv;
1193 	u8 modem;
1194 	unsigned int ret = 0;
1195 
1196 	priv = container_of(port, struct eg20t_port, port);
1197 	modem = pch_uart_hal_get_modem(priv);
1198 
1199 	if (modem & UART_MSR_DCD)
1200 		ret |= TIOCM_CAR;
1201 
1202 	if (modem & UART_MSR_RI)
1203 		ret |= TIOCM_RNG;
1204 
1205 	if (modem & UART_MSR_DSR)
1206 		ret |= TIOCM_DSR;
1207 
1208 	if (modem & UART_MSR_CTS)
1209 		ret |= TIOCM_CTS;
1210 
1211 	return ret;
1212 }
1213 
1214 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1215 {
1216 	u32 mcr = 0;
1217 	struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1218 
1219 	if (mctrl & TIOCM_DTR)
1220 		mcr |= UART_MCR_DTR;
1221 	if (mctrl & TIOCM_RTS)
1222 		mcr |= UART_MCR_RTS;
1223 	if (mctrl & TIOCM_LOOP)
1224 		mcr |= UART_MCR_LOOP;
1225 
1226 	if (priv->mcr & UART_MCR_AFE)
1227 		mcr |= UART_MCR_AFE;
1228 
1229 	if (mctrl)
1230 		iowrite8(mcr, priv->membase + UART_MCR);
1231 }
1232 
1233 static void pch_uart_stop_tx(struct uart_port *port)
1234 {
1235 	struct eg20t_port *priv;
1236 	priv = container_of(port, struct eg20t_port, port);
1237 	priv->start_tx = 0;
1238 	priv->tx_dma_use = 0;
1239 }
1240 
1241 static void pch_uart_start_tx(struct uart_port *port)
1242 {
1243 	struct eg20t_port *priv;
1244 
1245 	priv = container_of(port, struct eg20t_port, port);
1246 
1247 	if (priv->use_dma) {
1248 		if (priv->tx_dma_use) {
1249 			dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1250 				__func__);
1251 			return;
1252 		}
1253 	}
1254 
1255 	priv->start_tx = 1;
1256 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1257 }
1258 
1259 static void pch_uart_stop_rx(struct uart_port *port)
1260 {
1261 	struct eg20t_port *priv;
1262 	priv = container_of(port, struct eg20t_port, port);
1263 	priv->start_rx = 0;
1264 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1265 					     PCH_UART_HAL_RX_ERR_INT);
1266 }
1267 
1268 /* Enable the modem status interrupts. */
1269 static void pch_uart_enable_ms(struct uart_port *port)
1270 {
1271 	struct eg20t_port *priv;
1272 	priv = container_of(port, struct eg20t_port, port);
1273 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1274 }
1275 
1276 /* Control the transmission of a break signal. */
1277 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1278 {
1279 	struct eg20t_port *priv;
1280 	unsigned long flags;
1281 
1282 	priv = container_of(port, struct eg20t_port, port);
1283 	spin_lock_irqsave(&priv->lock, flags);
1284 	pch_uart_hal_set_break(priv, ctl);
1285 	spin_unlock_irqrestore(&priv->lock, flags);
1286 }
1287 
1288 /* Grab any interrupt resources and initialise any low level driver state. */
1289 static int pch_uart_startup(struct uart_port *port)
1290 {
1291 	struct eg20t_port *priv;
1292 	int ret;
1293 	int fifo_size;
1294 	int trigger_level;
1295 
1296 	priv = container_of(port, struct eg20t_port, port);
1297 	priv->tx_empty = 1;
1298 
1299 	if (port->uartclk)
1300 		priv->uartclk = port->uartclk;
1301 	else
1302 		port->uartclk = priv->uartclk;
1303 
1304 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1305 	ret = pch_uart_hal_set_line(priv, default_baud,
1306 			      PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1307 			      PCH_UART_HAL_STB1);
1308 	if (ret)
1309 		return ret;
1310 
1311 	switch (priv->fifo_size) {
1312 	case 256:
1313 		fifo_size = PCH_UART_HAL_FIFO256;
1314 		break;
1315 	case 64:
1316 		fifo_size = PCH_UART_HAL_FIFO64;
1317 		break;
1318 	case 16:
1319 		fifo_size = PCH_UART_HAL_FIFO16;
1320 		break;
1321 	case 1:
1322 	default:
1323 		fifo_size = PCH_UART_HAL_FIFO_DIS;
1324 		break;
1325 	}
1326 
1327 	switch (priv->trigger) {
1328 	case PCH_UART_HAL_TRIGGER1:
1329 		trigger_level = 1;
1330 		break;
1331 	case PCH_UART_HAL_TRIGGER_L:
1332 		trigger_level = priv->fifo_size / 4;
1333 		break;
1334 	case PCH_UART_HAL_TRIGGER_M:
1335 		trigger_level = priv->fifo_size / 2;
1336 		break;
1337 	case PCH_UART_HAL_TRIGGER_H:
1338 	default:
1339 		trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1340 		break;
1341 	}
1342 
1343 	priv->trigger_level = trigger_level;
1344 	ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1345 				    fifo_size, priv->trigger);
1346 	if (ret < 0)
1347 		return ret;
1348 
1349 	ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1350 			priv->irq_name, priv);
1351 	if (ret < 0)
1352 		return ret;
1353 
1354 	if (priv->use_dma)
1355 		pch_request_dma(port);
1356 
1357 	priv->start_rx = 1;
1358 	pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1359 					    PCH_UART_HAL_RX_ERR_INT);
1360 	uart_update_timeout(port, CS8, default_baud);
1361 
1362 	return 0;
1363 }
1364 
1365 static void pch_uart_shutdown(struct uart_port *port)
1366 {
1367 	struct eg20t_port *priv;
1368 	int ret;
1369 
1370 	priv = container_of(port, struct eg20t_port, port);
1371 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1372 	pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1373 	ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1374 			      PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1375 	if (ret)
1376 		dev_err(priv->port.dev,
1377 			"pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1378 
1379 	pch_free_dma(port);
1380 
1381 	free_irq(priv->port.irq, priv);
1382 }
1383 
1384 /* Change the port parameters, including word length, parity, stop
1385  *bits.  Update read_status_mask and ignore_status_mask to indicate
1386  *the types of events we are interested in receiving.  */
1387 static void pch_uart_set_termios(struct uart_port *port,
1388 				 struct ktermios *termios, struct ktermios *old)
1389 {
1390 	int rtn;
1391 	unsigned int baud, parity, bits, stb;
1392 	struct eg20t_port *priv;
1393 	unsigned long flags;
1394 
1395 	priv = container_of(port, struct eg20t_port, port);
1396 	switch (termios->c_cflag & CSIZE) {
1397 	case CS5:
1398 		bits = PCH_UART_HAL_5BIT;
1399 		break;
1400 	case CS6:
1401 		bits = PCH_UART_HAL_6BIT;
1402 		break;
1403 	case CS7:
1404 		bits = PCH_UART_HAL_7BIT;
1405 		break;
1406 	default:		/* CS8 */
1407 		bits = PCH_UART_HAL_8BIT;
1408 		break;
1409 	}
1410 	if (termios->c_cflag & CSTOPB)
1411 		stb = PCH_UART_HAL_STB2;
1412 	else
1413 		stb = PCH_UART_HAL_STB1;
1414 
1415 	if (termios->c_cflag & PARENB) {
1416 		if (termios->c_cflag & PARODD)
1417 			parity = PCH_UART_HAL_PARITY_ODD;
1418 		else
1419 			parity = PCH_UART_HAL_PARITY_EVEN;
1420 
1421 	} else
1422 		parity = PCH_UART_HAL_PARITY_NONE;
1423 
1424 	/* Only UART0 has auto hardware flow function */
1425 	if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1426 		priv->mcr |= UART_MCR_AFE;
1427 	else
1428 		priv->mcr &= ~UART_MCR_AFE;
1429 
1430 	termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1431 
1432 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1433 
1434 	spin_lock_irqsave(&priv->lock, flags);
1435 	spin_lock(&port->lock);
1436 
1437 	uart_update_timeout(port, termios->c_cflag, baud);
1438 	rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1439 	if (rtn)
1440 		goto out;
1441 
1442 	pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1443 	/* Don't rewrite B0 */
1444 	if (tty_termios_baud_rate(termios))
1445 		tty_termios_encode_baud_rate(termios, baud, baud);
1446 
1447 out:
1448 	spin_unlock(&port->lock);
1449 	spin_unlock_irqrestore(&priv->lock, flags);
1450 }
1451 
1452 static const char *pch_uart_type(struct uart_port *port)
1453 {
1454 	return KBUILD_MODNAME;
1455 }
1456 
1457 static void pch_uart_release_port(struct uart_port *port)
1458 {
1459 	struct eg20t_port *priv;
1460 
1461 	priv = container_of(port, struct eg20t_port, port);
1462 	pci_iounmap(priv->pdev, priv->membase);
1463 	pci_release_regions(priv->pdev);
1464 }
1465 
1466 static int pch_uart_request_port(struct uart_port *port)
1467 {
1468 	struct eg20t_port *priv;
1469 	int ret;
1470 	void __iomem *membase;
1471 
1472 	priv = container_of(port, struct eg20t_port, port);
1473 	ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1474 	if (ret < 0)
1475 		return -EBUSY;
1476 
1477 	membase = pci_iomap(priv->pdev, 1, 0);
1478 	if (!membase) {
1479 		pci_release_regions(priv->pdev);
1480 		return -EBUSY;
1481 	}
1482 	priv->membase = port->membase = membase;
1483 
1484 	return 0;
1485 }
1486 
1487 static void pch_uart_config_port(struct uart_port *port, int type)
1488 {
1489 	struct eg20t_port *priv;
1490 
1491 	priv = container_of(port, struct eg20t_port, port);
1492 	if (type & UART_CONFIG_TYPE) {
1493 		port->type = priv->port_type;
1494 		pch_uart_request_port(port);
1495 	}
1496 }
1497 
1498 static int pch_uart_verify_port(struct uart_port *port,
1499 				struct serial_struct *serinfo)
1500 {
1501 	struct eg20t_port *priv;
1502 
1503 	priv = container_of(port, struct eg20t_port, port);
1504 	if (serinfo->flags & UPF_LOW_LATENCY) {
1505 		dev_info(priv->port.dev,
1506 			"PCH UART : Use PIO Mode (without DMA)\n");
1507 		priv->use_dma = 0;
1508 		serinfo->flags &= ~UPF_LOW_LATENCY;
1509 	} else {
1510 #ifndef CONFIG_PCH_DMA
1511 		dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1512 			__func__);
1513 		return -EOPNOTSUPP;
1514 #endif
1515 		if (!priv->use_dma) {
1516 			pch_request_dma(port);
1517 			if (priv->chan_rx)
1518 				priv->use_dma = 1;
1519 		}
1520 		dev_info(priv->port.dev, "PCH UART: %s\n",
1521 				priv->use_dma ?
1522 				"Use DMA Mode" : "No DMA");
1523 	}
1524 
1525 	return 0;
1526 }
1527 
1528 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1529 /*
1530  *	Wait for transmitter & holding register to empty
1531  */
1532 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1533 {
1534 	unsigned int status, tmout = 10000;
1535 
1536 	/* Wait up to 10ms for the character(s) to be sent. */
1537 	for (;;) {
1538 		status = ioread8(up->membase + UART_LSR);
1539 
1540 		if ((status & bits) == bits)
1541 			break;
1542 		if (--tmout == 0)
1543 			break;
1544 		udelay(1);
1545 	}
1546 
1547 	/* Wait up to 1s for flow control if necessary */
1548 	if (up->port.flags & UPF_CONS_FLOW) {
1549 		unsigned int tmout;
1550 		for (tmout = 1000000; tmout; tmout--) {
1551 			unsigned int msr = ioread8(up->membase + UART_MSR);
1552 			if (msr & UART_MSR_CTS)
1553 				break;
1554 			udelay(1);
1555 			touch_nmi_watchdog();
1556 		}
1557 	}
1558 }
1559 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1560 
1561 #ifdef CONFIG_CONSOLE_POLL
1562 /*
1563  * Console polling routines for communicate via uart while
1564  * in an interrupt or debug context.
1565  */
1566 static int pch_uart_get_poll_char(struct uart_port *port)
1567 {
1568 	struct eg20t_port *priv =
1569 		container_of(port, struct eg20t_port, port);
1570 	u8 lsr = ioread8(priv->membase + UART_LSR);
1571 
1572 	if (!(lsr & UART_LSR_DR))
1573 		return NO_POLL_CHAR;
1574 
1575 	return ioread8(priv->membase + PCH_UART_RBR);
1576 }
1577 
1578 
1579 static void pch_uart_put_poll_char(struct uart_port *port,
1580 			 unsigned char c)
1581 {
1582 	unsigned int ier;
1583 	struct eg20t_port *priv =
1584 		container_of(port, struct eg20t_port, port);
1585 
1586 	/*
1587 	 * First save the IER then disable the interrupts
1588 	 */
1589 	ier = ioread8(priv->membase + UART_IER);
1590 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1591 
1592 	wait_for_xmitr(priv, UART_LSR_THRE);
1593 	/*
1594 	 * Send the character out.
1595 	 */
1596 	iowrite8(c, priv->membase + PCH_UART_THR);
1597 
1598 	/*
1599 	 * Finally, wait for transmitter to become empty
1600 	 * and restore the IER
1601 	 */
1602 	wait_for_xmitr(priv, BOTH_EMPTY);
1603 	iowrite8(ier, priv->membase + UART_IER);
1604 }
1605 #endif /* CONFIG_CONSOLE_POLL */
1606 
1607 static const struct uart_ops pch_uart_ops = {
1608 	.tx_empty = pch_uart_tx_empty,
1609 	.set_mctrl = pch_uart_set_mctrl,
1610 	.get_mctrl = pch_uart_get_mctrl,
1611 	.stop_tx = pch_uart_stop_tx,
1612 	.start_tx = pch_uart_start_tx,
1613 	.stop_rx = pch_uart_stop_rx,
1614 	.enable_ms = pch_uart_enable_ms,
1615 	.break_ctl = pch_uart_break_ctl,
1616 	.startup = pch_uart_startup,
1617 	.shutdown = pch_uart_shutdown,
1618 	.set_termios = pch_uart_set_termios,
1619 /*	.pm		= pch_uart_pm,		Not supported yet */
1620 	.type = pch_uart_type,
1621 	.release_port = pch_uart_release_port,
1622 	.request_port = pch_uart_request_port,
1623 	.config_port = pch_uart_config_port,
1624 	.verify_port = pch_uart_verify_port,
1625 #ifdef CONFIG_CONSOLE_POLL
1626 	.poll_get_char = pch_uart_get_poll_char,
1627 	.poll_put_char = pch_uart_put_poll_char,
1628 #endif
1629 };
1630 
1631 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1632 
1633 static void pch_console_putchar(struct uart_port *port, int ch)
1634 {
1635 	struct eg20t_port *priv =
1636 		container_of(port, struct eg20t_port, port);
1637 
1638 	wait_for_xmitr(priv, UART_LSR_THRE);
1639 	iowrite8(ch, priv->membase + PCH_UART_THR);
1640 }
1641 
1642 /*
1643  *	Print a string to the serial port trying not to disturb
1644  *	any possible real use of the port...
1645  *
1646  *	The console_lock must be held when we get here.
1647  */
1648 static void
1649 pch_console_write(struct console *co, const char *s, unsigned int count)
1650 {
1651 	struct eg20t_port *priv;
1652 	unsigned long flags;
1653 	int priv_locked = 1;
1654 	int port_locked = 1;
1655 	u8 ier;
1656 
1657 	priv = pch_uart_ports[co->index];
1658 
1659 	touch_nmi_watchdog();
1660 
1661 	local_irq_save(flags);
1662 	if (priv->port.sysrq) {
1663 		/* call to uart_handle_sysrq_char already took the priv lock */
1664 		priv_locked = 0;
1665 		/* serial8250_handle_port() already took the port lock */
1666 		port_locked = 0;
1667 	} else if (oops_in_progress) {
1668 		priv_locked = spin_trylock(&priv->lock);
1669 		port_locked = spin_trylock(&priv->port.lock);
1670 	} else {
1671 		spin_lock(&priv->lock);
1672 		spin_lock(&priv->port.lock);
1673 	}
1674 
1675 	/*
1676 	 *	First save the IER then disable the interrupts
1677 	 */
1678 	ier = ioread8(priv->membase + UART_IER);
1679 
1680 	pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1681 
1682 	uart_console_write(&priv->port, s, count, pch_console_putchar);
1683 
1684 	/*
1685 	 *	Finally, wait for transmitter to become empty
1686 	 *	and restore the IER
1687 	 */
1688 	wait_for_xmitr(priv, BOTH_EMPTY);
1689 	iowrite8(ier, priv->membase + UART_IER);
1690 
1691 	if (port_locked)
1692 		spin_unlock(&priv->port.lock);
1693 	if (priv_locked)
1694 		spin_unlock(&priv->lock);
1695 	local_irq_restore(flags);
1696 }
1697 
1698 static int __init pch_console_setup(struct console *co, char *options)
1699 {
1700 	struct uart_port *port;
1701 	int baud = default_baud;
1702 	int bits = 8;
1703 	int parity = 'n';
1704 	int flow = 'n';
1705 
1706 	/*
1707 	 * Check whether an invalid uart number has been specified, and
1708 	 * if so, search for the first available port that does have
1709 	 * console support.
1710 	 */
1711 	if (co->index >= PCH_UART_NR)
1712 		co->index = 0;
1713 	port = &pch_uart_ports[co->index]->port;
1714 
1715 	if (!port || (!port->iobase && !port->membase))
1716 		return -ENODEV;
1717 
1718 	port->uartclk = pch_uart_get_uartclk();
1719 
1720 	if (options)
1721 		uart_parse_options(options, &baud, &parity, &bits, &flow);
1722 
1723 	return uart_set_options(port, co, baud, parity, bits, flow);
1724 }
1725 
1726 static struct uart_driver pch_uart_driver;
1727 
1728 static struct console pch_console = {
1729 	.name		= PCH_UART_DRIVER_DEVICE,
1730 	.write		= pch_console_write,
1731 	.device		= uart_console_device,
1732 	.setup		= pch_console_setup,
1733 	.flags		= CON_PRINTBUFFER | CON_ANYTIME,
1734 	.index		= -1,
1735 	.data		= &pch_uart_driver,
1736 };
1737 
1738 #define PCH_CONSOLE	(&pch_console)
1739 #else
1740 #define PCH_CONSOLE	NULL
1741 #endif	/* CONFIG_SERIAL_PCH_UART_CONSOLE */
1742 
1743 static struct uart_driver pch_uart_driver = {
1744 	.owner = THIS_MODULE,
1745 	.driver_name = KBUILD_MODNAME,
1746 	.dev_name = PCH_UART_DRIVER_DEVICE,
1747 	.major = 0,
1748 	.minor = 0,
1749 	.nr = PCH_UART_NR,
1750 	.cons = PCH_CONSOLE,
1751 };
1752 
1753 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1754 					     const struct pci_device_id *id)
1755 {
1756 	struct eg20t_port *priv;
1757 	int ret;
1758 	unsigned int iobase;
1759 	unsigned int mapbase;
1760 	unsigned char *rxbuf;
1761 	int fifosize;
1762 	int port_type;
1763 	struct pch_uart_driver_data *board;
1764 #ifdef CONFIG_DEBUG_FS
1765 	char name[32];	/* for debugfs file name */
1766 #endif
1767 
1768 	board = &drv_dat[id->driver_data];
1769 	port_type = board->port_type;
1770 
1771 	priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1772 	if (priv == NULL)
1773 		goto init_port_alloc_err;
1774 
1775 	rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1776 	if (!rxbuf)
1777 		goto init_port_free_txbuf;
1778 
1779 	switch (port_type) {
1780 	case PORT_UNKNOWN:
1781 		fifosize = 256; /* EG20T/ML7213: UART0 */
1782 		break;
1783 	case PORT_8250:
1784 		fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1785 		break;
1786 	default:
1787 		dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1788 		goto init_port_hal_free;
1789 	}
1790 
1791 	pci_enable_msi(pdev);
1792 	pci_set_master(pdev);
1793 
1794 	spin_lock_init(&priv->lock);
1795 
1796 	iobase = pci_resource_start(pdev, 0);
1797 	mapbase = pci_resource_start(pdev, 1);
1798 	priv->mapbase = mapbase;
1799 	priv->iobase = iobase;
1800 	priv->pdev = pdev;
1801 	priv->tx_empty = 1;
1802 	priv->rxbuf.buf = rxbuf;
1803 	priv->rxbuf.size = PAGE_SIZE;
1804 
1805 	priv->fifo_size = fifosize;
1806 	priv->uartclk = pch_uart_get_uartclk();
1807 	priv->port_type = PORT_MAX_8250 + port_type + 1;
1808 	priv->port.dev = &pdev->dev;
1809 	priv->port.iobase = iobase;
1810 	priv->port.membase = NULL;
1811 	priv->port.mapbase = mapbase;
1812 	priv->port.irq = pdev->irq;
1813 	priv->port.iotype = UPIO_PORT;
1814 	priv->port.ops = &pch_uart_ops;
1815 	priv->port.flags = UPF_BOOT_AUTOCONF;
1816 	priv->port.fifosize = fifosize;
1817 	priv->port.line = board->line_no;
1818 	priv->trigger = PCH_UART_HAL_TRIGGER_M;
1819 
1820 	snprintf(priv->irq_name, IRQ_NAME_SIZE,
1821 		 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1822 		 priv->port.line);
1823 
1824 	spin_lock_init(&priv->port.lock);
1825 
1826 	pci_set_drvdata(pdev, priv);
1827 	priv->trigger_level = 1;
1828 	priv->fcr = 0;
1829 
1830 	if (pdev->dev.of_node)
1831 		of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1832 					 , &user_uartclk);
1833 
1834 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1835 	pch_uart_ports[board->line_no] = priv;
1836 #endif
1837 	ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1838 	if (ret < 0)
1839 		goto init_port_hal_free;
1840 
1841 #ifdef CONFIG_DEBUG_FS
1842 	snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1843 	priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1844 				NULL, priv, &port_regs_ops);
1845 #endif
1846 
1847 	return priv;
1848 
1849 init_port_hal_free:
1850 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1851 	pch_uart_ports[board->line_no] = NULL;
1852 #endif
1853 	free_page((unsigned long)rxbuf);
1854 init_port_free_txbuf:
1855 	kfree(priv);
1856 init_port_alloc_err:
1857 
1858 	return NULL;
1859 }
1860 
1861 static void pch_uart_exit_port(struct eg20t_port *priv)
1862 {
1863 
1864 #ifdef CONFIG_DEBUG_FS
1865 	if (priv->debugfs)
1866 		debugfs_remove(priv->debugfs);
1867 #endif
1868 	uart_remove_one_port(&pch_uart_driver, &priv->port);
1869 	free_page((unsigned long)priv->rxbuf.buf);
1870 }
1871 
1872 static void pch_uart_pci_remove(struct pci_dev *pdev)
1873 {
1874 	struct eg20t_port *priv = pci_get_drvdata(pdev);
1875 
1876 	pci_disable_msi(pdev);
1877 
1878 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1879 	pch_uart_ports[priv->port.line] = NULL;
1880 #endif
1881 	pch_uart_exit_port(priv);
1882 	pci_disable_device(pdev);
1883 	kfree(priv);
1884 	return;
1885 }
1886 #ifdef CONFIG_PM
1887 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1888 {
1889 	struct eg20t_port *priv = pci_get_drvdata(pdev);
1890 
1891 	uart_suspend_port(&pch_uart_driver, &priv->port);
1892 
1893 	pci_save_state(pdev);
1894 	pci_set_power_state(pdev, pci_choose_state(pdev, state));
1895 	return 0;
1896 }
1897 
1898 static int pch_uart_pci_resume(struct pci_dev *pdev)
1899 {
1900 	struct eg20t_port *priv = pci_get_drvdata(pdev);
1901 	int ret;
1902 
1903 	pci_set_power_state(pdev, PCI_D0);
1904 	pci_restore_state(pdev);
1905 
1906 	ret = pci_enable_device(pdev);
1907 	if (ret) {
1908 		dev_err(&pdev->dev,
1909 		"%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1910 		return ret;
1911 	}
1912 
1913 	uart_resume_port(&pch_uart_driver, &priv->port);
1914 
1915 	return 0;
1916 }
1917 #else
1918 #define pch_uart_pci_suspend NULL
1919 #define pch_uart_pci_resume NULL
1920 #endif
1921 
1922 static const struct pci_device_id pch_uart_pci_id[] = {
1923 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1924 	 .driver_data = pch_et20t_uart0},
1925 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1926 	 .driver_data = pch_et20t_uart1},
1927 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1928 	 .driver_data = pch_et20t_uart2},
1929 	{PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1930 	 .driver_data = pch_et20t_uart3},
1931 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1932 	 .driver_data = pch_ml7213_uart0},
1933 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1934 	 .driver_data = pch_ml7213_uart1},
1935 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1936 	 .driver_data = pch_ml7213_uart2},
1937 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1938 	 .driver_data = pch_ml7223_uart0},
1939 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1940 	 .driver_data = pch_ml7223_uart1},
1941 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1942 	 .driver_data = pch_ml7831_uart0},
1943 	{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1944 	 .driver_data = pch_ml7831_uart1},
1945 	{0,},
1946 };
1947 
1948 static int pch_uart_pci_probe(struct pci_dev *pdev,
1949 					const struct pci_device_id *id)
1950 {
1951 	int ret;
1952 	struct eg20t_port *priv;
1953 
1954 	ret = pci_enable_device(pdev);
1955 	if (ret < 0)
1956 		goto probe_error;
1957 
1958 	priv = pch_uart_init_port(pdev, id);
1959 	if (!priv) {
1960 		ret = -EBUSY;
1961 		goto probe_disable_device;
1962 	}
1963 	pci_set_drvdata(pdev, priv);
1964 
1965 	return ret;
1966 
1967 probe_disable_device:
1968 	pci_disable_msi(pdev);
1969 	pci_disable_device(pdev);
1970 probe_error:
1971 	return ret;
1972 }
1973 
1974 static struct pci_driver pch_uart_pci_driver = {
1975 	.name = "pch_uart",
1976 	.id_table = pch_uart_pci_id,
1977 	.probe = pch_uart_pci_probe,
1978 	.remove = pch_uart_pci_remove,
1979 	.suspend = pch_uart_pci_suspend,
1980 	.resume = pch_uart_pci_resume,
1981 };
1982 
1983 static int __init pch_uart_module_init(void)
1984 {
1985 	int ret;
1986 
1987 	/* register as UART driver */
1988 	ret = uart_register_driver(&pch_uart_driver);
1989 	if (ret < 0)
1990 		return ret;
1991 
1992 	/* register as PCI driver */
1993 	ret = pci_register_driver(&pch_uart_pci_driver);
1994 	if (ret < 0)
1995 		uart_unregister_driver(&pch_uart_driver);
1996 
1997 	return ret;
1998 }
1999 module_init(pch_uart_module_init);
2000 
2001 static void __exit pch_uart_module_exit(void)
2002 {
2003 	pci_unregister_driver(&pch_uart_pci_driver);
2004 	uart_unregister_driver(&pch_uart_driver);
2005 }
2006 module_exit(pch_uart_module_exit);
2007 
2008 MODULE_LICENSE("GPL v2");
2009 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2010 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2011 
2012 module_param(default_baud, uint, S_IRUGO);
2013 MODULE_PARM_DESC(default_baud,
2014                  "Default BAUD for initial driver state and console (default 9600)");
2015 module_param(user_uartclk, uint, S_IRUGO);
2016 MODULE_PARM_DESC(user_uartclk,
2017                  "Override UART default or board specific UART clock");
2018