1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/io.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/gpio.h> 43 #include <linux/pinctrl/consumer.h> 44 #include <linux/platform_data/serial-omap.h> 45 46 #define OMAP_MAX_HSUART_PORTS 6 47 48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 49 50 #define OMAP_UART_REV_42 0x0402 51 #define OMAP_UART_REV_46 0x0406 52 #define OMAP_UART_REV_52 0x0502 53 #define OMAP_UART_REV_63 0x0603 54 55 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 56 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 57 58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ 59 60 /* SCR register bitmasks */ 61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 62 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 63 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 64 65 /* FCR register bitmasks */ 66 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 67 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 68 69 /* MVR register bitmasks */ 70 #define OMAP_UART_MVR_SCHEME_SHIFT 30 71 72 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 73 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 74 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 75 76 #define OMAP_UART_MVR_MAJ_MASK 0x700 77 #define OMAP_UART_MVR_MAJ_SHIFT 8 78 #define OMAP_UART_MVR_MIN_MASK 0x3f 79 80 #define OMAP_UART_DMA_CH_FREE -1 81 82 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 83 #define OMAP_MODE13X_SPEED 230400 84 85 /* WER = 0x7F 86 * Enable module level wakeup in WER reg 87 */ 88 #define OMAP_UART_WER_MOD_WKUP 0X7F 89 90 /* Enable XON/XOFF flow control on output */ 91 #define OMAP_UART_SW_TX 0x08 92 93 /* Enable XON/XOFF flow control on input */ 94 #define OMAP_UART_SW_RX 0x02 95 96 #define OMAP_UART_SW_CLR 0xF0 97 98 #define OMAP_UART_TCR_TRIG 0x0F 99 100 struct uart_omap_dma { 101 u8 uart_dma_tx; 102 u8 uart_dma_rx; 103 int rx_dma_channel; 104 int tx_dma_channel; 105 dma_addr_t rx_buf_dma_phys; 106 dma_addr_t tx_buf_dma_phys; 107 unsigned int uart_base; 108 /* 109 * Buffer for rx dma.It is not required for tx because the buffer 110 * comes from port structure. 111 */ 112 unsigned char *rx_buf; 113 unsigned int prev_rx_dma_pos; 114 int tx_buf_size; 115 int tx_dma_used; 116 int rx_dma_used; 117 spinlock_t tx_lock; 118 spinlock_t rx_lock; 119 /* timer to poll activity on rx dma */ 120 struct timer_list rx_timer; 121 unsigned int rx_buf_size; 122 unsigned int rx_poll_rate; 123 unsigned int rx_timeout; 124 }; 125 126 struct uart_omap_port { 127 struct uart_port port; 128 struct uart_omap_dma uart_dma; 129 struct device *dev; 130 131 unsigned char ier; 132 unsigned char lcr; 133 unsigned char mcr; 134 unsigned char fcr; 135 unsigned char efr; 136 unsigned char dll; 137 unsigned char dlh; 138 unsigned char mdr1; 139 unsigned char scr; 140 141 int use_dma; 142 /* 143 * Some bits in registers are cleared on a read, so they must 144 * be saved whenever the register is read but the bits will not 145 * be immediately processed. 146 */ 147 unsigned int lsr_break_flag; 148 unsigned char msr_saved_flags; 149 char name[20]; 150 unsigned long port_activity; 151 int context_loss_cnt; 152 u32 errata; 153 u8 wakeups_enabled; 154 155 int DTR_gpio; 156 int DTR_inverted; 157 int DTR_active; 158 159 struct pm_qos_request pm_qos_request; 160 u32 latency; 161 u32 calc_latency; 162 struct work_struct qos_work; 163 struct pinctrl *pins; 164 }; 165 166 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 167 168 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 169 170 /* Forward declaration of functions */ 171 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 172 173 static struct workqueue_struct *serial_omap_uart_wq; 174 175 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 176 { 177 offset <<= up->port.regshift; 178 return readw(up->port.membase + offset); 179 } 180 181 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 182 { 183 offset <<= up->port.regshift; 184 writew(value, up->port.membase + offset); 185 } 186 187 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 188 { 189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 190 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 191 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 192 serial_out(up, UART_FCR, 0); 193 } 194 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 196 { 197 struct omap_uart_port_info *pdata = up->dev->platform_data; 198 199 if (!pdata || !pdata->get_context_loss_count) 200 return 0; 201 202 return pdata->get_context_loss_count(up->dev); 203 } 204 205 static void serial_omap_set_forceidle(struct uart_omap_port *up) 206 { 207 struct omap_uart_port_info *pdata = up->dev->platform_data; 208 209 if (!pdata || !pdata->set_forceidle) 210 return; 211 212 pdata->set_forceidle(up->dev); 213 } 214 215 static void serial_omap_set_noidle(struct uart_omap_port *up) 216 { 217 struct omap_uart_port_info *pdata = up->dev->platform_data; 218 219 if (!pdata || !pdata->set_noidle) 220 return; 221 222 pdata->set_noidle(up->dev); 223 } 224 225 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 226 { 227 struct omap_uart_port_info *pdata = up->dev->platform_data; 228 229 if (!pdata || !pdata->enable_wakeup) 230 return; 231 232 pdata->enable_wakeup(up->dev, enable); 233 } 234 235 /* 236 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 237 * @port: uart port info 238 * @baud: baudrate for which mode needs to be determined 239 * 240 * Returns true if baud rate is MODE16X and false if MODE13X 241 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 242 * and Error Rates" determines modes not for all common baud rates. 243 * E.g. for 1000000 baud rate mode must be 16x, but according to that 244 * table it's determined as 13x. 245 */ 246 static bool 247 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 248 { 249 unsigned int n13 = port->uartclk / (13 * baud); 250 unsigned int n16 = port->uartclk / (16 * baud); 251 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13)); 252 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16)); 253 if(baudAbsDiff13 < 0) 254 baudAbsDiff13 = -baudAbsDiff13; 255 if(baudAbsDiff16 < 0) 256 baudAbsDiff16 = -baudAbsDiff16; 257 258 return (baudAbsDiff13 > baudAbsDiff16); 259 } 260 261 /* 262 * serial_omap_get_divisor - calculate divisor value 263 * @port: uart port info 264 * @baud: baudrate for which divisor needs to be calculated. 265 */ 266 static unsigned int 267 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 268 { 269 unsigned int divisor; 270 271 if (!serial_omap_baud_is_mode16(port, baud)) 272 divisor = 13; 273 else 274 divisor = 16; 275 return port->uartclk/(baud * divisor); 276 } 277 278 static void serial_omap_enable_ms(struct uart_port *port) 279 { 280 struct uart_omap_port *up = to_uart_omap_port(port); 281 282 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 283 284 pm_runtime_get_sync(up->dev); 285 up->ier |= UART_IER_MSI; 286 serial_out(up, UART_IER, up->ier); 287 pm_runtime_mark_last_busy(up->dev); 288 pm_runtime_put_autosuspend(up->dev); 289 } 290 291 static void serial_omap_stop_tx(struct uart_port *port) 292 { 293 struct uart_omap_port *up = to_uart_omap_port(port); 294 295 pm_runtime_get_sync(up->dev); 296 if (up->ier & UART_IER_THRI) { 297 up->ier &= ~UART_IER_THRI; 298 serial_out(up, UART_IER, up->ier); 299 } 300 301 serial_omap_set_forceidle(up); 302 303 pm_runtime_mark_last_busy(up->dev); 304 pm_runtime_put_autosuspend(up->dev); 305 } 306 307 static void serial_omap_stop_rx(struct uart_port *port) 308 { 309 struct uart_omap_port *up = to_uart_omap_port(port); 310 311 pm_runtime_get_sync(up->dev); 312 up->ier &= ~UART_IER_RLSI; 313 up->port.read_status_mask &= ~UART_LSR_DR; 314 serial_out(up, UART_IER, up->ier); 315 pm_runtime_mark_last_busy(up->dev); 316 pm_runtime_put_autosuspend(up->dev); 317 } 318 319 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 320 { 321 struct circ_buf *xmit = &up->port.state->xmit; 322 int count; 323 324 if (up->port.x_char) { 325 serial_out(up, UART_TX, up->port.x_char); 326 up->port.icount.tx++; 327 up->port.x_char = 0; 328 return; 329 } 330 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 331 serial_omap_stop_tx(&up->port); 332 return; 333 } 334 count = up->port.fifosize / 4; 335 do { 336 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 337 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 338 up->port.icount.tx++; 339 if (uart_circ_empty(xmit)) 340 break; 341 } while (--count > 0); 342 343 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 344 spin_unlock(&up->port.lock); 345 uart_write_wakeup(&up->port); 346 spin_lock(&up->port.lock); 347 } 348 349 if (uart_circ_empty(xmit)) 350 serial_omap_stop_tx(&up->port); 351 } 352 353 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 354 { 355 if (!(up->ier & UART_IER_THRI)) { 356 up->ier |= UART_IER_THRI; 357 serial_out(up, UART_IER, up->ier); 358 } 359 } 360 361 static void serial_omap_start_tx(struct uart_port *port) 362 { 363 struct uart_omap_port *up = to_uart_omap_port(port); 364 365 pm_runtime_get_sync(up->dev); 366 serial_omap_enable_ier_thri(up); 367 serial_omap_set_noidle(up); 368 pm_runtime_mark_last_busy(up->dev); 369 pm_runtime_put_autosuspend(up->dev); 370 } 371 372 static void serial_omap_throttle(struct uart_port *port) 373 { 374 struct uart_omap_port *up = to_uart_omap_port(port); 375 unsigned long flags; 376 377 pm_runtime_get_sync(up->dev); 378 spin_lock_irqsave(&up->port.lock, flags); 379 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 380 serial_out(up, UART_IER, up->ier); 381 spin_unlock_irqrestore(&up->port.lock, flags); 382 pm_runtime_mark_last_busy(up->dev); 383 pm_runtime_put_autosuspend(up->dev); 384 } 385 386 static void serial_omap_unthrottle(struct uart_port *port) 387 { 388 struct uart_omap_port *up = to_uart_omap_port(port); 389 unsigned long flags; 390 391 pm_runtime_get_sync(up->dev); 392 spin_lock_irqsave(&up->port.lock, flags); 393 up->ier |= UART_IER_RLSI | UART_IER_RDI; 394 serial_out(up, UART_IER, up->ier); 395 spin_unlock_irqrestore(&up->port.lock, flags); 396 pm_runtime_mark_last_busy(up->dev); 397 pm_runtime_put_autosuspend(up->dev); 398 } 399 400 static unsigned int check_modem_status(struct uart_omap_port *up) 401 { 402 unsigned int status; 403 404 status = serial_in(up, UART_MSR); 405 status |= up->msr_saved_flags; 406 up->msr_saved_flags = 0; 407 if ((status & UART_MSR_ANY_DELTA) == 0) 408 return status; 409 410 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 411 up->port.state != NULL) { 412 if (status & UART_MSR_TERI) 413 up->port.icount.rng++; 414 if (status & UART_MSR_DDSR) 415 up->port.icount.dsr++; 416 if (status & UART_MSR_DDCD) 417 uart_handle_dcd_change 418 (&up->port, status & UART_MSR_DCD); 419 if (status & UART_MSR_DCTS) 420 uart_handle_cts_change 421 (&up->port, status & UART_MSR_CTS); 422 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 423 } 424 425 return status; 426 } 427 428 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 429 { 430 unsigned int flag; 431 unsigned char ch = 0; 432 433 if (likely(lsr & UART_LSR_DR)) 434 ch = serial_in(up, UART_RX); 435 436 up->port.icount.rx++; 437 flag = TTY_NORMAL; 438 439 if (lsr & UART_LSR_BI) { 440 flag = TTY_BREAK; 441 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 442 up->port.icount.brk++; 443 /* 444 * We do the SysRQ and SAK checking 445 * here because otherwise the break 446 * may get masked by ignore_status_mask 447 * or read_status_mask. 448 */ 449 if (uart_handle_break(&up->port)) 450 return; 451 452 } 453 454 if (lsr & UART_LSR_PE) { 455 flag = TTY_PARITY; 456 up->port.icount.parity++; 457 } 458 459 if (lsr & UART_LSR_FE) { 460 flag = TTY_FRAME; 461 up->port.icount.frame++; 462 } 463 464 if (lsr & UART_LSR_OE) 465 up->port.icount.overrun++; 466 467 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 468 if (up->port.line == up->port.cons->index) { 469 /* Recover the break flag from console xmit */ 470 lsr |= up->lsr_break_flag; 471 } 472 #endif 473 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 474 } 475 476 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 477 { 478 unsigned char ch = 0; 479 unsigned int flag; 480 481 if (!(lsr & UART_LSR_DR)) 482 return; 483 484 ch = serial_in(up, UART_RX); 485 flag = TTY_NORMAL; 486 up->port.icount.rx++; 487 488 if (uart_handle_sysrq_char(&up->port, ch)) 489 return; 490 491 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 492 } 493 494 /** 495 * serial_omap_irq() - This handles the interrupt from one port 496 * @irq: uart port irq number 497 * @dev_id: uart port info 498 */ 499 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 500 { 501 struct uart_omap_port *up = dev_id; 502 unsigned int iir, lsr; 503 unsigned int type; 504 irqreturn_t ret = IRQ_NONE; 505 int max_count = 256; 506 507 spin_lock(&up->port.lock); 508 pm_runtime_get_sync(up->dev); 509 510 do { 511 iir = serial_in(up, UART_IIR); 512 if (iir & UART_IIR_NO_INT) 513 break; 514 515 ret = IRQ_HANDLED; 516 lsr = serial_in(up, UART_LSR); 517 518 /* extract IRQ type from IIR register */ 519 type = iir & 0x3e; 520 521 switch (type) { 522 case UART_IIR_MSI: 523 check_modem_status(up); 524 break; 525 case UART_IIR_THRI: 526 transmit_chars(up, lsr); 527 break; 528 case UART_IIR_RX_TIMEOUT: 529 /* FALLTHROUGH */ 530 case UART_IIR_RDI: 531 serial_omap_rdi(up, lsr); 532 break; 533 case UART_IIR_RLSI: 534 serial_omap_rlsi(up, lsr); 535 break; 536 case UART_IIR_CTS_RTS_DSR: 537 /* simply try again */ 538 break; 539 case UART_IIR_XOFF: 540 /* FALLTHROUGH */ 541 default: 542 break; 543 } 544 } while (!(iir & UART_IIR_NO_INT) && max_count--); 545 546 spin_unlock(&up->port.lock); 547 548 tty_flip_buffer_push(&up->port.state->port); 549 550 pm_runtime_mark_last_busy(up->dev); 551 pm_runtime_put_autosuspend(up->dev); 552 up->port_activity = jiffies; 553 554 return ret; 555 } 556 557 static unsigned int serial_omap_tx_empty(struct uart_port *port) 558 { 559 struct uart_omap_port *up = to_uart_omap_port(port); 560 unsigned long flags = 0; 561 unsigned int ret = 0; 562 563 pm_runtime_get_sync(up->dev); 564 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 565 spin_lock_irqsave(&up->port.lock, flags); 566 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 567 spin_unlock_irqrestore(&up->port.lock, flags); 568 pm_runtime_mark_last_busy(up->dev); 569 pm_runtime_put_autosuspend(up->dev); 570 return ret; 571 } 572 573 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 574 { 575 struct uart_omap_port *up = to_uart_omap_port(port); 576 unsigned int status; 577 unsigned int ret = 0; 578 579 pm_runtime_get_sync(up->dev); 580 status = check_modem_status(up); 581 pm_runtime_mark_last_busy(up->dev); 582 pm_runtime_put_autosuspend(up->dev); 583 584 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 585 586 if (status & UART_MSR_DCD) 587 ret |= TIOCM_CAR; 588 if (status & UART_MSR_RI) 589 ret |= TIOCM_RNG; 590 if (status & UART_MSR_DSR) 591 ret |= TIOCM_DSR; 592 if (status & UART_MSR_CTS) 593 ret |= TIOCM_CTS; 594 return ret; 595 } 596 597 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 598 { 599 struct uart_omap_port *up = to_uart_omap_port(port); 600 unsigned char mcr = 0, old_mcr; 601 602 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 603 if (mctrl & TIOCM_RTS) 604 mcr |= UART_MCR_RTS; 605 if (mctrl & TIOCM_DTR) 606 mcr |= UART_MCR_DTR; 607 if (mctrl & TIOCM_OUT1) 608 mcr |= UART_MCR_OUT1; 609 if (mctrl & TIOCM_OUT2) 610 mcr |= UART_MCR_OUT2; 611 if (mctrl & TIOCM_LOOP) 612 mcr |= UART_MCR_LOOP; 613 614 pm_runtime_get_sync(up->dev); 615 old_mcr = serial_in(up, UART_MCR); 616 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 617 UART_MCR_DTR | UART_MCR_RTS); 618 up->mcr = old_mcr | mcr; 619 serial_out(up, UART_MCR, up->mcr); 620 pm_runtime_mark_last_busy(up->dev); 621 pm_runtime_put_autosuspend(up->dev); 622 623 if (gpio_is_valid(up->DTR_gpio) && 624 !!(mctrl & TIOCM_DTR) != up->DTR_active) { 625 up->DTR_active = !up->DTR_active; 626 if (gpio_cansleep(up->DTR_gpio)) 627 schedule_work(&up->qos_work); 628 else 629 gpio_set_value(up->DTR_gpio, 630 up->DTR_active != up->DTR_inverted); 631 } 632 } 633 634 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 635 { 636 struct uart_omap_port *up = to_uart_omap_port(port); 637 unsigned long flags = 0; 638 639 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 640 pm_runtime_get_sync(up->dev); 641 spin_lock_irqsave(&up->port.lock, flags); 642 if (break_state == -1) 643 up->lcr |= UART_LCR_SBC; 644 else 645 up->lcr &= ~UART_LCR_SBC; 646 serial_out(up, UART_LCR, up->lcr); 647 spin_unlock_irqrestore(&up->port.lock, flags); 648 pm_runtime_mark_last_busy(up->dev); 649 pm_runtime_put_autosuspend(up->dev); 650 } 651 652 static int serial_omap_startup(struct uart_port *port) 653 { 654 struct uart_omap_port *up = to_uart_omap_port(port); 655 unsigned long flags = 0; 656 int retval; 657 658 /* 659 * Allocate the IRQ 660 */ 661 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 662 up->name, up); 663 if (retval) 664 return retval; 665 666 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 667 668 pm_runtime_get_sync(up->dev); 669 /* 670 * Clear the FIFO buffers and disable them. 671 * (they will be reenabled in set_termios()) 672 */ 673 serial_omap_clear_fifos(up); 674 /* For Hardware flow control */ 675 serial_out(up, UART_MCR, UART_MCR_RTS); 676 677 /* 678 * Clear the interrupt registers. 679 */ 680 (void) serial_in(up, UART_LSR); 681 if (serial_in(up, UART_LSR) & UART_LSR_DR) 682 (void) serial_in(up, UART_RX); 683 (void) serial_in(up, UART_IIR); 684 (void) serial_in(up, UART_MSR); 685 686 /* 687 * Now, initialize the UART 688 */ 689 serial_out(up, UART_LCR, UART_LCR_WLEN8); 690 spin_lock_irqsave(&up->port.lock, flags); 691 /* 692 * Most PC uarts need OUT2 raised to enable interrupts. 693 */ 694 up->port.mctrl |= TIOCM_OUT2; 695 serial_omap_set_mctrl(&up->port, up->port.mctrl); 696 spin_unlock_irqrestore(&up->port.lock, flags); 697 698 up->msr_saved_flags = 0; 699 /* 700 * Finally, enable interrupts. Note: Modem status interrupts 701 * are set via set_termios(), which will be occurring imminently 702 * anyway, so we don't enable them here. 703 */ 704 up->ier = UART_IER_RLSI | UART_IER_RDI; 705 serial_out(up, UART_IER, up->ier); 706 707 /* Enable module level wake up */ 708 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 709 710 pm_runtime_mark_last_busy(up->dev); 711 pm_runtime_put_autosuspend(up->dev); 712 up->port_activity = jiffies; 713 return 0; 714 } 715 716 static void serial_omap_shutdown(struct uart_port *port) 717 { 718 struct uart_omap_port *up = to_uart_omap_port(port); 719 unsigned long flags = 0; 720 721 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 722 723 pm_runtime_get_sync(up->dev); 724 /* 725 * Disable interrupts from this port 726 */ 727 up->ier = 0; 728 serial_out(up, UART_IER, 0); 729 730 spin_lock_irqsave(&up->port.lock, flags); 731 up->port.mctrl &= ~TIOCM_OUT2; 732 serial_omap_set_mctrl(&up->port, up->port.mctrl); 733 spin_unlock_irqrestore(&up->port.lock, flags); 734 735 /* 736 * Disable break condition and FIFOs 737 */ 738 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 739 serial_omap_clear_fifos(up); 740 741 /* 742 * Read data port to reset things, and then free the irq 743 */ 744 if (serial_in(up, UART_LSR) & UART_LSR_DR) 745 (void) serial_in(up, UART_RX); 746 747 pm_runtime_mark_last_busy(up->dev); 748 pm_runtime_put_autosuspend(up->dev); 749 free_irq(up->port.irq, up); 750 } 751 752 static void serial_omap_uart_qos_work(struct work_struct *work) 753 { 754 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 755 qos_work); 756 757 pm_qos_update_request(&up->pm_qos_request, up->latency); 758 if (gpio_is_valid(up->DTR_gpio)) 759 gpio_set_value_cansleep(up->DTR_gpio, 760 up->DTR_active != up->DTR_inverted); 761 } 762 763 static void 764 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 765 struct ktermios *old) 766 { 767 struct uart_omap_port *up = to_uart_omap_port(port); 768 unsigned char cval = 0; 769 unsigned long flags = 0; 770 unsigned int baud, quot; 771 772 switch (termios->c_cflag & CSIZE) { 773 case CS5: 774 cval = UART_LCR_WLEN5; 775 break; 776 case CS6: 777 cval = UART_LCR_WLEN6; 778 break; 779 case CS7: 780 cval = UART_LCR_WLEN7; 781 break; 782 default: 783 case CS8: 784 cval = UART_LCR_WLEN8; 785 break; 786 } 787 788 if (termios->c_cflag & CSTOPB) 789 cval |= UART_LCR_STOP; 790 if (termios->c_cflag & PARENB) 791 cval |= UART_LCR_PARITY; 792 if (!(termios->c_cflag & PARODD)) 793 cval |= UART_LCR_EPAR; 794 if (termios->c_cflag & CMSPAR) 795 cval |= UART_LCR_SPAR; 796 797 /* 798 * Ask the core to calculate the divisor for us. 799 */ 800 801 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 802 quot = serial_omap_get_divisor(port, baud); 803 804 /* calculate wakeup latency constraint */ 805 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 806 up->latency = up->calc_latency; 807 schedule_work(&up->qos_work); 808 809 up->dll = quot & 0xff; 810 up->dlh = quot >> 8; 811 up->mdr1 = UART_OMAP_MDR1_DISABLE; 812 813 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 814 UART_FCR_ENABLE_FIFO; 815 816 /* 817 * Ok, we're now changing the port state. Do it with 818 * interrupts disabled. 819 */ 820 pm_runtime_get_sync(up->dev); 821 spin_lock_irqsave(&up->port.lock, flags); 822 823 /* 824 * Update the per-port timeout. 825 */ 826 uart_update_timeout(port, termios->c_cflag, baud); 827 828 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 829 if (termios->c_iflag & INPCK) 830 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 831 if (termios->c_iflag & (BRKINT | PARMRK)) 832 up->port.read_status_mask |= UART_LSR_BI; 833 834 /* 835 * Characters to ignore 836 */ 837 up->port.ignore_status_mask = 0; 838 if (termios->c_iflag & IGNPAR) 839 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 840 if (termios->c_iflag & IGNBRK) { 841 up->port.ignore_status_mask |= UART_LSR_BI; 842 /* 843 * If we're ignoring parity and break indicators, 844 * ignore overruns too (for real raw support). 845 */ 846 if (termios->c_iflag & IGNPAR) 847 up->port.ignore_status_mask |= UART_LSR_OE; 848 } 849 850 /* 851 * ignore all characters if CREAD is not set 852 */ 853 if ((termios->c_cflag & CREAD) == 0) 854 up->port.ignore_status_mask |= UART_LSR_DR; 855 856 /* 857 * Modem status interrupts 858 */ 859 up->ier &= ~UART_IER_MSI; 860 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 861 up->ier |= UART_IER_MSI; 862 serial_out(up, UART_IER, up->ier); 863 serial_out(up, UART_LCR, cval); /* reset DLAB */ 864 up->lcr = cval; 865 up->scr = 0; 866 867 /* FIFOs and DMA Settings */ 868 869 /* FCR can be changed only when the 870 * baud clock is not running 871 * DLL_REG and DLH_REG set to 0. 872 */ 873 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 874 serial_out(up, UART_DLL, 0); 875 serial_out(up, UART_DLM, 0); 876 serial_out(up, UART_LCR, 0); 877 878 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 879 880 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 881 up->efr &= ~UART_EFR_SCD; 882 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 883 884 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 885 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 886 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 887 /* FIFO ENABLE, DMA MODE */ 888 889 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 890 /* 891 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 892 * sets Enables the granularity of 1 for TRIGGER RX 893 * level. Along with setting RX FIFO trigger level 894 * to 1 (as noted below, 16 characters) and TLR[3:0] 895 * to zero this will result RX FIFO threshold level 896 * to 1 character, instead of 16 as noted in comment 897 * below. 898 */ 899 900 /* Set receive FIFO threshold to 16 characters and 901 * transmit FIFO threshold to 16 spaces 902 */ 903 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 904 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 905 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 906 UART_FCR_ENABLE_FIFO; 907 908 serial_out(up, UART_FCR, up->fcr); 909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 910 911 serial_out(up, UART_OMAP_SCR, up->scr); 912 913 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 914 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 915 serial_out(up, UART_MCR, up->mcr); 916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 917 serial_out(up, UART_EFR, up->efr); 918 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 919 920 /* Protocol, Baud Rate, and Interrupt Settings */ 921 922 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 923 serial_omap_mdr1_errataset(up, up->mdr1); 924 else 925 serial_out(up, UART_OMAP_MDR1, up->mdr1); 926 927 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 928 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 929 930 serial_out(up, UART_LCR, 0); 931 serial_out(up, UART_IER, 0); 932 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 933 934 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 935 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 936 937 serial_out(up, UART_LCR, 0); 938 serial_out(up, UART_IER, up->ier); 939 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 940 941 serial_out(up, UART_EFR, up->efr); 942 serial_out(up, UART_LCR, cval); 943 944 if (!serial_omap_baud_is_mode16(port, baud)) 945 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 946 else 947 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 948 949 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 950 serial_omap_mdr1_errataset(up, up->mdr1); 951 else 952 serial_out(up, UART_OMAP_MDR1, up->mdr1); 953 954 /* Configure flow control */ 955 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 956 957 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 958 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 959 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 960 961 /* Enable access to TCR/TLR */ 962 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 964 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 965 966 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 967 968 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 969 /* Enable AUTORTS and AUTOCTS */ 970 up->efr |= UART_EFR_CTS | UART_EFR_RTS; 971 972 /* Ensure MCR RTS is asserted */ 973 up->mcr |= UART_MCR_RTS; 974 } else { 975 /* Disable AUTORTS and AUTOCTS */ 976 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 977 } 978 979 if (up->port.flags & UPF_SOFT_FLOW) { 980 /* clear SW control mode bits */ 981 up->efr &= OMAP_UART_SW_CLR; 982 983 /* 984 * IXON Flag: 985 * Enable XON/XOFF flow control on input. 986 * Receiver compares XON1, XOFF1. 987 */ 988 if (termios->c_iflag & IXON) 989 up->efr |= OMAP_UART_SW_RX; 990 991 /* 992 * IXOFF Flag: 993 * Enable XON/XOFF flow control on output. 994 * Transmit XON1, XOFF1 995 */ 996 if (termios->c_iflag & IXOFF) 997 up->efr |= OMAP_UART_SW_TX; 998 999 /* 1000 * IXANY Flag: 1001 * Enable any character to restart output. 1002 * Operation resumes after receiving any 1003 * character after recognition of the XOFF character 1004 */ 1005 if (termios->c_iflag & IXANY) 1006 up->mcr |= UART_MCR_XONANY; 1007 else 1008 up->mcr &= ~UART_MCR_XONANY; 1009 } 1010 serial_out(up, UART_MCR, up->mcr); 1011 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1012 serial_out(up, UART_EFR, up->efr); 1013 serial_out(up, UART_LCR, up->lcr); 1014 1015 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1016 1017 spin_unlock_irqrestore(&up->port.lock, flags); 1018 pm_runtime_mark_last_busy(up->dev); 1019 pm_runtime_put_autosuspend(up->dev); 1020 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1021 } 1022 1023 static int serial_omap_set_wake(struct uart_port *port, unsigned int state) 1024 { 1025 struct uart_omap_port *up = to_uart_omap_port(port); 1026 1027 serial_omap_enable_wakeup(up, state); 1028 1029 return 0; 1030 } 1031 1032 static void 1033 serial_omap_pm(struct uart_port *port, unsigned int state, 1034 unsigned int oldstate) 1035 { 1036 struct uart_omap_port *up = to_uart_omap_port(port); 1037 unsigned char efr; 1038 1039 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1040 1041 pm_runtime_get_sync(up->dev); 1042 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1043 efr = serial_in(up, UART_EFR); 1044 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1045 serial_out(up, UART_LCR, 0); 1046 1047 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1048 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1049 serial_out(up, UART_EFR, efr); 1050 serial_out(up, UART_LCR, 0); 1051 1052 if (!device_may_wakeup(up->dev)) { 1053 if (!state) 1054 pm_runtime_forbid(up->dev); 1055 else 1056 pm_runtime_allow(up->dev); 1057 } 1058 1059 pm_runtime_mark_last_busy(up->dev); 1060 pm_runtime_put_autosuspend(up->dev); 1061 } 1062 1063 static void serial_omap_release_port(struct uart_port *port) 1064 { 1065 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1066 } 1067 1068 static int serial_omap_request_port(struct uart_port *port) 1069 { 1070 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1071 return 0; 1072 } 1073 1074 static void serial_omap_config_port(struct uart_port *port, int flags) 1075 { 1076 struct uart_omap_port *up = to_uart_omap_port(port); 1077 1078 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1079 up->port.line); 1080 up->port.type = PORT_OMAP; 1081 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1082 } 1083 1084 static int 1085 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1086 { 1087 /* we don't want the core code to modify any port params */ 1088 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1089 return -EINVAL; 1090 } 1091 1092 static const char * 1093 serial_omap_type(struct uart_port *port) 1094 { 1095 struct uart_omap_port *up = to_uart_omap_port(port); 1096 1097 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1098 return up->name; 1099 } 1100 1101 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1102 1103 static inline void wait_for_xmitr(struct uart_omap_port *up) 1104 { 1105 unsigned int status, tmout = 10000; 1106 1107 /* Wait up to 10ms for the character(s) to be sent. */ 1108 do { 1109 status = serial_in(up, UART_LSR); 1110 1111 if (status & UART_LSR_BI) 1112 up->lsr_break_flag = UART_LSR_BI; 1113 1114 if (--tmout == 0) 1115 break; 1116 udelay(1); 1117 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1118 1119 /* Wait up to 1s for flow control if necessary */ 1120 if (up->port.flags & UPF_CONS_FLOW) { 1121 tmout = 1000000; 1122 for (tmout = 1000000; tmout; tmout--) { 1123 unsigned int msr = serial_in(up, UART_MSR); 1124 1125 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1126 if (msr & UART_MSR_CTS) 1127 break; 1128 1129 udelay(1); 1130 } 1131 } 1132 } 1133 1134 #ifdef CONFIG_CONSOLE_POLL 1135 1136 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1137 { 1138 struct uart_omap_port *up = to_uart_omap_port(port); 1139 1140 pm_runtime_get_sync(up->dev); 1141 wait_for_xmitr(up); 1142 serial_out(up, UART_TX, ch); 1143 pm_runtime_mark_last_busy(up->dev); 1144 pm_runtime_put_autosuspend(up->dev); 1145 } 1146 1147 static int serial_omap_poll_get_char(struct uart_port *port) 1148 { 1149 struct uart_omap_port *up = to_uart_omap_port(port); 1150 unsigned int status; 1151 1152 pm_runtime_get_sync(up->dev); 1153 status = serial_in(up, UART_LSR); 1154 if (!(status & UART_LSR_DR)) { 1155 status = NO_POLL_CHAR; 1156 goto out; 1157 } 1158 1159 status = serial_in(up, UART_RX); 1160 1161 out: 1162 pm_runtime_mark_last_busy(up->dev); 1163 pm_runtime_put_autosuspend(up->dev); 1164 1165 return status; 1166 } 1167 1168 #endif /* CONFIG_CONSOLE_POLL */ 1169 1170 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1171 1172 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1173 1174 static struct uart_driver serial_omap_reg; 1175 1176 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1177 { 1178 struct uart_omap_port *up = to_uart_omap_port(port); 1179 1180 wait_for_xmitr(up); 1181 serial_out(up, UART_TX, ch); 1182 } 1183 1184 static void 1185 serial_omap_console_write(struct console *co, const char *s, 1186 unsigned int count) 1187 { 1188 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1189 unsigned long flags; 1190 unsigned int ier; 1191 int locked = 1; 1192 1193 pm_runtime_get_sync(up->dev); 1194 1195 local_irq_save(flags); 1196 if (up->port.sysrq) 1197 locked = 0; 1198 else if (oops_in_progress) 1199 locked = spin_trylock(&up->port.lock); 1200 else 1201 spin_lock(&up->port.lock); 1202 1203 /* 1204 * First save the IER then disable the interrupts 1205 */ 1206 ier = serial_in(up, UART_IER); 1207 serial_out(up, UART_IER, 0); 1208 1209 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1210 1211 /* 1212 * Finally, wait for transmitter to become empty 1213 * and restore the IER 1214 */ 1215 wait_for_xmitr(up); 1216 serial_out(up, UART_IER, ier); 1217 /* 1218 * The receive handling will happen properly because the 1219 * receive ready bit will still be set; it is not cleared 1220 * on read. However, modem control will not, we must 1221 * call it if we have saved something in the saved flags 1222 * while processing with interrupts off. 1223 */ 1224 if (up->msr_saved_flags) 1225 check_modem_status(up); 1226 1227 pm_runtime_mark_last_busy(up->dev); 1228 pm_runtime_put_autosuspend(up->dev); 1229 if (locked) 1230 spin_unlock(&up->port.lock); 1231 local_irq_restore(flags); 1232 } 1233 1234 static int __init 1235 serial_omap_console_setup(struct console *co, char *options) 1236 { 1237 struct uart_omap_port *up; 1238 int baud = 115200; 1239 int bits = 8; 1240 int parity = 'n'; 1241 int flow = 'n'; 1242 1243 if (serial_omap_console_ports[co->index] == NULL) 1244 return -ENODEV; 1245 up = serial_omap_console_ports[co->index]; 1246 1247 if (options) 1248 uart_parse_options(options, &baud, &parity, &bits, &flow); 1249 1250 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1251 } 1252 1253 static struct console serial_omap_console = { 1254 .name = OMAP_SERIAL_NAME, 1255 .write = serial_omap_console_write, 1256 .device = uart_console_device, 1257 .setup = serial_omap_console_setup, 1258 .flags = CON_PRINTBUFFER, 1259 .index = -1, 1260 .data = &serial_omap_reg, 1261 }; 1262 1263 static void serial_omap_add_console_port(struct uart_omap_port *up) 1264 { 1265 serial_omap_console_ports[up->port.line] = up; 1266 } 1267 1268 #define OMAP_CONSOLE (&serial_omap_console) 1269 1270 #else 1271 1272 #define OMAP_CONSOLE NULL 1273 1274 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1275 {} 1276 1277 #endif 1278 1279 static struct uart_ops serial_omap_pops = { 1280 .tx_empty = serial_omap_tx_empty, 1281 .set_mctrl = serial_omap_set_mctrl, 1282 .get_mctrl = serial_omap_get_mctrl, 1283 .stop_tx = serial_omap_stop_tx, 1284 .start_tx = serial_omap_start_tx, 1285 .throttle = serial_omap_throttle, 1286 .unthrottle = serial_omap_unthrottle, 1287 .stop_rx = serial_omap_stop_rx, 1288 .enable_ms = serial_omap_enable_ms, 1289 .break_ctl = serial_omap_break_ctl, 1290 .startup = serial_omap_startup, 1291 .shutdown = serial_omap_shutdown, 1292 .set_termios = serial_omap_set_termios, 1293 .pm = serial_omap_pm, 1294 .set_wake = serial_omap_set_wake, 1295 .type = serial_omap_type, 1296 .release_port = serial_omap_release_port, 1297 .request_port = serial_omap_request_port, 1298 .config_port = serial_omap_config_port, 1299 .verify_port = serial_omap_verify_port, 1300 #ifdef CONFIG_CONSOLE_POLL 1301 .poll_put_char = serial_omap_poll_put_char, 1302 .poll_get_char = serial_omap_poll_get_char, 1303 #endif 1304 }; 1305 1306 static struct uart_driver serial_omap_reg = { 1307 .owner = THIS_MODULE, 1308 .driver_name = "OMAP-SERIAL", 1309 .dev_name = OMAP_SERIAL_NAME, 1310 .nr = OMAP_MAX_HSUART_PORTS, 1311 .cons = OMAP_CONSOLE, 1312 }; 1313 1314 #ifdef CONFIG_PM_SLEEP 1315 static int serial_omap_suspend(struct device *dev) 1316 { 1317 struct uart_omap_port *up = dev_get_drvdata(dev); 1318 1319 uart_suspend_port(&serial_omap_reg, &up->port); 1320 flush_work(&up->qos_work); 1321 1322 return 0; 1323 } 1324 1325 static int serial_omap_resume(struct device *dev) 1326 { 1327 struct uart_omap_port *up = dev_get_drvdata(dev); 1328 1329 uart_resume_port(&serial_omap_reg, &up->port); 1330 1331 return 0; 1332 } 1333 #endif 1334 1335 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1336 { 1337 u32 mvr, scheme; 1338 u16 revision, major, minor; 1339 1340 mvr = serial_in(up, UART_OMAP_MVER); 1341 1342 /* Check revision register scheme */ 1343 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1344 1345 switch (scheme) { 1346 case 0: /* Legacy Scheme: OMAP2/3 */ 1347 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1348 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1349 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1350 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1351 break; 1352 case 1: 1353 /* New Scheme: OMAP4+ */ 1354 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1355 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1356 OMAP_UART_MVR_MAJ_SHIFT; 1357 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1358 break; 1359 default: 1360 dev_warn(up->dev, 1361 "Unknown %s revision, defaulting to highest\n", 1362 up->name); 1363 /* highest possible revision */ 1364 major = 0xff; 1365 minor = 0xff; 1366 } 1367 1368 /* normalize revision for the driver */ 1369 revision = UART_BUILD_REVISION(major, minor); 1370 1371 switch (revision) { 1372 case OMAP_UART_REV_46: 1373 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1374 UART_ERRATA_i291_DMA_FORCEIDLE); 1375 break; 1376 case OMAP_UART_REV_52: 1377 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1378 UART_ERRATA_i291_DMA_FORCEIDLE); 1379 break; 1380 case OMAP_UART_REV_63: 1381 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1382 break; 1383 default: 1384 break; 1385 } 1386 } 1387 1388 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1389 { 1390 struct omap_uart_port_info *omap_up_info; 1391 1392 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1393 if (!omap_up_info) 1394 return NULL; /* out of memory */ 1395 1396 of_property_read_u32(dev->of_node, "clock-frequency", 1397 &omap_up_info->uartclk); 1398 return omap_up_info; 1399 } 1400 1401 static int serial_omap_probe(struct platform_device *pdev) 1402 { 1403 struct uart_omap_port *up; 1404 struct resource *mem, *irq; 1405 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1406 int ret; 1407 1408 if (pdev->dev.of_node) 1409 omap_up_info = of_get_uart_port_info(&pdev->dev); 1410 1411 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1412 if (!mem) { 1413 dev_err(&pdev->dev, "no mem resource?\n"); 1414 return -ENODEV; 1415 } 1416 1417 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1418 if (!irq) { 1419 dev_err(&pdev->dev, "no irq resource?\n"); 1420 return -ENODEV; 1421 } 1422 1423 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), 1424 pdev->dev.driver->name)) { 1425 dev_err(&pdev->dev, "memory region already claimed\n"); 1426 return -EBUSY; 1427 } 1428 1429 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1430 omap_up_info->DTR_present) { 1431 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); 1432 if (ret < 0) 1433 return ret; 1434 ret = gpio_direction_output(omap_up_info->DTR_gpio, 1435 omap_up_info->DTR_inverted); 1436 if (ret < 0) 1437 return ret; 1438 } 1439 1440 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1441 if (!up) 1442 return -ENOMEM; 1443 1444 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1445 omap_up_info->DTR_present) { 1446 up->DTR_gpio = omap_up_info->DTR_gpio; 1447 up->DTR_inverted = omap_up_info->DTR_inverted; 1448 } else 1449 up->DTR_gpio = -EINVAL; 1450 up->DTR_active = 0; 1451 1452 up->dev = &pdev->dev; 1453 up->port.dev = &pdev->dev; 1454 up->port.type = PORT_OMAP; 1455 up->port.iotype = UPIO_MEM; 1456 up->port.irq = irq->start; 1457 1458 up->port.regshift = 2; 1459 up->port.fifosize = 64; 1460 up->port.ops = &serial_omap_pops; 1461 1462 if (pdev->dev.of_node) 1463 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); 1464 else 1465 up->port.line = pdev->id; 1466 1467 if (up->port.line < 0) { 1468 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1469 up->port.line); 1470 ret = -ENODEV; 1471 goto err_port_line; 1472 } 1473 1474 up->pins = devm_pinctrl_get_select_default(&pdev->dev); 1475 if (IS_ERR(up->pins)) { 1476 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n", 1477 up->port.line, PTR_ERR(up->pins)); 1478 up->pins = NULL; 1479 } 1480 1481 sprintf(up->name, "OMAP UART%d", up->port.line); 1482 up->port.mapbase = mem->start; 1483 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1484 resource_size(mem)); 1485 if (!up->port.membase) { 1486 dev_err(&pdev->dev, "can't ioremap UART\n"); 1487 ret = -ENOMEM; 1488 goto err_ioremap; 1489 } 1490 1491 up->port.flags = omap_up_info->flags; 1492 up->port.uartclk = omap_up_info->uartclk; 1493 if (!up->port.uartclk) { 1494 up->port.uartclk = DEFAULT_CLK_SPEED; 1495 dev_warn(&pdev->dev, "No clock speed specified: using default:" 1496 "%d\n", DEFAULT_CLK_SPEED); 1497 } 1498 1499 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1500 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1501 pm_qos_add_request(&up->pm_qos_request, 1502 PM_QOS_CPU_DMA_LATENCY, up->latency); 1503 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1504 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1505 1506 platform_set_drvdata(pdev, up); 1507 pm_runtime_enable(&pdev->dev); 1508 pm_runtime_use_autosuspend(&pdev->dev); 1509 pm_runtime_set_autosuspend_delay(&pdev->dev, 1510 omap_up_info->autosuspend_timeout); 1511 1512 pm_runtime_irq_safe(&pdev->dev); 1513 pm_runtime_get_sync(&pdev->dev); 1514 1515 omap_serial_fill_features_erratas(up); 1516 1517 ui[up->port.line] = up; 1518 serial_omap_add_console_port(up); 1519 1520 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1521 if (ret != 0) 1522 goto err_add_port; 1523 1524 pm_runtime_mark_last_busy(up->dev); 1525 pm_runtime_put_autosuspend(up->dev); 1526 return 0; 1527 1528 err_add_port: 1529 pm_runtime_put(&pdev->dev); 1530 pm_runtime_disable(&pdev->dev); 1531 err_ioremap: 1532 err_port_line: 1533 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1534 pdev->id, __func__, ret); 1535 return ret; 1536 } 1537 1538 static int serial_omap_remove(struct platform_device *dev) 1539 { 1540 struct uart_omap_port *up = platform_get_drvdata(dev); 1541 1542 pm_runtime_put_sync(up->dev); 1543 pm_runtime_disable(up->dev); 1544 uart_remove_one_port(&serial_omap_reg, &up->port); 1545 pm_qos_remove_request(&up->pm_qos_request); 1546 1547 return 0; 1548 } 1549 1550 /* 1551 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1552 * The access to uart register after MDR1 Access 1553 * causes UART to corrupt data. 1554 * 1555 * Need a delay = 1556 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1557 * give 10 times as much 1558 */ 1559 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1560 { 1561 u8 timeout = 255; 1562 1563 serial_out(up, UART_OMAP_MDR1, mdr1); 1564 udelay(2); 1565 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1566 UART_FCR_CLEAR_RCVR); 1567 /* 1568 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1569 * TX_FIFO_E bit is 1. 1570 */ 1571 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1572 (UART_LSR_THRE | UART_LSR_DR))) { 1573 timeout--; 1574 if (!timeout) { 1575 /* Should *never* happen. we warn and carry on */ 1576 dev_crit(up->dev, "Errata i202: timedout %x\n", 1577 serial_in(up, UART_LSR)); 1578 break; 1579 } 1580 udelay(1); 1581 } 1582 } 1583 1584 #ifdef CONFIG_PM_RUNTIME 1585 static void serial_omap_restore_context(struct uart_omap_port *up) 1586 { 1587 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1588 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1589 else 1590 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1591 1592 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1593 serial_out(up, UART_EFR, UART_EFR_ECB); 1594 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1595 serial_out(up, UART_IER, 0x0); 1596 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1597 serial_out(up, UART_DLL, up->dll); 1598 serial_out(up, UART_DLM, up->dlh); 1599 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1600 serial_out(up, UART_IER, up->ier); 1601 serial_out(up, UART_FCR, up->fcr); 1602 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1603 serial_out(up, UART_MCR, up->mcr); 1604 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1605 serial_out(up, UART_OMAP_SCR, up->scr); 1606 serial_out(up, UART_EFR, up->efr); 1607 serial_out(up, UART_LCR, up->lcr); 1608 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1609 serial_omap_mdr1_errataset(up, up->mdr1); 1610 else 1611 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1612 } 1613 1614 static int serial_omap_runtime_suspend(struct device *dev) 1615 { 1616 struct uart_omap_port *up = dev_get_drvdata(dev); 1617 struct omap_uart_port_info *pdata = dev->platform_data; 1618 1619 if (!up) 1620 return -EINVAL; 1621 1622 if (!pdata) 1623 return 0; 1624 1625 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1626 1627 if (device_may_wakeup(dev)) { 1628 if (!up->wakeups_enabled) { 1629 serial_omap_enable_wakeup(up, true); 1630 up->wakeups_enabled = true; 1631 } 1632 } else { 1633 if (up->wakeups_enabled) { 1634 serial_omap_enable_wakeup(up, false); 1635 up->wakeups_enabled = false; 1636 } 1637 } 1638 1639 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1640 schedule_work(&up->qos_work); 1641 1642 return 0; 1643 } 1644 1645 static int serial_omap_runtime_resume(struct device *dev) 1646 { 1647 struct uart_omap_port *up = dev_get_drvdata(dev); 1648 1649 int loss_cnt = serial_omap_get_context_loss_count(up); 1650 1651 if (loss_cnt < 0) { 1652 dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n", 1653 loss_cnt); 1654 serial_omap_restore_context(up); 1655 } else if (up->context_loss_cnt != loss_cnt) { 1656 serial_omap_restore_context(up); 1657 } 1658 up->latency = up->calc_latency; 1659 schedule_work(&up->qos_work); 1660 1661 return 0; 1662 } 1663 #endif 1664 1665 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1666 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1667 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1668 serial_omap_runtime_resume, NULL) 1669 }; 1670 1671 #if defined(CONFIG_OF) 1672 static const struct of_device_id omap_serial_of_match[] = { 1673 { .compatible = "ti,omap2-uart" }, 1674 { .compatible = "ti,omap3-uart" }, 1675 { .compatible = "ti,omap4-uart" }, 1676 {}, 1677 }; 1678 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1679 #endif 1680 1681 static struct platform_driver serial_omap_driver = { 1682 .probe = serial_omap_probe, 1683 .remove = serial_omap_remove, 1684 .driver = { 1685 .name = DRIVER_NAME, 1686 .pm = &serial_omap_dev_pm_ops, 1687 .of_match_table = of_match_ptr(omap_serial_of_match), 1688 }, 1689 }; 1690 1691 static int __init serial_omap_init(void) 1692 { 1693 int ret; 1694 1695 ret = uart_register_driver(&serial_omap_reg); 1696 if (ret != 0) 1697 return ret; 1698 ret = platform_driver_register(&serial_omap_driver); 1699 if (ret != 0) 1700 uart_unregister_driver(&serial_omap_reg); 1701 return ret; 1702 } 1703 1704 static void __exit serial_omap_exit(void) 1705 { 1706 platform_driver_unregister(&serial_omap_driver); 1707 uart_unregister_driver(&serial_omap_reg); 1708 } 1709 1710 module_init(serial_omap_init); 1711 module_exit(serial_omap_exit); 1712 1713 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1714 MODULE_LICENSE("GPL"); 1715 MODULE_AUTHOR("Texas Instruments Inc"); 1716