1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/io.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/gpio.h> 43 #include <linux/pinctrl/consumer.h> 44 #include <linux/platform_data/serial-omap.h> 45 46 #define OMAP_MAX_HSUART_PORTS 6 47 48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 49 50 #define OMAP_UART_REV_42 0x0402 51 #define OMAP_UART_REV_46 0x0406 52 #define OMAP_UART_REV_52 0x0502 53 #define OMAP_UART_REV_63 0x0603 54 55 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 56 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 57 58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ 59 60 /* SCR register bitmasks */ 61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 62 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 63 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 64 65 /* FCR register bitmasks */ 66 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 67 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 68 69 /* MVR register bitmasks */ 70 #define OMAP_UART_MVR_SCHEME_SHIFT 30 71 72 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 73 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 74 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 75 76 #define OMAP_UART_MVR_MAJ_MASK 0x700 77 #define OMAP_UART_MVR_MAJ_SHIFT 8 78 #define OMAP_UART_MVR_MIN_MASK 0x3f 79 80 #define OMAP_UART_DMA_CH_FREE -1 81 82 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 83 #define OMAP_MODE13X_SPEED 230400 84 85 /* WER = 0x7F 86 * Enable module level wakeup in WER reg 87 */ 88 #define OMAP_UART_WER_MOD_WKUP 0X7F 89 90 /* Enable XON/XOFF flow control on output */ 91 #define OMAP_UART_SW_TX 0x08 92 93 /* Enable XON/XOFF flow control on input */ 94 #define OMAP_UART_SW_RX 0x02 95 96 #define OMAP_UART_SW_CLR 0xF0 97 98 #define OMAP_UART_TCR_TRIG 0x0F 99 100 struct uart_omap_dma { 101 u8 uart_dma_tx; 102 u8 uart_dma_rx; 103 int rx_dma_channel; 104 int tx_dma_channel; 105 dma_addr_t rx_buf_dma_phys; 106 dma_addr_t tx_buf_dma_phys; 107 unsigned int uart_base; 108 /* 109 * Buffer for rx dma.It is not required for tx because the buffer 110 * comes from port structure. 111 */ 112 unsigned char *rx_buf; 113 unsigned int prev_rx_dma_pos; 114 int tx_buf_size; 115 int tx_dma_used; 116 int rx_dma_used; 117 spinlock_t tx_lock; 118 spinlock_t rx_lock; 119 /* timer to poll activity on rx dma */ 120 struct timer_list rx_timer; 121 unsigned int rx_buf_size; 122 unsigned int rx_poll_rate; 123 unsigned int rx_timeout; 124 }; 125 126 struct uart_omap_port { 127 struct uart_port port; 128 struct uart_omap_dma uart_dma; 129 struct device *dev; 130 131 unsigned char ier; 132 unsigned char lcr; 133 unsigned char mcr; 134 unsigned char fcr; 135 unsigned char efr; 136 unsigned char dll; 137 unsigned char dlh; 138 unsigned char mdr1; 139 unsigned char scr; 140 141 int use_dma; 142 /* 143 * Some bits in registers are cleared on a read, so they must 144 * be saved whenever the register is read but the bits will not 145 * be immediately processed. 146 */ 147 unsigned int lsr_break_flag; 148 unsigned char msr_saved_flags; 149 char name[20]; 150 unsigned long port_activity; 151 int context_loss_cnt; 152 u32 errata; 153 u8 wakeups_enabled; 154 155 int DTR_gpio; 156 int DTR_inverted; 157 int DTR_active; 158 159 struct pm_qos_request pm_qos_request; 160 u32 latency; 161 u32 calc_latency; 162 struct work_struct qos_work; 163 struct pinctrl *pins; 164 }; 165 166 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 167 168 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 169 170 /* Forward declaration of functions */ 171 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 172 173 static struct workqueue_struct *serial_omap_uart_wq; 174 175 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 176 { 177 offset <<= up->port.regshift; 178 return readw(up->port.membase + offset); 179 } 180 181 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 182 { 183 offset <<= up->port.regshift; 184 writew(value, up->port.membase + offset); 185 } 186 187 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 188 { 189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 190 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 191 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 192 serial_out(up, UART_FCR, 0); 193 } 194 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 196 { 197 struct omap_uart_port_info *pdata = up->dev->platform_data; 198 199 if (!pdata || !pdata->get_context_loss_count) 200 return 0; 201 202 return pdata->get_context_loss_count(up->dev); 203 } 204 205 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 206 { 207 struct omap_uart_port_info *pdata = up->dev->platform_data; 208 209 if (!pdata || !pdata->enable_wakeup) 210 return; 211 212 pdata->enable_wakeup(up->dev, enable); 213 } 214 215 /* 216 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 217 * @port: uart port info 218 * @baud: baudrate for which mode needs to be determined 219 * 220 * Returns true if baud rate is MODE16X and false if MODE13X 221 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 222 * and Error Rates" determines modes not for all common baud rates. 223 * E.g. for 1000000 baud rate mode must be 16x, but according to that 224 * table it's determined as 13x. 225 */ 226 static bool 227 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 228 { 229 unsigned int n13 = port->uartclk / (13 * baud); 230 unsigned int n16 = port->uartclk / (16 * baud); 231 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13)); 232 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16)); 233 if(baudAbsDiff13 < 0) 234 baudAbsDiff13 = -baudAbsDiff13; 235 if(baudAbsDiff16 < 0) 236 baudAbsDiff16 = -baudAbsDiff16; 237 238 return (baudAbsDiff13 > baudAbsDiff16); 239 } 240 241 /* 242 * serial_omap_get_divisor - calculate divisor value 243 * @port: uart port info 244 * @baud: baudrate for which divisor needs to be calculated. 245 */ 246 static unsigned int 247 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 248 { 249 unsigned int divisor; 250 251 if (!serial_omap_baud_is_mode16(port, baud)) 252 divisor = 13; 253 else 254 divisor = 16; 255 return port->uartclk/(baud * divisor); 256 } 257 258 static void serial_omap_enable_ms(struct uart_port *port) 259 { 260 struct uart_omap_port *up = to_uart_omap_port(port); 261 262 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 263 264 pm_runtime_get_sync(up->dev); 265 up->ier |= UART_IER_MSI; 266 serial_out(up, UART_IER, up->ier); 267 pm_runtime_mark_last_busy(up->dev); 268 pm_runtime_put_autosuspend(up->dev); 269 } 270 271 static void serial_omap_stop_tx(struct uart_port *port) 272 { 273 struct uart_omap_port *up = to_uart_omap_port(port); 274 275 pm_runtime_get_sync(up->dev); 276 if (up->ier & UART_IER_THRI) { 277 up->ier &= ~UART_IER_THRI; 278 serial_out(up, UART_IER, up->ier); 279 } 280 281 pm_runtime_mark_last_busy(up->dev); 282 pm_runtime_put_autosuspend(up->dev); 283 } 284 285 static void serial_omap_stop_rx(struct uart_port *port) 286 { 287 struct uart_omap_port *up = to_uart_omap_port(port); 288 289 pm_runtime_get_sync(up->dev); 290 up->ier &= ~UART_IER_RLSI; 291 up->port.read_status_mask &= ~UART_LSR_DR; 292 serial_out(up, UART_IER, up->ier); 293 pm_runtime_mark_last_busy(up->dev); 294 pm_runtime_put_autosuspend(up->dev); 295 } 296 297 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 298 { 299 struct circ_buf *xmit = &up->port.state->xmit; 300 int count; 301 302 if (up->port.x_char) { 303 serial_out(up, UART_TX, up->port.x_char); 304 up->port.icount.tx++; 305 up->port.x_char = 0; 306 return; 307 } 308 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 309 serial_omap_stop_tx(&up->port); 310 return; 311 } 312 count = up->port.fifosize / 4; 313 do { 314 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 315 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 316 up->port.icount.tx++; 317 if (uart_circ_empty(xmit)) 318 break; 319 } while (--count > 0); 320 321 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 322 spin_unlock(&up->port.lock); 323 uart_write_wakeup(&up->port); 324 spin_lock(&up->port.lock); 325 } 326 327 if (uart_circ_empty(xmit)) 328 serial_omap_stop_tx(&up->port); 329 } 330 331 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 332 { 333 if (!(up->ier & UART_IER_THRI)) { 334 up->ier |= UART_IER_THRI; 335 serial_out(up, UART_IER, up->ier); 336 } 337 } 338 339 static void serial_omap_start_tx(struct uart_port *port) 340 { 341 struct uart_omap_port *up = to_uart_omap_port(port); 342 343 pm_runtime_get_sync(up->dev); 344 serial_omap_enable_ier_thri(up); 345 pm_runtime_mark_last_busy(up->dev); 346 pm_runtime_put_autosuspend(up->dev); 347 } 348 349 static void serial_omap_throttle(struct uart_port *port) 350 { 351 struct uart_omap_port *up = to_uart_omap_port(port); 352 unsigned long flags; 353 354 pm_runtime_get_sync(up->dev); 355 spin_lock_irqsave(&up->port.lock, flags); 356 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 357 serial_out(up, UART_IER, up->ier); 358 spin_unlock_irqrestore(&up->port.lock, flags); 359 pm_runtime_mark_last_busy(up->dev); 360 pm_runtime_put_autosuspend(up->dev); 361 } 362 363 static void serial_omap_unthrottle(struct uart_port *port) 364 { 365 struct uart_omap_port *up = to_uart_omap_port(port); 366 unsigned long flags; 367 368 pm_runtime_get_sync(up->dev); 369 spin_lock_irqsave(&up->port.lock, flags); 370 up->ier |= UART_IER_RLSI | UART_IER_RDI; 371 serial_out(up, UART_IER, up->ier); 372 spin_unlock_irqrestore(&up->port.lock, flags); 373 pm_runtime_mark_last_busy(up->dev); 374 pm_runtime_put_autosuspend(up->dev); 375 } 376 377 static unsigned int check_modem_status(struct uart_omap_port *up) 378 { 379 unsigned int status; 380 381 status = serial_in(up, UART_MSR); 382 status |= up->msr_saved_flags; 383 up->msr_saved_flags = 0; 384 if ((status & UART_MSR_ANY_DELTA) == 0) 385 return status; 386 387 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 388 up->port.state != NULL) { 389 if (status & UART_MSR_TERI) 390 up->port.icount.rng++; 391 if (status & UART_MSR_DDSR) 392 up->port.icount.dsr++; 393 if (status & UART_MSR_DDCD) 394 uart_handle_dcd_change 395 (&up->port, status & UART_MSR_DCD); 396 if (status & UART_MSR_DCTS) 397 uart_handle_cts_change 398 (&up->port, status & UART_MSR_CTS); 399 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 400 } 401 402 return status; 403 } 404 405 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 406 { 407 unsigned int flag; 408 unsigned char ch = 0; 409 410 if (likely(lsr & UART_LSR_DR)) 411 ch = serial_in(up, UART_RX); 412 413 up->port.icount.rx++; 414 flag = TTY_NORMAL; 415 416 if (lsr & UART_LSR_BI) { 417 flag = TTY_BREAK; 418 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 419 up->port.icount.brk++; 420 /* 421 * We do the SysRQ and SAK checking 422 * here because otherwise the break 423 * may get masked by ignore_status_mask 424 * or read_status_mask. 425 */ 426 if (uart_handle_break(&up->port)) 427 return; 428 429 } 430 431 if (lsr & UART_LSR_PE) { 432 flag = TTY_PARITY; 433 up->port.icount.parity++; 434 } 435 436 if (lsr & UART_LSR_FE) { 437 flag = TTY_FRAME; 438 up->port.icount.frame++; 439 } 440 441 if (lsr & UART_LSR_OE) 442 up->port.icount.overrun++; 443 444 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 445 if (up->port.line == up->port.cons->index) { 446 /* Recover the break flag from console xmit */ 447 lsr |= up->lsr_break_flag; 448 } 449 #endif 450 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 451 } 452 453 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 454 { 455 unsigned char ch = 0; 456 unsigned int flag; 457 458 if (!(lsr & UART_LSR_DR)) 459 return; 460 461 ch = serial_in(up, UART_RX); 462 flag = TTY_NORMAL; 463 up->port.icount.rx++; 464 465 if (uart_handle_sysrq_char(&up->port, ch)) 466 return; 467 468 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 469 } 470 471 /** 472 * serial_omap_irq() - This handles the interrupt from one port 473 * @irq: uart port irq number 474 * @dev_id: uart port info 475 */ 476 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 477 { 478 struct uart_omap_port *up = dev_id; 479 unsigned int iir, lsr; 480 unsigned int type; 481 irqreturn_t ret = IRQ_NONE; 482 int max_count = 256; 483 484 spin_lock(&up->port.lock); 485 pm_runtime_get_sync(up->dev); 486 487 do { 488 iir = serial_in(up, UART_IIR); 489 if (iir & UART_IIR_NO_INT) 490 break; 491 492 ret = IRQ_HANDLED; 493 lsr = serial_in(up, UART_LSR); 494 495 /* extract IRQ type from IIR register */ 496 type = iir & 0x3e; 497 498 switch (type) { 499 case UART_IIR_MSI: 500 check_modem_status(up); 501 break; 502 case UART_IIR_THRI: 503 transmit_chars(up, lsr); 504 break; 505 case UART_IIR_RX_TIMEOUT: 506 /* FALLTHROUGH */ 507 case UART_IIR_RDI: 508 serial_omap_rdi(up, lsr); 509 break; 510 case UART_IIR_RLSI: 511 serial_omap_rlsi(up, lsr); 512 break; 513 case UART_IIR_CTS_RTS_DSR: 514 /* simply try again */ 515 break; 516 case UART_IIR_XOFF: 517 /* FALLTHROUGH */ 518 default: 519 break; 520 } 521 } while (!(iir & UART_IIR_NO_INT) && max_count--); 522 523 spin_unlock(&up->port.lock); 524 525 tty_flip_buffer_push(&up->port.state->port); 526 527 pm_runtime_mark_last_busy(up->dev); 528 pm_runtime_put_autosuspend(up->dev); 529 up->port_activity = jiffies; 530 531 return ret; 532 } 533 534 static unsigned int serial_omap_tx_empty(struct uart_port *port) 535 { 536 struct uart_omap_port *up = to_uart_omap_port(port); 537 unsigned long flags = 0; 538 unsigned int ret = 0; 539 540 pm_runtime_get_sync(up->dev); 541 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 542 spin_lock_irqsave(&up->port.lock, flags); 543 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 544 spin_unlock_irqrestore(&up->port.lock, flags); 545 pm_runtime_mark_last_busy(up->dev); 546 pm_runtime_put_autosuspend(up->dev); 547 return ret; 548 } 549 550 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 551 { 552 struct uart_omap_port *up = to_uart_omap_port(port); 553 unsigned int status; 554 unsigned int ret = 0; 555 556 pm_runtime_get_sync(up->dev); 557 status = check_modem_status(up); 558 pm_runtime_mark_last_busy(up->dev); 559 pm_runtime_put_autosuspend(up->dev); 560 561 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 562 563 if (status & UART_MSR_DCD) 564 ret |= TIOCM_CAR; 565 if (status & UART_MSR_RI) 566 ret |= TIOCM_RNG; 567 if (status & UART_MSR_DSR) 568 ret |= TIOCM_DSR; 569 if (status & UART_MSR_CTS) 570 ret |= TIOCM_CTS; 571 return ret; 572 } 573 574 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 575 { 576 struct uart_omap_port *up = to_uart_omap_port(port); 577 unsigned char mcr = 0, old_mcr; 578 579 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 580 if (mctrl & TIOCM_RTS) 581 mcr |= UART_MCR_RTS; 582 if (mctrl & TIOCM_DTR) 583 mcr |= UART_MCR_DTR; 584 if (mctrl & TIOCM_OUT1) 585 mcr |= UART_MCR_OUT1; 586 if (mctrl & TIOCM_OUT2) 587 mcr |= UART_MCR_OUT2; 588 if (mctrl & TIOCM_LOOP) 589 mcr |= UART_MCR_LOOP; 590 591 pm_runtime_get_sync(up->dev); 592 old_mcr = serial_in(up, UART_MCR); 593 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 594 UART_MCR_DTR | UART_MCR_RTS); 595 up->mcr = old_mcr | mcr; 596 serial_out(up, UART_MCR, up->mcr); 597 pm_runtime_mark_last_busy(up->dev); 598 pm_runtime_put_autosuspend(up->dev); 599 600 if (gpio_is_valid(up->DTR_gpio) && 601 !!(mctrl & TIOCM_DTR) != up->DTR_active) { 602 up->DTR_active = !up->DTR_active; 603 if (gpio_cansleep(up->DTR_gpio)) 604 schedule_work(&up->qos_work); 605 else 606 gpio_set_value(up->DTR_gpio, 607 up->DTR_active != up->DTR_inverted); 608 } 609 } 610 611 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 612 { 613 struct uart_omap_port *up = to_uart_omap_port(port); 614 unsigned long flags = 0; 615 616 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 617 pm_runtime_get_sync(up->dev); 618 spin_lock_irqsave(&up->port.lock, flags); 619 if (break_state == -1) 620 up->lcr |= UART_LCR_SBC; 621 else 622 up->lcr &= ~UART_LCR_SBC; 623 serial_out(up, UART_LCR, up->lcr); 624 spin_unlock_irqrestore(&up->port.lock, flags); 625 pm_runtime_mark_last_busy(up->dev); 626 pm_runtime_put_autosuspend(up->dev); 627 } 628 629 static int serial_omap_startup(struct uart_port *port) 630 { 631 struct uart_omap_port *up = to_uart_omap_port(port); 632 unsigned long flags = 0; 633 int retval; 634 635 /* 636 * Allocate the IRQ 637 */ 638 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 639 up->name, up); 640 if (retval) 641 return retval; 642 643 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 644 645 pm_runtime_get_sync(up->dev); 646 /* 647 * Clear the FIFO buffers and disable them. 648 * (they will be reenabled in set_termios()) 649 */ 650 serial_omap_clear_fifos(up); 651 /* For Hardware flow control */ 652 serial_out(up, UART_MCR, UART_MCR_RTS); 653 654 /* 655 * Clear the interrupt registers. 656 */ 657 (void) serial_in(up, UART_LSR); 658 if (serial_in(up, UART_LSR) & UART_LSR_DR) 659 (void) serial_in(up, UART_RX); 660 (void) serial_in(up, UART_IIR); 661 (void) serial_in(up, UART_MSR); 662 663 /* 664 * Now, initialize the UART 665 */ 666 serial_out(up, UART_LCR, UART_LCR_WLEN8); 667 spin_lock_irqsave(&up->port.lock, flags); 668 /* 669 * Most PC uarts need OUT2 raised to enable interrupts. 670 */ 671 up->port.mctrl |= TIOCM_OUT2; 672 serial_omap_set_mctrl(&up->port, up->port.mctrl); 673 spin_unlock_irqrestore(&up->port.lock, flags); 674 675 up->msr_saved_flags = 0; 676 /* 677 * Finally, enable interrupts. Note: Modem status interrupts 678 * are set via set_termios(), which will be occurring imminently 679 * anyway, so we don't enable them here. 680 */ 681 up->ier = UART_IER_RLSI | UART_IER_RDI; 682 serial_out(up, UART_IER, up->ier); 683 684 /* Enable module level wake up */ 685 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 686 687 pm_runtime_mark_last_busy(up->dev); 688 pm_runtime_put_autosuspend(up->dev); 689 up->port_activity = jiffies; 690 return 0; 691 } 692 693 static void serial_omap_shutdown(struct uart_port *port) 694 { 695 struct uart_omap_port *up = to_uart_omap_port(port); 696 unsigned long flags = 0; 697 698 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 699 700 pm_runtime_get_sync(up->dev); 701 /* 702 * Disable interrupts from this port 703 */ 704 up->ier = 0; 705 serial_out(up, UART_IER, 0); 706 707 spin_lock_irqsave(&up->port.lock, flags); 708 up->port.mctrl &= ~TIOCM_OUT2; 709 serial_omap_set_mctrl(&up->port, up->port.mctrl); 710 spin_unlock_irqrestore(&up->port.lock, flags); 711 712 /* 713 * Disable break condition and FIFOs 714 */ 715 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 716 serial_omap_clear_fifos(up); 717 718 /* 719 * Read data port to reset things, and then free the irq 720 */ 721 if (serial_in(up, UART_LSR) & UART_LSR_DR) 722 (void) serial_in(up, UART_RX); 723 724 pm_runtime_mark_last_busy(up->dev); 725 pm_runtime_put_autosuspend(up->dev); 726 free_irq(up->port.irq, up); 727 } 728 729 static void serial_omap_uart_qos_work(struct work_struct *work) 730 { 731 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 732 qos_work); 733 734 pm_qos_update_request(&up->pm_qos_request, up->latency); 735 if (gpio_is_valid(up->DTR_gpio)) 736 gpio_set_value_cansleep(up->DTR_gpio, 737 up->DTR_active != up->DTR_inverted); 738 } 739 740 static void 741 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 742 struct ktermios *old) 743 { 744 struct uart_omap_port *up = to_uart_omap_port(port); 745 unsigned char cval = 0; 746 unsigned long flags = 0; 747 unsigned int baud, quot; 748 749 switch (termios->c_cflag & CSIZE) { 750 case CS5: 751 cval = UART_LCR_WLEN5; 752 break; 753 case CS6: 754 cval = UART_LCR_WLEN6; 755 break; 756 case CS7: 757 cval = UART_LCR_WLEN7; 758 break; 759 default: 760 case CS8: 761 cval = UART_LCR_WLEN8; 762 break; 763 } 764 765 if (termios->c_cflag & CSTOPB) 766 cval |= UART_LCR_STOP; 767 if (termios->c_cflag & PARENB) 768 cval |= UART_LCR_PARITY; 769 if (!(termios->c_cflag & PARODD)) 770 cval |= UART_LCR_EPAR; 771 if (termios->c_cflag & CMSPAR) 772 cval |= UART_LCR_SPAR; 773 774 /* 775 * Ask the core to calculate the divisor for us. 776 */ 777 778 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 779 quot = serial_omap_get_divisor(port, baud); 780 781 /* calculate wakeup latency constraint */ 782 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 783 up->latency = up->calc_latency; 784 schedule_work(&up->qos_work); 785 786 up->dll = quot & 0xff; 787 up->dlh = quot >> 8; 788 up->mdr1 = UART_OMAP_MDR1_DISABLE; 789 790 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 791 UART_FCR_ENABLE_FIFO; 792 793 /* 794 * Ok, we're now changing the port state. Do it with 795 * interrupts disabled. 796 */ 797 pm_runtime_get_sync(up->dev); 798 spin_lock_irqsave(&up->port.lock, flags); 799 800 /* 801 * Update the per-port timeout. 802 */ 803 uart_update_timeout(port, termios->c_cflag, baud); 804 805 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 806 if (termios->c_iflag & INPCK) 807 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 808 if (termios->c_iflag & (BRKINT | PARMRK)) 809 up->port.read_status_mask |= UART_LSR_BI; 810 811 /* 812 * Characters to ignore 813 */ 814 up->port.ignore_status_mask = 0; 815 if (termios->c_iflag & IGNPAR) 816 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 817 if (termios->c_iflag & IGNBRK) { 818 up->port.ignore_status_mask |= UART_LSR_BI; 819 /* 820 * If we're ignoring parity and break indicators, 821 * ignore overruns too (for real raw support). 822 */ 823 if (termios->c_iflag & IGNPAR) 824 up->port.ignore_status_mask |= UART_LSR_OE; 825 } 826 827 /* 828 * ignore all characters if CREAD is not set 829 */ 830 if ((termios->c_cflag & CREAD) == 0) 831 up->port.ignore_status_mask |= UART_LSR_DR; 832 833 /* 834 * Modem status interrupts 835 */ 836 up->ier &= ~UART_IER_MSI; 837 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 838 up->ier |= UART_IER_MSI; 839 serial_out(up, UART_IER, up->ier); 840 serial_out(up, UART_LCR, cval); /* reset DLAB */ 841 up->lcr = cval; 842 up->scr = 0; 843 844 /* FIFOs and DMA Settings */ 845 846 /* FCR can be changed only when the 847 * baud clock is not running 848 * DLL_REG and DLH_REG set to 0. 849 */ 850 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 851 serial_out(up, UART_DLL, 0); 852 serial_out(up, UART_DLM, 0); 853 serial_out(up, UART_LCR, 0); 854 855 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 856 857 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 858 up->efr &= ~UART_EFR_SCD; 859 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 860 861 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 862 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 863 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 864 /* FIFO ENABLE, DMA MODE */ 865 866 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 867 /* 868 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 869 * sets Enables the granularity of 1 for TRIGGER RX 870 * level. Along with setting RX FIFO trigger level 871 * to 1 (as noted below, 16 characters) and TLR[3:0] 872 * to zero this will result RX FIFO threshold level 873 * to 1 character, instead of 16 as noted in comment 874 * below. 875 */ 876 877 /* Set receive FIFO threshold to 16 characters and 878 * transmit FIFO threshold to 16 spaces 879 */ 880 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 881 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 882 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 883 UART_FCR_ENABLE_FIFO; 884 885 serial_out(up, UART_FCR, up->fcr); 886 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 887 888 serial_out(up, UART_OMAP_SCR, up->scr); 889 890 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 891 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 892 serial_out(up, UART_MCR, up->mcr); 893 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 894 serial_out(up, UART_EFR, up->efr); 895 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 896 897 /* Protocol, Baud Rate, and Interrupt Settings */ 898 899 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 900 serial_omap_mdr1_errataset(up, up->mdr1); 901 else 902 serial_out(up, UART_OMAP_MDR1, up->mdr1); 903 904 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 905 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 906 907 serial_out(up, UART_LCR, 0); 908 serial_out(up, UART_IER, 0); 909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 910 911 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 912 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 913 914 serial_out(up, UART_LCR, 0); 915 serial_out(up, UART_IER, up->ier); 916 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 917 918 serial_out(up, UART_EFR, up->efr); 919 serial_out(up, UART_LCR, cval); 920 921 if (!serial_omap_baud_is_mode16(port, baud)) 922 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 923 else 924 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 925 926 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 927 serial_omap_mdr1_errataset(up, up->mdr1); 928 else 929 serial_out(up, UART_OMAP_MDR1, up->mdr1); 930 931 /* Configure flow control */ 932 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 933 934 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 935 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 936 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 937 938 /* Enable access to TCR/TLR */ 939 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 940 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 941 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 942 943 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 944 945 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 946 /* Enable AUTORTS and AUTOCTS */ 947 up->efr |= UART_EFR_CTS | UART_EFR_RTS; 948 949 /* Ensure MCR RTS is asserted */ 950 up->mcr |= UART_MCR_RTS; 951 } else { 952 /* Disable AUTORTS and AUTOCTS */ 953 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 954 } 955 956 if (up->port.flags & UPF_SOFT_FLOW) { 957 /* clear SW control mode bits */ 958 up->efr &= OMAP_UART_SW_CLR; 959 960 /* 961 * IXON Flag: 962 * Enable XON/XOFF flow control on input. 963 * Receiver compares XON1, XOFF1. 964 */ 965 if (termios->c_iflag & IXON) 966 up->efr |= OMAP_UART_SW_RX; 967 968 /* 969 * IXOFF Flag: 970 * Enable XON/XOFF flow control on output. 971 * Transmit XON1, XOFF1 972 */ 973 if (termios->c_iflag & IXOFF) 974 up->efr |= OMAP_UART_SW_TX; 975 976 /* 977 * IXANY Flag: 978 * Enable any character to restart output. 979 * Operation resumes after receiving any 980 * character after recognition of the XOFF character 981 */ 982 if (termios->c_iflag & IXANY) 983 up->mcr |= UART_MCR_XONANY; 984 else 985 up->mcr &= ~UART_MCR_XONANY; 986 } 987 serial_out(up, UART_MCR, up->mcr); 988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 989 serial_out(up, UART_EFR, up->efr); 990 serial_out(up, UART_LCR, up->lcr); 991 992 serial_omap_set_mctrl(&up->port, up->port.mctrl); 993 994 spin_unlock_irqrestore(&up->port.lock, flags); 995 pm_runtime_mark_last_busy(up->dev); 996 pm_runtime_put_autosuspend(up->dev); 997 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 998 } 999 1000 static int serial_omap_set_wake(struct uart_port *port, unsigned int state) 1001 { 1002 struct uart_omap_port *up = to_uart_omap_port(port); 1003 1004 serial_omap_enable_wakeup(up, state); 1005 1006 return 0; 1007 } 1008 1009 static void 1010 serial_omap_pm(struct uart_port *port, unsigned int state, 1011 unsigned int oldstate) 1012 { 1013 struct uart_omap_port *up = to_uart_omap_port(port); 1014 unsigned char efr; 1015 1016 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1017 1018 pm_runtime_get_sync(up->dev); 1019 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1020 efr = serial_in(up, UART_EFR); 1021 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1022 serial_out(up, UART_LCR, 0); 1023 1024 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1025 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1026 serial_out(up, UART_EFR, efr); 1027 serial_out(up, UART_LCR, 0); 1028 1029 if (!device_may_wakeup(up->dev)) { 1030 if (!state) 1031 pm_runtime_forbid(up->dev); 1032 else 1033 pm_runtime_allow(up->dev); 1034 } 1035 1036 pm_runtime_mark_last_busy(up->dev); 1037 pm_runtime_put_autosuspend(up->dev); 1038 } 1039 1040 static void serial_omap_release_port(struct uart_port *port) 1041 { 1042 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1043 } 1044 1045 static int serial_omap_request_port(struct uart_port *port) 1046 { 1047 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1048 return 0; 1049 } 1050 1051 static void serial_omap_config_port(struct uart_port *port, int flags) 1052 { 1053 struct uart_omap_port *up = to_uart_omap_port(port); 1054 1055 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1056 up->port.line); 1057 up->port.type = PORT_OMAP; 1058 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1059 } 1060 1061 static int 1062 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1063 { 1064 /* we don't want the core code to modify any port params */ 1065 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1066 return -EINVAL; 1067 } 1068 1069 static const char * 1070 serial_omap_type(struct uart_port *port) 1071 { 1072 struct uart_omap_port *up = to_uart_omap_port(port); 1073 1074 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1075 return up->name; 1076 } 1077 1078 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1079 1080 static inline void wait_for_xmitr(struct uart_omap_port *up) 1081 { 1082 unsigned int status, tmout = 10000; 1083 1084 /* Wait up to 10ms for the character(s) to be sent. */ 1085 do { 1086 status = serial_in(up, UART_LSR); 1087 1088 if (status & UART_LSR_BI) 1089 up->lsr_break_flag = UART_LSR_BI; 1090 1091 if (--tmout == 0) 1092 break; 1093 udelay(1); 1094 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1095 1096 /* Wait up to 1s for flow control if necessary */ 1097 if (up->port.flags & UPF_CONS_FLOW) { 1098 tmout = 1000000; 1099 for (tmout = 1000000; tmout; tmout--) { 1100 unsigned int msr = serial_in(up, UART_MSR); 1101 1102 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1103 if (msr & UART_MSR_CTS) 1104 break; 1105 1106 udelay(1); 1107 } 1108 } 1109 } 1110 1111 #ifdef CONFIG_CONSOLE_POLL 1112 1113 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1114 { 1115 struct uart_omap_port *up = to_uart_omap_port(port); 1116 1117 pm_runtime_get_sync(up->dev); 1118 wait_for_xmitr(up); 1119 serial_out(up, UART_TX, ch); 1120 pm_runtime_mark_last_busy(up->dev); 1121 pm_runtime_put_autosuspend(up->dev); 1122 } 1123 1124 static int serial_omap_poll_get_char(struct uart_port *port) 1125 { 1126 struct uart_omap_port *up = to_uart_omap_port(port); 1127 unsigned int status; 1128 1129 pm_runtime_get_sync(up->dev); 1130 status = serial_in(up, UART_LSR); 1131 if (!(status & UART_LSR_DR)) { 1132 status = NO_POLL_CHAR; 1133 goto out; 1134 } 1135 1136 status = serial_in(up, UART_RX); 1137 1138 out: 1139 pm_runtime_mark_last_busy(up->dev); 1140 pm_runtime_put_autosuspend(up->dev); 1141 1142 return status; 1143 } 1144 1145 #endif /* CONFIG_CONSOLE_POLL */ 1146 1147 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1148 1149 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1150 1151 static struct uart_driver serial_omap_reg; 1152 1153 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1154 { 1155 struct uart_omap_port *up = to_uart_omap_port(port); 1156 1157 wait_for_xmitr(up); 1158 serial_out(up, UART_TX, ch); 1159 } 1160 1161 static void 1162 serial_omap_console_write(struct console *co, const char *s, 1163 unsigned int count) 1164 { 1165 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1166 unsigned long flags; 1167 unsigned int ier; 1168 int locked = 1; 1169 1170 pm_runtime_get_sync(up->dev); 1171 1172 local_irq_save(flags); 1173 if (up->port.sysrq) 1174 locked = 0; 1175 else if (oops_in_progress) 1176 locked = spin_trylock(&up->port.lock); 1177 else 1178 spin_lock(&up->port.lock); 1179 1180 /* 1181 * First save the IER then disable the interrupts 1182 */ 1183 ier = serial_in(up, UART_IER); 1184 serial_out(up, UART_IER, 0); 1185 1186 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1187 1188 /* 1189 * Finally, wait for transmitter to become empty 1190 * and restore the IER 1191 */ 1192 wait_for_xmitr(up); 1193 serial_out(up, UART_IER, ier); 1194 /* 1195 * The receive handling will happen properly because the 1196 * receive ready bit will still be set; it is not cleared 1197 * on read. However, modem control will not, we must 1198 * call it if we have saved something in the saved flags 1199 * while processing with interrupts off. 1200 */ 1201 if (up->msr_saved_flags) 1202 check_modem_status(up); 1203 1204 pm_runtime_mark_last_busy(up->dev); 1205 pm_runtime_put_autosuspend(up->dev); 1206 if (locked) 1207 spin_unlock(&up->port.lock); 1208 local_irq_restore(flags); 1209 } 1210 1211 static int __init 1212 serial_omap_console_setup(struct console *co, char *options) 1213 { 1214 struct uart_omap_port *up; 1215 int baud = 115200; 1216 int bits = 8; 1217 int parity = 'n'; 1218 int flow = 'n'; 1219 1220 if (serial_omap_console_ports[co->index] == NULL) 1221 return -ENODEV; 1222 up = serial_omap_console_ports[co->index]; 1223 1224 if (options) 1225 uart_parse_options(options, &baud, &parity, &bits, &flow); 1226 1227 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1228 } 1229 1230 static struct console serial_omap_console = { 1231 .name = OMAP_SERIAL_NAME, 1232 .write = serial_omap_console_write, 1233 .device = uart_console_device, 1234 .setup = serial_omap_console_setup, 1235 .flags = CON_PRINTBUFFER, 1236 .index = -1, 1237 .data = &serial_omap_reg, 1238 }; 1239 1240 static void serial_omap_add_console_port(struct uart_omap_port *up) 1241 { 1242 serial_omap_console_ports[up->port.line] = up; 1243 } 1244 1245 #define OMAP_CONSOLE (&serial_omap_console) 1246 1247 #else 1248 1249 #define OMAP_CONSOLE NULL 1250 1251 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1252 {} 1253 1254 #endif 1255 1256 static struct uart_ops serial_omap_pops = { 1257 .tx_empty = serial_omap_tx_empty, 1258 .set_mctrl = serial_omap_set_mctrl, 1259 .get_mctrl = serial_omap_get_mctrl, 1260 .stop_tx = serial_omap_stop_tx, 1261 .start_tx = serial_omap_start_tx, 1262 .throttle = serial_omap_throttle, 1263 .unthrottle = serial_omap_unthrottle, 1264 .stop_rx = serial_omap_stop_rx, 1265 .enable_ms = serial_omap_enable_ms, 1266 .break_ctl = serial_omap_break_ctl, 1267 .startup = serial_omap_startup, 1268 .shutdown = serial_omap_shutdown, 1269 .set_termios = serial_omap_set_termios, 1270 .pm = serial_omap_pm, 1271 .set_wake = serial_omap_set_wake, 1272 .type = serial_omap_type, 1273 .release_port = serial_omap_release_port, 1274 .request_port = serial_omap_request_port, 1275 .config_port = serial_omap_config_port, 1276 .verify_port = serial_omap_verify_port, 1277 #ifdef CONFIG_CONSOLE_POLL 1278 .poll_put_char = serial_omap_poll_put_char, 1279 .poll_get_char = serial_omap_poll_get_char, 1280 #endif 1281 }; 1282 1283 static struct uart_driver serial_omap_reg = { 1284 .owner = THIS_MODULE, 1285 .driver_name = "OMAP-SERIAL", 1286 .dev_name = OMAP_SERIAL_NAME, 1287 .nr = OMAP_MAX_HSUART_PORTS, 1288 .cons = OMAP_CONSOLE, 1289 }; 1290 1291 #ifdef CONFIG_PM_SLEEP 1292 static int serial_omap_suspend(struct device *dev) 1293 { 1294 struct uart_omap_port *up = dev_get_drvdata(dev); 1295 1296 uart_suspend_port(&serial_omap_reg, &up->port); 1297 flush_work(&up->qos_work); 1298 1299 return 0; 1300 } 1301 1302 static int serial_omap_resume(struct device *dev) 1303 { 1304 struct uart_omap_port *up = dev_get_drvdata(dev); 1305 1306 uart_resume_port(&serial_omap_reg, &up->port); 1307 1308 return 0; 1309 } 1310 #endif 1311 1312 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1313 { 1314 u32 mvr, scheme; 1315 u16 revision, major, minor; 1316 1317 mvr = serial_in(up, UART_OMAP_MVER); 1318 1319 /* Check revision register scheme */ 1320 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1321 1322 switch (scheme) { 1323 case 0: /* Legacy Scheme: OMAP2/3 */ 1324 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1325 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1326 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1327 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1328 break; 1329 case 1: 1330 /* New Scheme: OMAP4+ */ 1331 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1332 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1333 OMAP_UART_MVR_MAJ_SHIFT; 1334 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1335 break; 1336 default: 1337 dev_warn(up->dev, 1338 "Unknown %s revision, defaulting to highest\n", 1339 up->name); 1340 /* highest possible revision */ 1341 major = 0xff; 1342 minor = 0xff; 1343 } 1344 1345 /* normalize revision for the driver */ 1346 revision = UART_BUILD_REVISION(major, minor); 1347 1348 switch (revision) { 1349 case OMAP_UART_REV_46: 1350 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1351 UART_ERRATA_i291_DMA_FORCEIDLE); 1352 break; 1353 case OMAP_UART_REV_52: 1354 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1355 UART_ERRATA_i291_DMA_FORCEIDLE); 1356 break; 1357 case OMAP_UART_REV_63: 1358 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1359 break; 1360 default: 1361 break; 1362 } 1363 } 1364 1365 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1366 { 1367 struct omap_uart_port_info *omap_up_info; 1368 1369 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1370 if (!omap_up_info) 1371 return NULL; /* out of memory */ 1372 1373 of_property_read_u32(dev->of_node, "clock-frequency", 1374 &omap_up_info->uartclk); 1375 return omap_up_info; 1376 } 1377 1378 static int serial_omap_probe(struct platform_device *pdev) 1379 { 1380 struct uart_omap_port *up; 1381 struct resource *mem, *irq; 1382 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1383 int ret; 1384 1385 if (pdev->dev.of_node) 1386 omap_up_info = of_get_uart_port_info(&pdev->dev); 1387 1388 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1389 if (!mem) { 1390 dev_err(&pdev->dev, "no mem resource?\n"); 1391 return -ENODEV; 1392 } 1393 1394 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1395 if (!irq) { 1396 dev_err(&pdev->dev, "no irq resource?\n"); 1397 return -ENODEV; 1398 } 1399 1400 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), 1401 pdev->dev.driver->name)) { 1402 dev_err(&pdev->dev, "memory region already claimed\n"); 1403 return -EBUSY; 1404 } 1405 1406 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1407 omap_up_info->DTR_present) { 1408 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); 1409 if (ret < 0) 1410 return ret; 1411 ret = gpio_direction_output(omap_up_info->DTR_gpio, 1412 omap_up_info->DTR_inverted); 1413 if (ret < 0) 1414 return ret; 1415 } 1416 1417 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1418 if (!up) 1419 return -ENOMEM; 1420 1421 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1422 omap_up_info->DTR_present) { 1423 up->DTR_gpio = omap_up_info->DTR_gpio; 1424 up->DTR_inverted = omap_up_info->DTR_inverted; 1425 } else 1426 up->DTR_gpio = -EINVAL; 1427 up->DTR_active = 0; 1428 1429 up->dev = &pdev->dev; 1430 up->port.dev = &pdev->dev; 1431 up->port.type = PORT_OMAP; 1432 up->port.iotype = UPIO_MEM; 1433 up->port.irq = irq->start; 1434 1435 up->port.regshift = 2; 1436 up->port.fifosize = 64; 1437 up->port.ops = &serial_omap_pops; 1438 1439 if (pdev->dev.of_node) 1440 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); 1441 else 1442 up->port.line = pdev->id; 1443 1444 if (up->port.line < 0) { 1445 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1446 up->port.line); 1447 ret = -ENODEV; 1448 goto err_port_line; 1449 } 1450 1451 up->pins = devm_pinctrl_get_select_default(&pdev->dev); 1452 if (IS_ERR(up->pins)) { 1453 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n", 1454 up->port.line, PTR_ERR(up->pins)); 1455 up->pins = NULL; 1456 } 1457 1458 sprintf(up->name, "OMAP UART%d", up->port.line); 1459 up->port.mapbase = mem->start; 1460 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1461 resource_size(mem)); 1462 if (!up->port.membase) { 1463 dev_err(&pdev->dev, "can't ioremap UART\n"); 1464 ret = -ENOMEM; 1465 goto err_ioremap; 1466 } 1467 1468 up->port.flags = omap_up_info->flags; 1469 up->port.uartclk = omap_up_info->uartclk; 1470 if (!up->port.uartclk) { 1471 up->port.uartclk = DEFAULT_CLK_SPEED; 1472 dev_warn(&pdev->dev, "No clock speed specified: using default:" 1473 "%d\n", DEFAULT_CLK_SPEED); 1474 } 1475 1476 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1477 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1478 pm_qos_add_request(&up->pm_qos_request, 1479 PM_QOS_CPU_DMA_LATENCY, up->latency); 1480 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1481 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1482 1483 platform_set_drvdata(pdev, up); 1484 pm_runtime_enable(&pdev->dev); 1485 pm_runtime_use_autosuspend(&pdev->dev); 1486 pm_runtime_set_autosuspend_delay(&pdev->dev, 1487 omap_up_info->autosuspend_timeout); 1488 1489 pm_runtime_irq_safe(&pdev->dev); 1490 pm_runtime_get_sync(&pdev->dev); 1491 1492 omap_serial_fill_features_erratas(up); 1493 1494 ui[up->port.line] = up; 1495 serial_omap_add_console_port(up); 1496 1497 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1498 if (ret != 0) 1499 goto err_add_port; 1500 1501 pm_runtime_mark_last_busy(up->dev); 1502 pm_runtime_put_autosuspend(up->dev); 1503 return 0; 1504 1505 err_add_port: 1506 pm_runtime_put(&pdev->dev); 1507 pm_runtime_disable(&pdev->dev); 1508 err_ioremap: 1509 err_port_line: 1510 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1511 pdev->id, __func__, ret); 1512 return ret; 1513 } 1514 1515 static int serial_omap_remove(struct platform_device *dev) 1516 { 1517 struct uart_omap_port *up = platform_get_drvdata(dev); 1518 1519 pm_runtime_put_sync(up->dev); 1520 pm_runtime_disable(up->dev); 1521 uart_remove_one_port(&serial_omap_reg, &up->port); 1522 pm_qos_remove_request(&up->pm_qos_request); 1523 1524 return 0; 1525 } 1526 1527 /* 1528 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1529 * The access to uart register after MDR1 Access 1530 * causes UART to corrupt data. 1531 * 1532 * Need a delay = 1533 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1534 * give 10 times as much 1535 */ 1536 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1537 { 1538 u8 timeout = 255; 1539 1540 serial_out(up, UART_OMAP_MDR1, mdr1); 1541 udelay(2); 1542 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1543 UART_FCR_CLEAR_RCVR); 1544 /* 1545 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1546 * TX_FIFO_E bit is 1. 1547 */ 1548 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1549 (UART_LSR_THRE | UART_LSR_DR))) { 1550 timeout--; 1551 if (!timeout) { 1552 /* Should *never* happen. we warn and carry on */ 1553 dev_crit(up->dev, "Errata i202: timedout %x\n", 1554 serial_in(up, UART_LSR)); 1555 break; 1556 } 1557 udelay(1); 1558 } 1559 } 1560 1561 #ifdef CONFIG_PM_RUNTIME 1562 static void serial_omap_restore_context(struct uart_omap_port *up) 1563 { 1564 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1565 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1566 else 1567 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1568 1569 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1570 serial_out(up, UART_EFR, UART_EFR_ECB); 1571 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1572 serial_out(up, UART_IER, 0x0); 1573 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1574 serial_out(up, UART_DLL, up->dll); 1575 serial_out(up, UART_DLM, up->dlh); 1576 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1577 serial_out(up, UART_IER, up->ier); 1578 serial_out(up, UART_FCR, up->fcr); 1579 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1580 serial_out(up, UART_MCR, up->mcr); 1581 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1582 serial_out(up, UART_OMAP_SCR, up->scr); 1583 serial_out(up, UART_EFR, up->efr); 1584 serial_out(up, UART_LCR, up->lcr); 1585 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1586 serial_omap_mdr1_errataset(up, up->mdr1); 1587 else 1588 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1589 } 1590 1591 static int serial_omap_runtime_suspend(struct device *dev) 1592 { 1593 struct uart_omap_port *up = dev_get_drvdata(dev); 1594 struct omap_uart_port_info *pdata = dev->platform_data; 1595 1596 if (!up) 1597 return -EINVAL; 1598 1599 if (!pdata) 1600 return 0; 1601 1602 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1603 1604 if (device_may_wakeup(dev)) { 1605 if (!up->wakeups_enabled) { 1606 serial_omap_enable_wakeup(up, true); 1607 up->wakeups_enabled = true; 1608 } 1609 } else { 1610 if (up->wakeups_enabled) { 1611 serial_omap_enable_wakeup(up, false); 1612 up->wakeups_enabled = false; 1613 } 1614 } 1615 1616 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1617 schedule_work(&up->qos_work); 1618 1619 return 0; 1620 } 1621 1622 static int serial_omap_runtime_resume(struct device *dev) 1623 { 1624 struct uart_omap_port *up = dev_get_drvdata(dev); 1625 1626 int loss_cnt = serial_omap_get_context_loss_count(up); 1627 1628 if (loss_cnt < 0) { 1629 dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n", 1630 loss_cnt); 1631 serial_omap_restore_context(up); 1632 } else if (up->context_loss_cnt != loss_cnt) { 1633 serial_omap_restore_context(up); 1634 } 1635 up->latency = up->calc_latency; 1636 schedule_work(&up->qos_work); 1637 1638 return 0; 1639 } 1640 #endif 1641 1642 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1643 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1644 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1645 serial_omap_runtime_resume, NULL) 1646 }; 1647 1648 #if defined(CONFIG_OF) 1649 static const struct of_device_id omap_serial_of_match[] = { 1650 { .compatible = "ti,omap2-uart" }, 1651 { .compatible = "ti,omap3-uart" }, 1652 { .compatible = "ti,omap4-uart" }, 1653 {}, 1654 }; 1655 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1656 #endif 1657 1658 static struct platform_driver serial_omap_driver = { 1659 .probe = serial_omap_probe, 1660 .remove = serial_omap_remove, 1661 .driver = { 1662 .name = DRIVER_NAME, 1663 .pm = &serial_omap_dev_pm_ops, 1664 .of_match_table = of_match_ptr(omap_serial_of_match), 1665 }, 1666 }; 1667 1668 static int __init serial_omap_init(void) 1669 { 1670 int ret; 1671 1672 ret = uart_register_driver(&serial_omap_reg); 1673 if (ret != 0) 1674 return ret; 1675 ret = platform_driver_register(&serial_omap_driver); 1676 if (ret != 0) 1677 uart_unregister_driver(&serial_omap_reg); 1678 return ret; 1679 } 1680 1681 static void __exit serial_omap_exit(void) 1682 { 1683 platform_driver_unregister(&serial_omap_driver); 1684 uart_unregister_driver(&serial_omap_reg); 1685 } 1686 1687 module_init(serial_omap_init); 1688 module_exit(serial_omap_exit); 1689 1690 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1691 MODULE_LICENSE("GPL"); 1692 MODULE_AUTHOR("Texas Instruments Inc"); 1693