1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for OMAP-UART controller. 4 * Based on drivers/serial/8250.c 5 * 6 * Copyright (C) 2010 Texas Instruments. 7 * 8 * Authors: 9 * Govindraj R <govindraj.raja@ti.com> 10 * Thara Gopinath <thara@ti.com> 11 * 12 * Note: This driver is made separate from 8250 driver as we cannot 13 * over load 8250 driver with omap platform specific configuration for 14 * features like DMA, it makes easier to implement features like DMA and 15 * hardware flow control and software flow control configuration with 16 * this driver as required for the omap-platform. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/console.h> 22 #include <linux/serial.h> 23 #include <linux/serial_reg.h> 24 #include <linux/delay.h> 25 #include <linux/slab.h> 26 #include <linux/tty.h> 27 #include <linux/tty_flip.h> 28 #include <linux/platform_device.h> 29 #include <linux/io.h> 30 #include <linux/clk.h> 31 #include <linux/serial_core.h> 32 #include <linux/irq.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/pm_wakeirq.h> 35 #include <linux/of.h> 36 #include <linux/of_irq.h> 37 #include <linux/gpio/consumer.h> 38 #include <linux/platform_data/serial-omap.h> 39 40 #define OMAP_MAX_HSUART_PORTS 10 41 42 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 43 44 #define OMAP_UART_REV_42 0x0402 45 #define OMAP_UART_REV_46 0x0406 46 #define OMAP_UART_REV_52 0x0502 47 #define OMAP_UART_REV_63 0x0603 48 49 #define OMAP_UART_TX_WAKEUP_EN BIT(7) 50 51 /* Feature flags */ 52 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) 53 54 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 55 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 56 57 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ 58 59 /* SCR register bitmasks */ 60 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 61 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 62 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 63 64 /* FCR register bitmasks */ 65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 67 68 /* MVR register bitmasks */ 69 #define OMAP_UART_MVR_SCHEME_SHIFT 30 70 71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 73 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 74 75 #define OMAP_UART_MVR_MAJ_MASK 0x700 76 #define OMAP_UART_MVR_MAJ_SHIFT 8 77 #define OMAP_UART_MVR_MIN_MASK 0x3f 78 79 #define OMAP_UART_DMA_CH_FREE -1 80 81 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 82 #define OMAP_MODE13X_SPEED 230400 83 84 /* WER = 0x7F 85 * Enable module level wakeup in WER reg 86 */ 87 #define OMAP_UART_WER_MOD_WKUP 0x7F 88 89 /* Enable XON/XOFF flow control on output */ 90 #define OMAP_UART_SW_TX 0x08 91 92 /* Enable XON/XOFF flow control on input */ 93 #define OMAP_UART_SW_RX 0x02 94 95 #define OMAP_UART_SW_CLR 0xF0 96 97 #define OMAP_UART_TCR_TRIG 0x0F 98 99 struct uart_omap_dma { 100 u8 uart_dma_tx; 101 u8 uart_dma_rx; 102 int rx_dma_channel; 103 int tx_dma_channel; 104 dma_addr_t rx_buf_dma_phys; 105 dma_addr_t tx_buf_dma_phys; 106 unsigned int uart_base; 107 /* 108 * Buffer for rx dma. It is not required for tx because the buffer 109 * comes from port structure. 110 */ 111 unsigned char *rx_buf; 112 unsigned int prev_rx_dma_pos; 113 int tx_buf_size; 114 int tx_dma_used; 115 int rx_dma_used; 116 spinlock_t tx_lock; 117 spinlock_t rx_lock; 118 /* timer to poll activity on rx dma */ 119 struct timer_list rx_timer; 120 unsigned int rx_buf_size; 121 unsigned int rx_poll_rate; 122 unsigned int rx_timeout; 123 }; 124 125 struct uart_omap_port { 126 struct uart_port port; 127 struct uart_omap_dma uart_dma; 128 struct device *dev; 129 int wakeirq; 130 131 unsigned char ier; 132 unsigned char lcr; 133 unsigned char mcr; 134 unsigned char fcr; 135 unsigned char efr; 136 unsigned char dll; 137 unsigned char dlh; 138 unsigned char mdr1; 139 unsigned char scr; 140 unsigned char wer; 141 142 int use_dma; 143 /* 144 * Some bits in registers are cleared on a read, so they must 145 * be saved whenever the register is read, but the bits will not 146 * be immediately processed. 147 */ 148 unsigned int lsr_break_flag; 149 unsigned char msr_saved_flags; 150 char name[20]; 151 unsigned long port_activity; 152 int context_loss_cnt; 153 u32 errata; 154 u32 features; 155 156 struct gpio_desc *rts_gpiod; 157 158 struct pm_qos_request pm_qos_request; 159 u32 latency; 160 u32 calc_latency; 161 struct work_struct qos_work; 162 bool is_suspending; 163 164 unsigned int rs485_tx_filter_count; 165 }; 166 167 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 168 169 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 170 171 /* Forward declaration of functions */ 172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 173 174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 175 { 176 offset <<= up->port.regshift; 177 return readw(up->port.membase + offset); 178 } 179 180 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 181 { 182 offset <<= up->port.regshift; 183 writew(value, up->port.membase + offset); 184 } 185 186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 187 { 188 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 189 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 190 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 191 serial_out(up, UART_FCR, 0); 192 } 193 194 #ifdef CONFIG_PM 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 196 { 197 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 198 199 if (!pdata || !pdata->get_context_loss_count) 200 return -EINVAL; 201 202 return pdata->get_context_loss_count(up->dev); 203 } 204 205 /* REVISIT: Remove this when omap3 boots in device tree only mode */ 206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 207 { 208 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 209 210 if (!pdata || !pdata->enable_wakeup) 211 return; 212 213 pdata->enable_wakeup(up->dev, enable); 214 } 215 #endif /* CONFIG_PM */ 216 217 /* 218 * Calculate the absolute difference between the desired and actual baud 219 * rate for the given mode. 220 */ 221 static inline int calculate_baud_abs_diff(struct uart_port *port, 222 unsigned int baud, unsigned int mode) 223 { 224 unsigned int n = port->uartclk / (mode * baud); 225 int abs_diff; 226 227 if (n == 0) 228 n = 1; 229 230 abs_diff = baud - (port->uartclk / (mode * n)); 231 if (abs_diff < 0) 232 abs_diff = -abs_diff; 233 234 return abs_diff; 235 } 236 237 /* 238 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 239 * @port: uart port info 240 * @baud: baudrate for which mode needs to be determined 241 * 242 * Returns true if baud rate is MODE16X and false if MODE13X 243 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 244 * and Error Rates" determines modes not for all common baud rates. 245 * E.g. for 1000000 baud rate mode must be 16x, but according to that 246 * table it's determined as 13x. 247 */ 248 static bool 249 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 250 { 251 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13); 252 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16); 253 254 return (abs_diff_13 >= abs_diff_16); 255 } 256 257 /* 258 * serial_omap_get_divisor - calculate divisor value 259 * @port: uart port info 260 * @baud: baudrate for which divisor needs to be calculated. 261 */ 262 static unsigned int 263 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 264 { 265 unsigned int mode; 266 267 if (!serial_omap_baud_is_mode16(port, baud)) 268 mode = 13; 269 else 270 mode = 16; 271 return port->uartclk/(mode * baud); 272 } 273 274 static void serial_omap_enable_ms(struct uart_port *port) 275 { 276 struct uart_omap_port *up = to_uart_omap_port(port); 277 278 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 279 280 up->ier |= UART_IER_MSI; 281 serial_out(up, UART_IER, up->ier); 282 } 283 284 static void serial_omap_stop_tx(struct uart_port *port) 285 { 286 struct uart_omap_port *up = to_uart_omap_port(port); 287 int res; 288 289 /* Handle RS-485 */ 290 if (port->rs485.flags & SER_RS485_ENABLED) { 291 if (up->scr & OMAP_UART_SCR_TX_EMPTY) { 292 /* THR interrupt is fired when both TX FIFO and TX 293 * shift register are empty. This means there's nothing 294 * left to transmit now, so make sure the THR interrupt 295 * is fired when TX FIFO is below the trigger level, 296 * disable THR interrupts and toggle the RS-485 GPIO 297 * data direction pin if needed. 298 */ 299 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 300 serial_out(up, UART_OMAP_SCR, up->scr); 301 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 302 1 : 0; 303 if (up->rts_gpiod && 304 gpiod_get_value(up->rts_gpiod) != res) { 305 if (port->rs485.delay_rts_after_send > 0) 306 mdelay( 307 port->rs485.delay_rts_after_send); 308 gpiod_set_value(up->rts_gpiod, res); 309 } 310 } else { 311 /* We're asked to stop, but there's still stuff in the 312 * UART FIFO, so make sure the THR interrupt is fired 313 * when both TX FIFO and TX shift register are empty. 314 * The next THR interrupt (if no transmission is started 315 * in the meantime) will indicate the end of a 316 * transmission. Therefore we _don't_ disable THR 317 * interrupts in this situation. 318 */ 319 up->scr |= OMAP_UART_SCR_TX_EMPTY; 320 serial_out(up, UART_OMAP_SCR, up->scr); 321 return; 322 } 323 } 324 325 if (up->ier & UART_IER_THRI) { 326 up->ier &= ~UART_IER_THRI; 327 serial_out(up, UART_IER, up->ier); 328 } 329 } 330 331 static void serial_omap_stop_rx(struct uart_port *port) 332 { 333 struct uart_omap_port *up = to_uart_omap_port(port); 334 335 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 336 up->port.read_status_mask &= ~UART_LSR_DR; 337 serial_out(up, UART_IER, up->ier); 338 } 339 340 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 341 { 342 struct circ_buf *xmit = &up->port.state->xmit; 343 int count; 344 345 if (up->port.x_char) { 346 serial_out(up, UART_TX, up->port.x_char); 347 up->port.icount.tx++; 348 up->port.x_char = 0; 349 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 350 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) 351 up->rs485_tx_filter_count++; 352 353 return; 354 } 355 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 356 serial_omap_stop_tx(&up->port); 357 return; 358 } 359 count = up->port.fifosize / 4; 360 do { 361 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 362 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 363 up->port.icount.tx++; 364 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 365 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX)) 366 up->rs485_tx_filter_count++; 367 368 if (uart_circ_empty(xmit)) 369 break; 370 } while (--count > 0); 371 372 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 373 uart_write_wakeup(&up->port); 374 375 if (uart_circ_empty(xmit)) 376 serial_omap_stop_tx(&up->port); 377 } 378 379 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 380 { 381 if (!(up->ier & UART_IER_THRI)) { 382 up->ier |= UART_IER_THRI; 383 serial_out(up, UART_IER, up->ier); 384 } 385 } 386 387 static void serial_omap_start_tx(struct uart_port *port) 388 { 389 struct uart_omap_port *up = to_uart_omap_port(port); 390 int res; 391 392 /* Handle RS-485 */ 393 if (port->rs485.flags & SER_RS485_ENABLED) { 394 /* Fire THR interrupts when FIFO is below trigger level */ 395 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 396 serial_out(up, UART_OMAP_SCR, up->scr); 397 398 /* if rts not already enabled */ 399 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; 400 if (up->rts_gpiod && gpiod_get_value(up->rts_gpiod) != res) { 401 gpiod_set_value(up->rts_gpiod, res); 402 if (port->rs485.delay_rts_before_send > 0) 403 mdelay(port->rs485.delay_rts_before_send); 404 } 405 } 406 407 if ((port->rs485.flags & SER_RS485_ENABLED) && 408 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 409 up->rs485_tx_filter_count = 0; 410 411 serial_omap_enable_ier_thri(up); 412 } 413 414 static void serial_omap_throttle(struct uart_port *port) 415 { 416 struct uart_omap_port *up = to_uart_omap_port(port); 417 unsigned long flags; 418 419 spin_lock_irqsave(&up->port.lock, flags); 420 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 421 serial_out(up, UART_IER, up->ier); 422 spin_unlock_irqrestore(&up->port.lock, flags); 423 } 424 425 static void serial_omap_unthrottle(struct uart_port *port) 426 { 427 struct uart_omap_port *up = to_uart_omap_port(port); 428 unsigned long flags; 429 430 spin_lock_irqsave(&up->port.lock, flags); 431 up->ier |= UART_IER_RLSI | UART_IER_RDI; 432 serial_out(up, UART_IER, up->ier); 433 spin_unlock_irqrestore(&up->port.lock, flags); 434 } 435 436 static unsigned int check_modem_status(struct uart_omap_port *up) 437 { 438 unsigned int status; 439 440 status = serial_in(up, UART_MSR); 441 status |= up->msr_saved_flags; 442 up->msr_saved_flags = 0; 443 if ((status & UART_MSR_ANY_DELTA) == 0) 444 return status; 445 446 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 447 up->port.state != NULL) { 448 if (status & UART_MSR_TERI) 449 up->port.icount.rng++; 450 if (status & UART_MSR_DDSR) 451 up->port.icount.dsr++; 452 if (status & UART_MSR_DDCD) 453 uart_handle_dcd_change 454 (&up->port, status & UART_MSR_DCD); 455 if (status & UART_MSR_DCTS) 456 uart_handle_cts_change 457 (&up->port, status & UART_MSR_CTS); 458 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 459 } 460 461 return status; 462 } 463 464 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 465 { 466 unsigned int flag; 467 468 /* 469 * Read one data character out to avoid stalling the receiver according 470 * to the table 23-246 of the omap4 TRM. 471 */ 472 if (likely(lsr & UART_LSR_DR)) { 473 serial_in(up, UART_RX); 474 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 475 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && 476 up->rs485_tx_filter_count) 477 up->rs485_tx_filter_count--; 478 } 479 480 up->port.icount.rx++; 481 flag = TTY_NORMAL; 482 483 if (lsr & UART_LSR_BI) { 484 flag = TTY_BREAK; 485 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 486 up->port.icount.brk++; 487 /* 488 * We do the SysRQ and SAK checking 489 * here because otherwise the break 490 * may get masked by ignore_status_mask 491 * or read_status_mask. 492 */ 493 if (uart_handle_break(&up->port)) 494 return; 495 496 } 497 498 if (lsr & UART_LSR_PE) { 499 flag = TTY_PARITY; 500 up->port.icount.parity++; 501 } 502 503 if (lsr & UART_LSR_FE) { 504 flag = TTY_FRAME; 505 up->port.icount.frame++; 506 } 507 508 if (lsr & UART_LSR_OE) 509 up->port.icount.overrun++; 510 511 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 512 if (up->port.line == up->port.cons->index) { 513 /* Recover the break flag from console xmit */ 514 lsr |= up->lsr_break_flag; 515 } 516 #endif 517 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 518 } 519 520 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 521 { 522 unsigned char ch = 0; 523 unsigned int flag; 524 525 if (!(lsr & UART_LSR_DR)) 526 return; 527 528 ch = serial_in(up, UART_RX); 529 if ((up->port.rs485.flags & SER_RS485_ENABLED) && 530 !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) && 531 up->rs485_tx_filter_count) { 532 up->rs485_tx_filter_count--; 533 return; 534 } 535 536 flag = TTY_NORMAL; 537 up->port.icount.rx++; 538 539 if (uart_handle_sysrq_char(&up->port, ch)) 540 return; 541 542 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 543 } 544 545 /** 546 * serial_omap_irq() - This handles the interrupt from one port 547 * @irq: uart port irq number 548 * @dev_id: uart port info 549 */ 550 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 551 { 552 struct uart_omap_port *up = dev_id; 553 unsigned int iir, lsr; 554 unsigned int type; 555 irqreturn_t ret = IRQ_NONE; 556 int max_count = 256; 557 558 spin_lock(&up->port.lock); 559 560 do { 561 iir = serial_in(up, UART_IIR); 562 if (iir & UART_IIR_NO_INT) 563 break; 564 565 ret = IRQ_HANDLED; 566 lsr = serial_in(up, UART_LSR); 567 568 /* extract IRQ type from IIR register */ 569 type = iir & 0x3e; 570 571 switch (type) { 572 case UART_IIR_MSI: 573 check_modem_status(up); 574 break; 575 case UART_IIR_THRI: 576 transmit_chars(up, lsr); 577 break; 578 case UART_IIR_RX_TIMEOUT: 579 case UART_IIR_RDI: 580 serial_omap_rdi(up, lsr); 581 break; 582 case UART_IIR_RLSI: 583 serial_omap_rlsi(up, lsr); 584 break; 585 case UART_IIR_CTS_RTS_DSR: 586 /* simply try again */ 587 break; 588 case UART_IIR_XOFF: 589 default: 590 break; 591 } 592 } while (max_count--); 593 594 spin_unlock(&up->port.lock); 595 596 tty_flip_buffer_push(&up->port.state->port); 597 598 up->port_activity = jiffies; 599 600 return ret; 601 } 602 603 static unsigned int serial_omap_tx_empty(struct uart_port *port) 604 { 605 struct uart_omap_port *up = to_uart_omap_port(port); 606 unsigned long flags; 607 unsigned int ret = 0; 608 609 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 610 spin_lock_irqsave(&up->port.lock, flags); 611 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 612 spin_unlock_irqrestore(&up->port.lock, flags); 613 614 return ret; 615 } 616 617 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 618 { 619 struct uart_omap_port *up = to_uart_omap_port(port); 620 unsigned int status; 621 unsigned int ret = 0; 622 623 status = check_modem_status(up); 624 625 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 626 627 if (status & UART_MSR_DCD) 628 ret |= TIOCM_CAR; 629 if (status & UART_MSR_RI) 630 ret |= TIOCM_RNG; 631 if (status & UART_MSR_DSR) 632 ret |= TIOCM_DSR; 633 if (status & UART_MSR_CTS) 634 ret |= TIOCM_CTS; 635 return ret; 636 } 637 638 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 639 { 640 struct uart_omap_port *up = to_uart_omap_port(port); 641 unsigned char mcr = 0, old_mcr, lcr; 642 643 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 644 if (mctrl & TIOCM_RTS) 645 mcr |= UART_MCR_RTS; 646 if (mctrl & TIOCM_DTR) 647 mcr |= UART_MCR_DTR; 648 if (mctrl & TIOCM_OUT1) 649 mcr |= UART_MCR_OUT1; 650 if (mctrl & TIOCM_OUT2) 651 mcr |= UART_MCR_OUT2; 652 if (mctrl & TIOCM_LOOP) 653 mcr |= UART_MCR_LOOP; 654 655 old_mcr = serial_in(up, UART_MCR); 656 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 657 UART_MCR_DTR | UART_MCR_RTS); 658 up->mcr = old_mcr | mcr; 659 serial_out(up, UART_MCR, up->mcr); 660 661 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */ 662 lcr = serial_in(up, UART_LCR); 663 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 664 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 665 up->efr |= UART_EFR_RTS; 666 else 667 up->efr &= ~UART_EFR_RTS; 668 serial_out(up, UART_EFR, up->efr); 669 serial_out(up, UART_LCR, lcr); 670 } 671 672 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 673 { 674 struct uart_omap_port *up = to_uart_omap_port(port); 675 unsigned long flags; 676 677 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 678 spin_lock_irqsave(&up->port.lock, flags); 679 if (break_state == -1) 680 up->lcr |= UART_LCR_SBC; 681 else 682 up->lcr &= ~UART_LCR_SBC; 683 serial_out(up, UART_LCR, up->lcr); 684 spin_unlock_irqrestore(&up->port.lock, flags); 685 } 686 687 static int serial_omap_startup(struct uart_port *port) 688 { 689 struct uart_omap_port *up = to_uart_omap_port(port); 690 unsigned long flags; 691 int retval; 692 693 /* 694 * Allocate the IRQ 695 */ 696 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 697 up->name, up); 698 if (retval) 699 return retval; 700 701 /* Optional wake-up IRQ */ 702 if (up->wakeirq) { 703 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); 704 if (retval) { 705 free_irq(up->port.irq, up); 706 return retval; 707 } 708 } 709 710 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 711 712 pm_runtime_get_sync(up->dev); 713 /* 714 * Clear the FIFO buffers and disable them. 715 * (they will be reenabled in set_termios()) 716 */ 717 serial_omap_clear_fifos(up); 718 719 /* 720 * Clear the interrupt registers. 721 */ 722 (void) serial_in(up, UART_LSR); 723 if (serial_in(up, UART_LSR) & UART_LSR_DR) 724 (void) serial_in(up, UART_RX); 725 (void) serial_in(up, UART_IIR); 726 (void) serial_in(up, UART_MSR); 727 728 /* 729 * Now, initialize the UART 730 */ 731 serial_out(up, UART_LCR, UART_LCR_WLEN8); 732 spin_lock_irqsave(&up->port.lock, flags); 733 /* 734 * Most PC uarts need OUT2 raised to enable interrupts. 735 */ 736 up->port.mctrl |= TIOCM_OUT2; 737 serial_omap_set_mctrl(&up->port, up->port.mctrl); 738 spin_unlock_irqrestore(&up->port.lock, flags); 739 740 up->msr_saved_flags = 0; 741 /* 742 * Finally, enable interrupts. Note: Modem status interrupts 743 * are set via set_termios(), which will be occurring imminently 744 * anyway, so we don't enable them here. 745 */ 746 up->ier = UART_IER_RLSI | UART_IER_RDI; 747 serial_out(up, UART_IER, up->ier); 748 749 /* Enable module level wake up */ 750 up->wer = OMAP_UART_WER_MOD_WKUP; 751 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) 752 up->wer |= OMAP_UART_TX_WAKEUP_EN; 753 754 serial_out(up, UART_OMAP_WER, up->wer); 755 756 up->port_activity = jiffies; 757 return 0; 758 } 759 760 static void serial_omap_shutdown(struct uart_port *port) 761 { 762 struct uart_omap_port *up = to_uart_omap_port(port); 763 unsigned long flags; 764 765 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 766 767 /* 768 * Disable interrupts from this port 769 */ 770 up->ier = 0; 771 serial_out(up, UART_IER, 0); 772 773 spin_lock_irqsave(&up->port.lock, flags); 774 up->port.mctrl &= ~TIOCM_OUT2; 775 serial_omap_set_mctrl(&up->port, up->port.mctrl); 776 spin_unlock_irqrestore(&up->port.lock, flags); 777 778 /* 779 * Disable break condition and FIFOs 780 */ 781 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 782 serial_omap_clear_fifos(up); 783 784 /* 785 * Read data port to reset things, and then free the irq 786 */ 787 if (serial_in(up, UART_LSR) & UART_LSR_DR) 788 (void) serial_in(up, UART_RX); 789 790 pm_runtime_put_sync(up->dev); 791 free_irq(up->port.irq, up); 792 dev_pm_clear_wake_irq(up->dev); 793 } 794 795 static void serial_omap_uart_qos_work(struct work_struct *work) 796 { 797 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 798 qos_work); 799 800 cpu_latency_qos_update_request(&up->pm_qos_request, up->latency); 801 } 802 803 static void 804 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 805 struct ktermios *old) 806 { 807 struct uart_omap_port *up = to_uart_omap_port(port); 808 unsigned char cval = 0; 809 unsigned long flags; 810 unsigned int baud, quot; 811 812 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag)); 813 814 if (termios->c_cflag & CSTOPB) 815 cval |= UART_LCR_STOP; 816 if (termios->c_cflag & PARENB) 817 cval |= UART_LCR_PARITY; 818 if (!(termios->c_cflag & PARODD)) 819 cval |= UART_LCR_EPAR; 820 if (termios->c_cflag & CMSPAR) 821 cval |= UART_LCR_SPAR; 822 823 /* 824 * Ask the core to calculate the divisor for us. 825 */ 826 827 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 828 quot = serial_omap_get_divisor(port, baud); 829 830 /* calculate wakeup latency constraint */ 831 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 832 up->latency = up->calc_latency; 833 schedule_work(&up->qos_work); 834 835 up->dll = quot & 0xff; 836 up->dlh = quot >> 8; 837 up->mdr1 = UART_OMAP_MDR1_DISABLE; 838 839 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 840 UART_FCR_ENABLE_FIFO; 841 842 /* 843 * Ok, we're now changing the port state. Do it with 844 * interrupts disabled. 845 */ 846 spin_lock_irqsave(&up->port.lock, flags); 847 848 /* 849 * Update the per-port timeout. 850 */ 851 uart_update_timeout(port, termios->c_cflag, baud); 852 853 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 854 if (termios->c_iflag & INPCK) 855 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 856 if (termios->c_iflag & (BRKINT | PARMRK)) 857 up->port.read_status_mask |= UART_LSR_BI; 858 859 /* 860 * Characters to ignore 861 */ 862 up->port.ignore_status_mask = 0; 863 if (termios->c_iflag & IGNPAR) 864 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 865 if (termios->c_iflag & IGNBRK) { 866 up->port.ignore_status_mask |= UART_LSR_BI; 867 /* 868 * If we're ignoring parity and break indicators, 869 * ignore overruns too (for real raw support). 870 */ 871 if (termios->c_iflag & IGNPAR) 872 up->port.ignore_status_mask |= UART_LSR_OE; 873 } 874 875 /* 876 * ignore all characters if CREAD is not set 877 */ 878 if ((termios->c_cflag & CREAD) == 0) 879 up->port.ignore_status_mask |= UART_LSR_DR; 880 881 /* 882 * Modem status interrupts 883 */ 884 up->ier &= ~UART_IER_MSI; 885 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 886 up->ier |= UART_IER_MSI; 887 serial_out(up, UART_IER, up->ier); 888 serial_out(up, UART_LCR, cval); /* reset DLAB */ 889 up->lcr = cval; 890 up->scr = 0; 891 892 /* FIFOs and DMA Settings */ 893 894 /* FCR can be changed only when the 895 * baud clock is not running 896 * DLL_REG and DLH_REG set to 0. 897 */ 898 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 899 serial_out(up, UART_DLL, 0); 900 serial_out(up, UART_DLM, 0); 901 serial_out(up, UART_LCR, 0); 902 903 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 904 905 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 906 up->efr &= ~UART_EFR_SCD; 907 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 908 909 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 910 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 911 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 912 /* FIFO ENABLE, DMA MODE */ 913 914 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 915 /* 916 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 917 * sets Enables the granularity of 1 for TRIGGER RX 918 * level. Along with setting RX FIFO trigger level 919 * to 1 (as noted below, 16 characters) and TLR[3:0] 920 * to zero this will result RX FIFO threshold level 921 * to 1 character, instead of 16 as noted in comment 922 * below. 923 */ 924 925 /* Set receive FIFO threshold to 16 characters and 926 * transmit FIFO threshold to 32 spaces 927 */ 928 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 929 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 930 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 931 UART_FCR_ENABLE_FIFO; 932 933 serial_out(up, UART_FCR, up->fcr); 934 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 935 936 serial_out(up, UART_OMAP_SCR, up->scr); 937 938 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 939 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 940 serial_out(up, UART_MCR, up->mcr); 941 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 942 serial_out(up, UART_EFR, up->efr); 943 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 944 945 /* Protocol, Baud Rate, and Interrupt Settings */ 946 947 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 948 serial_omap_mdr1_errataset(up, up->mdr1); 949 else 950 serial_out(up, UART_OMAP_MDR1, up->mdr1); 951 952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 953 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 954 955 serial_out(up, UART_LCR, 0); 956 serial_out(up, UART_IER, 0); 957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 958 959 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 960 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 961 962 serial_out(up, UART_LCR, 0); 963 serial_out(up, UART_IER, up->ier); 964 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 965 966 serial_out(up, UART_EFR, up->efr); 967 serial_out(up, UART_LCR, cval); 968 969 if (!serial_omap_baud_is_mode16(port, baud)) 970 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 971 else 972 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 973 974 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 975 serial_omap_mdr1_errataset(up, up->mdr1); 976 else 977 serial_out(up, UART_OMAP_MDR1, up->mdr1); 978 979 /* Configure flow control */ 980 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 981 982 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 983 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 984 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 985 986 /* Enable access to TCR/TLR */ 987 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 989 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 990 991 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 992 993 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 994 995 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 996 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 997 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 998 up->efr |= UART_EFR_CTS; 999 } else { 1000 /* Disable AUTORTS and AUTOCTS */ 1001 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 1002 } 1003 1004 if (up->port.flags & UPF_SOFT_FLOW) { 1005 /* clear SW control mode bits */ 1006 up->efr &= OMAP_UART_SW_CLR; 1007 1008 /* 1009 * IXON Flag: 1010 * Enable XON/XOFF flow control on input. 1011 * Receiver compares XON1, XOFF1. 1012 */ 1013 if (termios->c_iflag & IXON) 1014 up->efr |= OMAP_UART_SW_RX; 1015 1016 /* 1017 * IXOFF Flag: 1018 * Enable XON/XOFF flow control on output. 1019 * Transmit XON1, XOFF1 1020 */ 1021 if (termios->c_iflag & IXOFF) { 1022 up->port.status |= UPSTAT_AUTOXOFF; 1023 up->efr |= OMAP_UART_SW_TX; 1024 } 1025 1026 /* 1027 * IXANY Flag: 1028 * Enable any character to restart output. 1029 * Operation resumes after receiving any 1030 * character after recognition of the XOFF character 1031 */ 1032 if (termios->c_iflag & IXANY) 1033 up->mcr |= UART_MCR_XONANY; 1034 else 1035 up->mcr &= ~UART_MCR_XONANY; 1036 } 1037 serial_out(up, UART_MCR, up->mcr); 1038 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1039 serial_out(up, UART_EFR, up->efr); 1040 serial_out(up, UART_LCR, up->lcr); 1041 1042 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1043 1044 spin_unlock_irqrestore(&up->port.lock, flags); 1045 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1046 } 1047 1048 static void 1049 serial_omap_pm(struct uart_port *port, unsigned int state, 1050 unsigned int oldstate) 1051 { 1052 struct uart_omap_port *up = to_uart_omap_port(port); 1053 unsigned char efr; 1054 1055 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1056 1057 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1058 efr = serial_in(up, UART_EFR); 1059 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1060 serial_out(up, UART_LCR, 0); 1061 1062 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1063 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1064 serial_out(up, UART_EFR, efr); 1065 serial_out(up, UART_LCR, 0); 1066 } 1067 1068 static void serial_omap_release_port(struct uart_port *port) 1069 { 1070 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1071 } 1072 1073 static int serial_omap_request_port(struct uart_port *port) 1074 { 1075 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1076 return 0; 1077 } 1078 1079 static void serial_omap_config_port(struct uart_port *port, int flags) 1080 { 1081 struct uart_omap_port *up = to_uart_omap_port(port); 1082 1083 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1084 up->port.line); 1085 up->port.type = PORT_OMAP; 1086 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1087 } 1088 1089 static int 1090 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1091 { 1092 /* we don't want the core code to modify any port params */ 1093 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1094 return -EINVAL; 1095 } 1096 1097 static const char * 1098 serial_omap_type(struct uart_port *port) 1099 { 1100 struct uart_omap_port *up = to_uart_omap_port(port); 1101 1102 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1103 return up->name; 1104 } 1105 1106 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up) 1107 { 1108 unsigned int status, tmout = 10000; 1109 1110 /* Wait up to 10ms for the character(s) to be sent. */ 1111 do { 1112 status = serial_in(up, UART_LSR); 1113 1114 if (status & UART_LSR_BI) 1115 up->lsr_break_flag = UART_LSR_BI; 1116 1117 if (--tmout == 0) 1118 break; 1119 udelay(1); 1120 } while (!uart_lsr_tx_empty(status)); 1121 1122 /* Wait up to 1s for flow control if necessary */ 1123 if (up->port.flags & UPF_CONS_FLOW) { 1124 tmout = 1000000; 1125 for (tmout = 1000000; tmout; tmout--) { 1126 unsigned int msr = serial_in(up, UART_MSR); 1127 1128 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1129 if (msr & UART_MSR_CTS) 1130 break; 1131 1132 udelay(1); 1133 } 1134 } 1135 } 1136 1137 #ifdef CONFIG_CONSOLE_POLL 1138 1139 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1140 { 1141 struct uart_omap_port *up = to_uart_omap_port(port); 1142 1143 wait_for_xmitr(up); 1144 serial_out(up, UART_TX, ch); 1145 } 1146 1147 static int serial_omap_poll_get_char(struct uart_port *port) 1148 { 1149 struct uart_omap_port *up = to_uart_omap_port(port); 1150 unsigned int status; 1151 1152 status = serial_in(up, UART_LSR); 1153 if (!(status & UART_LSR_DR)) { 1154 status = NO_POLL_CHAR; 1155 goto out; 1156 } 1157 1158 status = serial_in(up, UART_RX); 1159 1160 out: 1161 return status; 1162 } 1163 1164 #endif /* CONFIG_CONSOLE_POLL */ 1165 1166 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1167 1168 #ifdef CONFIG_SERIAL_EARLYCON 1169 static unsigned int omap_serial_early_in(struct uart_port *port, int offset) 1170 { 1171 offset <<= port->regshift; 1172 return readw(port->membase + offset); 1173 } 1174 1175 static void omap_serial_early_out(struct uart_port *port, int offset, 1176 int value) 1177 { 1178 offset <<= port->regshift; 1179 writew(value, port->membase + offset); 1180 } 1181 1182 static void omap_serial_early_putc(struct uart_port *port, unsigned char c) 1183 { 1184 unsigned int status; 1185 1186 for (;;) { 1187 status = omap_serial_early_in(port, UART_LSR); 1188 if (uart_lsr_tx_empty(status)) 1189 break; 1190 cpu_relax(); 1191 } 1192 omap_serial_early_out(port, UART_TX, c); 1193 } 1194 1195 static void early_omap_serial_write(struct console *console, const char *s, 1196 unsigned int count) 1197 { 1198 struct earlycon_device *device = console->data; 1199 struct uart_port *port = &device->port; 1200 1201 uart_console_write(port, s, count, omap_serial_early_putc); 1202 } 1203 1204 static int __init early_omap_serial_setup(struct earlycon_device *device, 1205 const char *options) 1206 { 1207 struct uart_port *port = &device->port; 1208 1209 if (!(device->port.membase || device->port.iobase)) 1210 return -ENODEV; 1211 1212 port->regshift = 2; 1213 device->con->write = early_omap_serial_write; 1214 return 0; 1215 } 1216 1217 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup); 1218 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup); 1219 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup); 1220 #endif /* CONFIG_SERIAL_EARLYCON */ 1221 1222 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1223 1224 static struct uart_driver serial_omap_reg; 1225 1226 static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch) 1227 { 1228 struct uart_omap_port *up = to_uart_omap_port(port); 1229 1230 wait_for_xmitr(up); 1231 serial_out(up, UART_TX, ch); 1232 } 1233 1234 static void 1235 serial_omap_console_write(struct console *co, const char *s, 1236 unsigned int count) 1237 { 1238 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1239 unsigned long flags; 1240 unsigned int ier; 1241 int locked = 1; 1242 1243 local_irq_save(flags); 1244 if (up->port.sysrq) 1245 locked = 0; 1246 else if (oops_in_progress) 1247 locked = spin_trylock(&up->port.lock); 1248 else 1249 spin_lock(&up->port.lock); 1250 1251 /* 1252 * First save the IER then disable the interrupts 1253 */ 1254 ier = serial_in(up, UART_IER); 1255 serial_out(up, UART_IER, 0); 1256 1257 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1258 1259 /* 1260 * Finally, wait for transmitter to become empty 1261 * and restore the IER 1262 */ 1263 wait_for_xmitr(up); 1264 serial_out(up, UART_IER, ier); 1265 /* 1266 * The receive handling will happen properly because the 1267 * receive ready bit will still be set; it is not cleared 1268 * on read. However, modem control will not, we must 1269 * call it if we have saved something in the saved flags 1270 * while processing with interrupts off. 1271 */ 1272 if (up->msr_saved_flags) 1273 check_modem_status(up); 1274 1275 if (locked) 1276 spin_unlock(&up->port.lock); 1277 local_irq_restore(flags); 1278 } 1279 1280 static int __init 1281 serial_omap_console_setup(struct console *co, char *options) 1282 { 1283 struct uart_omap_port *up; 1284 int baud = 115200; 1285 int bits = 8; 1286 int parity = 'n'; 1287 int flow = 'n'; 1288 1289 if (serial_omap_console_ports[co->index] == NULL) 1290 return -ENODEV; 1291 up = serial_omap_console_ports[co->index]; 1292 1293 if (options) 1294 uart_parse_options(options, &baud, &parity, &bits, &flow); 1295 1296 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1297 } 1298 1299 static struct console serial_omap_console = { 1300 .name = OMAP_SERIAL_NAME, 1301 .write = serial_omap_console_write, 1302 .device = uart_console_device, 1303 .setup = serial_omap_console_setup, 1304 .flags = CON_PRINTBUFFER, 1305 .index = -1, 1306 .data = &serial_omap_reg, 1307 }; 1308 1309 static void serial_omap_add_console_port(struct uart_omap_port *up) 1310 { 1311 serial_omap_console_ports[up->port.line] = up; 1312 } 1313 1314 #define OMAP_CONSOLE (&serial_omap_console) 1315 1316 #else 1317 1318 #define OMAP_CONSOLE NULL 1319 1320 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1321 {} 1322 1323 #endif 1324 1325 /* Enable or disable the rs485 support */ 1326 static int 1327 serial_omap_config_rs485(struct uart_port *port, struct ktermios *termios, 1328 struct serial_rs485 *rs485) 1329 { 1330 struct uart_omap_port *up = to_uart_omap_port(port); 1331 unsigned int mode; 1332 int val; 1333 1334 /* Disable interrupts from this port */ 1335 mode = up->ier; 1336 up->ier = 0; 1337 serial_out(up, UART_IER, 0); 1338 1339 if (up->rts_gpiod) { 1340 /* enable / disable rts */ 1341 val = (rs485->flags & SER_RS485_ENABLED) ? 1342 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; 1343 val = (rs485->flags & val) ? 1 : 0; 1344 gpiod_set_value(up->rts_gpiod, val); 1345 } 1346 1347 /* Enable interrupts */ 1348 up->ier = mode; 1349 serial_out(up, UART_IER, up->ier); 1350 1351 /* If RS-485 is disabled, make sure the THR interrupt is fired when 1352 * TX FIFO is below the trigger level. 1353 */ 1354 if (!(rs485->flags & SER_RS485_ENABLED) && 1355 (up->scr & OMAP_UART_SCR_TX_EMPTY)) { 1356 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 1357 serial_out(up, UART_OMAP_SCR, up->scr); 1358 } 1359 1360 return 0; 1361 } 1362 1363 static const struct uart_ops serial_omap_pops = { 1364 .tx_empty = serial_omap_tx_empty, 1365 .set_mctrl = serial_omap_set_mctrl, 1366 .get_mctrl = serial_omap_get_mctrl, 1367 .stop_tx = serial_omap_stop_tx, 1368 .start_tx = serial_omap_start_tx, 1369 .throttle = serial_omap_throttle, 1370 .unthrottle = serial_omap_unthrottle, 1371 .stop_rx = serial_omap_stop_rx, 1372 .enable_ms = serial_omap_enable_ms, 1373 .break_ctl = serial_omap_break_ctl, 1374 .startup = serial_omap_startup, 1375 .shutdown = serial_omap_shutdown, 1376 .set_termios = serial_omap_set_termios, 1377 .pm = serial_omap_pm, 1378 .type = serial_omap_type, 1379 .release_port = serial_omap_release_port, 1380 .request_port = serial_omap_request_port, 1381 .config_port = serial_omap_config_port, 1382 .verify_port = serial_omap_verify_port, 1383 #ifdef CONFIG_CONSOLE_POLL 1384 .poll_put_char = serial_omap_poll_put_char, 1385 .poll_get_char = serial_omap_poll_get_char, 1386 #endif 1387 }; 1388 1389 static struct uart_driver serial_omap_reg = { 1390 .owner = THIS_MODULE, 1391 .driver_name = "OMAP-SERIAL", 1392 .dev_name = OMAP_SERIAL_NAME, 1393 .nr = OMAP_MAX_HSUART_PORTS, 1394 .cons = OMAP_CONSOLE, 1395 }; 1396 1397 #ifdef CONFIG_PM_SLEEP 1398 static int serial_omap_prepare(struct device *dev) 1399 { 1400 struct uart_omap_port *up = dev_get_drvdata(dev); 1401 1402 up->is_suspending = true; 1403 1404 return 0; 1405 } 1406 1407 static void serial_omap_complete(struct device *dev) 1408 { 1409 struct uart_omap_port *up = dev_get_drvdata(dev); 1410 1411 up->is_suspending = false; 1412 } 1413 1414 static int serial_omap_suspend(struct device *dev) 1415 { 1416 struct uart_omap_port *up = dev_get_drvdata(dev); 1417 1418 uart_suspend_port(&serial_omap_reg, &up->port); 1419 flush_work(&up->qos_work); 1420 1421 if (device_may_wakeup(dev)) 1422 serial_omap_enable_wakeup(up, true); 1423 else 1424 serial_omap_enable_wakeup(up, false); 1425 1426 return 0; 1427 } 1428 1429 static int serial_omap_resume(struct device *dev) 1430 { 1431 struct uart_omap_port *up = dev_get_drvdata(dev); 1432 1433 if (device_may_wakeup(dev)) 1434 serial_omap_enable_wakeup(up, false); 1435 1436 uart_resume_port(&serial_omap_reg, &up->port); 1437 1438 return 0; 1439 } 1440 #else 1441 #define serial_omap_prepare NULL 1442 #define serial_omap_complete NULL 1443 #endif /* CONFIG_PM_SLEEP */ 1444 1445 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1446 { 1447 u32 mvr, scheme; 1448 u16 revision, major, minor; 1449 1450 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); 1451 1452 /* Check revision register scheme */ 1453 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1454 1455 switch (scheme) { 1456 case 0: /* Legacy Scheme: OMAP2/3 */ 1457 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1458 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1459 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1460 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1461 break; 1462 case 1: 1463 /* New Scheme: OMAP4+ */ 1464 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1465 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1466 OMAP_UART_MVR_MAJ_SHIFT; 1467 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1468 break; 1469 default: 1470 dev_warn(up->dev, 1471 "Unknown %s revision, defaulting to highest\n", 1472 up->name); 1473 /* highest possible revision */ 1474 major = 0xff; 1475 minor = 0xff; 1476 } 1477 1478 /* normalize revision for the driver */ 1479 revision = UART_BUILD_REVISION(major, minor); 1480 1481 switch (revision) { 1482 case OMAP_UART_REV_46: 1483 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1484 UART_ERRATA_i291_DMA_FORCEIDLE); 1485 break; 1486 case OMAP_UART_REV_52: 1487 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1488 UART_ERRATA_i291_DMA_FORCEIDLE); 1489 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1490 break; 1491 case OMAP_UART_REV_63: 1492 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1493 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1494 break; 1495 default: 1496 break; 1497 } 1498 } 1499 1500 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1501 { 1502 struct omap_uart_port_info *omap_up_info; 1503 1504 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1505 if (!omap_up_info) 1506 return NULL; /* out of memory */ 1507 1508 of_property_read_u32(dev->of_node, "clock-frequency", 1509 &omap_up_info->uartclk); 1510 1511 omap_up_info->flags = UPF_BOOT_AUTOCONF; 1512 1513 return omap_up_info; 1514 } 1515 1516 static int serial_omap_probe_rs485(struct uart_omap_port *up, 1517 struct device *dev) 1518 { 1519 struct serial_rs485 *rs485conf = &up->port.rs485; 1520 struct device_node *np = dev->of_node; 1521 enum gpiod_flags gflags; 1522 int ret; 1523 1524 rs485conf->flags = 0; 1525 up->rts_gpiod = NULL; 1526 1527 if (!np) 1528 return 0; 1529 1530 ret = uart_get_rs485_mode(&up->port); 1531 if (ret) 1532 return ret; 1533 1534 if (of_property_read_bool(np, "rs485-rts-active-high")) { 1535 rs485conf->flags |= SER_RS485_RTS_ON_SEND; 1536 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; 1537 } else { 1538 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND; 1539 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1540 } 1541 1542 /* check for tx enable gpio */ 1543 gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ? 1544 GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 1545 up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags); 1546 if (IS_ERR(up->rts_gpiod)) { 1547 ret = PTR_ERR(up->rts_gpiod); 1548 if (ret == -EPROBE_DEFER) 1549 return ret; 1550 /* 1551 * FIXME: the code historically ignored any other error than 1552 * -EPROBE_DEFER and just went on without GPIO. 1553 */ 1554 up->rts_gpiod = NULL; 1555 } else { 1556 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial"); 1557 } 1558 1559 return 0; 1560 } 1561 1562 static const struct serial_rs485 serial_omap_rs485_supported = { 1563 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND | 1564 SER_RS485_RX_DURING_TX, 1565 .delay_rts_before_send = 1, 1566 .delay_rts_after_send = 1, 1567 }; 1568 1569 static int serial_omap_probe(struct platform_device *pdev) 1570 { 1571 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); 1572 struct uart_omap_port *up; 1573 struct resource *mem; 1574 void __iomem *base; 1575 int uartirq = 0; 1576 int wakeirq = 0; 1577 int ret; 1578 1579 /* The optional wakeirq may be specified in the board dts file */ 1580 if (pdev->dev.of_node) { 1581 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1582 if (!uartirq) 1583 return -EPROBE_DEFER; 1584 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1585 omap_up_info = of_get_uart_port_info(&pdev->dev); 1586 pdev->dev.platform_data = omap_up_info; 1587 } else { 1588 uartirq = platform_get_irq(pdev, 0); 1589 if (uartirq < 0) 1590 return -EPROBE_DEFER; 1591 } 1592 1593 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1594 if (!up) 1595 return -ENOMEM; 1596 1597 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1598 base = devm_ioremap_resource(&pdev->dev, mem); 1599 if (IS_ERR(base)) 1600 return PTR_ERR(base); 1601 1602 up->dev = &pdev->dev; 1603 up->port.dev = &pdev->dev; 1604 up->port.type = PORT_OMAP; 1605 up->port.iotype = UPIO_MEM; 1606 up->port.irq = uartirq; 1607 up->port.regshift = 2; 1608 up->port.fifosize = 64; 1609 up->port.ops = &serial_omap_pops; 1610 up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE); 1611 1612 if (pdev->dev.of_node) 1613 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1614 else 1615 ret = pdev->id; 1616 1617 if (ret < 0) { 1618 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1619 ret); 1620 goto err_port_line; 1621 } 1622 up->port.line = ret; 1623 1624 if (up->port.line >= OMAP_MAX_HSUART_PORTS) { 1625 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, 1626 OMAP_MAX_HSUART_PORTS); 1627 ret = -ENXIO; 1628 goto err_port_line; 1629 } 1630 1631 up->wakeirq = wakeirq; 1632 if (!up->wakeirq) 1633 dev_info(up->port.dev, "no wakeirq for uart%d\n", 1634 up->port.line); 1635 1636 ret = serial_omap_probe_rs485(up, &pdev->dev); 1637 if (ret < 0) 1638 goto err_rs485; 1639 1640 sprintf(up->name, "OMAP UART%d", up->port.line); 1641 up->port.mapbase = mem->start; 1642 up->port.membase = base; 1643 up->port.flags = omap_up_info->flags; 1644 up->port.uartclk = omap_up_info->uartclk; 1645 up->port.rs485_config = serial_omap_config_rs485; 1646 up->port.rs485_supported = serial_omap_rs485_supported; 1647 if (!up->port.uartclk) { 1648 up->port.uartclk = DEFAULT_CLK_SPEED; 1649 dev_warn(&pdev->dev, 1650 "No clock speed specified: using default: %d\n", 1651 DEFAULT_CLK_SPEED); 1652 } 1653 1654 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1655 up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1656 cpu_latency_qos_add_request(&up->pm_qos_request, up->latency); 1657 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1658 1659 platform_set_drvdata(pdev, up); 1660 if (omap_up_info->autosuspend_timeout == 0) 1661 omap_up_info->autosuspend_timeout = -1; 1662 1663 device_init_wakeup(up->dev, true); 1664 1665 pm_runtime_enable(&pdev->dev); 1666 1667 pm_runtime_get_sync(&pdev->dev); 1668 1669 omap_serial_fill_features_erratas(up); 1670 1671 ui[up->port.line] = up; 1672 serial_omap_add_console_port(up); 1673 1674 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1675 if (ret != 0) 1676 goto err_add_port; 1677 1678 return 0; 1679 1680 err_add_port: 1681 pm_runtime_put_sync(&pdev->dev); 1682 pm_runtime_disable(&pdev->dev); 1683 cpu_latency_qos_remove_request(&up->pm_qos_request); 1684 device_init_wakeup(up->dev, false); 1685 err_rs485: 1686 err_port_line: 1687 return ret; 1688 } 1689 1690 static int serial_omap_remove(struct platform_device *dev) 1691 { 1692 struct uart_omap_port *up = platform_get_drvdata(dev); 1693 1694 pm_runtime_get_sync(up->dev); 1695 1696 uart_remove_one_port(&serial_omap_reg, &up->port); 1697 1698 pm_runtime_put_sync(up->dev); 1699 pm_runtime_disable(up->dev); 1700 cpu_latency_qos_remove_request(&up->pm_qos_request); 1701 device_init_wakeup(&dev->dev, false); 1702 1703 return 0; 1704 } 1705 1706 /* 1707 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1708 * The access to uart register after MDR1 Access 1709 * causes UART to corrupt data. 1710 * 1711 * Need a delay = 1712 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1713 * give 10 times as much 1714 */ 1715 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1716 { 1717 u8 timeout = 255; 1718 1719 serial_out(up, UART_OMAP_MDR1, mdr1); 1720 udelay(2); 1721 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1722 UART_FCR_CLEAR_RCVR); 1723 /* 1724 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1725 * TX_FIFO_E bit is 1. 1726 */ 1727 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1728 (UART_LSR_THRE | UART_LSR_DR))) { 1729 timeout--; 1730 if (!timeout) { 1731 /* Should *never* happen. we warn and carry on */ 1732 dev_crit(up->dev, "Errata i202: timedout %x\n", 1733 serial_in(up, UART_LSR)); 1734 break; 1735 } 1736 udelay(1); 1737 } 1738 } 1739 1740 #ifdef CONFIG_PM 1741 static void serial_omap_restore_context(struct uart_omap_port *up) 1742 { 1743 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1744 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1745 else 1746 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1747 1748 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1749 serial_out(up, UART_EFR, UART_EFR_ECB); 1750 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1751 serial_out(up, UART_IER, 0x0); 1752 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1753 serial_out(up, UART_DLL, up->dll); 1754 serial_out(up, UART_DLM, up->dlh); 1755 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1756 serial_out(up, UART_IER, up->ier); 1757 serial_out(up, UART_FCR, up->fcr); 1758 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1759 serial_out(up, UART_MCR, up->mcr); 1760 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1761 serial_out(up, UART_OMAP_SCR, up->scr); 1762 serial_out(up, UART_EFR, up->efr); 1763 serial_out(up, UART_LCR, up->lcr); 1764 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1765 serial_omap_mdr1_errataset(up, up->mdr1); 1766 else 1767 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1768 serial_out(up, UART_OMAP_WER, up->wer); 1769 } 1770 1771 static int serial_omap_runtime_suspend(struct device *dev) 1772 { 1773 struct uart_omap_port *up = dev_get_drvdata(dev); 1774 1775 if (!up) 1776 return -EINVAL; 1777 1778 /* 1779 * When using 'no_console_suspend', the console UART must not be 1780 * suspended. Since driver suspend is managed by runtime suspend, 1781 * preventing runtime suspend (by returning error) will keep device 1782 * active during suspend. 1783 */ 1784 if (up->is_suspending && !console_suspend_enabled && 1785 uart_console(&up->port)) 1786 return -EBUSY; 1787 1788 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1789 1790 serial_omap_enable_wakeup(up, true); 1791 1792 up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE; 1793 schedule_work(&up->qos_work); 1794 1795 return 0; 1796 } 1797 1798 static int serial_omap_runtime_resume(struct device *dev) 1799 { 1800 struct uart_omap_port *up = dev_get_drvdata(dev); 1801 1802 int loss_cnt = serial_omap_get_context_loss_count(up); 1803 1804 serial_omap_enable_wakeup(up, false); 1805 1806 if (loss_cnt < 0) { 1807 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", 1808 loss_cnt); 1809 serial_omap_restore_context(up); 1810 } else if (up->context_loss_cnt != loss_cnt) { 1811 serial_omap_restore_context(up); 1812 } 1813 up->latency = up->calc_latency; 1814 schedule_work(&up->qos_work); 1815 1816 return 0; 1817 } 1818 #endif 1819 1820 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1821 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1822 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1823 serial_omap_runtime_resume, NULL) 1824 .prepare = serial_omap_prepare, 1825 .complete = serial_omap_complete, 1826 }; 1827 1828 #if defined(CONFIG_OF) 1829 static const struct of_device_id omap_serial_of_match[] = { 1830 { .compatible = "ti,omap2-uart" }, 1831 { .compatible = "ti,omap3-uart" }, 1832 { .compatible = "ti,omap4-uart" }, 1833 {}, 1834 }; 1835 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1836 #endif 1837 1838 static struct platform_driver serial_omap_driver = { 1839 .probe = serial_omap_probe, 1840 .remove = serial_omap_remove, 1841 .driver = { 1842 .name = OMAP_SERIAL_DRIVER_NAME, 1843 .pm = &serial_omap_dev_pm_ops, 1844 .of_match_table = of_match_ptr(omap_serial_of_match), 1845 }, 1846 }; 1847 1848 static int __init serial_omap_init(void) 1849 { 1850 int ret; 1851 1852 ret = uart_register_driver(&serial_omap_reg); 1853 if (ret != 0) 1854 return ret; 1855 ret = platform_driver_register(&serial_omap_driver); 1856 if (ret != 0) 1857 uart_unregister_driver(&serial_omap_reg); 1858 return ret; 1859 } 1860 1861 static void __exit serial_omap_exit(void) 1862 { 1863 platform_driver_unregister(&serial_omap_driver); 1864 uart_unregister_driver(&serial_omap_reg); 1865 } 1866 1867 module_init(serial_omap_init); 1868 module_exit(serial_omap_exit); 1869 1870 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1871 MODULE_LICENSE("GPL"); 1872 MODULE_AUTHOR("Texas Instruments Inc"); 1873