1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/io.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/pm_wakeirq.h> 42 #include <linux/of.h> 43 #include <linux/of_irq.h> 44 #include <linux/gpio.h> 45 #include <linux/of_gpio.h> 46 #include <linux/platform_data/serial-omap.h> 47 48 #include <dt-bindings/gpio/gpio.h> 49 50 #define OMAP_MAX_HSUART_PORTS 10 51 52 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 53 54 #define OMAP_UART_REV_42 0x0402 55 #define OMAP_UART_REV_46 0x0406 56 #define OMAP_UART_REV_52 0x0502 57 #define OMAP_UART_REV_63 0x0603 58 59 #define OMAP_UART_TX_WAKEUP_EN BIT(7) 60 61 /* Feature flags */ 62 #define OMAP_UART_WER_HAS_TX_WAKEUP BIT(0) 63 64 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 65 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 66 67 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */ 68 69 /* SCR register bitmasks */ 70 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 71 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 72 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 73 74 /* FCR register bitmasks */ 75 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 76 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 77 78 /* MVR register bitmasks */ 79 #define OMAP_UART_MVR_SCHEME_SHIFT 30 80 81 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 82 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 83 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 84 85 #define OMAP_UART_MVR_MAJ_MASK 0x700 86 #define OMAP_UART_MVR_MAJ_SHIFT 8 87 #define OMAP_UART_MVR_MIN_MASK 0x3f 88 89 #define OMAP_UART_DMA_CH_FREE -1 90 91 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 92 #define OMAP_MODE13X_SPEED 230400 93 94 /* WER = 0x7F 95 * Enable module level wakeup in WER reg 96 */ 97 #define OMAP_UART_WER_MOD_WKUP 0x7F 98 99 /* Enable XON/XOFF flow control on output */ 100 #define OMAP_UART_SW_TX 0x08 101 102 /* Enable XON/XOFF flow control on input */ 103 #define OMAP_UART_SW_RX 0x02 104 105 #define OMAP_UART_SW_CLR 0xF0 106 107 #define OMAP_UART_TCR_TRIG 0x0F 108 109 struct uart_omap_dma { 110 u8 uart_dma_tx; 111 u8 uart_dma_rx; 112 int rx_dma_channel; 113 int tx_dma_channel; 114 dma_addr_t rx_buf_dma_phys; 115 dma_addr_t tx_buf_dma_phys; 116 unsigned int uart_base; 117 /* 118 * Buffer for rx dma. It is not required for tx because the buffer 119 * comes from port structure. 120 */ 121 unsigned char *rx_buf; 122 unsigned int prev_rx_dma_pos; 123 int tx_buf_size; 124 int tx_dma_used; 125 int rx_dma_used; 126 spinlock_t tx_lock; 127 spinlock_t rx_lock; 128 /* timer to poll activity on rx dma */ 129 struct timer_list rx_timer; 130 unsigned int rx_buf_size; 131 unsigned int rx_poll_rate; 132 unsigned int rx_timeout; 133 }; 134 135 struct uart_omap_port { 136 struct uart_port port; 137 struct uart_omap_dma uart_dma; 138 struct device *dev; 139 int wakeirq; 140 141 unsigned char ier; 142 unsigned char lcr; 143 unsigned char mcr; 144 unsigned char fcr; 145 unsigned char efr; 146 unsigned char dll; 147 unsigned char dlh; 148 unsigned char mdr1; 149 unsigned char scr; 150 unsigned char wer; 151 152 int use_dma; 153 /* 154 * Some bits in registers are cleared on a read, so they must 155 * be saved whenever the register is read, but the bits will not 156 * be immediately processed. 157 */ 158 unsigned int lsr_break_flag; 159 unsigned char msr_saved_flags; 160 char name[20]; 161 unsigned long port_activity; 162 int context_loss_cnt; 163 u32 errata; 164 u32 features; 165 166 int rts_gpio; 167 168 struct pm_qos_request pm_qos_request; 169 u32 latency; 170 u32 calc_latency; 171 struct work_struct qos_work; 172 bool is_suspending; 173 }; 174 175 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 176 177 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 178 179 /* Forward declaration of functions */ 180 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 181 182 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 183 { 184 offset <<= up->port.regshift; 185 return readw(up->port.membase + offset); 186 } 187 188 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 189 { 190 offset <<= up->port.regshift; 191 writew(value, up->port.membase + offset); 192 } 193 194 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 195 { 196 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 197 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 198 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 199 serial_out(up, UART_FCR, 0); 200 } 201 202 #ifdef CONFIG_PM 203 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 204 { 205 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 206 207 if (!pdata || !pdata->get_context_loss_count) 208 return -EINVAL; 209 210 return pdata->get_context_loss_count(up->dev); 211 } 212 213 /* REVISIT: Remove this when omap3 boots in device tree only mode */ 214 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 215 { 216 struct omap_uart_port_info *pdata = dev_get_platdata(up->dev); 217 218 if (!pdata || !pdata->enable_wakeup) 219 return; 220 221 pdata->enable_wakeup(up->dev, enable); 222 } 223 #endif /* CONFIG_PM */ 224 225 /* 226 * Calculate the absolute difference between the desired and actual baud 227 * rate for the given mode. 228 */ 229 static inline int calculate_baud_abs_diff(struct uart_port *port, 230 unsigned int baud, unsigned int mode) 231 { 232 unsigned int n = port->uartclk / (mode * baud); 233 int abs_diff; 234 235 if (n == 0) 236 n = 1; 237 238 abs_diff = baud - (port->uartclk / (mode * n)); 239 if (abs_diff < 0) 240 abs_diff = -abs_diff; 241 242 return abs_diff; 243 } 244 245 /* 246 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 247 * @port: uart port info 248 * @baud: baudrate for which mode needs to be determined 249 * 250 * Returns true if baud rate is MODE16X and false if MODE13X 251 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 252 * and Error Rates" determines modes not for all common baud rates. 253 * E.g. for 1000000 baud rate mode must be 16x, but according to that 254 * table it's determined as 13x. 255 */ 256 static bool 257 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 258 { 259 int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13); 260 int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16); 261 262 return (abs_diff_13 >= abs_diff_16); 263 } 264 265 /* 266 * serial_omap_get_divisor - calculate divisor value 267 * @port: uart port info 268 * @baud: baudrate for which divisor needs to be calculated. 269 */ 270 static unsigned int 271 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 272 { 273 unsigned int mode; 274 275 if (!serial_omap_baud_is_mode16(port, baud)) 276 mode = 13; 277 else 278 mode = 16; 279 return port->uartclk/(mode * baud); 280 } 281 282 static void serial_omap_enable_ms(struct uart_port *port) 283 { 284 struct uart_omap_port *up = to_uart_omap_port(port); 285 286 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 287 288 pm_runtime_get_sync(up->dev); 289 up->ier |= UART_IER_MSI; 290 serial_out(up, UART_IER, up->ier); 291 pm_runtime_mark_last_busy(up->dev); 292 pm_runtime_put_autosuspend(up->dev); 293 } 294 295 static void serial_omap_stop_tx(struct uart_port *port) 296 { 297 struct uart_omap_port *up = to_uart_omap_port(port); 298 int res; 299 300 pm_runtime_get_sync(up->dev); 301 302 /* Handle RS-485 */ 303 if (port->rs485.flags & SER_RS485_ENABLED) { 304 if (up->scr & OMAP_UART_SCR_TX_EMPTY) { 305 /* THR interrupt is fired when both TX FIFO and TX 306 * shift register are empty. This means there's nothing 307 * left to transmit now, so make sure the THR interrupt 308 * is fired when TX FIFO is below the trigger level, 309 * disable THR interrupts and toggle the RS-485 GPIO 310 * data direction pin if needed. 311 */ 312 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 313 serial_out(up, UART_OMAP_SCR, up->scr); 314 res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ? 315 1 : 0; 316 if (gpio_get_value(up->rts_gpio) != res) { 317 if (port->rs485.delay_rts_after_send > 0) 318 mdelay( 319 port->rs485.delay_rts_after_send); 320 gpio_set_value(up->rts_gpio, res); 321 } 322 } else { 323 /* We're asked to stop, but there's still stuff in the 324 * UART FIFO, so make sure the THR interrupt is fired 325 * when both TX FIFO and TX shift register are empty. 326 * The next THR interrupt (if no transmission is started 327 * in the meantime) will indicate the end of a 328 * transmission. Therefore we _don't_ disable THR 329 * interrupts in this situation. 330 */ 331 up->scr |= OMAP_UART_SCR_TX_EMPTY; 332 serial_out(up, UART_OMAP_SCR, up->scr); 333 return; 334 } 335 } 336 337 if (up->ier & UART_IER_THRI) { 338 up->ier &= ~UART_IER_THRI; 339 serial_out(up, UART_IER, up->ier); 340 } 341 342 if ((port->rs485.flags & SER_RS485_ENABLED) && 343 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) { 344 /* 345 * Empty the RX FIFO, we are not interested in anything 346 * received during the half-duplex transmission. 347 */ 348 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_RCVR); 349 /* Re-enable RX interrupts */ 350 up->ier |= UART_IER_RLSI | UART_IER_RDI; 351 up->port.read_status_mask |= UART_LSR_DR; 352 serial_out(up, UART_IER, up->ier); 353 } 354 355 pm_runtime_mark_last_busy(up->dev); 356 pm_runtime_put_autosuspend(up->dev); 357 } 358 359 static void serial_omap_stop_rx(struct uart_port *port) 360 { 361 struct uart_omap_port *up = to_uart_omap_port(port); 362 363 pm_runtime_get_sync(up->dev); 364 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 365 up->port.read_status_mask &= ~UART_LSR_DR; 366 serial_out(up, UART_IER, up->ier); 367 pm_runtime_mark_last_busy(up->dev); 368 pm_runtime_put_autosuspend(up->dev); 369 } 370 371 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 372 { 373 struct circ_buf *xmit = &up->port.state->xmit; 374 int count; 375 376 if (up->port.x_char) { 377 serial_out(up, UART_TX, up->port.x_char); 378 up->port.icount.tx++; 379 up->port.x_char = 0; 380 return; 381 } 382 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 383 serial_omap_stop_tx(&up->port); 384 return; 385 } 386 count = up->port.fifosize / 4; 387 do { 388 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 389 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 390 up->port.icount.tx++; 391 if (uart_circ_empty(xmit)) 392 break; 393 } while (--count > 0); 394 395 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 396 uart_write_wakeup(&up->port); 397 398 if (uart_circ_empty(xmit)) 399 serial_omap_stop_tx(&up->port); 400 } 401 402 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 403 { 404 if (!(up->ier & UART_IER_THRI)) { 405 up->ier |= UART_IER_THRI; 406 serial_out(up, UART_IER, up->ier); 407 } 408 } 409 410 static void serial_omap_start_tx(struct uart_port *port) 411 { 412 struct uart_omap_port *up = to_uart_omap_port(port); 413 int res; 414 415 pm_runtime_get_sync(up->dev); 416 417 /* Handle RS-485 */ 418 if (port->rs485.flags & SER_RS485_ENABLED) { 419 /* Fire THR interrupts when FIFO is below trigger level */ 420 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 421 serial_out(up, UART_OMAP_SCR, up->scr); 422 423 /* if rts not already enabled */ 424 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0; 425 if (gpio_get_value(up->rts_gpio) != res) { 426 gpio_set_value(up->rts_gpio, res); 427 if (port->rs485.delay_rts_before_send > 0) 428 mdelay(port->rs485.delay_rts_before_send); 429 } 430 } 431 432 if ((port->rs485.flags & SER_RS485_ENABLED) && 433 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) 434 serial_omap_stop_rx(port); 435 436 serial_omap_enable_ier_thri(up); 437 pm_runtime_mark_last_busy(up->dev); 438 pm_runtime_put_autosuspend(up->dev); 439 } 440 441 static void serial_omap_throttle(struct uart_port *port) 442 { 443 struct uart_omap_port *up = to_uart_omap_port(port); 444 unsigned long flags; 445 446 pm_runtime_get_sync(up->dev); 447 spin_lock_irqsave(&up->port.lock, flags); 448 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 449 serial_out(up, UART_IER, up->ier); 450 spin_unlock_irqrestore(&up->port.lock, flags); 451 pm_runtime_mark_last_busy(up->dev); 452 pm_runtime_put_autosuspend(up->dev); 453 } 454 455 static void serial_omap_unthrottle(struct uart_port *port) 456 { 457 struct uart_omap_port *up = to_uart_omap_port(port); 458 unsigned long flags; 459 460 pm_runtime_get_sync(up->dev); 461 spin_lock_irqsave(&up->port.lock, flags); 462 up->ier |= UART_IER_RLSI | UART_IER_RDI; 463 serial_out(up, UART_IER, up->ier); 464 spin_unlock_irqrestore(&up->port.lock, flags); 465 pm_runtime_mark_last_busy(up->dev); 466 pm_runtime_put_autosuspend(up->dev); 467 } 468 469 static unsigned int check_modem_status(struct uart_omap_port *up) 470 { 471 unsigned int status; 472 473 status = serial_in(up, UART_MSR); 474 status |= up->msr_saved_flags; 475 up->msr_saved_flags = 0; 476 if ((status & UART_MSR_ANY_DELTA) == 0) 477 return status; 478 479 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 480 up->port.state != NULL) { 481 if (status & UART_MSR_TERI) 482 up->port.icount.rng++; 483 if (status & UART_MSR_DDSR) 484 up->port.icount.dsr++; 485 if (status & UART_MSR_DDCD) 486 uart_handle_dcd_change 487 (&up->port, status & UART_MSR_DCD); 488 if (status & UART_MSR_DCTS) 489 uart_handle_cts_change 490 (&up->port, status & UART_MSR_CTS); 491 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 492 } 493 494 return status; 495 } 496 497 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 498 { 499 unsigned int flag; 500 unsigned char ch = 0; 501 502 if (likely(lsr & UART_LSR_DR)) 503 ch = serial_in(up, UART_RX); 504 505 up->port.icount.rx++; 506 flag = TTY_NORMAL; 507 508 if (lsr & UART_LSR_BI) { 509 flag = TTY_BREAK; 510 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 511 up->port.icount.brk++; 512 /* 513 * We do the SysRQ and SAK checking 514 * here because otherwise the break 515 * may get masked by ignore_status_mask 516 * or read_status_mask. 517 */ 518 if (uart_handle_break(&up->port)) 519 return; 520 521 } 522 523 if (lsr & UART_LSR_PE) { 524 flag = TTY_PARITY; 525 up->port.icount.parity++; 526 } 527 528 if (lsr & UART_LSR_FE) { 529 flag = TTY_FRAME; 530 up->port.icount.frame++; 531 } 532 533 if (lsr & UART_LSR_OE) 534 up->port.icount.overrun++; 535 536 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 537 if (up->port.line == up->port.cons->index) { 538 /* Recover the break flag from console xmit */ 539 lsr |= up->lsr_break_flag; 540 } 541 #endif 542 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 543 } 544 545 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 546 { 547 unsigned char ch = 0; 548 unsigned int flag; 549 550 if (!(lsr & UART_LSR_DR)) 551 return; 552 553 ch = serial_in(up, UART_RX); 554 flag = TTY_NORMAL; 555 up->port.icount.rx++; 556 557 if (uart_handle_sysrq_char(&up->port, ch)) 558 return; 559 560 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 561 } 562 563 /** 564 * serial_omap_irq() - This handles the interrupt from one port 565 * @irq: uart port irq number 566 * @dev_id: uart port info 567 */ 568 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 569 { 570 struct uart_omap_port *up = dev_id; 571 unsigned int iir, lsr; 572 unsigned int type; 573 irqreturn_t ret = IRQ_NONE; 574 int max_count = 256; 575 576 spin_lock(&up->port.lock); 577 pm_runtime_get_sync(up->dev); 578 579 do { 580 iir = serial_in(up, UART_IIR); 581 if (iir & UART_IIR_NO_INT) 582 break; 583 584 ret = IRQ_HANDLED; 585 lsr = serial_in(up, UART_LSR); 586 587 /* extract IRQ type from IIR register */ 588 type = iir & 0x3e; 589 590 switch (type) { 591 case UART_IIR_MSI: 592 check_modem_status(up); 593 break; 594 case UART_IIR_THRI: 595 transmit_chars(up, lsr); 596 break; 597 case UART_IIR_RX_TIMEOUT: 598 /* FALLTHROUGH */ 599 case UART_IIR_RDI: 600 serial_omap_rdi(up, lsr); 601 break; 602 case UART_IIR_RLSI: 603 serial_omap_rlsi(up, lsr); 604 break; 605 case UART_IIR_CTS_RTS_DSR: 606 /* simply try again */ 607 break; 608 case UART_IIR_XOFF: 609 /* FALLTHROUGH */ 610 default: 611 break; 612 } 613 } while (!(iir & UART_IIR_NO_INT) && max_count--); 614 615 spin_unlock(&up->port.lock); 616 617 tty_flip_buffer_push(&up->port.state->port); 618 619 pm_runtime_mark_last_busy(up->dev); 620 pm_runtime_put_autosuspend(up->dev); 621 up->port_activity = jiffies; 622 623 return ret; 624 } 625 626 static unsigned int serial_omap_tx_empty(struct uart_port *port) 627 { 628 struct uart_omap_port *up = to_uart_omap_port(port); 629 unsigned long flags = 0; 630 unsigned int ret = 0; 631 632 pm_runtime_get_sync(up->dev); 633 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 634 spin_lock_irqsave(&up->port.lock, flags); 635 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 636 spin_unlock_irqrestore(&up->port.lock, flags); 637 pm_runtime_mark_last_busy(up->dev); 638 pm_runtime_put_autosuspend(up->dev); 639 return ret; 640 } 641 642 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 643 { 644 struct uart_omap_port *up = to_uart_omap_port(port); 645 unsigned int status; 646 unsigned int ret = 0; 647 648 pm_runtime_get_sync(up->dev); 649 status = check_modem_status(up); 650 pm_runtime_mark_last_busy(up->dev); 651 pm_runtime_put_autosuspend(up->dev); 652 653 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 654 655 if (status & UART_MSR_DCD) 656 ret |= TIOCM_CAR; 657 if (status & UART_MSR_RI) 658 ret |= TIOCM_RNG; 659 if (status & UART_MSR_DSR) 660 ret |= TIOCM_DSR; 661 if (status & UART_MSR_CTS) 662 ret |= TIOCM_CTS; 663 return ret; 664 } 665 666 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 667 { 668 struct uart_omap_port *up = to_uart_omap_port(port); 669 unsigned char mcr = 0, old_mcr, lcr; 670 671 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 672 if (mctrl & TIOCM_RTS) 673 mcr |= UART_MCR_RTS; 674 if (mctrl & TIOCM_DTR) 675 mcr |= UART_MCR_DTR; 676 if (mctrl & TIOCM_OUT1) 677 mcr |= UART_MCR_OUT1; 678 if (mctrl & TIOCM_OUT2) 679 mcr |= UART_MCR_OUT2; 680 if (mctrl & TIOCM_LOOP) 681 mcr |= UART_MCR_LOOP; 682 683 pm_runtime_get_sync(up->dev); 684 old_mcr = serial_in(up, UART_MCR); 685 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 686 UART_MCR_DTR | UART_MCR_RTS); 687 up->mcr = old_mcr | mcr; 688 serial_out(up, UART_MCR, up->mcr); 689 690 /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */ 691 lcr = serial_in(up, UART_LCR); 692 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 693 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) 694 up->efr |= UART_EFR_RTS; 695 else 696 up->efr &= UART_EFR_RTS; 697 serial_out(up, UART_EFR, up->efr); 698 serial_out(up, UART_LCR, lcr); 699 700 pm_runtime_mark_last_busy(up->dev); 701 pm_runtime_put_autosuspend(up->dev); 702 } 703 704 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 705 { 706 struct uart_omap_port *up = to_uart_omap_port(port); 707 unsigned long flags = 0; 708 709 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 710 pm_runtime_get_sync(up->dev); 711 spin_lock_irqsave(&up->port.lock, flags); 712 if (break_state == -1) 713 up->lcr |= UART_LCR_SBC; 714 else 715 up->lcr &= ~UART_LCR_SBC; 716 serial_out(up, UART_LCR, up->lcr); 717 spin_unlock_irqrestore(&up->port.lock, flags); 718 pm_runtime_mark_last_busy(up->dev); 719 pm_runtime_put_autosuspend(up->dev); 720 } 721 722 static int serial_omap_startup(struct uart_port *port) 723 { 724 struct uart_omap_port *up = to_uart_omap_port(port); 725 unsigned long flags = 0; 726 int retval; 727 728 /* 729 * Allocate the IRQ 730 */ 731 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 732 up->name, up); 733 if (retval) 734 return retval; 735 736 /* Optional wake-up IRQ */ 737 if (up->wakeirq) { 738 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq); 739 if (retval) { 740 free_irq(up->port.irq, up); 741 return retval; 742 } 743 } 744 745 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 746 747 pm_runtime_get_sync(up->dev); 748 /* 749 * Clear the FIFO buffers and disable them. 750 * (they will be reenabled in set_termios()) 751 */ 752 serial_omap_clear_fifos(up); 753 754 /* 755 * Clear the interrupt registers. 756 */ 757 (void) serial_in(up, UART_LSR); 758 if (serial_in(up, UART_LSR) & UART_LSR_DR) 759 (void) serial_in(up, UART_RX); 760 (void) serial_in(up, UART_IIR); 761 (void) serial_in(up, UART_MSR); 762 763 /* 764 * Now, initialize the UART 765 */ 766 serial_out(up, UART_LCR, UART_LCR_WLEN8); 767 spin_lock_irqsave(&up->port.lock, flags); 768 /* 769 * Most PC uarts need OUT2 raised to enable interrupts. 770 */ 771 up->port.mctrl |= TIOCM_OUT2; 772 serial_omap_set_mctrl(&up->port, up->port.mctrl); 773 spin_unlock_irqrestore(&up->port.lock, flags); 774 775 up->msr_saved_flags = 0; 776 /* 777 * Finally, enable interrupts. Note: Modem status interrupts 778 * are set via set_termios(), which will be occurring imminently 779 * anyway, so we don't enable them here. 780 */ 781 up->ier = UART_IER_RLSI | UART_IER_RDI; 782 serial_out(up, UART_IER, up->ier); 783 784 /* Enable module level wake up */ 785 up->wer = OMAP_UART_WER_MOD_WKUP; 786 if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP) 787 up->wer |= OMAP_UART_TX_WAKEUP_EN; 788 789 serial_out(up, UART_OMAP_WER, up->wer); 790 791 pm_runtime_mark_last_busy(up->dev); 792 pm_runtime_put_autosuspend(up->dev); 793 up->port_activity = jiffies; 794 return 0; 795 } 796 797 static void serial_omap_shutdown(struct uart_port *port) 798 { 799 struct uart_omap_port *up = to_uart_omap_port(port); 800 unsigned long flags = 0; 801 802 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 803 804 pm_runtime_get_sync(up->dev); 805 /* 806 * Disable interrupts from this port 807 */ 808 up->ier = 0; 809 serial_out(up, UART_IER, 0); 810 811 spin_lock_irqsave(&up->port.lock, flags); 812 up->port.mctrl &= ~TIOCM_OUT2; 813 serial_omap_set_mctrl(&up->port, up->port.mctrl); 814 spin_unlock_irqrestore(&up->port.lock, flags); 815 816 /* 817 * Disable break condition and FIFOs 818 */ 819 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 820 serial_omap_clear_fifos(up); 821 822 /* 823 * Read data port to reset things, and then free the irq 824 */ 825 if (serial_in(up, UART_LSR) & UART_LSR_DR) 826 (void) serial_in(up, UART_RX); 827 828 pm_runtime_mark_last_busy(up->dev); 829 pm_runtime_put_autosuspend(up->dev); 830 free_irq(up->port.irq, up); 831 dev_pm_clear_wake_irq(up->dev); 832 } 833 834 static void serial_omap_uart_qos_work(struct work_struct *work) 835 { 836 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 837 qos_work); 838 839 pm_qos_update_request(&up->pm_qos_request, up->latency); 840 } 841 842 static void 843 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 844 struct ktermios *old) 845 { 846 struct uart_omap_port *up = to_uart_omap_port(port); 847 unsigned char cval = 0; 848 unsigned long flags = 0; 849 unsigned int baud, quot; 850 851 switch (termios->c_cflag & CSIZE) { 852 case CS5: 853 cval = UART_LCR_WLEN5; 854 break; 855 case CS6: 856 cval = UART_LCR_WLEN6; 857 break; 858 case CS7: 859 cval = UART_LCR_WLEN7; 860 break; 861 default: 862 case CS8: 863 cval = UART_LCR_WLEN8; 864 break; 865 } 866 867 if (termios->c_cflag & CSTOPB) 868 cval |= UART_LCR_STOP; 869 if (termios->c_cflag & PARENB) 870 cval |= UART_LCR_PARITY; 871 if (!(termios->c_cflag & PARODD)) 872 cval |= UART_LCR_EPAR; 873 if (termios->c_cflag & CMSPAR) 874 cval |= UART_LCR_SPAR; 875 876 /* 877 * Ask the core to calculate the divisor for us. 878 */ 879 880 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 881 quot = serial_omap_get_divisor(port, baud); 882 883 /* calculate wakeup latency constraint */ 884 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 885 up->latency = up->calc_latency; 886 schedule_work(&up->qos_work); 887 888 up->dll = quot & 0xff; 889 up->dlh = quot >> 8; 890 up->mdr1 = UART_OMAP_MDR1_DISABLE; 891 892 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 893 UART_FCR_ENABLE_FIFO; 894 895 /* 896 * Ok, we're now changing the port state. Do it with 897 * interrupts disabled. 898 */ 899 pm_runtime_get_sync(up->dev); 900 spin_lock_irqsave(&up->port.lock, flags); 901 902 /* 903 * Update the per-port timeout. 904 */ 905 uart_update_timeout(port, termios->c_cflag, baud); 906 907 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 908 if (termios->c_iflag & INPCK) 909 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 910 if (termios->c_iflag & (BRKINT | PARMRK)) 911 up->port.read_status_mask |= UART_LSR_BI; 912 913 /* 914 * Characters to ignore 915 */ 916 up->port.ignore_status_mask = 0; 917 if (termios->c_iflag & IGNPAR) 918 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 919 if (termios->c_iflag & IGNBRK) { 920 up->port.ignore_status_mask |= UART_LSR_BI; 921 /* 922 * If we're ignoring parity and break indicators, 923 * ignore overruns too (for real raw support). 924 */ 925 if (termios->c_iflag & IGNPAR) 926 up->port.ignore_status_mask |= UART_LSR_OE; 927 } 928 929 /* 930 * ignore all characters if CREAD is not set 931 */ 932 if ((termios->c_cflag & CREAD) == 0) 933 up->port.ignore_status_mask |= UART_LSR_DR; 934 935 /* 936 * Modem status interrupts 937 */ 938 up->ier &= ~UART_IER_MSI; 939 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 940 up->ier |= UART_IER_MSI; 941 serial_out(up, UART_IER, up->ier); 942 serial_out(up, UART_LCR, cval); /* reset DLAB */ 943 up->lcr = cval; 944 up->scr = 0; 945 946 /* FIFOs and DMA Settings */ 947 948 /* FCR can be changed only when the 949 * baud clock is not running 950 * DLL_REG and DLH_REG set to 0. 951 */ 952 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 953 serial_out(up, UART_DLL, 0); 954 serial_out(up, UART_DLM, 0); 955 serial_out(up, UART_LCR, 0); 956 957 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 958 959 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 960 up->efr &= ~UART_EFR_SCD; 961 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 962 963 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 964 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 965 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 966 /* FIFO ENABLE, DMA MODE */ 967 968 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 969 /* 970 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 971 * sets Enables the granularity of 1 for TRIGGER RX 972 * level. Along with setting RX FIFO trigger level 973 * to 1 (as noted below, 16 characters) and TLR[3:0] 974 * to zero this will result RX FIFO threshold level 975 * to 1 character, instead of 16 as noted in comment 976 * below. 977 */ 978 979 /* Set receive FIFO threshold to 16 characters and 980 * transmit FIFO threshold to 32 spaces 981 */ 982 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 983 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 984 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 985 UART_FCR_ENABLE_FIFO; 986 987 serial_out(up, UART_FCR, up->fcr); 988 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 989 990 serial_out(up, UART_OMAP_SCR, up->scr); 991 992 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 993 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 994 serial_out(up, UART_MCR, up->mcr); 995 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 996 serial_out(up, UART_EFR, up->efr); 997 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 998 999 /* Protocol, Baud Rate, and Interrupt Settings */ 1000 1001 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1002 serial_omap_mdr1_errataset(up, up->mdr1); 1003 else 1004 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1005 1006 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1007 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 1008 1009 serial_out(up, UART_LCR, 0); 1010 serial_out(up, UART_IER, 0); 1011 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1012 1013 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 1014 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 1015 1016 serial_out(up, UART_LCR, 0); 1017 serial_out(up, UART_IER, up->ier); 1018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1019 1020 serial_out(up, UART_EFR, up->efr); 1021 serial_out(up, UART_LCR, cval); 1022 1023 if (!serial_omap_baud_is_mode16(port, baud)) 1024 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 1025 else 1026 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 1027 1028 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1029 serial_omap_mdr1_errataset(up, up->mdr1); 1030 else 1031 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1032 1033 /* Configure flow control */ 1034 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1035 1036 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 1037 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 1038 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 1039 1040 /* Enable access to TCR/TLR */ 1041 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 1042 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1043 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 1044 1045 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 1046 1047 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 1048 1049 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 1050 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */ 1051 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 1052 up->efr |= UART_EFR_CTS; 1053 } else { 1054 /* Disable AUTORTS and AUTOCTS */ 1055 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 1056 } 1057 1058 if (up->port.flags & UPF_SOFT_FLOW) { 1059 /* clear SW control mode bits */ 1060 up->efr &= OMAP_UART_SW_CLR; 1061 1062 /* 1063 * IXON Flag: 1064 * Enable XON/XOFF flow control on input. 1065 * Receiver compares XON1, XOFF1. 1066 */ 1067 if (termios->c_iflag & IXON) 1068 up->efr |= OMAP_UART_SW_RX; 1069 1070 /* 1071 * IXOFF Flag: 1072 * Enable XON/XOFF flow control on output. 1073 * Transmit XON1, XOFF1 1074 */ 1075 if (termios->c_iflag & IXOFF) { 1076 up->port.status |= UPSTAT_AUTOXOFF; 1077 up->efr |= OMAP_UART_SW_TX; 1078 } 1079 1080 /* 1081 * IXANY Flag: 1082 * Enable any character to restart output. 1083 * Operation resumes after receiving any 1084 * character after recognition of the XOFF character 1085 */ 1086 if (termios->c_iflag & IXANY) 1087 up->mcr |= UART_MCR_XONANY; 1088 else 1089 up->mcr &= ~UART_MCR_XONANY; 1090 } 1091 serial_out(up, UART_MCR, up->mcr); 1092 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1093 serial_out(up, UART_EFR, up->efr); 1094 serial_out(up, UART_LCR, up->lcr); 1095 1096 serial_omap_set_mctrl(&up->port, up->port.mctrl); 1097 1098 spin_unlock_irqrestore(&up->port.lock, flags); 1099 pm_runtime_mark_last_busy(up->dev); 1100 pm_runtime_put_autosuspend(up->dev); 1101 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 1102 } 1103 1104 static void 1105 serial_omap_pm(struct uart_port *port, unsigned int state, 1106 unsigned int oldstate) 1107 { 1108 struct uart_omap_port *up = to_uart_omap_port(port); 1109 unsigned char efr; 1110 1111 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1112 1113 pm_runtime_get_sync(up->dev); 1114 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1115 efr = serial_in(up, UART_EFR); 1116 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1117 serial_out(up, UART_LCR, 0); 1118 1119 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1120 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1121 serial_out(up, UART_EFR, efr); 1122 serial_out(up, UART_LCR, 0); 1123 1124 pm_runtime_mark_last_busy(up->dev); 1125 pm_runtime_put_autosuspend(up->dev); 1126 } 1127 1128 static void serial_omap_release_port(struct uart_port *port) 1129 { 1130 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1131 } 1132 1133 static int serial_omap_request_port(struct uart_port *port) 1134 { 1135 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1136 return 0; 1137 } 1138 1139 static void serial_omap_config_port(struct uart_port *port, int flags) 1140 { 1141 struct uart_omap_port *up = to_uart_omap_port(port); 1142 1143 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1144 up->port.line); 1145 up->port.type = PORT_OMAP; 1146 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1147 } 1148 1149 static int 1150 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1151 { 1152 /* we don't want the core code to modify any port params */ 1153 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1154 return -EINVAL; 1155 } 1156 1157 static const char * 1158 serial_omap_type(struct uart_port *port) 1159 { 1160 struct uart_omap_port *up = to_uart_omap_port(port); 1161 1162 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1163 return up->name; 1164 } 1165 1166 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1167 1168 static inline void wait_for_xmitr(struct uart_omap_port *up) 1169 { 1170 unsigned int status, tmout = 10000; 1171 1172 /* Wait up to 10ms for the character(s) to be sent. */ 1173 do { 1174 status = serial_in(up, UART_LSR); 1175 1176 if (status & UART_LSR_BI) 1177 up->lsr_break_flag = UART_LSR_BI; 1178 1179 if (--tmout == 0) 1180 break; 1181 udelay(1); 1182 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1183 1184 /* Wait up to 1s for flow control if necessary */ 1185 if (up->port.flags & UPF_CONS_FLOW) { 1186 tmout = 1000000; 1187 for (tmout = 1000000; tmout; tmout--) { 1188 unsigned int msr = serial_in(up, UART_MSR); 1189 1190 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1191 if (msr & UART_MSR_CTS) 1192 break; 1193 1194 udelay(1); 1195 } 1196 } 1197 } 1198 1199 #ifdef CONFIG_CONSOLE_POLL 1200 1201 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1202 { 1203 struct uart_omap_port *up = to_uart_omap_port(port); 1204 1205 pm_runtime_get_sync(up->dev); 1206 wait_for_xmitr(up); 1207 serial_out(up, UART_TX, ch); 1208 pm_runtime_mark_last_busy(up->dev); 1209 pm_runtime_put_autosuspend(up->dev); 1210 } 1211 1212 static int serial_omap_poll_get_char(struct uart_port *port) 1213 { 1214 struct uart_omap_port *up = to_uart_omap_port(port); 1215 unsigned int status; 1216 1217 pm_runtime_get_sync(up->dev); 1218 status = serial_in(up, UART_LSR); 1219 if (!(status & UART_LSR_DR)) { 1220 status = NO_POLL_CHAR; 1221 goto out; 1222 } 1223 1224 status = serial_in(up, UART_RX); 1225 1226 out: 1227 pm_runtime_mark_last_busy(up->dev); 1228 pm_runtime_put_autosuspend(up->dev); 1229 1230 return status; 1231 } 1232 1233 #endif /* CONFIG_CONSOLE_POLL */ 1234 1235 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1236 1237 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1238 1239 static struct uart_driver serial_omap_reg; 1240 1241 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1242 { 1243 struct uart_omap_port *up = to_uart_omap_port(port); 1244 1245 wait_for_xmitr(up); 1246 serial_out(up, UART_TX, ch); 1247 } 1248 1249 static void 1250 serial_omap_console_write(struct console *co, const char *s, 1251 unsigned int count) 1252 { 1253 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1254 unsigned long flags; 1255 unsigned int ier; 1256 int locked = 1; 1257 1258 pm_runtime_get_sync(up->dev); 1259 1260 local_irq_save(flags); 1261 if (up->port.sysrq) 1262 locked = 0; 1263 else if (oops_in_progress) 1264 locked = spin_trylock(&up->port.lock); 1265 else 1266 spin_lock(&up->port.lock); 1267 1268 /* 1269 * First save the IER then disable the interrupts 1270 */ 1271 ier = serial_in(up, UART_IER); 1272 serial_out(up, UART_IER, 0); 1273 1274 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1275 1276 /* 1277 * Finally, wait for transmitter to become empty 1278 * and restore the IER 1279 */ 1280 wait_for_xmitr(up); 1281 serial_out(up, UART_IER, ier); 1282 /* 1283 * The receive handling will happen properly because the 1284 * receive ready bit will still be set; it is not cleared 1285 * on read. However, modem control will not, we must 1286 * call it if we have saved something in the saved flags 1287 * while processing with interrupts off. 1288 */ 1289 if (up->msr_saved_flags) 1290 check_modem_status(up); 1291 1292 pm_runtime_mark_last_busy(up->dev); 1293 pm_runtime_put_autosuspend(up->dev); 1294 if (locked) 1295 spin_unlock(&up->port.lock); 1296 local_irq_restore(flags); 1297 } 1298 1299 static int __init 1300 serial_omap_console_setup(struct console *co, char *options) 1301 { 1302 struct uart_omap_port *up; 1303 int baud = 115200; 1304 int bits = 8; 1305 int parity = 'n'; 1306 int flow = 'n'; 1307 1308 if (serial_omap_console_ports[co->index] == NULL) 1309 return -ENODEV; 1310 up = serial_omap_console_ports[co->index]; 1311 1312 if (options) 1313 uart_parse_options(options, &baud, &parity, &bits, &flow); 1314 1315 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1316 } 1317 1318 static struct console serial_omap_console = { 1319 .name = OMAP_SERIAL_NAME, 1320 .write = serial_omap_console_write, 1321 .device = uart_console_device, 1322 .setup = serial_omap_console_setup, 1323 .flags = CON_PRINTBUFFER, 1324 .index = -1, 1325 .data = &serial_omap_reg, 1326 }; 1327 1328 static void serial_omap_add_console_port(struct uart_omap_port *up) 1329 { 1330 serial_omap_console_ports[up->port.line] = up; 1331 } 1332 1333 #define OMAP_CONSOLE (&serial_omap_console) 1334 1335 #else 1336 1337 #define OMAP_CONSOLE NULL 1338 1339 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1340 {} 1341 1342 #endif 1343 1344 /* Enable or disable the rs485 support */ 1345 static int 1346 serial_omap_config_rs485(struct uart_port *port, struct serial_rs485 *rs485conf) 1347 { 1348 struct uart_omap_port *up = to_uart_omap_port(port); 1349 unsigned int mode; 1350 int val; 1351 1352 pm_runtime_get_sync(up->dev); 1353 1354 /* Disable interrupts from this port */ 1355 mode = up->ier; 1356 up->ier = 0; 1357 serial_out(up, UART_IER, 0); 1358 1359 /* store new config */ 1360 port->rs485 = *rs485conf; 1361 1362 /* 1363 * Just as a precaution, only allow rs485 1364 * to be enabled if the gpio pin is valid 1365 */ 1366 if (gpio_is_valid(up->rts_gpio)) { 1367 /* enable / disable rts */ 1368 val = (port->rs485.flags & SER_RS485_ENABLED) ? 1369 SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND; 1370 val = (port->rs485.flags & val) ? 1 : 0; 1371 gpio_set_value(up->rts_gpio, val); 1372 } else 1373 port->rs485.flags &= ~SER_RS485_ENABLED; 1374 1375 /* Enable interrupts */ 1376 up->ier = mode; 1377 serial_out(up, UART_IER, up->ier); 1378 1379 /* If RS-485 is disabled, make sure the THR interrupt is fired when 1380 * TX FIFO is below the trigger level. 1381 */ 1382 if (!(port->rs485.flags & SER_RS485_ENABLED) && 1383 (up->scr & OMAP_UART_SCR_TX_EMPTY)) { 1384 up->scr &= ~OMAP_UART_SCR_TX_EMPTY; 1385 serial_out(up, UART_OMAP_SCR, up->scr); 1386 } 1387 1388 pm_runtime_mark_last_busy(up->dev); 1389 pm_runtime_put_autosuspend(up->dev); 1390 1391 return 0; 1392 } 1393 1394 static struct uart_ops serial_omap_pops = { 1395 .tx_empty = serial_omap_tx_empty, 1396 .set_mctrl = serial_omap_set_mctrl, 1397 .get_mctrl = serial_omap_get_mctrl, 1398 .stop_tx = serial_omap_stop_tx, 1399 .start_tx = serial_omap_start_tx, 1400 .throttle = serial_omap_throttle, 1401 .unthrottle = serial_omap_unthrottle, 1402 .stop_rx = serial_omap_stop_rx, 1403 .enable_ms = serial_omap_enable_ms, 1404 .break_ctl = serial_omap_break_ctl, 1405 .startup = serial_omap_startup, 1406 .shutdown = serial_omap_shutdown, 1407 .set_termios = serial_omap_set_termios, 1408 .pm = serial_omap_pm, 1409 .type = serial_omap_type, 1410 .release_port = serial_omap_release_port, 1411 .request_port = serial_omap_request_port, 1412 .config_port = serial_omap_config_port, 1413 .verify_port = serial_omap_verify_port, 1414 #ifdef CONFIG_CONSOLE_POLL 1415 .poll_put_char = serial_omap_poll_put_char, 1416 .poll_get_char = serial_omap_poll_get_char, 1417 #endif 1418 }; 1419 1420 static struct uart_driver serial_omap_reg = { 1421 .owner = THIS_MODULE, 1422 .driver_name = "OMAP-SERIAL", 1423 .dev_name = OMAP_SERIAL_NAME, 1424 .nr = OMAP_MAX_HSUART_PORTS, 1425 .cons = OMAP_CONSOLE, 1426 }; 1427 1428 #ifdef CONFIG_PM_SLEEP 1429 static int serial_omap_prepare(struct device *dev) 1430 { 1431 struct uart_omap_port *up = dev_get_drvdata(dev); 1432 1433 up->is_suspending = true; 1434 1435 return 0; 1436 } 1437 1438 static void serial_omap_complete(struct device *dev) 1439 { 1440 struct uart_omap_port *up = dev_get_drvdata(dev); 1441 1442 up->is_suspending = false; 1443 } 1444 1445 static int serial_omap_suspend(struct device *dev) 1446 { 1447 struct uart_omap_port *up = dev_get_drvdata(dev); 1448 1449 uart_suspend_port(&serial_omap_reg, &up->port); 1450 flush_work(&up->qos_work); 1451 1452 if (device_may_wakeup(dev)) 1453 serial_omap_enable_wakeup(up, true); 1454 else 1455 serial_omap_enable_wakeup(up, false); 1456 1457 return 0; 1458 } 1459 1460 static int serial_omap_resume(struct device *dev) 1461 { 1462 struct uart_omap_port *up = dev_get_drvdata(dev); 1463 1464 if (device_may_wakeup(dev)) 1465 serial_omap_enable_wakeup(up, false); 1466 1467 uart_resume_port(&serial_omap_reg, &up->port); 1468 1469 return 0; 1470 } 1471 #else 1472 #define serial_omap_prepare NULL 1473 #define serial_omap_complete NULL 1474 #endif /* CONFIG_PM_SLEEP */ 1475 1476 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1477 { 1478 u32 mvr, scheme; 1479 u16 revision, major, minor; 1480 1481 mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift)); 1482 1483 /* Check revision register scheme */ 1484 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1485 1486 switch (scheme) { 1487 case 0: /* Legacy Scheme: OMAP2/3 */ 1488 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1489 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1490 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1491 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1492 break; 1493 case 1: 1494 /* New Scheme: OMAP4+ */ 1495 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1496 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1497 OMAP_UART_MVR_MAJ_SHIFT; 1498 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1499 break; 1500 default: 1501 dev_warn(up->dev, 1502 "Unknown %s revision, defaulting to highest\n", 1503 up->name); 1504 /* highest possible revision */ 1505 major = 0xff; 1506 minor = 0xff; 1507 } 1508 1509 /* normalize revision for the driver */ 1510 revision = UART_BUILD_REVISION(major, minor); 1511 1512 switch (revision) { 1513 case OMAP_UART_REV_46: 1514 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1515 UART_ERRATA_i291_DMA_FORCEIDLE); 1516 break; 1517 case OMAP_UART_REV_52: 1518 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1519 UART_ERRATA_i291_DMA_FORCEIDLE); 1520 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1521 break; 1522 case OMAP_UART_REV_63: 1523 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1524 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP; 1525 break; 1526 default: 1527 break; 1528 } 1529 } 1530 1531 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1532 { 1533 struct omap_uart_port_info *omap_up_info; 1534 1535 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1536 if (!omap_up_info) 1537 return NULL; /* out of memory */ 1538 1539 of_property_read_u32(dev->of_node, "clock-frequency", 1540 &omap_up_info->uartclk); 1541 return omap_up_info; 1542 } 1543 1544 static int serial_omap_probe_rs485(struct uart_omap_port *up, 1545 struct device_node *np) 1546 { 1547 struct serial_rs485 *rs485conf = &up->port.rs485; 1548 u32 rs485_delay[2]; 1549 enum of_gpio_flags flags; 1550 int ret; 1551 1552 rs485conf->flags = 0; 1553 up->rts_gpio = -EINVAL; 1554 1555 if (!np) 1556 return 0; 1557 1558 if (of_property_read_bool(np, "rs485-rts-active-high")) 1559 rs485conf->flags |= SER_RS485_RTS_ON_SEND; 1560 else 1561 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; 1562 1563 /* check for tx enable gpio */ 1564 up->rts_gpio = of_get_named_gpio_flags(np, "rts-gpio", 0, &flags); 1565 if (gpio_is_valid(up->rts_gpio)) { 1566 ret = devm_gpio_request(up->dev, up->rts_gpio, "omap-serial"); 1567 if (ret < 0) 1568 return ret; 1569 ret = gpio_direction_output(up->rts_gpio, 1570 flags & SER_RS485_RTS_AFTER_SEND); 1571 if (ret < 0) 1572 return ret; 1573 } else if (up->rts_gpio == -EPROBE_DEFER) { 1574 return -EPROBE_DEFER; 1575 } else { 1576 up->rts_gpio = -EINVAL; 1577 } 1578 1579 if (of_property_read_u32_array(np, "rs485-rts-delay", 1580 rs485_delay, 2) == 0) { 1581 rs485conf->delay_rts_before_send = rs485_delay[0]; 1582 rs485conf->delay_rts_after_send = rs485_delay[1]; 1583 } 1584 1585 if (of_property_read_bool(np, "rs485-rx-during-tx")) 1586 rs485conf->flags |= SER_RS485_RX_DURING_TX; 1587 1588 if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) 1589 rs485conf->flags |= SER_RS485_ENABLED; 1590 1591 return 0; 1592 } 1593 1594 static int serial_omap_probe(struct platform_device *pdev) 1595 { 1596 struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev); 1597 struct uart_omap_port *up; 1598 struct resource *mem; 1599 void __iomem *base; 1600 int uartirq = 0; 1601 int wakeirq = 0; 1602 int ret; 1603 1604 /* The optional wakeirq may be specified in the board dts file */ 1605 if (pdev->dev.of_node) { 1606 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1607 if (!uartirq) 1608 return -EPROBE_DEFER; 1609 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1); 1610 omap_up_info = of_get_uart_port_info(&pdev->dev); 1611 pdev->dev.platform_data = omap_up_info; 1612 } else { 1613 uartirq = platform_get_irq(pdev, 0); 1614 if (uartirq < 0) 1615 return -EPROBE_DEFER; 1616 } 1617 1618 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1619 if (!up) 1620 return -ENOMEM; 1621 1622 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1623 base = devm_ioremap_resource(&pdev->dev, mem); 1624 if (IS_ERR(base)) 1625 return PTR_ERR(base); 1626 1627 up->dev = &pdev->dev; 1628 up->port.dev = &pdev->dev; 1629 up->port.type = PORT_OMAP; 1630 up->port.iotype = UPIO_MEM; 1631 up->port.irq = uartirq; 1632 up->port.regshift = 2; 1633 up->port.fifosize = 64; 1634 up->port.ops = &serial_omap_pops; 1635 1636 if (pdev->dev.of_node) 1637 ret = of_alias_get_id(pdev->dev.of_node, "serial"); 1638 else 1639 ret = pdev->id; 1640 1641 if (ret < 0) { 1642 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1643 ret); 1644 goto err_port_line; 1645 } 1646 up->port.line = ret; 1647 1648 if (up->port.line >= OMAP_MAX_HSUART_PORTS) { 1649 dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line, 1650 OMAP_MAX_HSUART_PORTS); 1651 ret = -ENXIO; 1652 goto err_port_line; 1653 } 1654 1655 up->wakeirq = wakeirq; 1656 if (!up->wakeirq) 1657 dev_info(up->port.dev, "no wakeirq for uart%d\n", 1658 up->port.line); 1659 1660 ret = serial_omap_probe_rs485(up, pdev->dev.of_node); 1661 if (ret < 0) 1662 goto err_rs485; 1663 1664 sprintf(up->name, "OMAP UART%d", up->port.line); 1665 up->port.mapbase = mem->start; 1666 up->port.membase = base; 1667 up->port.flags = omap_up_info->flags; 1668 up->port.uartclk = omap_up_info->uartclk; 1669 up->port.rs485_config = serial_omap_config_rs485; 1670 if (!up->port.uartclk) { 1671 up->port.uartclk = DEFAULT_CLK_SPEED; 1672 dev_warn(&pdev->dev, 1673 "No clock speed specified: using default: %d\n", 1674 DEFAULT_CLK_SPEED); 1675 } 1676 1677 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1678 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1679 pm_qos_add_request(&up->pm_qos_request, 1680 PM_QOS_CPU_DMA_LATENCY, up->latency); 1681 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1682 1683 platform_set_drvdata(pdev, up); 1684 if (omap_up_info->autosuspend_timeout == 0) 1685 omap_up_info->autosuspend_timeout = -1; 1686 1687 device_init_wakeup(up->dev, true); 1688 pm_runtime_use_autosuspend(&pdev->dev); 1689 pm_runtime_set_autosuspend_delay(&pdev->dev, 1690 omap_up_info->autosuspend_timeout); 1691 1692 pm_runtime_irq_safe(&pdev->dev); 1693 pm_runtime_enable(&pdev->dev); 1694 1695 pm_runtime_get_sync(&pdev->dev); 1696 1697 omap_serial_fill_features_erratas(up); 1698 1699 ui[up->port.line] = up; 1700 serial_omap_add_console_port(up); 1701 1702 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1703 if (ret != 0) 1704 goto err_add_port; 1705 1706 pm_runtime_mark_last_busy(up->dev); 1707 pm_runtime_put_autosuspend(up->dev); 1708 return 0; 1709 1710 err_add_port: 1711 pm_runtime_put(&pdev->dev); 1712 pm_runtime_disable(&pdev->dev); 1713 pm_qos_remove_request(&up->pm_qos_request); 1714 device_init_wakeup(up->dev, false); 1715 err_rs485: 1716 err_port_line: 1717 return ret; 1718 } 1719 1720 static int serial_omap_remove(struct platform_device *dev) 1721 { 1722 struct uart_omap_port *up = platform_get_drvdata(dev); 1723 1724 pm_runtime_put_sync(up->dev); 1725 pm_runtime_disable(up->dev); 1726 uart_remove_one_port(&serial_omap_reg, &up->port); 1727 pm_qos_remove_request(&up->pm_qos_request); 1728 device_init_wakeup(&dev->dev, false); 1729 1730 return 0; 1731 } 1732 1733 /* 1734 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1735 * The access to uart register after MDR1 Access 1736 * causes UART to corrupt data. 1737 * 1738 * Need a delay = 1739 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1740 * give 10 times as much 1741 */ 1742 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1743 { 1744 u8 timeout = 255; 1745 1746 serial_out(up, UART_OMAP_MDR1, mdr1); 1747 udelay(2); 1748 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1749 UART_FCR_CLEAR_RCVR); 1750 /* 1751 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1752 * TX_FIFO_E bit is 1. 1753 */ 1754 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1755 (UART_LSR_THRE | UART_LSR_DR))) { 1756 timeout--; 1757 if (!timeout) { 1758 /* Should *never* happen. we warn and carry on */ 1759 dev_crit(up->dev, "Errata i202: timedout %x\n", 1760 serial_in(up, UART_LSR)); 1761 break; 1762 } 1763 udelay(1); 1764 } 1765 } 1766 1767 #ifdef CONFIG_PM 1768 static void serial_omap_restore_context(struct uart_omap_port *up) 1769 { 1770 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1771 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1772 else 1773 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1774 1775 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1776 serial_out(up, UART_EFR, UART_EFR_ECB); 1777 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1778 serial_out(up, UART_IER, 0x0); 1779 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1780 serial_out(up, UART_DLL, up->dll); 1781 serial_out(up, UART_DLM, up->dlh); 1782 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1783 serial_out(up, UART_IER, up->ier); 1784 serial_out(up, UART_FCR, up->fcr); 1785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1786 serial_out(up, UART_MCR, up->mcr); 1787 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1788 serial_out(up, UART_OMAP_SCR, up->scr); 1789 serial_out(up, UART_EFR, up->efr); 1790 serial_out(up, UART_LCR, up->lcr); 1791 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1792 serial_omap_mdr1_errataset(up, up->mdr1); 1793 else 1794 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1795 serial_out(up, UART_OMAP_WER, up->wer); 1796 } 1797 1798 static int serial_omap_runtime_suspend(struct device *dev) 1799 { 1800 struct uart_omap_port *up = dev_get_drvdata(dev); 1801 1802 if (!up) 1803 return -EINVAL; 1804 1805 /* 1806 * When using 'no_console_suspend', the console UART must not be 1807 * suspended. Since driver suspend is managed by runtime suspend, 1808 * preventing runtime suspend (by returning error) will keep device 1809 * active during suspend. 1810 */ 1811 if (up->is_suspending && !console_suspend_enabled && 1812 uart_console(&up->port)) 1813 return -EBUSY; 1814 1815 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1816 1817 serial_omap_enable_wakeup(up, true); 1818 1819 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1820 schedule_work(&up->qos_work); 1821 1822 return 0; 1823 } 1824 1825 static int serial_omap_runtime_resume(struct device *dev) 1826 { 1827 struct uart_omap_port *up = dev_get_drvdata(dev); 1828 1829 int loss_cnt = serial_omap_get_context_loss_count(up); 1830 1831 serial_omap_enable_wakeup(up, false); 1832 1833 if (loss_cnt < 0) { 1834 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", 1835 loss_cnt); 1836 serial_omap_restore_context(up); 1837 } else if (up->context_loss_cnt != loss_cnt) { 1838 serial_omap_restore_context(up); 1839 } 1840 up->latency = up->calc_latency; 1841 schedule_work(&up->qos_work); 1842 1843 return 0; 1844 } 1845 #endif 1846 1847 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1848 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1849 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1850 serial_omap_runtime_resume, NULL) 1851 .prepare = serial_omap_prepare, 1852 .complete = serial_omap_complete, 1853 }; 1854 1855 #if defined(CONFIG_OF) 1856 static const struct of_device_id omap_serial_of_match[] = { 1857 { .compatible = "ti,omap2-uart" }, 1858 { .compatible = "ti,omap3-uart" }, 1859 { .compatible = "ti,omap4-uart" }, 1860 {}, 1861 }; 1862 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1863 #endif 1864 1865 static struct platform_driver serial_omap_driver = { 1866 .probe = serial_omap_probe, 1867 .remove = serial_omap_remove, 1868 .driver = { 1869 .name = DRIVER_NAME, 1870 .pm = &serial_omap_dev_pm_ops, 1871 .of_match_table = of_match_ptr(omap_serial_of_match), 1872 }, 1873 }; 1874 1875 static int __init serial_omap_init(void) 1876 { 1877 int ret; 1878 1879 ret = uart_register_driver(&serial_omap_reg); 1880 if (ret != 0) 1881 return ret; 1882 ret = platform_driver_register(&serial_omap_driver); 1883 if (ret != 0) 1884 uart_unregister_driver(&serial_omap_reg); 1885 return ret; 1886 } 1887 1888 static void __exit serial_omap_exit(void) 1889 { 1890 platform_driver_unregister(&serial_omap_driver); 1891 uart_unregister_driver(&serial_omap_reg); 1892 } 1893 1894 module_init(serial_omap_init); 1895 module_exit(serial_omap_exit); 1896 1897 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1898 MODULE_LICENSE("GPL"); 1899 MODULE_AUTHOR("Texas Instruments Inc"); 1900