1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/io.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 43 #include <plat/dma.h> 44 #include <plat/dmtimer.h> 45 #include <plat/omap-serial.h> 46 47 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ 48 49 /* SCR register bitmasks */ 50 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 51 52 /* FCR register bitmasks */ 53 #define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6 54 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 55 56 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 57 58 /* Forward declaration of functions */ 59 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data); 60 static void serial_omap_rxdma_poll(unsigned long uart_no); 61 static int serial_omap_start_rxdma(struct uart_omap_port *up); 62 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 63 64 static struct workqueue_struct *serial_omap_uart_wq; 65 66 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 67 { 68 offset <<= up->port.regshift; 69 return readw(up->port.membase + offset); 70 } 71 72 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 73 { 74 offset <<= up->port.regshift; 75 writew(value, up->port.membase + offset); 76 } 77 78 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 79 { 80 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 81 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 82 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 83 serial_out(up, UART_FCR, 0); 84 } 85 86 /* 87 * serial_omap_get_divisor - calculate divisor value 88 * @port: uart port info 89 * @baud: baudrate for which divisor needs to be calculated. 90 * 91 * We have written our own function to get the divisor so as to support 92 * 13x mode. 3Mbps Baudrate as an different divisor. 93 * Reference OMAP TRM Chapter 17: 94 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates 95 * referring to oversampling - divisor value 96 * baudrate 460,800 to 3,686,400 all have divisor 13 97 * except 3,000,000 which has divisor value 16 98 */ 99 static unsigned int 100 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 101 { 102 unsigned int divisor; 103 104 if (baud > OMAP_MODE13X_SPEED && baud != 3000000) 105 divisor = 13; 106 else 107 divisor = 16; 108 return port->uartclk/(baud * divisor); 109 } 110 111 static void serial_omap_stop_rxdma(struct uart_omap_port *up) 112 { 113 if (up->uart_dma.rx_dma_used) { 114 del_timer(&up->uart_dma.rx_timer); 115 omap_stop_dma(up->uart_dma.rx_dma_channel); 116 omap_free_dma(up->uart_dma.rx_dma_channel); 117 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 118 up->uart_dma.rx_dma_used = false; 119 pm_runtime_mark_last_busy(&up->pdev->dev); 120 pm_runtime_put_autosuspend(&up->pdev->dev); 121 } 122 } 123 124 static void serial_omap_enable_ms(struct uart_port *port) 125 { 126 struct uart_omap_port *up = (struct uart_omap_port *)port; 127 128 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 129 130 pm_runtime_get_sync(&up->pdev->dev); 131 up->ier |= UART_IER_MSI; 132 serial_out(up, UART_IER, up->ier); 133 pm_runtime_put(&up->pdev->dev); 134 } 135 136 static void serial_omap_stop_tx(struct uart_port *port) 137 { 138 struct uart_omap_port *up = (struct uart_omap_port *)port; 139 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data; 140 141 if (up->use_dma && 142 up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { 143 /* 144 * Check if dma is still active. If yes do nothing, 145 * return. Else stop dma 146 */ 147 if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) 148 return; 149 omap_stop_dma(up->uart_dma.tx_dma_channel); 150 omap_free_dma(up->uart_dma.tx_dma_channel); 151 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 152 pm_runtime_mark_last_busy(&up->pdev->dev); 153 pm_runtime_put_autosuspend(&up->pdev->dev); 154 } 155 156 pm_runtime_get_sync(&up->pdev->dev); 157 if (up->ier & UART_IER_THRI) { 158 up->ier &= ~UART_IER_THRI; 159 serial_out(up, UART_IER, up->ier); 160 } 161 162 if (!up->use_dma && pdata && pdata->set_forceidle) 163 pdata->set_forceidle(up->pdev); 164 165 pm_runtime_mark_last_busy(&up->pdev->dev); 166 pm_runtime_put_autosuspend(&up->pdev->dev); 167 } 168 169 static void serial_omap_stop_rx(struct uart_port *port) 170 { 171 struct uart_omap_port *up = (struct uart_omap_port *)port; 172 173 pm_runtime_get_sync(&up->pdev->dev); 174 if (up->use_dma) 175 serial_omap_stop_rxdma(up); 176 up->ier &= ~UART_IER_RLSI; 177 up->port.read_status_mask &= ~UART_LSR_DR; 178 serial_out(up, UART_IER, up->ier); 179 pm_runtime_mark_last_busy(&up->pdev->dev); 180 pm_runtime_put_autosuspend(&up->pdev->dev); 181 } 182 183 static inline void receive_chars(struct uart_omap_port *up, 184 unsigned int *status) 185 { 186 struct tty_struct *tty = up->port.state->port.tty; 187 unsigned int flag, lsr = *status; 188 unsigned char ch = 0; 189 int max_count = 256; 190 191 do { 192 if (likely(lsr & UART_LSR_DR)) 193 ch = serial_in(up, UART_RX); 194 flag = TTY_NORMAL; 195 up->port.icount.rx++; 196 197 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 198 /* 199 * For statistics only 200 */ 201 if (lsr & UART_LSR_BI) { 202 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 203 up->port.icount.brk++; 204 /* 205 * We do the SysRQ and SAK checking 206 * here because otherwise the break 207 * may get masked by ignore_status_mask 208 * or read_status_mask. 209 */ 210 if (uart_handle_break(&up->port)) 211 goto ignore_char; 212 } else if (lsr & UART_LSR_PE) { 213 up->port.icount.parity++; 214 } else if (lsr & UART_LSR_FE) { 215 up->port.icount.frame++; 216 } 217 218 if (lsr & UART_LSR_OE) 219 up->port.icount.overrun++; 220 221 /* 222 * Mask off conditions which should be ignored. 223 */ 224 lsr &= up->port.read_status_mask; 225 226 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 227 if (up->port.line == up->port.cons->index) { 228 /* Recover the break flag from console xmit */ 229 lsr |= up->lsr_break_flag; 230 } 231 #endif 232 if (lsr & UART_LSR_BI) 233 flag = TTY_BREAK; 234 else if (lsr & UART_LSR_PE) 235 flag = TTY_PARITY; 236 else if (lsr & UART_LSR_FE) 237 flag = TTY_FRAME; 238 } 239 240 if (uart_handle_sysrq_char(&up->port, ch)) 241 goto ignore_char; 242 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 243 ignore_char: 244 lsr = serial_in(up, UART_LSR); 245 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0)); 246 spin_unlock(&up->port.lock); 247 tty_flip_buffer_push(tty); 248 spin_lock(&up->port.lock); 249 } 250 251 static void transmit_chars(struct uart_omap_port *up) 252 { 253 struct circ_buf *xmit = &up->port.state->xmit; 254 int count; 255 256 if (up->port.x_char) { 257 serial_out(up, UART_TX, up->port.x_char); 258 up->port.icount.tx++; 259 up->port.x_char = 0; 260 return; 261 } 262 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 263 serial_omap_stop_tx(&up->port); 264 return; 265 } 266 count = up->port.fifosize / 4; 267 do { 268 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 269 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 270 up->port.icount.tx++; 271 if (uart_circ_empty(xmit)) 272 break; 273 } while (--count > 0); 274 275 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 276 uart_write_wakeup(&up->port); 277 278 if (uart_circ_empty(xmit)) 279 serial_omap_stop_tx(&up->port); 280 } 281 282 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 283 { 284 if (!(up->ier & UART_IER_THRI)) { 285 up->ier |= UART_IER_THRI; 286 serial_out(up, UART_IER, up->ier); 287 } 288 } 289 290 static void serial_omap_start_tx(struct uart_port *port) 291 { 292 struct uart_omap_port *up = (struct uart_omap_port *)port; 293 struct omap_uart_port_info *pdata = up->pdev->dev.platform_data; 294 struct circ_buf *xmit; 295 unsigned int start; 296 int ret = 0; 297 298 if (!up->use_dma) { 299 pm_runtime_get_sync(&up->pdev->dev); 300 serial_omap_enable_ier_thri(up); 301 if (pdata && pdata->set_noidle) 302 pdata->set_noidle(up->pdev); 303 pm_runtime_mark_last_busy(&up->pdev->dev); 304 pm_runtime_put_autosuspend(&up->pdev->dev); 305 return; 306 } 307 308 if (up->uart_dma.tx_dma_used) 309 return; 310 311 xmit = &up->port.state->xmit; 312 313 if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) { 314 pm_runtime_get_sync(&up->pdev->dev); 315 ret = omap_request_dma(up->uart_dma.uart_dma_tx, 316 "UART Tx DMA", 317 (void *)uart_tx_dma_callback, up, 318 &(up->uart_dma.tx_dma_channel)); 319 320 if (ret < 0) { 321 serial_omap_enable_ier_thri(up); 322 return; 323 } 324 } 325 spin_lock(&(up->uart_dma.tx_lock)); 326 up->uart_dma.tx_dma_used = true; 327 spin_unlock(&(up->uart_dma.tx_lock)); 328 329 start = up->uart_dma.tx_buf_dma_phys + 330 (xmit->tail & (UART_XMIT_SIZE - 1)); 331 332 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); 333 /* 334 * It is a circular buffer. See if the buffer has wounded back. 335 * If yes it will have to be transferred in two separate dma 336 * transfers 337 */ 338 if (start + up->uart_dma.tx_buf_size >= 339 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) 340 up->uart_dma.tx_buf_size = 341 (up->uart_dma.tx_buf_dma_phys + 342 UART_XMIT_SIZE) - start; 343 344 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, 345 OMAP_DMA_AMODE_CONSTANT, 346 up->uart_dma.uart_base, 0, 0); 347 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, 348 OMAP_DMA_AMODE_POST_INC, start, 0, 0); 349 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, 350 OMAP_DMA_DATA_TYPE_S8, 351 up->uart_dma.tx_buf_size, 1, 352 OMAP_DMA_SYNC_ELEMENT, 353 up->uart_dma.uart_dma_tx, 0); 354 /* FIXME: Cache maintenance needed here? */ 355 omap_start_dma(up->uart_dma.tx_dma_channel); 356 } 357 358 static unsigned int check_modem_status(struct uart_omap_port *up) 359 { 360 unsigned int status; 361 362 status = serial_in(up, UART_MSR); 363 status |= up->msr_saved_flags; 364 up->msr_saved_flags = 0; 365 if ((status & UART_MSR_ANY_DELTA) == 0) 366 return status; 367 368 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 369 up->port.state != NULL) { 370 if (status & UART_MSR_TERI) 371 up->port.icount.rng++; 372 if (status & UART_MSR_DDSR) 373 up->port.icount.dsr++; 374 if (status & UART_MSR_DDCD) 375 uart_handle_dcd_change 376 (&up->port, status & UART_MSR_DCD); 377 if (status & UART_MSR_DCTS) 378 uart_handle_cts_change 379 (&up->port, status & UART_MSR_CTS); 380 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 381 } 382 383 return status; 384 } 385 386 /** 387 * serial_omap_irq() - This handles the interrupt from one port 388 * @irq: uart port irq number 389 * @dev_id: uart port info 390 */ 391 static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) 392 { 393 struct uart_omap_port *up = dev_id; 394 unsigned int iir, lsr; 395 unsigned long flags; 396 397 pm_runtime_get_sync(&up->pdev->dev); 398 iir = serial_in(up, UART_IIR); 399 if (iir & UART_IIR_NO_INT) { 400 pm_runtime_mark_last_busy(&up->pdev->dev); 401 pm_runtime_put_autosuspend(&up->pdev->dev); 402 return IRQ_NONE; 403 } 404 405 spin_lock_irqsave(&up->port.lock, flags); 406 lsr = serial_in(up, UART_LSR); 407 if (iir & UART_IIR_RLSI) { 408 if (!up->use_dma) { 409 if (lsr & UART_LSR_DR) 410 receive_chars(up, &lsr); 411 } else { 412 up->ier &= ~(UART_IER_RDI | UART_IER_RLSI); 413 serial_out(up, UART_IER, up->ier); 414 if ((serial_omap_start_rxdma(up) != 0) && 415 (lsr & UART_LSR_DR)) 416 receive_chars(up, &lsr); 417 } 418 } 419 420 check_modem_status(up); 421 if ((lsr & UART_LSR_THRE) && (iir & UART_IIR_THRI)) 422 transmit_chars(up); 423 424 spin_unlock_irqrestore(&up->port.lock, flags); 425 pm_runtime_mark_last_busy(&up->pdev->dev); 426 pm_runtime_put_autosuspend(&up->pdev->dev); 427 428 up->port_activity = jiffies; 429 return IRQ_HANDLED; 430 } 431 432 static unsigned int serial_omap_tx_empty(struct uart_port *port) 433 { 434 struct uart_omap_port *up = (struct uart_omap_port *)port; 435 unsigned long flags = 0; 436 unsigned int ret = 0; 437 438 pm_runtime_get_sync(&up->pdev->dev); 439 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 440 spin_lock_irqsave(&up->port.lock, flags); 441 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 442 spin_unlock_irqrestore(&up->port.lock, flags); 443 pm_runtime_put(&up->pdev->dev); 444 return ret; 445 } 446 447 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 448 { 449 struct uart_omap_port *up = (struct uart_omap_port *)port; 450 unsigned int status; 451 unsigned int ret = 0; 452 453 pm_runtime_get_sync(&up->pdev->dev); 454 status = check_modem_status(up); 455 pm_runtime_put(&up->pdev->dev); 456 457 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 458 459 if (status & UART_MSR_DCD) 460 ret |= TIOCM_CAR; 461 if (status & UART_MSR_RI) 462 ret |= TIOCM_RNG; 463 if (status & UART_MSR_DSR) 464 ret |= TIOCM_DSR; 465 if (status & UART_MSR_CTS) 466 ret |= TIOCM_CTS; 467 return ret; 468 } 469 470 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 471 { 472 struct uart_omap_port *up = (struct uart_omap_port *)port; 473 unsigned char mcr = 0; 474 475 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 476 if (mctrl & TIOCM_RTS) 477 mcr |= UART_MCR_RTS; 478 if (mctrl & TIOCM_DTR) 479 mcr |= UART_MCR_DTR; 480 if (mctrl & TIOCM_OUT1) 481 mcr |= UART_MCR_OUT1; 482 if (mctrl & TIOCM_OUT2) 483 mcr |= UART_MCR_OUT2; 484 if (mctrl & TIOCM_LOOP) 485 mcr |= UART_MCR_LOOP; 486 487 pm_runtime_get_sync(&up->pdev->dev); 488 up->mcr = serial_in(up, UART_MCR); 489 up->mcr |= mcr; 490 serial_out(up, UART_MCR, up->mcr); 491 pm_runtime_put(&up->pdev->dev); 492 } 493 494 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 495 { 496 struct uart_omap_port *up = (struct uart_omap_port *)port; 497 unsigned long flags = 0; 498 499 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 500 pm_runtime_get_sync(&up->pdev->dev); 501 spin_lock_irqsave(&up->port.lock, flags); 502 if (break_state == -1) 503 up->lcr |= UART_LCR_SBC; 504 else 505 up->lcr &= ~UART_LCR_SBC; 506 serial_out(up, UART_LCR, up->lcr); 507 spin_unlock_irqrestore(&up->port.lock, flags); 508 pm_runtime_put(&up->pdev->dev); 509 } 510 511 static int serial_omap_startup(struct uart_port *port) 512 { 513 struct uart_omap_port *up = (struct uart_omap_port *)port; 514 unsigned long flags = 0; 515 int retval; 516 517 /* 518 * Allocate the IRQ 519 */ 520 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 521 up->name, up); 522 if (retval) 523 return retval; 524 525 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 526 527 pm_runtime_get_sync(&up->pdev->dev); 528 /* 529 * Clear the FIFO buffers and disable them. 530 * (they will be reenabled in set_termios()) 531 */ 532 serial_omap_clear_fifos(up); 533 /* For Hardware flow control */ 534 serial_out(up, UART_MCR, UART_MCR_RTS); 535 536 /* 537 * Clear the interrupt registers. 538 */ 539 (void) serial_in(up, UART_LSR); 540 if (serial_in(up, UART_LSR) & UART_LSR_DR) 541 (void) serial_in(up, UART_RX); 542 (void) serial_in(up, UART_IIR); 543 (void) serial_in(up, UART_MSR); 544 545 /* 546 * Now, initialize the UART 547 */ 548 serial_out(up, UART_LCR, UART_LCR_WLEN8); 549 spin_lock_irqsave(&up->port.lock, flags); 550 /* 551 * Most PC uarts need OUT2 raised to enable interrupts. 552 */ 553 up->port.mctrl |= TIOCM_OUT2; 554 serial_omap_set_mctrl(&up->port, up->port.mctrl); 555 spin_unlock_irqrestore(&up->port.lock, flags); 556 557 up->msr_saved_flags = 0; 558 if (up->use_dma) { 559 free_page((unsigned long)up->port.state->xmit.buf); 560 up->port.state->xmit.buf = dma_alloc_coherent(NULL, 561 UART_XMIT_SIZE, 562 (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), 563 0); 564 init_timer(&(up->uart_dma.rx_timer)); 565 up->uart_dma.rx_timer.function = serial_omap_rxdma_poll; 566 up->uart_dma.rx_timer.data = up->port.line; 567 /* Currently the buffer size is 4KB. Can increase it */ 568 up->uart_dma.rx_buf = dma_alloc_coherent(NULL, 569 up->uart_dma.rx_buf_size, 570 (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); 571 } 572 /* 573 * Finally, enable interrupts. Note: Modem status interrupts 574 * are set via set_termios(), which will be occurring imminently 575 * anyway, so we don't enable them here. 576 */ 577 up->ier = UART_IER_RLSI | UART_IER_RDI; 578 serial_out(up, UART_IER, up->ier); 579 580 /* Enable module level wake up */ 581 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 582 583 pm_runtime_mark_last_busy(&up->pdev->dev); 584 pm_runtime_put_autosuspend(&up->pdev->dev); 585 up->port_activity = jiffies; 586 return 0; 587 } 588 589 static void serial_omap_shutdown(struct uart_port *port) 590 { 591 struct uart_omap_port *up = (struct uart_omap_port *)port; 592 unsigned long flags = 0; 593 594 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 595 596 pm_runtime_get_sync(&up->pdev->dev); 597 /* 598 * Disable interrupts from this port 599 */ 600 up->ier = 0; 601 serial_out(up, UART_IER, 0); 602 603 spin_lock_irqsave(&up->port.lock, flags); 604 up->port.mctrl &= ~TIOCM_OUT2; 605 serial_omap_set_mctrl(&up->port, up->port.mctrl); 606 spin_unlock_irqrestore(&up->port.lock, flags); 607 608 /* 609 * Disable break condition and FIFOs 610 */ 611 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 612 serial_omap_clear_fifos(up); 613 614 /* 615 * Read data port to reset things, and then free the irq 616 */ 617 if (serial_in(up, UART_LSR) & UART_LSR_DR) 618 (void) serial_in(up, UART_RX); 619 if (up->use_dma) { 620 dma_free_coherent(up->port.dev, 621 UART_XMIT_SIZE, up->port.state->xmit.buf, 622 up->uart_dma.tx_buf_dma_phys); 623 up->port.state->xmit.buf = NULL; 624 serial_omap_stop_rx(port); 625 dma_free_coherent(up->port.dev, 626 up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, 627 up->uart_dma.rx_buf_dma_phys); 628 up->uart_dma.rx_buf = NULL; 629 } 630 631 pm_runtime_put(&up->pdev->dev); 632 free_irq(up->port.irq, up); 633 } 634 635 static inline void 636 serial_omap_configure_xonxoff 637 (struct uart_omap_port *up, struct ktermios *termios) 638 { 639 up->lcr = serial_in(up, UART_LCR); 640 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 641 up->efr = serial_in(up, UART_EFR); 642 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); 643 644 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 645 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 646 647 /* clear SW control mode bits */ 648 up->efr &= OMAP_UART_SW_CLR; 649 650 /* 651 * IXON Flag: 652 * Enable XON/XOFF flow control on output. 653 * Transmit XON1, XOFF1 654 */ 655 if (termios->c_iflag & IXON) 656 up->efr |= OMAP_UART_SW_TX; 657 658 /* 659 * IXOFF Flag: 660 * Enable XON/XOFF flow control on input. 661 * Receiver compares XON1, XOFF1. 662 */ 663 if (termios->c_iflag & IXOFF) 664 up->efr |= OMAP_UART_SW_RX; 665 666 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 667 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 668 669 up->mcr = serial_in(up, UART_MCR); 670 671 /* 672 * IXANY Flag: 673 * Enable any character to restart output. 674 * Operation resumes after receiving any 675 * character after recognition of the XOFF character 676 */ 677 if (termios->c_iflag & IXANY) 678 up->mcr |= UART_MCR_XONANY; 679 680 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 681 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 682 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 683 /* Enable special char function UARTi.EFR_REG[5] and 684 * load the new software flow control mode IXON or IXOFF 685 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. 686 */ 687 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD); 688 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 689 690 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); 691 serial_out(up, UART_LCR, up->lcr); 692 } 693 694 static void serial_omap_uart_qos_work(struct work_struct *work) 695 { 696 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 697 qos_work); 698 699 pm_qos_update_request(&up->pm_qos_request, up->latency); 700 } 701 702 static void 703 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 704 struct ktermios *old) 705 { 706 struct uart_omap_port *up = (struct uart_omap_port *)port; 707 unsigned char cval = 0; 708 unsigned char efr = 0; 709 unsigned long flags = 0; 710 unsigned int baud, quot; 711 712 switch (termios->c_cflag & CSIZE) { 713 case CS5: 714 cval = UART_LCR_WLEN5; 715 break; 716 case CS6: 717 cval = UART_LCR_WLEN6; 718 break; 719 case CS7: 720 cval = UART_LCR_WLEN7; 721 break; 722 default: 723 case CS8: 724 cval = UART_LCR_WLEN8; 725 break; 726 } 727 728 if (termios->c_cflag & CSTOPB) 729 cval |= UART_LCR_STOP; 730 if (termios->c_cflag & PARENB) 731 cval |= UART_LCR_PARITY; 732 if (!(termios->c_cflag & PARODD)) 733 cval |= UART_LCR_EPAR; 734 735 /* 736 * Ask the core to calculate the divisor for us. 737 */ 738 739 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 740 quot = serial_omap_get_divisor(port, baud); 741 742 /* calculate wakeup latency constraint */ 743 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 744 up->latency = up->calc_latency; 745 schedule_work(&up->qos_work); 746 747 up->dll = quot & 0xff; 748 up->dlh = quot >> 8; 749 up->mdr1 = UART_OMAP_MDR1_DISABLE; 750 751 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 752 UART_FCR_ENABLE_FIFO; 753 if (up->use_dma) 754 up->fcr |= UART_FCR_DMA_SELECT; 755 756 /* 757 * Ok, we're now changing the port state. Do it with 758 * interrupts disabled. 759 */ 760 pm_runtime_get_sync(&up->pdev->dev); 761 spin_lock_irqsave(&up->port.lock, flags); 762 763 /* 764 * Update the per-port timeout. 765 */ 766 uart_update_timeout(port, termios->c_cflag, baud); 767 768 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 769 if (termios->c_iflag & INPCK) 770 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 771 if (termios->c_iflag & (BRKINT | PARMRK)) 772 up->port.read_status_mask |= UART_LSR_BI; 773 774 /* 775 * Characters to ignore 776 */ 777 up->port.ignore_status_mask = 0; 778 if (termios->c_iflag & IGNPAR) 779 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 780 if (termios->c_iflag & IGNBRK) { 781 up->port.ignore_status_mask |= UART_LSR_BI; 782 /* 783 * If we're ignoring parity and break indicators, 784 * ignore overruns too (for real raw support). 785 */ 786 if (termios->c_iflag & IGNPAR) 787 up->port.ignore_status_mask |= UART_LSR_OE; 788 } 789 790 /* 791 * ignore all characters if CREAD is not set 792 */ 793 if ((termios->c_cflag & CREAD) == 0) 794 up->port.ignore_status_mask |= UART_LSR_DR; 795 796 /* 797 * Modem status interrupts 798 */ 799 up->ier &= ~UART_IER_MSI; 800 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 801 up->ier |= UART_IER_MSI; 802 serial_out(up, UART_IER, up->ier); 803 serial_out(up, UART_LCR, cval); /* reset DLAB */ 804 up->lcr = cval; 805 up->scr = OMAP_UART_SCR_TX_EMPTY; 806 807 /* FIFOs and DMA Settings */ 808 809 /* FCR can be changed only when the 810 * baud clock is not running 811 * DLL_REG and DLH_REG set to 0. 812 */ 813 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 814 serial_out(up, UART_DLL, 0); 815 serial_out(up, UART_DLM, 0); 816 serial_out(up, UART_LCR, 0); 817 818 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 819 820 up->efr = serial_in(up, UART_EFR); 821 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 822 823 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 824 up->mcr = serial_in(up, UART_MCR); 825 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 826 /* FIFO ENABLE, DMA MODE */ 827 828 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 829 830 if (up->use_dma) { 831 serial_out(up, UART_TI752_TLR, 0); 832 up->scr |= UART_FCR_TRIGGER_4; 833 } else { 834 /* Set receive FIFO threshold to 1 byte */ 835 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 836 up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT); 837 } 838 839 serial_out(up, UART_FCR, up->fcr); 840 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 841 842 serial_out(up, UART_OMAP_SCR, up->scr); 843 844 serial_out(up, UART_EFR, up->efr); 845 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 846 serial_out(up, UART_MCR, up->mcr); 847 848 /* Protocol, Baud Rate, and Interrupt Settings */ 849 850 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 851 serial_omap_mdr1_errataset(up, up->mdr1); 852 else 853 serial_out(up, UART_OMAP_MDR1, up->mdr1); 854 855 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 856 857 up->efr = serial_in(up, UART_EFR); 858 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 859 860 serial_out(up, UART_LCR, 0); 861 serial_out(up, UART_IER, 0); 862 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 863 864 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 865 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 866 867 serial_out(up, UART_LCR, 0); 868 serial_out(up, UART_IER, up->ier); 869 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 870 871 serial_out(up, UART_EFR, up->efr); 872 serial_out(up, UART_LCR, cval); 873 874 if (baud > 230400 && baud != 3000000) 875 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 876 else 877 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 878 879 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 880 serial_omap_mdr1_errataset(up, up->mdr1); 881 else 882 serial_out(up, UART_OMAP_MDR1, up->mdr1); 883 884 /* Hardware Flow Control Configuration */ 885 886 if (termios->c_cflag & CRTSCTS) { 887 efr |= (UART_EFR_CTS | UART_EFR_RTS); 888 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 889 890 up->mcr = serial_in(up, UART_MCR); 891 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 892 893 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 894 up->efr = serial_in(up, UART_EFR); 895 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 896 897 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 898 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ 899 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 900 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); 901 serial_out(up, UART_LCR, cval); 902 } 903 904 serial_omap_set_mctrl(&up->port, up->port.mctrl); 905 /* Software Flow Control Configuration */ 906 serial_omap_configure_xonxoff(up, termios); 907 908 spin_unlock_irqrestore(&up->port.lock, flags); 909 pm_runtime_put(&up->pdev->dev); 910 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 911 } 912 913 static void 914 serial_omap_pm(struct uart_port *port, unsigned int state, 915 unsigned int oldstate) 916 { 917 struct uart_omap_port *up = (struct uart_omap_port *)port; 918 unsigned char efr; 919 920 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 921 922 pm_runtime_get_sync(&up->pdev->dev); 923 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 924 efr = serial_in(up, UART_EFR); 925 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 926 serial_out(up, UART_LCR, 0); 927 928 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 929 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 930 serial_out(up, UART_EFR, efr); 931 serial_out(up, UART_LCR, 0); 932 933 if (!device_may_wakeup(&up->pdev->dev)) { 934 if (!state) 935 pm_runtime_forbid(&up->pdev->dev); 936 else 937 pm_runtime_allow(&up->pdev->dev); 938 } 939 940 pm_runtime_put(&up->pdev->dev); 941 } 942 943 static void serial_omap_release_port(struct uart_port *port) 944 { 945 dev_dbg(port->dev, "serial_omap_release_port+\n"); 946 } 947 948 static int serial_omap_request_port(struct uart_port *port) 949 { 950 dev_dbg(port->dev, "serial_omap_request_port+\n"); 951 return 0; 952 } 953 954 static void serial_omap_config_port(struct uart_port *port, int flags) 955 { 956 struct uart_omap_port *up = (struct uart_omap_port *)port; 957 958 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 959 up->port.line); 960 up->port.type = PORT_OMAP; 961 } 962 963 static int 964 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 965 { 966 /* we don't want the core code to modify any port params */ 967 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 968 return -EINVAL; 969 } 970 971 static const char * 972 serial_omap_type(struct uart_port *port) 973 { 974 struct uart_omap_port *up = (struct uart_omap_port *)port; 975 976 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 977 return up->name; 978 } 979 980 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 981 982 static inline void wait_for_xmitr(struct uart_omap_port *up) 983 { 984 unsigned int status, tmout = 10000; 985 986 /* Wait up to 10ms for the character(s) to be sent. */ 987 do { 988 status = serial_in(up, UART_LSR); 989 990 if (status & UART_LSR_BI) 991 up->lsr_break_flag = UART_LSR_BI; 992 993 if (--tmout == 0) 994 break; 995 udelay(1); 996 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 997 998 /* Wait up to 1s for flow control if necessary */ 999 if (up->port.flags & UPF_CONS_FLOW) { 1000 tmout = 1000000; 1001 for (tmout = 1000000; tmout; tmout--) { 1002 unsigned int msr = serial_in(up, UART_MSR); 1003 1004 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1005 if (msr & UART_MSR_CTS) 1006 break; 1007 1008 udelay(1); 1009 } 1010 } 1011 } 1012 1013 #ifdef CONFIG_CONSOLE_POLL 1014 1015 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1016 { 1017 struct uart_omap_port *up = (struct uart_omap_port *)port; 1018 1019 pm_runtime_get_sync(&up->pdev->dev); 1020 wait_for_xmitr(up); 1021 serial_out(up, UART_TX, ch); 1022 pm_runtime_put(&up->pdev->dev); 1023 } 1024 1025 static int serial_omap_poll_get_char(struct uart_port *port) 1026 { 1027 struct uart_omap_port *up = (struct uart_omap_port *)port; 1028 unsigned int status; 1029 1030 pm_runtime_get_sync(&up->pdev->dev); 1031 status = serial_in(up, UART_LSR); 1032 if (!(status & UART_LSR_DR)) 1033 return NO_POLL_CHAR; 1034 1035 status = serial_in(up, UART_RX); 1036 pm_runtime_put(&up->pdev->dev); 1037 return status; 1038 } 1039 1040 #endif /* CONFIG_CONSOLE_POLL */ 1041 1042 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1043 1044 static struct uart_omap_port *serial_omap_console_ports[4]; 1045 1046 static struct uart_driver serial_omap_reg; 1047 1048 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1049 { 1050 struct uart_omap_port *up = (struct uart_omap_port *)port; 1051 1052 wait_for_xmitr(up); 1053 serial_out(up, UART_TX, ch); 1054 } 1055 1056 static void 1057 serial_omap_console_write(struct console *co, const char *s, 1058 unsigned int count) 1059 { 1060 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1061 unsigned long flags; 1062 unsigned int ier; 1063 int locked = 1; 1064 1065 pm_runtime_get_sync(&up->pdev->dev); 1066 1067 local_irq_save(flags); 1068 if (up->port.sysrq) 1069 locked = 0; 1070 else if (oops_in_progress) 1071 locked = spin_trylock(&up->port.lock); 1072 else 1073 spin_lock(&up->port.lock); 1074 1075 /* 1076 * First save the IER then disable the interrupts 1077 */ 1078 ier = serial_in(up, UART_IER); 1079 serial_out(up, UART_IER, 0); 1080 1081 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1082 1083 /* 1084 * Finally, wait for transmitter to become empty 1085 * and restore the IER 1086 */ 1087 wait_for_xmitr(up); 1088 serial_out(up, UART_IER, ier); 1089 /* 1090 * The receive handling will happen properly because the 1091 * receive ready bit will still be set; it is not cleared 1092 * on read. However, modem control will not, we must 1093 * call it if we have saved something in the saved flags 1094 * while processing with interrupts off. 1095 */ 1096 if (up->msr_saved_flags) 1097 check_modem_status(up); 1098 1099 pm_runtime_mark_last_busy(&up->pdev->dev); 1100 pm_runtime_put_autosuspend(&up->pdev->dev); 1101 if (locked) 1102 spin_unlock(&up->port.lock); 1103 local_irq_restore(flags); 1104 } 1105 1106 static int __init 1107 serial_omap_console_setup(struct console *co, char *options) 1108 { 1109 struct uart_omap_port *up; 1110 int baud = 115200; 1111 int bits = 8; 1112 int parity = 'n'; 1113 int flow = 'n'; 1114 1115 if (serial_omap_console_ports[co->index] == NULL) 1116 return -ENODEV; 1117 up = serial_omap_console_ports[co->index]; 1118 1119 if (options) 1120 uart_parse_options(options, &baud, &parity, &bits, &flow); 1121 1122 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1123 } 1124 1125 static struct console serial_omap_console = { 1126 .name = OMAP_SERIAL_NAME, 1127 .write = serial_omap_console_write, 1128 .device = uart_console_device, 1129 .setup = serial_omap_console_setup, 1130 .flags = CON_PRINTBUFFER, 1131 .index = -1, 1132 .data = &serial_omap_reg, 1133 }; 1134 1135 static void serial_omap_add_console_port(struct uart_omap_port *up) 1136 { 1137 serial_omap_console_ports[up->port.line] = up; 1138 } 1139 1140 #define OMAP_CONSOLE (&serial_omap_console) 1141 1142 #else 1143 1144 #define OMAP_CONSOLE NULL 1145 1146 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1147 {} 1148 1149 #endif 1150 1151 static struct uart_ops serial_omap_pops = { 1152 .tx_empty = serial_omap_tx_empty, 1153 .set_mctrl = serial_omap_set_mctrl, 1154 .get_mctrl = serial_omap_get_mctrl, 1155 .stop_tx = serial_omap_stop_tx, 1156 .start_tx = serial_omap_start_tx, 1157 .stop_rx = serial_omap_stop_rx, 1158 .enable_ms = serial_omap_enable_ms, 1159 .break_ctl = serial_omap_break_ctl, 1160 .startup = serial_omap_startup, 1161 .shutdown = serial_omap_shutdown, 1162 .set_termios = serial_omap_set_termios, 1163 .pm = serial_omap_pm, 1164 .type = serial_omap_type, 1165 .release_port = serial_omap_release_port, 1166 .request_port = serial_omap_request_port, 1167 .config_port = serial_omap_config_port, 1168 .verify_port = serial_omap_verify_port, 1169 #ifdef CONFIG_CONSOLE_POLL 1170 .poll_put_char = serial_omap_poll_put_char, 1171 .poll_get_char = serial_omap_poll_get_char, 1172 #endif 1173 }; 1174 1175 static struct uart_driver serial_omap_reg = { 1176 .owner = THIS_MODULE, 1177 .driver_name = "OMAP-SERIAL", 1178 .dev_name = OMAP_SERIAL_NAME, 1179 .nr = OMAP_MAX_HSUART_PORTS, 1180 .cons = OMAP_CONSOLE, 1181 }; 1182 1183 #ifdef CONFIG_PM_SLEEP 1184 static int serial_omap_suspend(struct device *dev) 1185 { 1186 struct uart_omap_port *up = dev_get_drvdata(dev); 1187 1188 if (up) { 1189 uart_suspend_port(&serial_omap_reg, &up->port); 1190 flush_work_sync(&up->qos_work); 1191 } 1192 1193 return 0; 1194 } 1195 1196 static int serial_omap_resume(struct device *dev) 1197 { 1198 struct uart_omap_port *up = dev_get_drvdata(dev); 1199 1200 if (up) 1201 uart_resume_port(&serial_omap_reg, &up->port); 1202 return 0; 1203 } 1204 #endif 1205 1206 static void serial_omap_rxdma_poll(unsigned long uart_no) 1207 { 1208 struct uart_omap_port *up = ui[uart_no]; 1209 unsigned int curr_dma_pos, curr_transmitted_size; 1210 int ret = 0; 1211 1212 curr_dma_pos = omap_get_dma_dst_pos(up->uart_dma.rx_dma_channel); 1213 if ((curr_dma_pos == up->uart_dma.prev_rx_dma_pos) || 1214 (curr_dma_pos == 0)) { 1215 if (jiffies_to_msecs(jiffies - up->port_activity) < 1216 up->uart_dma.rx_timeout) { 1217 mod_timer(&up->uart_dma.rx_timer, jiffies + 1218 usecs_to_jiffies(up->uart_dma.rx_poll_rate)); 1219 } else { 1220 serial_omap_stop_rxdma(up); 1221 up->ier |= (UART_IER_RDI | UART_IER_RLSI); 1222 serial_out(up, UART_IER, up->ier); 1223 } 1224 return; 1225 } 1226 1227 curr_transmitted_size = curr_dma_pos - 1228 up->uart_dma.prev_rx_dma_pos; 1229 up->port.icount.rx += curr_transmitted_size; 1230 tty_insert_flip_string(up->port.state->port.tty, 1231 up->uart_dma.rx_buf + 1232 (up->uart_dma.prev_rx_dma_pos - 1233 up->uart_dma.rx_buf_dma_phys), 1234 curr_transmitted_size); 1235 tty_flip_buffer_push(up->port.state->port.tty); 1236 up->uart_dma.prev_rx_dma_pos = curr_dma_pos; 1237 if (up->uart_dma.rx_buf_size + 1238 up->uart_dma.rx_buf_dma_phys == curr_dma_pos) { 1239 ret = serial_omap_start_rxdma(up); 1240 if (ret < 0) { 1241 serial_omap_stop_rxdma(up); 1242 up->ier |= (UART_IER_RDI | UART_IER_RLSI); 1243 serial_out(up, UART_IER, up->ier); 1244 } 1245 } else { 1246 mod_timer(&up->uart_dma.rx_timer, jiffies + 1247 usecs_to_jiffies(up->uart_dma.rx_poll_rate)); 1248 } 1249 up->port_activity = jiffies; 1250 } 1251 1252 static void uart_rx_dma_callback(int lch, u16 ch_status, void *data) 1253 { 1254 return; 1255 } 1256 1257 static int serial_omap_start_rxdma(struct uart_omap_port *up) 1258 { 1259 int ret = 0; 1260 1261 if (up->uart_dma.rx_dma_channel == -1) { 1262 pm_runtime_get_sync(&up->pdev->dev); 1263 ret = omap_request_dma(up->uart_dma.uart_dma_rx, 1264 "UART Rx DMA", 1265 (void *)uart_rx_dma_callback, up, 1266 &(up->uart_dma.rx_dma_channel)); 1267 if (ret < 0) 1268 return ret; 1269 1270 omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, 1271 OMAP_DMA_AMODE_CONSTANT, 1272 up->uart_dma.uart_base, 0, 0); 1273 omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, 1274 OMAP_DMA_AMODE_POST_INC, 1275 up->uart_dma.rx_buf_dma_phys, 0, 0); 1276 omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, 1277 OMAP_DMA_DATA_TYPE_S8, 1278 up->uart_dma.rx_buf_size, 1, 1279 OMAP_DMA_SYNC_ELEMENT, 1280 up->uart_dma.uart_dma_rx, 0); 1281 } 1282 up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; 1283 /* FIXME: Cache maintenance needed here? */ 1284 omap_start_dma(up->uart_dma.rx_dma_channel); 1285 mod_timer(&up->uart_dma.rx_timer, jiffies + 1286 usecs_to_jiffies(up->uart_dma.rx_poll_rate)); 1287 up->uart_dma.rx_dma_used = true; 1288 return ret; 1289 } 1290 1291 static void serial_omap_continue_tx(struct uart_omap_port *up) 1292 { 1293 struct circ_buf *xmit = &up->port.state->xmit; 1294 unsigned int start = up->uart_dma.tx_buf_dma_phys 1295 + (xmit->tail & (UART_XMIT_SIZE - 1)); 1296 1297 if (uart_circ_empty(xmit)) 1298 return; 1299 1300 up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); 1301 /* 1302 * It is a circular buffer. See if the buffer has wounded back. 1303 * If yes it will have to be transferred in two separate dma 1304 * transfers 1305 */ 1306 if (start + up->uart_dma.tx_buf_size >= 1307 up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) 1308 up->uart_dma.tx_buf_size = 1309 (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; 1310 omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, 1311 OMAP_DMA_AMODE_CONSTANT, 1312 up->uart_dma.uart_base, 0, 0); 1313 omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, 1314 OMAP_DMA_AMODE_POST_INC, start, 0, 0); 1315 omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, 1316 OMAP_DMA_DATA_TYPE_S8, 1317 up->uart_dma.tx_buf_size, 1, 1318 OMAP_DMA_SYNC_ELEMENT, 1319 up->uart_dma.uart_dma_tx, 0); 1320 /* FIXME: Cache maintenance needed here? */ 1321 omap_start_dma(up->uart_dma.tx_dma_channel); 1322 } 1323 1324 static void uart_tx_dma_callback(int lch, u16 ch_status, void *data) 1325 { 1326 struct uart_omap_port *up = (struct uart_omap_port *)data; 1327 struct circ_buf *xmit = &up->port.state->xmit; 1328 1329 xmit->tail = (xmit->tail + up->uart_dma.tx_buf_size) & \ 1330 (UART_XMIT_SIZE - 1); 1331 up->port.icount.tx += up->uart_dma.tx_buf_size; 1332 1333 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1334 uart_write_wakeup(&up->port); 1335 1336 if (uart_circ_empty(xmit)) { 1337 spin_lock(&(up->uart_dma.tx_lock)); 1338 serial_omap_stop_tx(&up->port); 1339 up->uart_dma.tx_dma_used = false; 1340 spin_unlock(&(up->uart_dma.tx_lock)); 1341 } else { 1342 omap_stop_dma(up->uart_dma.tx_dma_channel); 1343 serial_omap_continue_tx(up); 1344 } 1345 up->port_activity = jiffies; 1346 return; 1347 } 1348 1349 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1350 { 1351 struct omap_uart_port_info *omap_up_info; 1352 1353 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1354 if (!omap_up_info) 1355 return NULL; /* out of memory */ 1356 1357 of_property_read_u32(dev->of_node, "clock-frequency", 1358 &omap_up_info->uartclk); 1359 return omap_up_info; 1360 } 1361 1362 static int serial_omap_probe(struct platform_device *pdev) 1363 { 1364 struct uart_omap_port *up; 1365 struct resource *mem, *irq, *dma_tx, *dma_rx; 1366 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1367 int ret = -ENOSPC; 1368 1369 if (pdev->dev.of_node) 1370 omap_up_info = of_get_uart_port_info(&pdev->dev); 1371 1372 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1373 if (!mem) { 1374 dev_err(&pdev->dev, "no mem resource?\n"); 1375 return -ENODEV; 1376 } 1377 1378 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1379 if (!irq) { 1380 dev_err(&pdev->dev, "no irq resource?\n"); 1381 return -ENODEV; 1382 } 1383 1384 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), 1385 pdev->dev.driver->name)) { 1386 dev_err(&pdev->dev, "memory region already claimed\n"); 1387 return -EBUSY; 1388 } 1389 1390 dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1391 if (!dma_rx) 1392 return -ENXIO; 1393 1394 dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1395 if (!dma_tx) 1396 return -ENXIO; 1397 1398 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1399 if (!up) 1400 return -ENOMEM; 1401 1402 up->pdev = pdev; 1403 up->port.dev = &pdev->dev; 1404 up->port.type = PORT_OMAP; 1405 up->port.iotype = UPIO_MEM; 1406 up->port.irq = irq->start; 1407 1408 up->port.regshift = 2; 1409 up->port.fifosize = 64; 1410 up->port.ops = &serial_omap_pops; 1411 1412 if (pdev->dev.of_node) 1413 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); 1414 else 1415 up->port.line = pdev->id; 1416 1417 if (up->port.line < 0) { 1418 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1419 up->port.line); 1420 ret = -ENODEV; 1421 goto err_port_line; 1422 } 1423 1424 sprintf(up->name, "OMAP UART%d", up->port.line); 1425 up->port.mapbase = mem->start; 1426 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1427 resource_size(mem)); 1428 if (!up->port.membase) { 1429 dev_err(&pdev->dev, "can't ioremap UART\n"); 1430 ret = -ENOMEM; 1431 goto err_ioremap; 1432 } 1433 1434 up->port.flags = omap_up_info->flags; 1435 up->port.uartclk = omap_up_info->uartclk; 1436 if (!up->port.uartclk) { 1437 up->port.uartclk = DEFAULT_CLK_SPEED; 1438 dev_warn(&pdev->dev, "No clock speed specified: using default:" 1439 "%d\n", DEFAULT_CLK_SPEED); 1440 } 1441 up->uart_dma.uart_base = mem->start; 1442 up->errata = omap_up_info->errata; 1443 1444 if (omap_up_info->dma_enabled) { 1445 up->uart_dma.uart_dma_tx = dma_tx->start; 1446 up->uart_dma.uart_dma_rx = dma_rx->start; 1447 up->use_dma = 1; 1448 up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size; 1449 up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout; 1450 up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate; 1451 spin_lock_init(&(up->uart_dma.tx_lock)); 1452 spin_lock_init(&(up->uart_dma.rx_lock)); 1453 up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; 1454 up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; 1455 } 1456 1457 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1458 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1459 pm_qos_add_request(&up->pm_qos_request, 1460 PM_QOS_CPU_DMA_LATENCY, up->latency); 1461 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1462 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1463 1464 pm_runtime_use_autosuspend(&pdev->dev); 1465 pm_runtime_set_autosuspend_delay(&pdev->dev, 1466 omap_up_info->autosuspend_timeout); 1467 1468 pm_runtime_irq_safe(&pdev->dev); 1469 pm_runtime_enable(&pdev->dev); 1470 pm_runtime_get_sync(&pdev->dev); 1471 1472 ui[up->port.line] = up; 1473 serial_omap_add_console_port(up); 1474 1475 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1476 if (ret != 0) 1477 goto err_add_port; 1478 1479 pm_runtime_put(&pdev->dev); 1480 platform_set_drvdata(pdev, up); 1481 return 0; 1482 1483 err_add_port: 1484 pm_runtime_put(&pdev->dev); 1485 pm_runtime_disable(&pdev->dev); 1486 err_ioremap: 1487 err_port_line: 1488 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1489 pdev->id, __func__, ret); 1490 return ret; 1491 } 1492 1493 static int serial_omap_remove(struct platform_device *dev) 1494 { 1495 struct uart_omap_port *up = platform_get_drvdata(dev); 1496 1497 if (up) { 1498 pm_runtime_disable(&up->pdev->dev); 1499 uart_remove_one_port(&serial_omap_reg, &up->port); 1500 pm_qos_remove_request(&up->pm_qos_request); 1501 } 1502 1503 platform_set_drvdata(dev, NULL); 1504 return 0; 1505 } 1506 1507 /* 1508 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1509 * The access to uart register after MDR1 Access 1510 * causes UART to corrupt data. 1511 * 1512 * Need a delay = 1513 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1514 * give 10 times as much 1515 */ 1516 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1517 { 1518 u8 timeout = 255; 1519 1520 serial_out(up, UART_OMAP_MDR1, mdr1); 1521 udelay(2); 1522 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1523 UART_FCR_CLEAR_RCVR); 1524 /* 1525 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1526 * TX_FIFO_E bit is 1. 1527 */ 1528 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1529 (UART_LSR_THRE | UART_LSR_DR))) { 1530 timeout--; 1531 if (!timeout) { 1532 /* Should *never* happen. we warn and carry on */ 1533 dev_crit(&up->pdev->dev, "Errata i202: timedout %x\n", 1534 serial_in(up, UART_LSR)); 1535 break; 1536 } 1537 udelay(1); 1538 } 1539 } 1540 1541 #ifdef CONFIG_PM_RUNTIME 1542 static void serial_omap_restore_context(struct uart_omap_port *up) 1543 { 1544 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1545 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1546 else 1547 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1548 1549 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1550 serial_out(up, UART_EFR, UART_EFR_ECB); 1551 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1552 serial_out(up, UART_IER, 0x0); 1553 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1554 serial_out(up, UART_DLL, up->dll); 1555 serial_out(up, UART_DLM, up->dlh); 1556 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1557 serial_out(up, UART_IER, up->ier); 1558 serial_out(up, UART_FCR, up->fcr); 1559 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1560 serial_out(up, UART_MCR, up->mcr); 1561 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1562 serial_out(up, UART_OMAP_SCR, up->scr); 1563 serial_out(up, UART_EFR, up->efr); 1564 serial_out(up, UART_LCR, up->lcr); 1565 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1566 serial_omap_mdr1_errataset(up, up->mdr1); 1567 else 1568 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1569 } 1570 1571 static int serial_omap_runtime_suspend(struct device *dev) 1572 { 1573 struct uart_omap_port *up = dev_get_drvdata(dev); 1574 struct omap_uart_port_info *pdata = dev->platform_data; 1575 1576 if (!up) 1577 return -EINVAL; 1578 1579 if (!pdata || !pdata->enable_wakeup) 1580 return 0; 1581 1582 if (pdata->get_context_loss_count) 1583 up->context_loss_cnt = pdata->get_context_loss_count(dev); 1584 1585 if (device_may_wakeup(dev)) { 1586 if (!up->wakeups_enabled) { 1587 pdata->enable_wakeup(up->pdev, true); 1588 up->wakeups_enabled = true; 1589 } 1590 } else { 1591 if (up->wakeups_enabled) { 1592 pdata->enable_wakeup(up->pdev, false); 1593 up->wakeups_enabled = false; 1594 } 1595 } 1596 1597 /* Errata i291 */ 1598 if (up->use_dma && pdata->set_forceidle && 1599 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE)) 1600 pdata->set_forceidle(up->pdev); 1601 1602 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1603 schedule_work(&up->qos_work); 1604 1605 return 0; 1606 } 1607 1608 static int serial_omap_runtime_resume(struct device *dev) 1609 { 1610 struct uart_omap_port *up = dev_get_drvdata(dev); 1611 struct omap_uart_port_info *pdata = dev->platform_data; 1612 1613 if (up && pdata) { 1614 if (pdata->get_context_loss_count) { 1615 u32 loss_cnt = pdata->get_context_loss_count(dev); 1616 1617 if (up->context_loss_cnt != loss_cnt) 1618 serial_omap_restore_context(up); 1619 } 1620 1621 /* Errata i291 */ 1622 if (up->use_dma && pdata->set_noidle && 1623 (up->errata & UART_ERRATA_i291_DMA_FORCEIDLE)) 1624 pdata->set_noidle(up->pdev); 1625 1626 up->latency = up->calc_latency; 1627 schedule_work(&up->qos_work); 1628 } 1629 1630 return 0; 1631 } 1632 #endif 1633 1634 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1635 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1636 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1637 serial_omap_runtime_resume, NULL) 1638 }; 1639 1640 #if defined(CONFIG_OF) 1641 static const struct of_device_id omap_serial_of_match[] = { 1642 { .compatible = "ti,omap2-uart" }, 1643 { .compatible = "ti,omap3-uart" }, 1644 { .compatible = "ti,omap4-uart" }, 1645 {}, 1646 }; 1647 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1648 #endif 1649 1650 static struct platform_driver serial_omap_driver = { 1651 .probe = serial_omap_probe, 1652 .remove = serial_omap_remove, 1653 .driver = { 1654 .name = DRIVER_NAME, 1655 .pm = &serial_omap_dev_pm_ops, 1656 .of_match_table = of_match_ptr(omap_serial_of_match), 1657 }, 1658 }; 1659 1660 static int __init serial_omap_init(void) 1661 { 1662 int ret; 1663 1664 ret = uart_register_driver(&serial_omap_reg); 1665 if (ret != 0) 1666 return ret; 1667 ret = platform_driver_register(&serial_omap_driver); 1668 if (ret != 0) 1669 uart_unregister_driver(&serial_omap_reg); 1670 return ret; 1671 } 1672 1673 static void __exit serial_omap_exit(void) 1674 { 1675 platform_driver_unregister(&serial_omap_driver); 1676 uart_unregister_driver(&serial_omap_reg); 1677 } 1678 1679 module_init(serial_omap_init); 1680 module_exit(serial_omap_exit); 1681 1682 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1683 MODULE_LICENSE("GPL"); 1684 MODULE_AUTHOR("Texas Instruments Inc"); 1685