1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/io.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/gpio.h> 43 #include <linux/pinctrl/consumer.h> 44 #include <linux/platform_data/serial-omap.h> 45 46 #define OMAP_MAX_HSUART_PORTS 6 47 48 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 49 50 #define OMAP_UART_REV_42 0x0402 51 #define OMAP_UART_REV_46 0x0406 52 #define OMAP_UART_REV_52 0x0502 53 #define OMAP_UART_REV_63 0x0603 54 55 #define UART_ERRATA_i202_MDR1_ACCESS BIT(0) 56 #define UART_ERRATA_i291_DMA_FORCEIDLE BIT(1) 57 58 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ 59 60 /* SCR register bitmasks */ 61 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 62 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) 63 #define OMAP_UART_SCR_TX_EMPTY (1 << 3) 64 65 /* FCR register bitmasks */ 66 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 67 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 68 69 /* MVR register bitmasks */ 70 #define OMAP_UART_MVR_SCHEME_SHIFT 30 71 72 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 73 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 74 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 75 76 #define OMAP_UART_MVR_MAJ_MASK 0x700 77 #define OMAP_UART_MVR_MAJ_SHIFT 8 78 #define OMAP_UART_MVR_MIN_MASK 0x3f 79 80 #define OMAP_UART_DMA_CH_FREE -1 81 82 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA 83 #define OMAP_MODE13X_SPEED 230400 84 85 /* WER = 0x7F 86 * Enable module level wakeup in WER reg 87 */ 88 #define OMAP_UART_WER_MOD_WKUP 0X7F 89 90 /* Enable XON/XOFF flow control on output */ 91 #define OMAP_UART_SW_TX 0x08 92 93 /* Enable XON/XOFF flow control on input */ 94 #define OMAP_UART_SW_RX 0x02 95 96 #define OMAP_UART_SW_CLR 0xF0 97 98 #define OMAP_UART_TCR_TRIG 0x0F 99 100 struct uart_omap_dma { 101 u8 uart_dma_tx; 102 u8 uart_dma_rx; 103 int rx_dma_channel; 104 int tx_dma_channel; 105 dma_addr_t rx_buf_dma_phys; 106 dma_addr_t tx_buf_dma_phys; 107 unsigned int uart_base; 108 /* 109 * Buffer for rx dma.It is not required for tx because the buffer 110 * comes from port structure. 111 */ 112 unsigned char *rx_buf; 113 unsigned int prev_rx_dma_pos; 114 int tx_buf_size; 115 int tx_dma_used; 116 int rx_dma_used; 117 spinlock_t tx_lock; 118 spinlock_t rx_lock; 119 /* timer to poll activity on rx dma */ 120 struct timer_list rx_timer; 121 unsigned int rx_buf_size; 122 unsigned int rx_poll_rate; 123 unsigned int rx_timeout; 124 }; 125 126 struct uart_omap_port { 127 struct uart_port port; 128 struct uart_omap_dma uart_dma; 129 struct device *dev; 130 131 unsigned char ier; 132 unsigned char lcr; 133 unsigned char mcr; 134 unsigned char fcr; 135 unsigned char efr; 136 unsigned char dll; 137 unsigned char dlh; 138 unsigned char mdr1; 139 unsigned char scr; 140 141 int use_dma; 142 /* 143 * Some bits in registers are cleared on a read, so they must 144 * be saved whenever the register is read but the bits will not 145 * be immediately processed. 146 */ 147 unsigned int lsr_break_flag; 148 unsigned char msr_saved_flags; 149 char name[20]; 150 unsigned long port_activity; 151 int context_loss_cnt; 152 u32 errata; 153 u8 wakeups_enabled; 154 155 int DTR_gpio; 156 int DTR_inverted; 157 int DTR_active; 158 159 struct pm_qos_request pm_qos_request; 160 u32 latency; 161 u32 calc_latency; 162 struct work_struct qos_work; 163 struct pinctrl *pins; 164 bool is_suspending; 165 }; 166 167 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 168 169 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 170 171 /* Forward declaration of functions */ 172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 173 174 static struct workqueue_struct *serial_omap_uart_wq; 175 176 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 177 { 178 offset <<= up->port.regshift; 179 return readw(up->port.membase + offset); 180 } 181 182 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 183 { 184 offset <<= up->port.regshift; 185 writew(value, up->port.membase + offset); 186 } 187 188 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 189 { 190 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 191 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 192 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 193 serial_out(up, UART_FCR, 0); 194 } 195 196 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 197 { 198 struct omap_uart_port_info *pdata = up->dev->platform_data; 199 200 if (!pdata || !pdata->get_context_loss_count) 201 return -EINVAL; 202 203 return pdata->get_context_loss_count(up->dev); 204 } 205 206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 207 { 208 struct omap_uart_port_info *pdata = up->dev->platform_data; 209 210 if (!pdata || !pdata->enable_wakeup) 211 return; 212 213 pdata->enable_wakeup(up->dev, enable); 214 } 215 216 /* 217 * serial_omap_baud_is_mode16 - check if baud rate is MODE16X 218 * @port: uart port info 219 * @baud: baudrate for which mode needs to be determined 220 * 221 * Returns true if baud rate is MODE16X and false if MODE13X 222 * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values, 223 * and Error Rates" determines modes not for all common baud rates. 224 * E.g. for 1000000 baud rate mode must be 16x, but according to that 225 * table it's determined as 13x. 226 */ 227 static bool 228 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud) 229 { 230 unsigned int n13 = port->uartclk / (13 * baud); 231 unsigned int n16 = port->uartclk / (16 * baud); 232 int baudAbsDiff13 = baud - (port->uartclk / (13 * n13)); 233 int baudAbsDiff16 = baud - (port->uartclk / (16 * n16)); 234 if(baudAbsDiff13 < 0) 235 baudAbsDiff13 = -baudAbsDiff13; 236 if(baudAbsDiff16 < 0) 237 baudAbsDiff16 = -baudAbsDiff16; 238 239 return (baudAbsDiff13 > baudAbsDiff16); 240 } 241 242 /* 243 * serial_omap_get_divisor - calculate divisor value 244 * @port: uart port info 245 * @baud: baudrate for which divisor needs to be calculated. 246 */ 247 static unsigned int 248 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 249 { 250 unsigned int divisor; 251 252 if (!serial_omap_baud_is_mode16(port, baud)) 253 divisor = 13; 254 else 255 divisor = 16; 256 return port->uartclk/(baud * divisor); 257 } 258 259 static void serial_omap_enable_ms(struct uart_port *port) 260 { 261 struct uart_omap_port *up = to_uart_omap_port(port); 262 263 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 264 265 pm_runtime_get_sync(up->dev); 266 up->ier |= UART_IER_MSI; 267 serial_out(up, UART_IER, up->ier); 268 pm_runtime_mark_last_busy(up->dev); 269 pm_runtime_put_autosuspend(up->dev); 270 } 271 272 static void serial_omap_stop_tx(struct uart_port *port) 273 { 274 struct uart_omap_port *up = to_uart_omap_port(port); 275 276 pm_runtime_get_sync(up->dev); 277 if (up->ier & UART_IER_THRI) { 278 up->ier &= ~UART_IER_THRI; 279 serial_out(up, UART_IER, up->ier); 280 } 281 282 pm_runtime_mark_last_busy(up->dev); 283 pm_runtime_put_autosuspend(up->dev); 284 } 285 286 static void serial_omap_stop_rx(struct uart_port *port) 287 { 288 struct uart_omap_port *up = to_uart_omap_port(port); 289 290 pm_runtime_get_sync(up->dev); 291 up->ier &= ~UART_IER_RLSI; 292 up->port.read_status_mask &= ~UART_LSR_DR; 293 serial_out(up, UART_IER, up->ier); 294 pm_runtime_mark_last_busy(up->dev); 295 pm_runtime_put_autosuspend(up->dev); 296 } 297 298 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 299 { 300 struct circ_buf *xmit = &up->port.state->xmit; 301 int count; 302 303 if (up->port.x_char) { 304 serial_out(up, UART_TX, up->port.x_char); 305 up->port.icount.tx++; 306 up->port.x_char = 0; 307 return; 308 } 309 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 310 serial_omap_stop_tx(&up->port); 311 return; 312 } 313 count = up->port.fifosize / 4; 314 do { 315 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 316 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 317 up->port.icount.tx++; 318 if (uart_circ_empty(xmit)) 319 break; 320 } while (--count > 0); 321 322 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 323 spin_unlock(&up->port.lock); 324 uart_write_wakeup(&up->port); 325 spin_lock(&up->port.lock); 326 } 327 328 if (uart_circ_empty(xmit)) 329 serial_omap_stop_tx(&up->port); 330 } 331 332 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 333 { 334 if (!(up->ier & UART_IER_THRI)) { 335 up->ier |= UART_IER_THRI; 336 serial_out(up, UART_IER, up->ier); 337 } 338 } 339 340 static void serial_omap_start_tx(struct uart_port *port) 341 { 342 struct uart_omap_port *up = to_uart_omap_port(port); 343 344 pm_runtime_get_sync(up->dev); 345 serial_omap_enable_ier_thri(up); 346 pm_runtime_mark_last_busy(up->dev); 347 pm_runtime_put_autosuspend(up->dev); 348 } 349 350 static void serial_omap_throttle(struct uart_port *port) 351 { 352 struct uart_omap_port *up = to_uart_omap_port(port); 353 unsigned long flags; 354 355 pm_runtime_get_sync(up->dev); 356 spin_lock_irqsave(&up->port.lock, flags); 357 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 358 serial_out(up, UART_IER, up->ier); 359 spin_unlock_irqrestore(&up->port.lock, flags); 360 pm_runtime_mark_last_busy(up->dev); 361 pm_runtime_put_autosuspend(up->dev); 362 } 363 364 static void serial_omap_unthrottle(struct uart_port *port) 365 { 366 struct uart_omap_port *up = to_uart_omap_port(port); 367 unsigned long flags; 368 369 pm_runtime_get_sync(up->dev); 370 spin_lock_irqsave(&up->port.lock, flags); 371 up->ier |= UART_IER_RLSI | UART_IER_RDI; 372 serial_out(up, UART_IER, up->ier); 373 spin_unlock_irqrestore(&up->port.lock, flags); 374 pm_runtime_mark_last_busy(up->dev); 375 pm_runtime_put_autosuspend(up->dev); 376 } 377 378 static unsigned int check_modem_status(struct uart_omap_port *up) 379 { 380 unsigned int status; 381 382 status = serial_in(up, UART_MSR); 383 status |= up->msr_saved_flags; 384 up->msr_saved_flags = 0; 385 if ((status & UART_MSR_ANY_DELTA) == 0) 386 return status; 387 388 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 389 up->port.state != NULL) { 390 if (status & UART_MSR_TERI) 391 up->port.icount.rng++; 392 if (status & UART_MSR_DDSR) 393 up->port.icount.dsr++; 394 if (status & UART_MSR_DDCD) 395 uart_handle_dcd_change 396 (&up->port, status & UART_MSR_DCD); 397 if (status & UART_MSR_DCTS) 398 uart_handle_cts_change 399 (&up->port, status & UART_MSR_CTS); 400 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 401 } 402 403 return status; 404 } 405 406 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 407 { 408 unsigned int flag; 409 unsigned char ch = 0; 410 411 if (likely(lsr & UART_LSR_DR)) 412 ch = serial_in(up, UART_RX); 413 414 up->port.icount.rx++; 415 flag = TTY_NORMAL; 416 417 if (lsr & UART_LSR_BI) { 418 flag = TTY_BREAK; 419 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 420 up->port.icount.brk++; 421 /* 422 * We do the SysRQ and SAK checking 423 * here because otherwise the break 424 * may get masked by ignore_status_mask 425 * or read_status_mask. 426 */ 427 if (uart_handle_break(&up->port)) 428 return; 429 430 } 431 432 if (lsr & UART_LSR_PE) { 433 flag = TTY_PARITY; 434 up->port.icount.parity++; 435 } 436 437 if (lsr & UART_LSR_FE) { 438 flag = TTY_FRAME; 439 up->port.icount.frame++; 440 } 441 442 if (lsr & UART_LSR_OE) 443 up->port.icount.overrun++; 444 445 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 446 if (up->port.line == up->port.cons->index) { 447 /* Recover the break flag from console xmit */ 448 lsr |= up->lsr_break_flag; 449 } 450 #endif 451 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 452 } 453 454 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 455 { 456 unsigned char ch = 0; 457 unsigned int flag; 458 459 if (!(lsr & UART_LSR_DR)) 460 return; 461 462 ch = serial_in(up, UART_RX); 463 flag = TTY_NORMAL; 464 up->port.icount.rx++; 465 466 if (uart_handle_sysrq_char(&up->port, ch)) 467 return; 468 469 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 470 } 471 472 /** 473 * serial_omap_irq() - This handles the interrupt from one port 474 * @irq: uart port irq number 475 * @dev_id: uart port info 476 */ 477 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 478 { 479 struct uart_omap_port *up = dev_id; 480 unsigned int iir, lsr; 481 unsigned int type; 482 irqreturn_t ret = IRQ_NONE; 483 int max_count = 256; 484 485 spin_lock(&up->port.lock); 486 pm_runtime_get_sync(up->dev); 487 488 do { 489 iir = serial_in(up, UART_IIR); 490 if (iir & UART_IIR_NO_INT) 491 break; 492 493 ret = IRQ_HANDLED; 494 lsr = serial_in(up, UART_LSR); 495 496 /* extract IRQ type from IIR register */ 497 type = iir & 0x3e; 498 499 switch (type) { 500 case UART_IIR_MSI: 501 check_modem_status(up); 502 break; 503 case UART_IIR_THRI: 504 transmit_chars(up, lsr); 505 break; 506 case UART_IIR_RX_TIMEOUT: 507 /* FALLTHROUGH */ 508 case UART_IIR_RDI: 509 serial_omap_rdi(up, lsr); 510 break; 511 case UART_IIR_RLSI: 512 serial_omap_rlsi(up, lsr); 513 break; 514 case UART_IIR_CTS_RTS_DSR: 515 /* simply try again */ 516 break; 517 case UART_IIR_XOFF: 518 /* FALLTHROUGH */ 519 default: 520 break; 521 } 522 } while (!(iir & UART_IIR_NO_INT) && max_count--); 523 524 spin_unlock(&up->port.lock); 525 526 tty_flip_buffer_push(&up->port.state->port); 527 528 pm_runtime_mark_last_busy(up->dev); 529 pm_runtime_put_autosuspend(up->dev); 530 up->port_activity = jiffies; 531 532 return ret; 533 } 534 535 static unsigned int serial_omap_tx_empty(struct uart_port *port) 536 { 537 struct uart_omap_port *up = to_uart_omap_port(port); 538 unsigned long flags = 0; 539 unsigned int ret = 0; 540 541 pm_runtime_get_sync(up->dev); 542 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 543 spin_lock_irqsave(&up->port.lock, flags); 544 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 545 spin_unlock_irqrestore(&up->port.lock, flags); 546 pm_runtime_mark_last_busy(up->dev); 547 pm_runtime_put_autosuspend(up->dev); 548 return ret; 549 } 550 551 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 552 { 553 struct uart_omap_port *up = to_uart_omap_port(port); 554 unsigned int status; 555 unsigned int ret = 0; 556 557 pm_runtime_get_sync(up->dev); 558 status = check_modem_status(up); 559 pm_runtime_mark_last_busy(up->dev); 560 pm_runtime_put_autosuspend(up->dev); 561 562 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 563 564 if (status & UART_MSR_DCD) 565 ret |= TIOCM_CAR; 566 if (status & UART_MSR_RI) 567 ret |= TIOCM_RNG; 568 if (status & UART_MSR_DSR) 569 ret |= TIOCM_DSR; 570 if (status & UART_MSR_CTS) 571 ret |= TIOCM_CTS; 572 return ret; 573 } 574 575 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 576 { 577 struct uart_omap_port *up = to_uart_omap_port(port); 578 unsigned char mcr = 0, old_mcr; 579 580 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 581 if (mctrl & TIOCM_RTS) 582 mcr |= UART_MCR_RTS; 583 if (mctrl & TIOCM_DTR) 584 mcr |= UART_MCR_DTR; 585 if (mctrl & TIOCM_OUT1) 586 mcr |= UART_MCR_OUT1; 587 if (mctrl & TIOCM_OUT2) 588 mcr |= UART_MCR_OUT2; 589 if (mctrl & TIOCM_LOOP) 590 mcr |= UART_MCR_LOOP; 591 592 pm_runtime_get_sync(up->dev); 593 old_mcr = serial_in(up, UART_MCR); 594 old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 | 595 UART_MCR_DTR | UART_MCR_RTS); 596 up->mcr = old_mcr | mcr; 597 serial_out(up, UART_MCR, up->mcr); 598 pm_runtime_mark_last_busy(up->dev); 599 pm_runtime_put_autosuspend(up->dev); 600 601 if (gpio_is_valid(up->DTR_gpio) && 602 !!(mctrl & TIOCM_DTR) != up->DTR_active) { 603 up->DTR_active = !up->DTR_active; 604 if (gpio_cansleep(up->DTR_gpio)) 605 schedule_work(&up->qos_work); 606 else 607 gpio_set_value(up->DTR_gpio, 608 up->DTR_active != up->DTR_inverted); 609 } 610 } 611 612 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 613 { 614 struct uart_omap_port *up = to_uart_omap_port(port); 615 unsigned long flags = 0; 616 617 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 618 pm_runtime_get_sync(up->dev); 619 spin_lock_irqsave(&up->port.lock, flags); 620 if (break_state == -1) 621 up->lcr |= UART_LCR_SBC; 622 else 623 up->lcr &= ~UART_LCR_SBC; 624 serial_out(up, UART_LCR, up->lcr); 625 spin_unlock_irqrestore(&up->port.lock, flags); 626 pm_runtime_mark_last_busy(up->dev); 627 pm_runtime_put_autosuspend(up->dev); 628 } 629 630 static int serial_omap_startup(struct uart_port *port) 631 { 632 struct uart_omap_port *up = to_uart_omap_port(port); 633 unsigned long flags = 0; 634 int retval; 635 636 /* 637 * Allocate the IRQ 638 */ 639 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 640 up->name, up); 641 if (retval) 642 return retval; 643 644 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 645 646 pm_runtime_get_sync(up->dev); 647 /* 648 * Clear the FIFO buffers and disable them. 649 * (they will be reenabled in set_termios()) 650 */ 651 serial_omap_clear_fifos(up); 652 /* For Hardware flow control */ 653 serial_out(up, UART_MCR, UART_MCR_RTS); 654 655 /* 656 * Clear the interrupt registers. 657 */ 658 (void) serial_in(up, UART_LSR); 659 if (serial_in(up, UART_LSR) & UART_LSR_DR) 660 (void) serial_in(up, UART_RX); 661 (void) serial_in(up, UART_IIR); 662 (void) serial_in(up, UART_MSR); 663 664 /* 665 * Now, initialize the UART 666 */ 667 serial_out(up, UART_LCR, UART_LCR_WLEN8); 668 spin_lock_irqsave(&up->port.lock, flags); 669 /* 670 * Most PC uarts need OUT2 raised to enable interrupts. 671 */ 672 up->port.mctrl |= TIOCM_OUT2; 673 serial_omap_set_mctrl(&up->port, up->port.mctrl); 674 spin_unlock_irqrestore(&up->port.lock, flags); 675 676 up->msr_saved_flags = 0; 677 /* 678 * Finally, enable interrupts. Note: Modem status interrupts 679 * are set via set_termios(), which will be occurring imminently 680 * anyway, so we don't enable them here. 681 */ 682 up->ier = UART_IER_RLSI | UART_IER_RDI; 683 serial_out(up, UART_IER, up->ier); 684 685 /* Enable module level wake up */ 686 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 687 688 pm_runtime_mark_last_busy(up->dev); 689 pm_runtime_put_autosuspend(up->dev); 690 up->port_activity = jiffies; 691 return 0; 692 } 693 694 static void serial_omap_shutdown(struct uart_port *port) 695 { 696 struct uart_omap_port *up = to_uart_omap_port(port); 697 unsigned long flags = 0; 698 699 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 700 701 pm_runtime_get_sync(up->dev); 702 /* 703 * Disable interrupts from this port 704 */ 705 up->ier = 0; 706 serial_out(up, UART_IER, 0); 707 708 spin_lock_irqsave(&up->port.lock, flags); 709 up->port.mctrl &= ~TIOCM_OUT2; 710 serial_omap_set_mctrl(&up->port, up->port.mctrl); 711 spin_unlock_irqrestore(&up->port.lock, flags); 712 713 /* 714 * Disable break condition and FIFOs 715 */ 716 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 717 serial_omap_clear_fifos(up); 718 719 /* 720 * Read data port to reset things, and then free the irq 721 */ 722 if (serial_in(up, UART_LSR) & UART_LSR_DR) 723 (void) serial_in(up, UART_RX); 724 725 pm_runtime_mark_last_busy(up->dev); 726 pm_runtime_put_autosuspend(up->dev); 727 free_irq(up->port.irq, up); 728 } 729 730 static void serial_omap_uart_qos_work(struct work_struct *work) 731 { 732 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 733 qos_work); 734 735 pm_qos_update_request(&up->pm_qos_request, up->latency); 736 if (gpio_is_valid(up->DTR_gpio)) 737 gpio_set_value_cansleep(up->DTR_gpio, 738 up->DTR_active != up->DTR_inverted); 739 } 740 741 static void 742 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 743 struct ktermios *old) 744 { 745 struct uart_omap_port *up = to_uart_omap_port(port); 746 unsigned char cval = 0; 747 unsigned long flags = 0; 748 unsigned int baud, quot; 749 750 switch (termios->c_cflag & CSIZE) { 751 case CS5: 752 cval = UART_LCR_WLEN5; 753 break; 754 case CS6: 755 cval = UART_LCR_WLEN6; 756 break; 757 case CS7: 758 cval = UART_LCR_WLEN7; 759 break; 760 default: 761 case CS8: 762 cval = UART_LCR_WLEN8; 763 break; 764 } 765 766 if (termios->c_cflag & CSTOPB) 767 cval |= UART_LCR_STOP; 768 if (termios->c_cflag & PARENB) 769 cval |= UART_LCR_PARITY; 770 if (!(termios->c_cflag & PARODD)) 771 cval |= UART_LCR_EPAR; 772 if (termios->c_cflag & CMSPAR) 773 cval |= UART_LCR_SPAR; 774 775 /* 776 * Ask the core to calculate the divisor for us. 777 */ 778 779 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 780 quot = serial_omap_get_divisor(port, baud); 781 782 /* calculate wakeup latency constraint */ 783 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 784 up->latency = up->calc_latency; 785 schedule_work(&up->qos_work); 786 787 up->dll = quot & 0xff; 788 up->dlh = quot >> 8; 789 up->mdr1 = UART_OMAP_MDR1_DISABLE; 790 791 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 792 UART_FCR_ENABLE_FIFO; 793 794 /* 795 * Ok, we're now changing the port state. Do it with 796 * interrupts disabled. 797 */ 798 pm_runtime_get_sync(up->dev); 799 spin_lock_irqsave(&up->port.lock, flags); 800 801 /* 802 * Update the per-port timeout. 803 */ 804 uart_update_timeout(port, termios->c_cflag, baud); 805 806 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 807 if (termios->c_iflag & INPCK) 808 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 809 if (termios->c_iflag & (BRKINT | PARMRK)) 810 up->port.read_status_mask |= UART_LSR_BI; 811 812 /* 813 * Characters to ignore 814 */ 815 up->port.ignore_status_mask = 0; 816 if (termios->c_iflag & IGNPAR) 817 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 818 if (termios->c_iflag & IGNBRK) { 819 up->port.ignore_status_mask |= UART_LSR_BI; 820 /* 821 * If we're ignoring parity and break indicators, 822 * ignore overruns too (for real raw support). 823 */ 824 if (termios->c_iflag & IGNPAR) 825 up->port.ignore_status_mask |= UART_LSR_OE; 826 } 827 828 /* 829 * ignore all characters if CREAD is not set 830 */ 831 if ((termios->c_cflag & CREAD) == 0) 832 up->port.ignore_status_mask |= UART_LSR_DR; 833 834 /* 835 * Modem status interrupts 836 */ 837 up->ier &= ~UART_IER_MSI; 838 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 839 up->ier |= UART_IER_MSI; 840 serial_out(up, UART_IER, up->ier); 841 serial_out(up, UART_LCR, cval); /* reset DLAB */ 842 up->lcr = cval; 843 up->scr = 0; 844 845 /* FIFOs and DMA Settings */ 846 847 /* FCR can be changed only when the 848 * baud clock is not running 849 * DLL_REG and DLH_REG set to 0. 850 */ 851 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 852 serial_out(up, UART_DLL, 0); 853 serial_out(up, UART_DLM, 0); 854 serial_out(up, UART_LCR, 0); 855 856 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 857 858 up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB; 859 up->efr &= ~UART_EFR_SCD; 860 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 861 862 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 863 up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR; 864 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 865 /* FIFO ENABLE, DMA MODE */ 866 867 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 868 /* 869 * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK 870 * sets Enables the granularity of 1 for TRIGGER RX 871 * level. Along with setting RX FIFO trigger level 872 * to 1 (as noted below, 16 characters) and TLR[3:0] 873 * to zero this will result RX FIFO threshold level 874 * to 1 character, instead of 16 as noted in comment 875 * below. 876 */ 877 878 /* Set receive FIFO threshold to 16 characters and 879 * transmit FIFO threshold to 16 spaces 880 */ 881 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 882 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 883 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 884 UART_FCR_ENABLE_FIFO; 885 886 serial_out(up, UART_FCR, up->fcr); 887 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 888 889 serial_out(up, UART_OMAP_SCR, up->scr); 890 891 /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */ 892 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 893 serial_out(up, UART_MCR, up->mcr); 894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 895 serial_out(up, UART_EFR, up->efr); 896 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 897 898 /* Protocol, Baud Rate, and Interrupt Settings */ 899 900 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 901 serial_omap_mdr1_errataset(up, up->mdr1); 902 else 903 serial_out(up, UART_OMAP_MDR1, up->mdr1); 904 905 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 906 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 907 908 serial_out(up, UART_LCR, 0); 909 serial_out(up, UART_IER, 0); 910 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 911 912 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 913 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 914 915 serial_out(up, UART_LCR, 0); 916 serial_out(up, UART_IER, up->ier); 917 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 918 919 serial_out(up, UART_EFR, up->efr); 920 serial_out(up, UART_LCR, cval); 921 922 if (!serial_omap_baud_is_mode16(port, baud)) 923 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 924 else 925 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 926 927 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 928 serial_omap_mdr1_errataset(up, up->mdr1); 929 else 930 serial_out(up, UART_OMAP_MDR1, up->mdr1); 931 932 /* Configure flow control */ 933 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 934 935 /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */ 936 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 937 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 938 939 /* Enable access to TCR/TLR */ 940 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 941 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 942 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 943 944 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 945 946 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) { 947 /* Enable AUTORTS and AUTOCTS */ 948 up->efr |= UART_EFR_CTS | UART_EFR_RTS; 949 950 /* Ensure MCR RTS is asserted */ 951 up->mcr |= UART_MCR_RTS; 952 } else { 953 /* Disable AUTORTS and AUTOCTS */ 954 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); 955 } 956 957 if (up->port.flags & UPF_SOFT_FLOW) { 958 /* clear SW control mode bits */ 959 up->efr &= OMAP_UART_SW_CLR; 960 961 /* 962 * IXON Flag: 963 * Enable XON/XOFF flow control on input. 964 * Receiver compares XON1, XOFF1. 965 */ 966 if (termios->c_iflag & IXON) 967 up->efr |= OMAP_UART_SW_RX; 968 969 /* 970 * IXOFF Flag: 971 * Enable XON/XOFF flow control on output. 972 * Transmit XON1, XOFF1 973 */ 974 if (termios->c_iflag & IXOFF) 975 up->efr |= OMAP_UART_SW_TX; 976 977 /* 978 * IXANY Flag: 979 * Enable any character to restart output. 980 * Operation resumes after receiving any 981 * character after recognition of the XOFF character 982 */ 983 if (termios->c_iflag & IXANY) 984 up->mcr |= UART_MCR_XONANY; 985 else 986 up->mcr &= ~UART_MCR_XONANY; 987 } 988 serial_out(up, UART_MCR, up->mcr); 989 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 990 serial_out(up, UART_EFR, up->efr); 991 serial_out(up, UART_LCR, up->lcr); 992 993 serial_omap_set_mctrl(&up->port, up->port.mctrl); 994 995 spin_unlock_irqrestore(&up->port.lock, flags); 996 pm_runtime_mark_last_busy(up->dev); 997 pm_runtime_put_autosuspend(up->dev); 998 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 999 } 1000 1001 static int serial_omap_set_wake(struct uart_port *port, unsigned int state) 1002 { 1003 struct uart_omap_port *up = to_uart_omap_port(port); 1004 1005 serial_omap_enable_wakeup(up, state); 1006 1007 return 0; 1008 } 1009 1010 static void 1011 serial_omap_pm(struct uart_port *port, unsigned int state, 1012 unsigned int oldstate) 1013 { 1014 struct uart_omap_port *up = to_uart_omap_port(port); 1015 unsigned char efr; 1016 1017 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 1018 1019 pm_runtime_get_sync(up->dev); 1020 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1021 efr = serial_in(up, UART_EFR); 1022 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 1023 serial_out(up, UART_LCR, 0); 1024 1025 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 1026 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1027 serial_out(up, UART_EFR, efr); 1028 serial_out(up, UART_LCR, 0); 1029 1030 if (!device_may_wakeup(up->dev)) { 1031 if (!state) 1032 pm_runtime_forbid(up->dev); 1033 else 1034 pm_runtime_allow(up->dev); 1035 } 1036 1037 pm_runtime_mark_last_busy(up->dev); 1038 pm_runtime_put_autosuspend(up->dev); 1039 } 1040 1041 static void serial_omap_release_port(struct uart_port *port) 1042 { 1043 dev_dbg(port->dev, "serial_omap_release_port+\n"); 1044 } 1045 1046 static int serial_omap_request_port(struct uart_port *port) 1047 { 1048 dev_dbg(port->dev, "serial_omap_request_port+\n"); 1049 return 0; 1050 } 1051 1052 static void serial_omap_config_port(struct uart_port *port, int flags) 1053 { 1054 struct uart_omap_port *up = to_uart_omap_port(port); 1055 1056 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 1057 up->port.line); 1058 up->port.type = PORT_OMAP; 1059 up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW; 1060 } 1061 1062 static int 1063 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 1064 { 1065 /* we don't want the core code to modify any port params */ 1066 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1067 return -EINVAL; 1068 } 1069 1070 static const char * 1071 serial_omap_type(struct uart_port *port) 1072 { 1073 struct uart_omap_port *up = to_uart_omap_port(port); 1074 1075 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1076 return up->name; 1077 } 1078 1079 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1080 1081 static inline void wait_for_xmitr(struct uart_omap_port *up) 1082 { 1083 unsigned int status, tmout = 10000; 1084 1085 /* Wait up to 10ms for the character(s) to be sent. */ 1086 do { 1087 status = serial_in(up, UART_LSR); 1088 1089 if (status & UART_LSR_BI) 1090 up->lsr_break_flag = UART_LSR_BI; 1091 1092 if (--tmout == 0) 1093 break; 1094 udelay(1); 1095 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1096 1097 /* Wait up to 1s for flow control if necessary */ 1098 if (up->port.flags & UPF_CONS_FLOW) { 1099 tmout = 1000000; 1100 for (tmout = 1000000; tmout; tmout--) { 1101 unsigned int msr = serial_in(up, UART_MSR); 1102 1103 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1104 if (msr & UART_MSR_CTS) 1105 break; 1106 1107 udelay(1); 1108 } 1109 } 1110 } 1111 1112 #ifdef CONFIG_CONSOLE_POLL 1113 1114 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1115 { 1116 struct uart_omap_port *up = to_uart_omap_port(port); 1117 1118 pm_runtime_get_sync(up->dev); 1119 wait_for_xmitr(up); 1120 serial_out(up, UART_TX, ch); 1121 pm_runtime_mark_last_busy(up->dev); 1122 pm_runtime_put_autosuspend(up->dev); 1123 } 1124 1125 static int serial_omap_poll_get_char(struct uart_port *port) 1126 { 1127 struct uart_omap_port *up = to_uart_omap_port(port); 1128 unsigned int status; 1129 1130 pm_runtime_get_sync(up->dev); 1131 status = serial_in(up, UART_LSR); 1132 if (!(status & UART_LSR_DR)) { 1133 status = NO_POLL_CHAR; 1134 goto out; 1135 } 1136 1137 status = serial_in(up, UART_RX); 1138 1139 out: 1140 pm_runtime_mark_last_busy(up->dev); 1141 pm_runtime_put_autosuspend(up->dev); 1142 1143 return status; 1144 } 1145 1146 #endif /* CONFIG_CONSOLE_POLL */ 1147 1148 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1149 1150 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS]; 1151 1152 static struct uart_driver serial_omap_reg; 1153 1154 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1155 { 1156 struct uart_omap_port *up = to_uart_omap_port(port); 1157 1158 wait_for_xmitr(up); 1159 serial_out(up, UART_TX, ch); 1160 } 1161 1162 static void 1163 serial_omap_console_write(struct console *co, const char *s, 1164 unsigned int count) 1165 { 1166 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1167 unsigned long flags; 1168 unsigned int ier; 1169 int locked = 1; 1170 1171 pm_runtime_get_sync(up->dev); 1172 1173 local_irq_save(flags); 1174 if (up->port.sysrq) 1175 locked = 0; 1176 else if (oops_in_progress) 1177 locked = spin_trylock(&up->port.lock); 1178 else 1179 spin_lock(&up->port.lock); 1180 1181 /* 1182 * First save the IER then disable the interrupts 1183 */ 1184 ier = serial_in(up, UART_IER); 1185 serial_out(up, UART_IER, 0); 1186 1187 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1188 1189 /* 1190 * Finally, wait for transmitter to become empty 1191 * and restore the IER 1192 */ 1193 wait_for_xmitr(up); 1194 serial_out(up, UART_IER, ier); 1195 /* 1196 * The receive handling will happen properly because the 1197 * receive ready bit will still be set; it is not cleared 1198 * on read. However, modem control will not, we must 1199 * call it if we have saved something in the saved flags 1200 * while processing with interrupts off. 1201 */ 1202 if (up->msr_saved_flags) 1203 check_modem_status(up); 1204 1205 pm_runtime_mark_last_busy(up->dev); 1206 pm_runtime_put_autosuspend(up->dev); 1207 if (locked) 1208 spin_unlock(&up->port.lock); 1209 local_irq_restore(flags); 1210 } 1211 1212 static int __init 1213 serial_omap_console_setup(struct console *co, char *options) 1214 { 1215 struct uart_omap_port *up; 1216 int baud = 115200; 1217 int bits = 8; 1218 int parity = 'n'; 1219 int flow = 'n'; 1220 1221 if (serial_omap_console_ports[co->index] == NULL) 1222 return -ENODEV; 1223 up = serial_omap_console_ports[co->index]; 1224 1225 if (options) 1226 uart_parse_options(options, &baud, &parity, &bits, &flow); 1227 1228 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1229 } 1230 1231 static struct console serial_omap_console = { 1232 .name = OMAP_SERIAL_NAME, 1233 .write = serial_omap_console_write, 1234 .device = uart_console_device, 1235 .setup = serial_omap_console_setup, 1236 .flags = CON_PRINTBUFFER, 1237 .index = -1, 1238 .data = &serial_omap_reg, 1239 }; 1240 1241 static void serial_omap_add_console_port(struct uart_omap_port *up) 1242 { 1243 serial_omap_console_ports[up->port.line] = up; 1244 } 1245 1246 #define OMAP_CONSOLE (&serial_omap_console) 1247 1248 #else 1249 1250 #define OMAP_CONSOLE NULL 1251 1252 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1253 {} 1254 1255 #endif 1256 1257 static struct uart_ops serial_omap_pops = { 1258 .tx_empty = serial_omap_tx_empty, 1259 .set_mctrl = serial_omap_set_mctrl, 1260 .get_mctrl = serial_omap_get_mctrl, 1261 .stop_tx = serial_omap_stop_tx, 1262 .start_tx = serial_omap_start_tx, 1263 .throttle = serial_omap_throttle, 1264 .unthrottle = serial_omap_unthrottle, 1265 .stop_rx = serial_omap_stop_rx, 1266 .enable_ms = serial_omap_enable_ms, 1267 .break_ctl = serial_omap_break_ctl, 1268 .startup = serial_omap_startup, 1269 .shutdown = serial_omap_shutdown, 1270 .set_termios = serial_omap_set_termios, 1271 .pm = serial_omap_pm, 1272 .set_wake = serial_omap_set_wake, 1273 .type = serial_omap_type, 1274 .release_port = serial_omap_release_port, 1275 .request_port = serial_omap_request_port, 1276 .config_port = serial_omap_config_port, 1277 .verify_port = serial_omap_verify_port, 1278 #ifdef CONFIG_CONSOLE_POLL 1279 .poll_put_char = serial_omap_poll_put_char, 1280 .poll_get_char = serial_omap_poll_get_char, 1281 #endif 1282 }; 1283 1284 static struct uart_driver serial_omap_reg = { 1285 .owner = THIS_MODULE, 1286 .driver_name = "OMAP-SERIAL", 1287 .dev_name = OMAP_SERIAL_NAME, 1288 .nr = OMAP_MAX_HSUART_PORTS, 1289 .cons = OMAP_CONSOLE, 1290 }; 1291 1292 #ifdef CONFIG_PM_SLEEP 1293 static int serial_omap_prepare(struct device *dev) 1294 { 1295 struct uart_omap_port *up = dev_get_drvdata(dev); 1296 1297 up->is_suspending = true; 1298 1299 return 0; 1300 } 1301 1302 static void serial_omap_complete(struct device *dev) 1303 { 1304 struct uart_omap_port *up = dev_get_drvdata(dev); 1305 1306 up->is_suspending = false; 1307 } 1308 1309 static int serial_omap_suspend(struct device *dev) 1310 { 1311 struct uart_omap_port *up = dev_get_drvdata(dev); 1312 1313 uart_suspend_port(&serial_omap_reg, &up->port); 1314 flush_work(&up->qos_work); 1315 1316 return 0; 1317 } 1318 1319 static int serial_omap_resume(struct device *dev) 1320 { 1321 struct uart_omap_port *up = dev_get_drvdata(dev); 1322 1323 uart_resume_port(&serial_omap_reg, &up->port); 1324 1325 return 0; 1326 } 1327 #else 1328 #define serial_omap_prepare NULL 1329 #define serial_omap_complete NULL 1330 #endif /* CONFIG_PM_SLEEP */ 1331 1332 static void omap_serial_fill_features_erratas(struct uart_omap_port *up) 1333 { 1334 u32 mvr, scheme; 1335 u16 revision, major, minor; 1336 1337 mvr = serial_in(up, UART_OMAP_MVER); 1338 1339 /* Check revision register scheme */ 1340 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1341 1342 switch (scheme) { 1343 case 0: /* Legacy Scheme: OMAP2/3 */ 1344 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1345 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1346 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1347 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1348 break; 1349 case 1: 1350 /* New Scheme: OMAP4+ */ 1351 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1352 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1353 OMAP_UART_MVR_MAJ_SHIFT; 1354 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1355 break; 1356 default: 1357 dev_warn(up->dev, 1358 "Unknown %s revision, defaulting to highest\n", 1359 up->name); 1360 /* highest possible revision */ 1361 major = 0xff; 1362 minor = 0xff; 1363 } 1364 1365 /* normalize revision for the driver */ 1366 revision = UART_BUILD_REVISION(major, minor); 1367 1368 switch (revision) { 1369 case OMAP_UART_REV_46: 1370 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1371 UART_ERRATA_i291_DMA_FORCEIDLE); 1372 break; 1373 case OMAP_UART_REV_52: 1374 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1375 UART_ERRATA_i291_DMA_FORCEIDLE); 1376 break; 1377 case OMAP_UART_REV_63: 1378 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1379 break; 1380 default: 1381 break; 1382 } 1383 } 1384 1385 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1386 { 1387 struct omap_uart_port_info *omap_up_info; 1388 1389 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1390 if (!omap_up_info) 1391 return NULL; /* out of memory */ 1392 1393 of_property_read_u32(dev->of_node, "clock-frequency", 1394 &omap_up_info->uartclk); 1395 return omap_up_info; 1396 } 1397 1398 static int serial_omap_probe(struct platform_device *pdev) 1399 { 1400 struct uart_omap_port *up; 1401 struct resource *mem, *irq; 1402 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1403 int ret; 1404 1405 if (pdev->dev.of_node) 1406 omap_up_info = of_get_uart_port_info(&pdev->dev); 1407 1408 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1409 if (!mem) { 1410 dev_err(&pdev->dev, "no mem resource?\n"); 1411 return -ENODEV; 1412 } 1413 1414 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1415 if (!irq) { 1416 dev_err(&pdev->dev, "no irq resource?\n"); 1417 return -ENODEV; 1418 } 1419 1420 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), 1421 pdev->dev.driver->name)) { 1422 dev_err(&pdev->dev, "memory region already claimed\n"); 1423 return -EBUSY; 1424 } 1425 1426 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1427 omap_up_info->DTR_present) { 1428 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); 1429 if (ret < 0) 1430 return ret; 1431 ret = gpio_direction_output(omap_up_info->DTR_gpio, 1432 omap_up_info->DTR_inverted); 1433 if (ret < 0) 1434 return ret; 1435 } 1436 1437 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1438 if (!up) 1439 return -ENOMEM; 1440 1441 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1442 omap_up_info->DTR_present) { 1443 up->DTR_gpio = omap_up_info->DTR_gpio; 1444 up->DTR_inverted = omap_up_info->DTR_inverted; 1445 } else 1446 up->DTR_gpio = -EINVAL; 1447 up->DTR_active = 0; 1448 1449 up->dev = &pdev->dev; 1450 up->port.dev = &pdev->dev; 1451 up->port.type = PORT_OMAP; 1452 up->port.iotype = UPIO_MEM; 1453 up->port.irq = irq->start; 1454 1455 up->port.regshift = 2; 1456 up->port.fifosize = 64; 1457 up->port.ops = &serial_omap_pops; 1458 1459 if (pdev->dev.of_node) 1460 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); 1461 else 1462 up->port.line = pdev->id; 1463 1464 if (up->port.line < 0) { 1465 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1466 up->port.line); 1467 ret = -ENODEV; 1468 goto err_port_line; 1469 } 1470 1471 up->pins = devm_pinctrl_get_select_default(&pdev->dev); 1472 if (IS_ERR(up->pins)) { 1473 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n", 1474 up->port.line, PTR_ERR(up->pins)); 1475 up->pins = NULL; 1476 } 1477 1478 sprintf(up->name, "OMAP UART%d", up->port.line); 1479 up->port.mapbase = mem->start; 1480 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1481 resource_size(mem)); 1482 if (!up->port.membase) { 1483 dev_err(&pdev->dev, "can't ioremap UART\n"); 1484 ret = -ENOMEM; 1485 goto err_ioremap; 1486 } 1487 1488 up->port.flags = omap_up_info->flags; 1489 up->port.uartclk = omap_up_info->uartclk; 1490 if (!up->port.uartclk) { 1491 up->port.uartclk = DEFAULT_CLK_SPEED; 1492 dev_warn(&pdev->dev, "No clock speed specified: using default:" 1493 "%d\n", DEFAULT_CLK_SPEED); 1494 } 1495 1496 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1497 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1498 pm_qos_add_request(&up->pm_qos_request, 1499 PM_QOS_CPU_DMA_LATENCY, up->latency); 1500 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1501 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1502 1503 platform_set_drvdata(pdev, up); 1504 pm_runtime_enable(&pdev->dev); 1505 if (omap_up_info->autosuspend_timeout == 0) 1506 omap_up_info->autosuspend_timeout = -1; 1507 device_init_wakeup(up->dev, true); 1508 pm_runtime_use_autosuspend(&pdev->dev); 1509 pm_runtime_set_autosuspend_delay(&pdev->dev, 1510 omap_up_info->autosuspend_timeout); 1511 1512 pm_runtime_irq_safe(&pdev->dev); 1513 pm_runtime_get_sync(&pdev->dev); 1514 1515 omap_serial_fill_features_erratas(up); 1516 1517 ui[up->port.line] = up; 1518 serial_omap_add_console_port(up); 1519 1520 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1521 if (ret != 0) 1522 goto err_add_port; 1523 1524 pm_runtime_mark_last_busy(up->dev); 1525 pm_runtime_put_autosuspend(up->dev); 1526 return 0; 1527 1528 err_add_port: 1529 pm_runtime_put(&pdev->dev); 1530 pm_runtime_disable(&pdev->dev); 1531 err_ioremap: 1532 err_port_line: 1533 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1534 pdev->id, __func__, ret); 1535 return ret; 1536 } 1537 1538 static int serial_omap_remove(struct platform_device *dev) 1539 { 1540 struct uart_omap_port *up = platform_get_drvdata(dev); 1541 1542 pm_runtime_put_sync(up->dev); 1543 pm_runtime_disable(up->dev); 1544 uart_remove_one_port(&serial_omap_reg, &up->port); 1545 pm_qos_remove_request(&up->pm_qos_request); 1546 1547 return 0; 1548 } 1549 1550 /* 1551 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1552 * The access to uart register after MDR1 Access 1553 * causes UART to corrupt data. 1554 * 1555 * Need a delay = 1556 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1557 * give 10 times as much 1558 */ 1559 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1560 { 1561 u8 timeout = 255; 1562 1563 serial_out(up, UART_OMAP_MDR1, mdr1); 1564 udelay(2); 1565 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1566 UART_FCR_CLEAR_RCVR); 1567 /* 1568 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1569 * TX_FIFO_E bit is 1. 1570 */ 1571 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1572 (UART_LSR_THRE | UART_LSR_DR))) { 1573 timeout--; 1574 if (!timeout) { 1575 /* Should *never* happen. we warn and carry on */ 1576 dev_crit(up->dev, "Errata i202: timedout %x\n", 1577 serial_in(up, UART_LSR)); 1578 break; 1579 } 1580 udelay(1); 1581 } 1582 } 1583 1584 #ifdef CONFIG_PM_RUNTIME 1585 static void serial_omap_restore_context(struct uart_omap_port *up) 1586 { 1587 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1588 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1589 else 1590 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1591 1592 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1593 serial_out(up, UART_EFR, UART_EFR_ECB); 1594 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1595 serial_out(up, UART_IER, 0x0); 1596 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1597 serial_out(up, UART_DLL, up->dll); 1598 serial_out(up, UART_DLM, up->dlh); 1599 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1600 serial_out(up, UART_IER, up->ier); 1601 serial_out(up, UART_FCR, up->fcr); 1602 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1603 serial_out(up, UART_MCR, up->mcr); 1604 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1605 serial_out(up, UART_OMAP_SCR, up->scr); 1606 serial_out(up, UART_EFR, up->efr); 1607 serial_out(up, UART_LCR, up->lcr); 1608 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1609 serial_omap_mdr1_errataset(up, up->mdr1); 1610 else 1611 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1612 } 1613 1614 static int serial_omap_runtime_suspend(struct device *dev) 1615 { 1616 struct uart_omap_port *up = dev_get_drvdata(dev); 1617 1618 if (!up) 1619 return -EINVAL; 1620 1621 /* 1622 * When using 'no_console_suspend', the console UART must not be 1623 * suspended. Since driver suspend is managed by runtime suspend, 1624 * preventing runtime suspend (by returning error) will keep device 1625 * active during suspend. 1626 */ 1627 if (up->is_suspending && !console_suspend_enabled && 1628 uart_console(&up->port)) 1629 return -EBUSY; 1630 1631 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1632 1633 if (device_may_wakeup(dev)) { 1634 if (!up->wakeups_enabled) { 1635 serial_omap_enable_wakeup(up, true); 1636 up->wakeups_enabled = true; 1637 } 1638 } else { 1639 if (up->wakeups_enabled) { 1640 serial_omap_enable_wakeup(up, false); 1641 up->wakeups_enabled = false; 1642 } 1643 } 1644 1645 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1646 schedule_work(&up->qos_work); 1647 1648 return 0; 1649 } 1650 1651 static int serial_omap_runtime_resume(struct device *dev) 1652 { 1653 struct uart_omap_port *up = dev_get_drvdata(dev); 1654 1655 int loss_cnt = serial_omap_get_context_loss_count(up); 1656 1657 if (loss_cnt < 0) { 1658 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n", 1659 loss_cnt); 1660 serial_omap_restore_context(up); 1661 } else if (up->context_loss_cnt != loss_cnt) { 1662 serial_omap_restore_context(up); 1663 } 1664 up->latency = up->calc_latency; 1665 schedule_work(&up->qos_work); 1666 1667 return 0; 1668 } 1669 #endif 1670 1671 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1672 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1673 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1674 serial_omap_runtime_resume, NULL) 1675 .prepare = serial_omap_prepare, 1676 .complete = serial_omap_complete, 1677 }; 1678 1679 #if defined(CONFIG_OF) 1680 static const struct of_device_id omap_serial_of_match[] = { 1681 { .compatible = "ti,omap2-uart" }, 1682 { .compatible = "ti,omap3-uart" }, 1683 { .compatible = "ti,omap4-uart" }, 1684 {}, 1685 }; 1686 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1687 #endif 1688 1689 static struct platform_driver serial_omap_driver = { 1690 .probe = serial_omap_probe, 1691 .remove = serial_omap_remove, 1692 .driver = { 1693 .name = DRIVER_NAME, 1694 .pm = &serial_omap_dev_pm_ops, 1695 .of_match_table = of_match_ptr(omap_serial_of_match), 1696 }, 1697 }; 1698 1699 static int __init serial_omap_init(void) 1700 { 1701 int ret; 1702 1703 ret = uart_register_driver(&serial_omap_reg); 1704 if (ret != 0) 1705 return ret; 1706 ret = platform_driver_register(&serial_omap_driver); 1707 if (ret != 0) 1708 uart_unregister_driver(&serial_omap_reg); 1709 return ret; 1710 } 1711 1712 static void __exit serial_omap_exit(void) 1713 { 1714 platform_driver_unregister(&serial_omap_driver); 1715 uart_unregister_driver(&serial_omap_reg); 1716 } 1717 1718 module_init(serial_omap_init); 1719 module_exit(serial_omap_exit); 1720 1721 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1722 MODULE_LICENSE("GPL"); 1723 MODULE_AUTHOR("Texas Instruments Inc"); 1724