1 /* 2 * Driver for OMAP-UART controller. 3 * Based on drivers/serial/8250.c 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Authors: 8 * Govindraj R <govindraj.raja@ti.com> 9 * Thara Gopinath <thara@ti.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * Note: This driver is made separate from 8250 driver as we cannot 17 * over load 8250 driver with omap platform specific configuration for 18 * features like DMA, it makes easier to implement features like DMA and 19 * hardware flow control and software flow control configuration with 20 * this driver as required for the omap-platform. 21 */ 22 23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 24 #define SUPPORT_SYSRQ 25 #endif 26 27 #include <linux/module.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/serial_reg.h> 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 #include <linux/tty.h> 34 #include <linux/tty_flip.h> 35 #include <linux/platform_device.h> 36 #include <linux/io.h> 37 #include <linux/clk.h> 38 #include <linux/serial_core.h> 39 #include <linux/irq.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/of.h> 42 #include <linux/gpio.h> 43 #include <linux/pinctrl/consumer.h> 44 45 #include <plat/omap-serial.h> 46 47 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y)) 48 49 #define OMAP_UART_REV_42 0x0402 50 #define OMAP_UART_REV_46 0x0406 51 #define OMAP_UART_REV_52 0x0502 52 #define OMAP_UART_REV_63 0x0603 53 54 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/ 55 56 /* SCR register bitmasks */ 57 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) 58 59 /* FCR register bitmasks */ 60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6) 61 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK (0x3 << 4) 62 63 /* MVR register bitmasks */ 64 #define OMAP_UART_MVR_SCHEME_SHIFT 30 65 66 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0 67 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4 68 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f 69 70 #define OMAP_UART_MVR_MAJ_MASK 0x700 71 #define OMAP_UART_MVR_MAJ_SHIFT 8 72 #define OMAP_UART_MVR_MIN_MASK 0x3f 73 74 struct uart_omap_port { 75 struct uart_port port; 76 struct uart_omap_dma uart_dma; 77 struct device *dev; 78 79 unsigned char ier; 80 unsigned char lcr; 81 unsigned char mcr; 82 unsigned char fcr; 83 unsigned char efr; 84 unsigned char dll; 85 unsigned char dlh; 86 unsigned char mdr1; 87 unsigned char scr; 88 89 int use_dma; 90 /* 91 * Some bits in registers are cleared on a read, so they must 92 * be saved whenever the register is read but the bits will not 93 * be immediately processed. 94 */ 95 unsigned int lsr_break_flag; 96 unsigned char msr_saved_flags; 97 char name[20]; 98 unsigned long port_activity; 99 u32 context_loss_cnt; 100 u32 errata; 101 u8 wakeups_enabled; 102 unsigned int irq_pending:1; 103 104 int DTR_gpio; 105 int DTR_inverted; 106 int DTR_active; 107 108 struct pm_qos_request pm_qos_request; 109 u32 latency; 110 u32 calc_latency; 111 struct work_struct qos_work; 112 struct pinctrl *pins; 113 }; 114 115 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port))) 116 117 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS]; 118 119 /* Forward declaration of functions */ 120 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1); 121 122 static struct workqueue_struct *serial_omap_uart_wq; 123 124 static inline unsigned int serial_in(struct uart_omap_port *up, int offset) 125 { 126 offset <<= up->port.regshift; 127 return readw(up->port.membase + offset); 128 } 129 130 static inline void serial_out(struct uart_omap_port *up, int offset, int value) 131 { 132 offset <<= up->port.regshift; 133 writew(value, up->port.membase + offset); 134 } 135 136 static inline void serial_omap_clear_fifos(struct uart_omap_port *up) 137 { 138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 139 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 140 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 141 serial_out(up, UART_FCR, 0); 142 } 143 144 static int serial_omap_get_context_loss_count(struct uart_omap_port *up) 145 { 146 struct omap_uart_port_info *pdata = up->dev->platform_data; 147 148 if (!pdata || !pdata->get_context_loss_count) 149 return 0; 150 151 return pdata->get_context_loss_count(up->dev); 152 } 153 154 static void serial_omap_set_forceidle(struct uart_omap_port *up) 155 { 156 struct omap_uart_port_info *pdata = up->dev->platform_data; 157 158 if (!pdata || !pdata->set_forceidle) 159 return; 160 161 pdata->set_forceidle(up->dev); 162 } 163 164 static void serial_omap_set_noidle(struct uart_omap_port *up) 165 { 166 struct omap_uart_port_info *pdata = up->dev->platform_data; 167 168 if (!pdata || !pdata->set_noidle) 169 return; 170 171 pdata->set_noidle(up->dev); 172 } 173 174 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable) 175 { 176 struct omap_uart_port_info *pdata = up->dev->platform_data; 177 178 if (!pdata || !pdata->enable_wakeup) 179 return; 180 181 pdata->enable_wakeup(up->dev, enable); 182 } 183 184 /* 185 * serial_omap_get_divisor - calculate divisor value 186 * @port: uart port info 187 * @baud: baudrate for which divisor needs to be calculated. 188 * 189 * We have written our own function to get the divisor so as to support 190 * 13x mode. 3Mbps Baudrate as an different divisor. 191 * Reference OMAP TRM Chapter 17: 192 * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates 193 * referring to oversampling - divisor value 194 * baudrate 460,800 to 3,686,400 all have divisor 13 195 * except 3,000,000 which has divisor value 16 196 */ 197 static unsigned int 198 serial_omap_get_divisor(struct uart_port *port, unsigned int baud) 199 { 200 unsigned int divisor; 201 202 if (baud > OMAP_MODE13X_SPEED && baud != 3000000) 203 divisor = 13; 204 else 205 divisor = 16; 206 return port->uartclk/(baud * divisor); 207 } 208 209 static void serial_omap_enable_ms(struct uart_port *port) 210 { 211 struct uart_omap_port *up = to_uart_omap_port(port); 212 213 dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line); 214 215 pm_runtime_get_sync(up->dev); 216 up->ier |= UART_IER_MSI; 217 serial_out(up, UART_IER, up->ier); 218 pm_runtime_mark_last_busy(up->dev); 219 pm_runtime_put_autosuspend(up->dev); 220 } 221 222 static void serial_omap_stop_tx(struct uart_port *port) 223 { 224 struct uart_omap_port *up = to_uart_omap_port(port); 225 226 pm_runtime_get_sync(up->dev); 227 if (up->ier & UART_IER_THRI) { 228 up->ier &= ~UART_IER_THRI; 229 serial_out(up, UART_IER, up->ier); 230 } 231 232 serial_omap_set_forceidle(up); 233 234 pm_runtime_mark_last_busy(up->dev); 235 pm_runtime_put_autosuspend(up->dev); 236 } 237 238 static void serial_omap_stop_rx(struct uart_port *port) 239 { 240 struct uart_omap_port *up = to_uart_omap_port(port); 241 242 pm_runtime_get_sync(up->dev); 243 up->ier &= ~UART_IER_RLSI; 244 up->port.read_status_mask &= ~UART_LSR_DR; 245 serial_out(up, UART_IER, up->ier); 246 pm_runtime_mark_last_busy(up->dev); 247 pm_runtime_put_autosuspend(up->dev); 248 } 249 250 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr) 251 { 252 struct circ_buf *xmit = &up->port.state->xmit; 253 int count; 254 255 if (!(lsr & UART_LSR_THRE)) 256 return; 257 258 if (up->port.x_char) { 259 serial_out(up, UART_TX, up->port.x_char); 260 up->port.icount.tx++; 261 up->port.x_char = 0; 262 return; 263 } 264 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 265 serial_omap_stop_tx(&up->port); 266 return; 267 } 268 count = up->port.fifosize / 4; 269 do { 270 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 271 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 272 up->port.icount.tx++; 273 if (uart_circ_empty(xmit)) 274 break; 275 } while (--count > 0); 276 277 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) { 278 spin_unlock(&up->port.lock); 279 uart_write_wakeup(&up->port); 280 spin_lock(&up->port.lock); 281 } 282 283 if (uart_circ_empty(xmit)) 284 serial_omap_stop_tx(&up->port); 285 } 286 287 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up) 288 { 289 if (!(up->ier & UART_IER_THRI)) { 290 up->ier |= UART_IER_THRI; 291 serial_out(up, UART_IER, up->ier); 292 } 293 } 294 295 static void serial_omap_start_tx(struct uart_port *port) 296 { 297 struct uart_omap_port *up = to_uart_omap_port(port); 298 299 pm_runtime_get_sync(up->dev); 300 serial_omap_enable_ier_thri(up); 301 serial_omap_set_noidle(up); 302 pm_runtime_mark_last_busy(up->dev); 303 pm_runtime_put_autosuspend(up->dev); 304 } 305 306 static unsigned int check_modem_status(struct uart_omap_port *up) 307 { 308 unsigned int status; 309 310 status = serial_in(up, UART_MSR); 311 status |= up->msr_saved_flags; 312 up->msr_saved_flags = 0; 313 if ((status & UART_MSR_ANY_DELTA) == 0) 314 return status; 315 316 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 317 up->port.state != NULL) { 318 if (status & UART_MSR_TERI) 319 up->port.icount.rng++; 320 if (status & UART_MSR_DDSR) 321 up->port.icount.dsr++; 322 if (status & UART_MSR_DDCD) 323 uart_handle_dcd_change 324 (&up->port, status & UART_MSR_DCD); 325 if (status & UART_MSR_DCTS) 326 uart_handle_cts_change 327 (&up->port, status & UART_MSR_CTS); 328 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 329 } 330 331 return status; 332 } 333 334 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr) 335 { 336 unsigned int flag; 337 unsigned char ch = 0; 338 339 if (likely(lsr & UART_LSR_DR)) 340 ch = serial_in(up, UART_RX); 341 342 up->port.icount.rx++; 343 flag = TTY_NORMAL; 344 345 if (lsr & UART_LSR_BI) { 346 flag = TTY_BREAK; 347 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 348 up->port.icount.brk++; 349 /* 350 * We do the SysRQ and SAK checking 351 * here because otherwise the break 352 * may get masked by ignore_status_mask 353 * or read_status_mask. 354 */ 355 if (uart_handle_break(&up->port)) 356 return; 357 358 } 359 360 if (lsr & UART_LSR_PE) { 361 flag = TTY_PARITY; 362 up->port.icount.parity++; 363 } 364 365 if (lsr & UART_LSR_FE) { 366 flag = TTY_FRAME; 367 up->port.icount.frame++; 368 } 369 370 if (lsr & UART_LSR_OE) 371 up->port.icount.overrun++; 372 373 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 374 if (up->port.line == up->port.cons->index) { 375 /* Recover the break flag from console xmit */ 376 lsr |= up->lsr_break_flag; 377 } 378 #endif 379 uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag); 380 } 381 382 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr) 383 { 384 unsigned char ch = 0; 385 unsigned int flag; 386 387 if (!(lsr & UART_LSR_DR)) 388 return; 389 390 ch = serial_in(up, UART_RX); 391 flag = TTY_NORMAL; 392 up->port.icount.rx++; 393 394 if (uart_handle_sysrq_char(&up->port, ch)) 395 return; 396 397 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag); 398 } 399 400 /** 401 * serial_omap_irq() - This handles the interrupt from one port 402 * @irq: uart port irq number 403 * @dev_id: uart port info 404 */ 405 static irqreturn_t serial_omap_irq(int irq, void *dev_id) 406 { 407 struct uart_omap_port *up = dev_id; 408 struct tty_struct *tty = up->port.state->port.tty; 409 unsigned int iir, lsr; 410 unsigned int type; 411 irqreturn_t ret = IRQ_NONE; 412 int max_count = 256; 413 414 spin_lock(&up->port.lock); 415 pm_runtime_get_sync(up->dev); 416 417 do { 418 iir = serial_in(up, UART_IIR); 419 if (iir & UART_IIR_NO_INT) 420 break; 421 422 ret = IRQ_HANDLED; 423 lsr = serial_in(up, UART_LSR); 424 425 /* extract IRQ type from IIR register */ 426 type = iir & 0x3e; 427 428 switch (type) { 429 case UART_IIR_MSI: 430 check_modem_status(up); 431 break; 432 case UART_IIR_THRI: 433 transmit_chars(up, lsr); 434 break; 435 case UART_IIR_RX_TIMEOUT: 436 /* FALLTHROUGH */ 437 case UART_IIR_RDI: 438 serial_omap_rdi(up, lsr); 439 break; 440 case UART_IIR_RLSI: 441 serial_omap_rlsi(up, lsr); 442 break; 443 case UART_IIR_CTS_RTS_DSR: 444 /* simply try again */ 445 break; 446 case UART_IIR_XOFF: 447 /* FALLTHROUGH */ 448 default: 449 break; 450 } 451 } while (!(iir & UART_IIR_NO_INT) && max_count--); 452 453 spin_unlock(&up->port.lock); 454 455 tty_flip_buffer_push(tty); 456 457 pm_runtime_mark_last_busy(up->dev); 458 pm_runtime_put_autosuspend(up->dev); 459 up->port_activity = jiffies; 460 461 return ret; 462 } 463 464 static unsigned int serial_omap_tx_empty(struct uart_port *port) 465 { 466 struct uart_omap_port *up = to_uart_omap_port(port); 467 unsigned long flags = 0; 468 unsigned int ret = 0; 469 470 pm_runtime_get_sync(up->dev); 471 dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line); 472 spin_lock_irqsave(&up->port.lock, flags); 473 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; 474 spin_unlock_irqrestore(&up->port.lock, flags); 475 pm_runtime_mark_last_busy(up->dev); 476 pm_runtime_put_autosuspend(up->dev); 477 return ret; 478 } 479 480 static unsigned int serial_omap_get_mctrl(struct uart_port *port) 481 { 482 struct uart_omap_port *up = to_uart_omap_port(port); 483 unsigned int status; 484 unsigned int ret = 0; 485 486 pm_runtime_get_sync(up->dev); 487 status = check_modem_status(up); 488 pm_runtime_mark_last_busy(up->dev); 489 pm_runtime_put_autosuspend(up->dev); 490 491 dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line); 492 493 if (status & UART_MSR_DCD) 494 ret |= TIOCM_CAR; 495 if (status & UART_MSR_RI) 496 ret |= TIOCM_RNG; 497 if (status & UART_MSR_DSR) 498 ret |= TIOCM_DSR; 499 if (status & UART_MSR_CTS) 500 ret |= TIOCM_CTS; 501 return ret; 502 } 503 504 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) 505 { 506 struct uart_omap_port *up = to_uart_omap_port(port); 507 unsigned char mcr = 0; 508 509 dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line); 510 if (mctrl & TIOCM_RTS) 511 mcr |= UART_MCR_RTS; 512 if (mctrl & TIOCM_DTR) 513 mcr |= UART_MCR_DTR; 514 if (mctrl & TIOCM_OUT1) 515 mcr |= UART_MCR_OUT1; 516 if (mctrl & TIOCM_OUT2) 517 mcr |= UART_MCR_OUT2; 518 if (mctrl & TIOCM_LOOP) 519 mcr |= UART_MCR_LOOP; 520 521 pm_runtime_get_sync(up->dev); 522 up->mcr = serial_in(up, UART_MCR); 523 up->mcr |= mcr; 524 serial_out(up, UART_MCR, up->mcr); 525 pm_runtime_mark_last_busy(up->dev); 526 pm_runtime_put_autosuspend(up->dev); 527 528 if (gpio_is_valid(up->DTR_gpio) && 529 !!(mctrl & TIOCM_DTR) != up->DTR_active) { 530 up->DTR_active = !up->DTR_active; 531 if (gpio_cansleep(up->DTR_gpio)) 532 schedule_work(&up->qos_work); 533 else 534 gpio_set_value(up->DTR_gpio, 535 up->DTR_active != up->DTR_inverted); 536 } 537 } 538 539 static void serial_omap_break_ctl(struct uart_port *port, int break_state) 540 { 541 struct uart_omap_port *up = to_uart_omap_port(port); 542 unsigned long flags = 0; 543 544 dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line); 545 pm_runtime_get_sync(up->dev); 546 spin_lock_irqsave(&up->port.lock, flags); 547 if (break_state == -1) 548 up->lcr |= UART_LCR_SBC; 549 else 550 up->lcr &= ~UART_LCR_SBC; 551 serial_out(up, UART_LCR, up->lcr); 552 spin_unlock_irqrestore(&up->port.lock, flags); 553 pm_runtime_mark_last_busy(up->dev); 554 pm_runtime_put_autosuspend(up->dev); 555 } 556 557 static int serial_omap_startup(struct uart_port *port) 558 { 559 struct uart_omap_port *up = to_uart_omap_port(port); 560 unsigned long flags = 0; 561 int retval; 562 563 /* 564 * Allocate the IRQ 565 */ 566 retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, 567 up->name, up); 568 if (retval) 569 return retval; 570 571 dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line); 572 573 pm_runtime_get_sync(up->dev); 574 /* 575 * Clear the FIFO buffers and disable them. 576 * (they will be reenabled in set_termios()) 577 */ 578 serial_omap_clear_fifos(up); 579 /* For Hardware flow control */ 580 serial_out(up, UART_MCR, UART_MCR_RTS); 581 582 /* 583 * Clear the interrupt registers. 584 */ 585 (void) serial_in(up, UART_LSR); 586 if (serial_in(up, UART_LSR) & UART_LSR_DR) 587 (void) serial_in(up, UART_RX); 588 (void) serial_in(up, UART_IIR); 589 (void) serial_in(up, UART_MSR); 590 591 /* 592 * Now, initialize the UART 593 */ 594 serial_out(up, UART_LCR, UART_LCR_WLEN8); 595 spin_lock_irqsave(&up->port.lock, flags); 596 /* 597 * Most PC uarts need OUT2 raised to enable interrupts. 598 */ 599 up->port.mctrl |= TIOCM_OUT2; 600 serial_omap_set_mctrl(&up->port, up->port.mctrl); 601 spin_unlock_irqrestore(&up->port.lock, flags); 602 603 up->msr_saved_flags = 0; 604 /* 605 * Finally, enable interrupts. Note: Modem status interrupts 606 * are set via set_termios(), which will be occurring imminently 607 * anyway, so we don't enable them here. 608 */ 609 up->ier = UART_IER_RLSI | UART_IER_RDI; 610 serial_out(up, UART_IER, up->ier); 611 612 /* Enable module level wake up */ 613 serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP); 614 615 pm_runtime_mark_last_busy(up->dev); 616 pm_runtime_put_autosuspend(up->dev); 617 up->port_activity = jiffies; 618 return 0; 619 } 620 621 static void serial_omap_shutdown(struct uart_port *port) 622 { 623 struct uart_omap_port *up = to_uart_omap_port(port); 624 unsigned long flags = 0; 625 626 dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line); 627 628 pm_runtime_get_sync(up->dev); 629 /* 630 * Disable interrupts from this port 631 */ 632 up->ier = 0; 633 serial_out(up, UART_IER, 0); 634 635 spin_lock_irqsave(&up->port.lock, flags); 636 up->port.mctrl &= ~TIOCM_OUT2; 637 serial_omap_set_mctrl(&up->port, up->port.mctrl); 638 spin_unlock_irqrestore(&up->port.lock, flags); 639 640 /* 641 * Disable break condition and FIFOs 642 */ 643 serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); 644 serial_omap_clear_fifos(up); 645 646 /* 647 * Read data port to reset things, and then free the irq 648 */ 649 if (serial_in(up, UART_LSR) & UART_LSR_DR) 650 (void) serial_in(up, UART_RX); 651 652 pm_runtime_mark_last_busy(up->dev); 653 pm_runtime_put_autosuspend(up->dev); 654 free_irq(up->port.irq, up); 655 } 656 657 static inline void 658 serial_omap_configure_xonxoff 659 (struct uart_omap_port *up, struct ktermios *termios) 660 { 661 up->lcr = serial_in(up, UART_LCR); 662 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 663 up->efr = serial_in(up, UART_EFR); 664 serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB); 665 666 serial_out(up, UART_XON1, termios->c_cc[VSTART]); 667 serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]); 668 669 /* clear SW control mode bits */ 670 up->efr &= OMAP_UART_SW_CLR; 671 672 /* 673 * IXON Flag: 674 * Enable XON/XOFF flow control on output. 675 * Transmit XON1, XOFF1 676 */ 677 if (termios->c_iflag & IXON) 678 up->efr |= OMAP_UART_SW_TX; 679 680 /* 681 * IXOFF Flag: 682 * Enable XON/XOFF flow control on input. 683 * Receiver compares XON1, XOFF1. 684 */ 685 if (termios->c_iflag & IXOFF) 686 up->efr |= OMAP_UART_SW_RX; 687 688 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 689 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 690 691 up->mcr = serial_in(up, UART_MCR); 692 693 /* 694 * IXANY Flag: 695 * Enable any character to restart output. 696 * Operation resumes after receiving any 697 * character after recognition of the XOFF character 698 */ 699 if (termios->c_iflag & IXANY) 700 up->mcr |= UART_MCR_XONANY; 701 702 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 703 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 704 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 705 /* Enable special char function UARTi.EFR_REG[5] and 706 * load the new software flow control mode IXON or IXOFF 707 * and restore the UARTi.EFR_REG[4] ENHANCED_EN value. 708 */ 709 serial_out(up, UART_EFR, up->efr | UART_EFR_SCD); 710 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 711 712 serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR); 713 serial_out(up, UART_LCR, up->lcr); 714 } 715 716 static void serial_omap_uart_qos_work(struct work_struct *work) 717 { 718 struct uart_omap_port *up = container_of(work, struct uart_omap_port, 719 qos_work); 720 721 pm_qos_update_request(&up->pm_qos_request, up->latency); 722 if (gpio_is_valid(up->DTR_gpio)) 723 gpio_set_value_cansleep(up->DTR_gpio, 724 up->DTR_active != up->DTR_inverted); 725 } 726 727 static void 728 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, 729 struct ktermios *old) 730 { 731 struct uart_omap_port *up = to_uart_omap_port(port); 732 unsigned char cval = 0; 733 unsigned char efr = 0; 734 unsigned long flags = 0; 735 unsigned int baud, quot; 736 737 switch (termios->c_cflag & CSIZE) { 738 case CS5: 739 cval = UART_LCR_WLEN5; 740 break; 741 case CS6: 742 cval = UART_LCR_WLEN6; 743 break; 744 case CS7: 745 cval = UART_LCR_WLEN7; 746 break; 747 default: 748 case CS8: 749 cval = UART_LCR_WLEN8; 750 break; 751 } 752 753 if (termios->c_cflag & CSTOPB) 754 cval |= UART_LCR_STOP; 755 if (termios->c_cflag & PARENB) 756 cval |= UART_LCR_PARITY; 757 if (!(termios->c_cflag & PARODD)) 758 cval |= UART_LCR_EPAR; 759 760 /* 761 * Ask the core to calculate the divisor for us. 762 */ 763 764 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); 765 quot = serial_omap_get_divisor(port, baud); 766 767 /* calculate wakeup latency constraint */ 768 up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8); 769 up->latency = up->calc_latency; 770 schedule_work(&up->qos_work); 771 772 up->dll = quot & 0xff; 773 up->dlh = quot >> 8; 774 up->mdr1 = UART_OMAP_MDR1_DISABLE; 775 776 up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | 777 UART_FCR_ENABLE_FIFO; 778 779 /* 780 * Ok, we're now changing the port state. Do it with 781 * interrupts disabled. 782 */ 783 pm_runtime_get_sync(up->dev); 784 spin_lock_irqsave(&up->port.lock, flags); 785 786 /* 787 * Update the per-port timeout. 788 */ 789 uart_update_timeout(port, termios->c_cflag, baud); 790 791 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 792 if (termios->c_iflag & INPCK) 793 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; 794 if (termios->c_iflag & (BRKINT | PARMRK)) 795 up->port.read_status_mask |= UART_LSR_BI; 796 797 /* 798 * Characters to ignore 799 */ 800 up->port.ignore_status_mask = 0; 801 if (termios->c_iflag & IGNPAR) 802 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 803 if (termios->c_iflag & IGNBRK) { 804 up->port.ignore_status_mask |= UART_LSR_BI; 805 /* 806 * If we're ignoring parity and break indicators, 807 * ignore overruns too (for real raw support). 808 */ 809 if (termios->c_iflag & IGNPAR) 810 up->port.ignore_status_mask |= UART_LSR_OE; 811 } 812 813 /* 814 * ignore all characters if CREAD is not set 815 */ 816 if ((termios->c_cflag & CREAD) == 0) 817 up->port.ignore_status_mask |= UART_LSR_DR; 818 819 /* 820 * Modem status interrupts 821 */ 822 up->ier &= ~UART_IER_MSI; 823 if (UART_ENABLE_MS(&up->port, termios->c_cflag)) 824 up->ier |= UART_IER_MSI; 825 serial_out(up, UART_IER, up->ier); 826 serial_out(up, UART_LCR, cval); /* reset DLAB */ 827 up->lcr = cval; 828 up->scr = OMAP_UART_SCR_TX_EMPTY; 829 830 /* FIFOs and DMA Settings */ 831 832 /* FCR can be changed only when the 833 * baud clock is not running 834 * DLL_REG and DLH_REG set to 0. 835 */ 836 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 837 serial_out(up, UART_DLL, 0); 838 serial_out(up, UART_DLM, 0); 839 serial_out(up, UART_LCR, 0); 840 841 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 842 843 up->efr = serial_in(up, UART_EFR); 844 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 845 846 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 847 up->mcr = serial_in(up, UART_MCR); 848 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 849 /* FIFO ENABLE, DMA MODE */ 850 851 up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; 852 853 /* Set receive FIFO threshold to 16 characters and 854 * transmit FIFO threshold to 16 spaces 855 */ 856 up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK; 857 up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK; 858 up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 | 859 UART_FCR_ENABLE_FIFO; 860 861 serial_out(up, UART_FCR, up->fcr); 862 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 863 864 serial_out(up, UART_OMAP_SCR, up->scr); 865 866 serial_out(up, UART_EFR, up->efr); 867 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 868 serial_out(up, UART_MCR, up->mcr); 869 870 /* Protocol, Baud Rate, and Interrupt Settings */ 871 872 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 873 serial_omap_mdr1_errataset(up, up->mdr1); 874 else 875 serial_out(up, UART_OMAP_MDR1, up->mdr1); 876 877 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 878 879 up->efr = serial_in(up, UART_EFR); 880 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 881 882 serial_out(up, UART_LCR, 0); 883 serial_out(up, UART_IER, 0); 884 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 885 886 serial_out(up, UART_DLL, up->dll); /* LS of divisor */ 887 serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ 888 889 serial_out(up, UART_LCR, 0); 890 serial_out(up, UART_IER, up->ier); 891 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 892 893 serial_out(up, UART_EFR, up->efr); 894 serial_out(up, UART_LCR, cval); 895 896 if (baud > 230400 && baud != 3000000) 897 up->mdr1 = UART_OMAP_MDR1_13X_MODE; 898 else 899 up->mdr1 = UART_OMAP_MDR1_16X_MODE; 900 901 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 902 serial_omap_mdr1_errataset(up, up->mdr1); 903 else 904 serial_out(up, UART_OMAP_MDR1, up->mdr1); 905 906 /* Hardware Flow Control Configuration */ 907 908 if (termios->c_cflag & CRTSCTS) { 909 efr |= (UART_EFR_CTS | UART_EFR_RTS); 910 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 911 912 up->mcr = serial_in(up, UART_MCR); 913 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); 914 915 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 916 up->efr = serial_in(up, UART_EFR); 917 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); 918 919 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); 920 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */ 921 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 922 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS); 923 serial_out(up, UART_LCR, cval); 924 } 925 926 serial_omap_set_mctrl(&up->port, up->port.mctrl); 927 /* Software Flow Control Configuration */ 928 serial_omap_configure_xonxoff(up, termios); 929 930 spin_unlock_irqrestore(&up->port.lock, flags); 931 pm_runtime_mark_last_busy(up->dev); 932 pm_runtime_put_autosuspend(up->dev); 933 dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line); 934 } 935 936 static int serial_omap_set_wake(struct uart_port *port, unsigned int state) 937 { 938 struct uart_omap_port *up = to_uart_omap_port(port); 939 940 serial_omap_enable_wakeup(up, state); 941 942 return 0; 943 } 944 945 static void 946 serial_omap_pm(struct uart_port *port, unsigned int state, 947 unsigned int oldstate) 948 { 949 struct uart_omap_port *up = to_uart_omap_port(port); 950 unsigned char efr; 951 952 dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line); 953 954 pm_runtime_get_sync(up->dev); 955 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 956 efr = serial_in(up, UART_EFR); 957 serial_out(up, UART_EFR, efr | UART_EFR_ECB); 958 serial_out(up, UART_LCR, 0); 959 960 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); 961 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 962 serial_out(up, UART_EFR, efr); 963 serial_out(up, UART_LCR, 0); 964 965 if (!device_may_wakeup(up->dev)) { 966 if (!state) 967 pm_runtime_forbid(up->dev); 968 else 969 pm_runtime_allow(up->dev); 970 } 971 972 pm_runtime_mark_last_busy(up->dev); 973 pm_runtime_put_autosuspend(up->dev); 974 } 975 976 static void serial_omap_release_port(struct uart_port *port) 977 { 978 dev_dbg(port->dev, "serial_omap_release_port+\n"); 979 } 980 981 static int serial_omap_request_port(struct uart_port *port) 982 { 983 dev_dbg(port->dev, "serial_omap_request_port+\n"); 984 return 0; 985 } 986 987 static void serial_omap_config_port(struct uart_port *port, int flags) 988 { 989 struct uart_omap_port *up = to_uart_omap_port(port); 990 991 dev_dbg(up->port.dev, "serial_omap_config_port+%d\n", 992 up->port.line); 993 up->port.type = PORT_OMAP; 994 } 995 996 static int 997 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser) 998 { 999 /* we don't want the core code to modify any port params */ 1000 dev_dbg(port->dev, "serial_omap_verify_port+\n"); 1001 return -EINVAL; 1002 } 1003 1004 static const char * 1005 serial_omap_type(struct uart_port *port) 1006 { 1007 struct uart_omap_port *up = to_uart_omap_port(port); 1008 1009 dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line); 1010 return up->name; 1011 } 1012 1013 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 1014 1015 static inline void wait_for_xmitr(struct uart_omap_port *up) 1016 { 1017 unsigned int status, tmout = 10000; 1018 1019 /* Wait up to 10ms for the character(s) to be sent. */ 1020 do { 1021 status = serial_in(up, UART_LSR); 1022 1023 if (status & UART_LSR_BI) 1024 up->lsr_break_flag = UART_LSR_BI; 1025 1026 if (--tmout == 0) 1027 break; 1028 udelay(1); 1029 } while ((status & BOTH_EMPTY) != BOTH_EMPTY); 1030 1031 /* Wait up to 1s for flow control if necessary */ 1032 if (up->port.flags & UPF_CONS_FLOW) { 1033 tmout = 1000000; 1034 for (tmout = 1000000; tmout; tmout--) { 1035 unsigned int msr = serial_in(up, UART_MSR); 1036 1037 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 1038 if (msr & UART_MSR_CTS) 1039 break; 1040 1041 udelay(1); 1042 } 1043 } 1044 } 1045 1046 #ifdef CONFIG_CONSOLE_POLL 1047 1048 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) 1049 { 1050 struct uart_omap_port *up = to_uart_omap_port(port); 1051 1052 pm_runtime_get_sync(up->dev); 1053 wait_for_xmitr(up); 1054 serial_out(up, UART_TX, ch); 1055 pm_runtime_mark_last_busy(up->dev); 1056 pm_runtime_put_autosuspend(up->dev); 1057 } 1058 1059 static int serial_omap_poll_get_char(struct uart_port *port) 1060 { 1061 struct uart_omap_port *up = to_uart_omap_port(port); 1062 unsigned int status; 1063 1064 pm_runtime_get_sync(up->dev); 1065 status = serial_in(up, UART_LSR); 1066 if (!(status & UART_LSR_DR)) { 1067 status = NO_POLL_CHAR; 1068 goto out; 1069 } 1070 1071 status = serial_in(up, UART_RX); 1072 1073 out: 1074 pm_runtime_mark_last_busy(up->dev); 1075 pm_runtime_put_autosuspend(up->dev); 1076 1077 return status; 1078 } 1079 1080 #endif /* CONFIG_CONSOLE_POLL */ 1081 1082 #ifdef CONFIG_SERIAL_OMAP_CONSOLE 1083 1084 static struct uart_omap_port *serial_omap_console_ports[4]; 1085 1086 static struct uart_driver serial_omap_reg; 1087 1088 static void serial_omap_console_putchar(struct uart_port *port, int ch) 1089 { 1090 struct uart_omap_port *up = to_uart_omap_port(port); 1091 1092 wait_for_xmitr(up); 1093 serial_out(up, UART_TX, ch); 1094 } 1095 1096 static void 1097 serial_omap_console_write(struct console *co, const char *s, 1098 unsigned int count) 1099 { 1100 struct uart_omap_port *up = serial_omap_console_ports[co->index]; 1101 unsigned long flags; 1102 unsigned int ier; 1103 int locked = 1; 1104 1105 pm_runtime_get_sync(up->dev); 1106 1107 local_irq_save(flags); 1108 if (up->port.sysrq) 1109 locked = 0; 1110 else if (oops_in_progress) 1111 locked = spin_trylock(&up->port.lock); 1112 else 1113 spin_lock(&up->port.lock); 1114 1115 /* 1116 * First save the IER then disable the interrupts 1117 */ 1118 ier = serial_in(up, UART_IER); 1119 serial_out(up, UART_IER, 0); 1120 1121 uart_console_write(&up->port, s, count, serial_omap_console_putchar); 1122 1123 /* 1124 * Finally, wait for transmitter to become empty 1125 * and restore the IER 1126 */ 1127 wait_for_xmitr(up); 1128 serial_out(up, UART_IER, ier); 1129 /* 1130 * The receive handling will happen properly because the 1131 * receive ready bit will still be set; it is not cleared 1132 * on read. However, modem control will not, we must 1133 * call it if we have saved something in the saved flags 1134 * while processing with interrupts off. 1135 */ 1136 if (up->msr_saved_flags) 1137 check_modem_status(up); 1138 1139 pm_runtime_mark_last_busy(up->dev); 1140 pm_runtime_put_autosuspend(up->dev); 1141 if (locked) 1142 spin_unlock(&up->port.lock); 1143 local_irq_restore(flags); 1144 } 1145 1146 static int __init 1147 serial_omap_console_setup(struct console *co, char *options) 1148 { 1149 struct uart_omap_port *up; 1150 int baud = 115200; 1151 int bits = 8; 1152 int parity = 'n'; 1153 int flow = 'n'; 1154 1155 if (serial_omap_console_ports[co->index] == NULL) 1156 return -ENODEV; 1157 up = serial_omap_console_ports[co->index]; 1158 1159 if (options) 1160 uart_parse_options(options, &baud, &parity, &bits, &flow); 1161 1162 return uart_set_options(&up->port, co, baud, parity, bits, flow); 1163 } 1164 1165 static struct console serial_omap_console = { 1166 .name = OMAP_SERIAL_NAME, 1167 .write = serial_omap_console_write, 1168 .device = uart_console_device, 1169 .setup = serial_omap_console_setup, 1170 .flags = CON_PRINTBUFFER, 1171 .index = -1, 1172 .data = &serial_omap_reg, 1173 }; 1174 1175 static void serial_omap_add_console_port(struct uart_omap_port *up) 1176 { 1177 serial_omap_console_ports[up->port.line] = up; 1178 } 1179 1180 #define OMAP_CONSOLE (&serial_omap_console) 1181 1182 #else 1183 1184 #define OMAP_CONSOLE NULL 1185 1186 static inline void serial_omap_add_console_port(struct uart_omap_port *up) 1187 {} 1188 1189 #endif 1190 1191 static struct uart_ops serial_omap_pops = { 1192 .tx_empty = serial_omap_tx_empty, 1193 .set_mctrl = serial_omap_set_mctrl, 1194 .get_mctrl = serial_omap_get_mctrl, 1195 .stop_tx = serial_omap_stop_tx, 1196 .start_tx = serial_omap_start_tx, 1197 .stop_rx = serial_omap_stop_rx, 1198 .enable_ms = serial_omap_enable_ms, 1199 .break_ctl = serial_omap_break_ctl, 1200 .startup = serial_omap_startup, 1201 .shutdown = serial_omap_shutdown, 1202 .set_termios = serial_omap_set_termios, 1203 .pm = serial_omap_pm, 1204 .set_wake = serial_omap_set_wake, 1205 .type = serial_omap_type, 1206 .release_port = serial_omap_release_port, 1207 .request_port = serial_omap_request_port, 1208 .config_port = serial_omap_config_port, 1209 .verify_port = serial_omap_verify_port, 1210 #ifdef CONFIG_CONSOLE_POLL 1211 .poll_put_char = serial_omap_poll_put_char, 1212 .poll_get_char = serial_omap_poll_get_char, 1213 #endif 1214 }; 1215 1216 static struct uart_driver serial_omap_reg = { 1217 .owner = THIS_MODULE, 1218 .driver_name = "OMAP-SERIAL", 1219 .dev_name = OMAP_SERIAL_NAME, 1220 .nr = OMAP_MAX_HSUART_PORTS, 1221 .cons = OMAP_CONSOLE, 1222 }; 1223 1224 #ifdef CONFIG_PM_SLEEP 1225 static int serial_omap_suspend(struct device *dev) 1226 { 1227 struct uart_omap_port *up = dev_get_drvdata(dev); 1228 1229 uart_suspend_port(&serial_omap_reg, &up->port); 1230 flush_work(&up->qos_work); 1231 1232 return 0; 1233 } 1234 1235 static int serial_omap_resume(struct device *dev) 1236 { 1237 struct uart_omap_port *up = dev_get_drvdata(dev); 1238 1239 uart_resume_port(&serial_omap_reg, &up->port); 1240 1241 return 0; 1242 } 1243 #endif 1244 1245 static void __devinit omap_serial_fill_features_erratas(struct uart_omap_port *up) 1246 { 1247 u32 mvr, scheme; 1248 u16 revision, major, minor; 1249 1250 mvr = serial_in(up, UART_OMAP_MVER); 1251 1252 /* Check revision register scheme */ 1253 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT; 1254 1255 switch (scheme) { 1256 case 0: /* Legacy Scheme: OMAP2/3 */ 1257 /* MINOR_REV[0:4], MAJOR_REV[4:7] */ 1258 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >> 1259 OMAP_UART_LEGACY_MVR_MAJ_SHIFT; 1260 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK); 1261 break; 1262 case 1: 1263 /* New Scheme: OMAP4+ */ 1264 /* MINOR_REV[0:5], MAJOR_REV[8:10] */ 1265 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >> 1266 OMAP_UART_MVR_MAJ_SHIFT; 1267 minor = (mvr & OMAP_UART_MVR_MIN_MASK); 1268 break; 1269 default: 1270 dev_warn(up->dev, 1271 "Unknown %s revision, defaulting to highest\n", 1272 up->name); 1273 /* highest possible revision */ 1274 major = 0xff; 1275 minor = 0xff; 1276 } 1277 1278 /* normalize revision for the driver */ 1279 revision = UART_BUILD_REVISION(major, minor); 1280 1281 switch (revision) { 1282 case OMAP_UART_REV_46: 1283 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1284 UART_ERRATA_i291_DMA_FORCEIDLE); 1285 break; 1286 case OMAP_UART_REV_52: 1287 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS | 1288 UART_ERRATA_i291_DMA_FORCEIDLE); 1289 break; 1290 case OMAP_UART_REV_63: 1291 up->errata |= UART_ERRATA_i202_MDR1_ACCESS; 1292 break; 1293 default: 1294 break; 1295 } 1296 } 1297 1298 static __devinit struct omap_uart_port_info *of_get_uart_port_info(struct device *dev) 1299 { 1300 struct omap_uart_port_info *omap_up_info; 1301 1302 omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL); 1303 if (!omap_up_info) 1304 return NULL; /* out of memory */ 1305 1306 of_property_read_u32(dev->of_node, "clock-frequency", 1307 &omap_up_info->uartclk); 1308 return omap_up_info; 1309 } 1310 1311 static int __devinit serial_omap_probe(struct platform_device *pdev) 1312 { 1313 struct uart_omap_port *up; 1314 struct resource *mem, *irq; 1315 struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; 1316 int ret; 1317 1318 if (pdev->dev.of_node) 1319 omap_up_info = of_get_uart_port_info(&pdev->dev); 1320 1321 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1322 if (!mem) { 1323 dev_err(&pdev->dev, "no mem resource?\n"); 1324 return -ENODEV; 1325 } 1326 1327 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1328 if (!irq) { 1329 dev_err(&pdev->dev, "no irq resource?\n"); 1330 return -ENODEV; 1331 } 1332 1333 if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem), 1334 pdev->dev.driver->name)) { 1335 dev_err(&pdev->dev, "memory region already claimed\n"); 1336 return -EBUSY; 1337 } 1338 1339 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1340 omap_up_info->DTR_present) { 1341 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial"); 1342 if (ret < 0) 1343 return ret; 1344 ret = gpio_direction_output(omap_up_info->DTR_gpio, 1345 omap_up_info->DTR_inverted); 1346 if (ret < 0) 1347 return ret; 1348 } 1349 1350 up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL); 1351 if (!up) 1352 return -ENOMEM; 1353 1354 if (gpio_is_valid(omap_up_info->DTR_gpio) && 1355 omap_up_info->DTR_present) { 1356 up->DTR_gpio = omap_up_info->DTR_gpio; 1357 up->DTR_inverted = omap_up_info->DTR_inverted; 1358 } else 1359 up->DTR_gpio = -EINVAL; 1360 up->DTR_active = 0; 1361 1362 up->dev = &pdev->dev; 1363 up->port.dev = &pdev->dev; 1364 up->port.type = PORT_OMAP; 1365 up->port.iotype = UPIO_MEM; 1366 up->port.irq = irq->start; 1367 1368 up->port.regshift = 2; 1369 up->port.fifosize = 64; 1370 up->port.ops = &serial_omap_pops; 1371 1372 if (pdev->dev.of_node) 1373 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial"); 1374 else 1375 up->port.line = pdev->id; 1376 1377 if (up->port.line < 0) { 1378 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n", 1379 up->port.line); 1380 ret = -ENODEV; 1381 goto err_port_line; 1382 } 1383 1384 up->pins = devm_pinctrl_get_select_default(&pdev->dev); 1385 if (IS_ERR(up->pins)) { 1386 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n", 1387 up->port.line, PTR_ERR(up->pins)); 1388 up->pins = NULL; 1389 } 1390 1391 sprintf(up->name, "OMAP UART%d", up->port.line); 1392 up->port.mapbase = mem->start; 1393 up->port.membase = devm_ioremap(&pdev->dev, mem->start, 1394 resource_size(mem)); 1395 if (!up->port.membase) { 1396 dev_err(&pdev->dev, "can't ioremap UART\n"); 1397 ret = -ENOMEM; 1398 goto err_ioremap; 1399 } 1400 1401 up->port.flags = omap_up_info->flags; 1402 up->port.uartclk = omap_up_info->uartclk; 1403 if (!up->port.uartclk) { 1404 up->port.uartclk = DEFAULT_CLK_SPEED; 1405 dev_warn(&pdev->dev, "No clock speed specified: using default:" 1406 "%d\n", DEFAULT_CLK_SPEED); 1407 } 1408 1409 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1410 up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1411 pm_qos_add_request(&up->pm_qos_request, 1412 PM_QOS_CPU_DMA_LATENCY, up->latency); 1413 serial_omap_uart_wq = create_singlethread_workqueue(up->name); 1414 INIT_WORK(&up->qos_work, serial_omap_uart_qos_work); 1415 1416 platform_set_drvdata(pdev, up); 1417 pm_runtime_enable(&pdev->dev); 1418 pm_runtime_use_autosuspend(&pdev->dev); 1419 pm_runtime_set_autosuspend_delay(&pdev->dev, 1420 omap_up_info->autosuspend_timeout); 1421 1422 pm_runtime_irq_safe(&pdev->dev); 1423 pm_runtime_get_sync(&pdev->dev); 1424 1425 omap_serial_fill_features_erratas(up); 1426 1427 ui[up->port.line] = up; 1428 serial_omap_add_console_port(up); 1429 1430 ret = uart_add_one_port(&serial_omap_reg, &up->port); 1431 if (ret != 0) 1432 goto err_add_port; 1433 1434 pm_runtime_mark_last_busy(up->dev); 1435 pm_runtime_put_autosuspend(up->dev); 1436 return 0; 1437 1438 err_add_port: 1439 pm_runtime_put(&pdev->dev); 1440 pm_runtime_disable(&pdev->dev); 1441 err_ioremap: 1442 err_port_line: 1443 dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", 1444 pdev->id, __func__, ret); 1445 return ret; 1446 } 1447 1448 static int __devexit serial_omap_remove(struct platform_device *dev) 1449 { 1450 struct uart_omap_port *up = platform_get_drvdata(dev); 1451 1452 pm_runtime_put_sync(up->dev); 1453 pm_runtime_disable(up->dev); 1454 uart_remove_one_port(&serial_omap_reg, &up->port); 1455 pm_qos_remove_request(&up->pm_qos_request); 1456 1457 return 0; 1458 } 1459 1460 /* 1461 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460) 1462 * The access to uart register after MDR1 Access 1463 * causes UART to corrupt data. 1464 * 1465 * Need a delay = 1466 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS) 1467 * give 10 times as much 1468 */ 1469 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1) 1470 { 1471 u8 timeout = 255; 1472 1473 serial_out(up, UART_OMAP_MDR1, mdr1); 1474 udelay(2); 1475 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT | 1476 UART_FCR_CLEAR_RCVR); 1477 /* 1478 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and 1479 * TX_FIFO_E bit is 1. 1480 */ 1481 while (UART_LSR_THRE != (serial_in(up, UART_LSR) & 1482 (UART_LSR_THRE | UART_LSR_DR))) { 1483 timeout--; 1484 if (!timeout) { 1485 /* Should *never* happen. we warn and carry on */ 1486 dev_crit(up->dev, "Errata i202: timedout %x\n", 1487 serial_in(up, UART_LSR)); 1488 break; 1489 } 1490 udelay(1); 1491 } 1492 } 1493 1494 #ifdef CONFIG_PM_RUNTIME 1495 static void serial_omap_restore_context(struct uart_omap_port *up) 1496 { 1497 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1498 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE); 1499 else 1500 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); 1501 1502 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1503 serial_out(up, UART_EFR, UART_EFR_ECB); 1504 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1505 serial_out(up, UART_IER, 0x0); 1506 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1507 serial_out(up, UART_DLL, up->dll); 1508 serial_out(up, UART_DLM, up->dlh); 1509 serial_out(up, UART_LCR, 0x0); /* Operational mode */ 1510 serial_out(up, UART_IER, up->ier); 1511 serial_out(up, UART_FCR, up->fcr); 1512 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1513 serial_out(up, UART_MCR, up->mcr); 1514 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */ 1515 serial_out(up, UART_OMAP_SCR, up->scr); 1516 serial_out(up, UART_EFR, up->efr); 1517 serial_out(up, UART_LCR, up->lcr); 1518 if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) 1519 serial_omap_mdr1_errataset(up, up->mdr1); 1520 else 1521 serial_out(up, UART_OMAP_MDR1, up->mdr1); 1522 } 1523 1524 static int serial_omap_runtime_suspend(struct device *dev) 1525 { 1526 struct uart_omap_port *up = dev_get_drvdata(dev); 1527 struct omap_uart_port_info *pdata = dev->platform_data; 1528 1529 if (!up) 1530 return -EINVAL; 1531 1532 if (!pdata) 1533 return 0; 1534 1535 up->context_loss_cnt = serial_omap_get_context_loss_count(up); 1536 1537 if (device_may_wakeup(dev)) { 1538 if (!up->wakeups_enabled) { 1539 serial_omap_enable_wakeup(up, true); 1540 up->wakeups_enabled = true; 1541 } 1542 } else { 1543 if (up->wakeups_enabled) { 1544 serial_omap_enable_wakeup(up, false); 1545 up->wakeups_enabled = false; 1546 } 1547 } 1548 1549 up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE; 1550 schedule_work(&up->qos_work); 1551 1552 return 0; 1553 } 1554 1555 static int serial_omap_runtime_resume(struct device *dev) 1556 { 1557 struct uart_omap_port *up = dev_get_drvdata(dev); 1558 1559 u32 loss_cnt = serial_omap_get_context_loss_count(up); 1560 1561 if (up->context_loss_cnt != loss_cnt) 1562 serial_omap_restore_context(up); 1563 1564 up->latency = up->calc_latency; 1565 schedule_work(&up->qos_work); 1566 1567 return 0; 1568 } 1569 #endif 1570 1571 static const struct dev_pm_ops serial_omap_dev_pm_ops = { 1572 SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume) 1573 SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend, 1574 serial_omap_runtime_resume, NULL) 1575 }; 1576 1577 #if defined(CONFIG_OF) 1578 static const struct of_device_id omap_serial_of_match[] = { 1579 { .compatible = "ti,omap2-uart" }, 1580 { .compatible = "ti,omap3-uart" }, 1581 { .compatible = "ti,omap4-uart" }, 1582 {}, 1583 }; 1584 MODULE_DEVICE_TABLE(of, omap_serial_of_match); 1585 #endif 1586 1587 static struct platform_driver serial_omap_driver = { 1588 .probe = serial_omap_probe, 1589 .remove = __devexit_p(serial_omap_remove), 1590 .driver = { 1591 .name = DRIVER_NAME, 1592 .pm = &serial_omap_dev_pm_ops, 1593 .of_match_table = of_match_ptr(omap_serial_of_match), 1594 }, 1595 }; 1596 1597 static int __init serial_omap_init(void) 1598 { 1599 int ret; 1600 1601 ret = uart_register_driver(&serial_omap_reg); 1602 if (ret != 0) 1603 return ret; 1604 ret = platform_driver_register(&serial_omap_driver); 1605 if (ret != 0) 1606 uart_unregister_driver(&serial_omap_reg); 1607 return ret; 1608 } 1609 1610 static void __exit serial_omap_exit(void) 1611 { 1612 platform_driver_unregister(&serial_omap_driver); 1613 uart_unregister_driver(&serial_omap_reg); 1614 } 1615 1616 module_init(serial_omap_init); 1617 module_exit(serial_omap_exit); 1618 1619 MODULE_DESCRIPTION("OMAP High Speed UART driver"); 1620 MODULE_LICENSE("GPL"); 1621 MODULE_AUTHOR("Texas Instruments Inc"); 1622