1 /* 2 * Freescale STMP37XX/STMP378X Application UART driver 3 * 4 * Author: dmitry pervushin <dimka@embeddedalley.com> 5 * 6 * Copyright 2008-2010 Freescale Semiconductor, Inc. 7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 8 * 9 * The code contained herein is licensed under the GNU General Public 10 * License. You may obtain a copy of the GNU General Public License 11 * Version 2 or later at the following locations: 12 * 13 * http://www.opensource.org/licenses/gpl-license.html 14 * http://www.gnu.org/copyleft/gpl.html 15 */ 16 17 #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 18 #define SUPPORT_SYSRQ 19 #endif 20 21 #include <linux/kernel.h> 22 #include <linux/errno.h> 23 #include <linux/init.h> 24 #include <linux/console.h> 25 #include <linux/interrupt.h> 26 #include <linux/module.h> 27 #include <linux/slab.h> 28 #include <linux/wait.h> 29 #include <linux/tty.h> 30 #include <linux/tty_driver.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial.h> 33 #include <linux/serial_core.h> 34 #include <linux/platform_device.h> 35 #include <linux/device.h> 36 #include <linux/clk.h> 37 #include <linux/delay.h> 38 #include <linux/io.h> 39 #include <linux/of_device.h> 40 #include <linux/dma-mapping.h> 41 #include <linux/dmaengine.h> 42 43 #include <asm/cacheflush.h> 44 45 #include <linux/gpio.h> 46 #include <linux/gpio/consumer.h> 47 #include <linux/err.h> 48 #include <linux/irq.h> 49 #include "serial_mctrl_gpio.h" 50 51 #define MXS_AUART_PORTS 5 52 #define MXS_AUART_FIFO_SIZE 16 53 54 #define AUART_CTRL0 0x00000000 55 #define AUART_CTRL0_SET 0x00000004 56 #define AUART_CTRL0_CLR 0x00000008 57 #define AUART_CTRL0_TOG 0x0000000c 58 #define AUART_CTRL1 0x00000010 59 #define AUART_CTRL1_SET 0x00000014 60 #define AUART_CTRL1_CLR 0x00000018 61 #define AUART_CTRL1_TOG 0x0000001c 62 #define AUART_CTRL2 0x00000020 63 #define AUART_CTRL2_SET 0x00000024 64 #define AUART_CTRL2_CLR 0x00000028 65 #define AUART_CTRL2_TOG 0x0000002c 66 #define AUART_LINECTRL 0x00000030 67 #define AUART_LINECTRL_SET 0x00000034 68 #define AUART_LINECTRL_CLR 0x00000038 69 #define AUART_LINECTRL_TOG 0x0000003c 70 #define AUART_LINECTRL2 0x00000040 71 #define AUART_LINECTRL2_SET 0x00000044 72 #define AUART_LINECTRL2_CLR 0x00000048 73 #define AUART_LINECTRL2_TOG 0x0000004c 74 #define AUART_INTR 0x00000050 75 #define AUART_INTR_SET 0x00000054 76 #define AUART_INTR_CLR 0x00000058 77 #define AUART_INTR_TOG 0x0000005c 78 #define AUART_DATA 0x00000060 79 #define AUART_STAT 0x00000070 80 #define AUART_DEBUG 0x00000080 81 #define AUART_VERSION 0x00000090 82 #define AUART_AUTOBAUD 0x000000a0 83 84 #define AUART_CTRL0_SFTRST (1 << 31) 85 #define AUART_CTRL0_CLKGATE (1 << 30) 86 #define AUART_CTRL0_RXTO_ENABLE (1 << 27) 87 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) 88 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) 89 90 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) 91 92 #define AUART_CTRL2_DMAONERR (1 << 26) 93 #define AUART_CTRL2_TXDMAE (1 << 25) 94 #define AUART_CTRL2_RXDMAE (1 << 24) 95 96 #define AUART_CTRL2_CTSEN (1 << 15) 97 #define AUART_CTRL2_RTSEN (1 << 14) 98 #define AUART_CTRL2_RTS (1 << 11) 99 #define AUART_CTRL2_RXE (1 << 9) 100 #define AUART_CTRL2_TXE (1 << 8) 101 #define AUART_CTRL2_UARTEN (1 << 0) 102 103 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 104 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 105 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) 106 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 107 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 108 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) 109 #define AUART_LINECTRL_WLEN_MASK 0x00000060 110 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) 111 #define AUART_LINECTRL_FEN (1 << 4) 112 #define AUART_LINECTRL_STP2 (1 << 3) 113 #define AUART_LINECTRL_EPS (1 << 2) 114 #define AUART_LINECTRL_PEN (1 << 1) 115 #define AUART_LINECTRL_BRK (1 << 0) 116 117 #define AUART_INTR_RTIEN (1 << 22) 118 #define AUART_INTR_TXIEN (1 << 21) 119 #define AUART_INTR_RXIEN (1 << 20) 120 #define AUART_INTR_CTSMIEN (1 << 17) 121 #define AUART_INTR_RTIS (1 << 6) 122 #define AUART_INTR_TXIS (1 << 5) 123 #define AUART_INTR_RXIS (1 << 4) 124 #define AUART_INTR_CTSMIS (1 << 1) 125 126 #define AUART_STAT_BUSY (1 << 29) 127 #define AUART_STAT_CTS (1 << 28) 128 #define AUART_STAT_TXFE (1 << 27) 129 #define AUART_STAT_TXFF (1 << 25) 130 #define AUART_STAT_RXFE (1 << 24) 131 #define AUART_STAT_OERR (1 << 19) 132 #define AUART_STAT_BERR (1 << 18) 133 #define AUART_STAT_PERR (1 << 17) 134 #define AUART_STAT_FERR (1 << 16) 135 #define AUART_STAT_RXCOUNT_MASK 0xffff 136 137 static struct uart_driver auart_driver; 138 139 enum mxs_auart_type { 140 IMX23_AUART, 141 IMX28_AUART, 142 }; 143 144 struct mxs_auart_port { 145 struct uart_port port; 146 147 #define MXS_AUART_DMA_ENABLED 0x2 148 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ 149 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ 150 #define MXS_AUART_RTSCTS 4 /* bit 4 */ 151 unsigned long flags; 152 unsigned int mctrl_prev; 153 enum mxs_auart_type devtype; 154 155 unsigned int irq; 156 157 struct clk *clk; 158 struct device *dev; 159 160 /* for DMA */ 161 struct scatterlist tx_sgl; 162 struct dma_chan *tx_dma_chan; 163 void *tx_dma_buf; 164 165 struct scatterlist rx_sgl; 166 struct dma_chan *rx_dma_chan; 167 void *rx_dma_buf; 168 169 struct mctrl_gpios *gpios; 170 int gpio_irq[UART_GPIO_MAX]; 171 bool ms_irq_enabled; 172 }; 173 174 static struct platform_device_id mxs_auart_devtype[] = { 175 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART }, 176 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART }, 177 { /* sentinel */ } 178 }; 179 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); 180 181 static struct of_device_id mxs_auart_dt_ids[] = { 182 { 183 .compatible = "fsl,imx28-auart", 184 .data = &mxs_auart_devtype[IMX28_AUART] 185 }, { 186 .compatible = "fsl,imx23-auart", 187 .data = &mxs_auart_devtype[IMX23_AUART] 188 }, { /* sentinel */ } 189 }; 190 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); 191 192 static inline int is_imx28_auart(struct mxs_auart_port *s) 193 { 194 return s->devtype == IMX28_AUART; 195 } 196 197 static inline bool auart_dma_enabled(struct mxs_auart_port *s) 198 { 199 return s->flags & MXS_AUART_DMA_ENABLED; 200 } 201 202 static void mxs_auart_stop_tx(struct uart_port *u); 203 204 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) 205 206 static void mxs_auart_tx_chars(struct mxs_auart_port *s); 207 208 static void dma_tx_callback(void *param) 209 { 210 struct mxs_auart_port *s = param; 211 struct circ_buf *xmit = &s->port.state->xmit; 212 213 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); 214 215 /* clear the bit used to serialize the DMA tx. */ 216 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 217 smp_mb__after_atomic(); 218 219 /* wake up the possible processes. */ 220 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 221 uart_write_wakeup(&s->port); 222 223 mxs_auart_tx_chars(s); 224 } 225 226 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) 227 { 228 struct dma_async_tx_descriptor *desc; 229 struct scatterlist *sgl = &s->tx_sgl; 230 struct dma_chan *channel = s->tx_dma_chan; 231 u32 pio; 232 233 /* [1] : send PIO. Note, the first pio word is CTRL1. */ 234 pio = AUART_CTRL1_XFER_COUNT(size); 235 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, 236 1, DMA_TRANS_NONE, 0); 237 if (!desc) { 238 dev_err(s->dev, "step 1 error\n"); 239 return -EINVAL; 240 } 241 242 /* [2] : set DMA buffer. */ 243 sg_init_one(sgl, s->tx_dma_buf, size); 244 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); 245 desc = dmaengine_prep_slave_sg(channel, sgl, 246 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 247 if (!desc) { 248 dev_err(s->dev, "step 2 error\n"); 249 return -EINVAL; 250 } 251 252 /* [3] : submit the DMA */ 253 desc->callback = dma_tx_callback; 254 desc->callback_param = s; 255 dmaengine_submit(desc); 256 dma_async_issue_pending(channel); 257 return 0; 258 } 259 260 static void mxs_auart_tx_chars(struct mxs_auart_port *s) 261 { 262 struct circ_buf *xmit = &s->port.state->xmit; 263 264 if (auart_dma_enabled(s)) { 265 u32 i = 0; 266 int size; 267 void *buffer = s->tx_dma_buf; 268 269 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) 270 return; 271 272 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 273 size = min_t(u32, UART_XMIT_SIZE - i, 274 CIRC_CNT_TO_END(xmit->head, 275 xmit->tail, 276 UART_XMIT_SIZE)); 277 memcpy(buffer + i, xmit->buf + xmit->tail, size); 278 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); 279 280 i += size; 281 if (i >= UART_XMIT_SIZE) 282 break; 283 } 284 285 if (uart_tx_stopped(&s->port)) 286 mxs_auart_stop_tx(&s->port); 287 288 if (i) { 289 mxs_auart_dma_tx(s, i); 290 } else { 291 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 292 smp_mb__after_atomic(); 293 } 294 return; 295 } 296 297 298 while (!(readl(s->port.membase + AUART_STAT) & 299 AUART_STAT_TXFF)) { 300 if (s->port.x_char) { 301 s->port.icount.tx++; 302 writel(s->port.x_char, 303 s->port.membase + AUART_DATA); 304 s->port.x_char = 0; 305 continue; 306 } 307 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 308 s->port.icount.tx++; 309 writel(xmit->buf[xmit->tail], 310 s->port.membase + AUART_DATA); 311 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 312 } else 313 break; 314 } 315 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 316 uart_write_wakeup(&s->port); 317 318 if (uart_circ_empty(&(s->port.state->xmit))) 319 writel(AUART_INTR_TXIEN, 320 s->port.membase + AUART_INTR_CLR); 321 else 322 writel(AUART_INTR_TXIEN, 323 s->port.membase + AUART_INTR_SET); 324 325 if (uart_tx_stopped(&s->port)) 326 mxs_auart_stop_tx(&s->port); 327 } 328 329 static void mxs_auart_rx_char(struct mxs_auart_port *s) 330 { 331 int flag; 332 u32 stat; 333 u8 c; 334 335 c = readl(s->port.membase + AUART_DATA); 336 stat = readl(s->port.membase + AUART_STAT); 337 338 flag = TTY_NORMAL; 339 s->port.icount.rx++; 340 341 if (stat & AUART_STAT_BERR) { 342 s->port.icount.brk++; 343 if (uart_handle_break(&s->port)) 344 goto out; 345 } else if (stat & AUART_STAT_PERR) { 346 s->port.icount.parity++; 347 } else if (stat & AUART_STAT_FERR) { 348 s->port.icount.frame++; 349 } 350 351 /* 352 * Mask off conditions which should be ingored. 353 */ 354 stat &= s->port.read_status_mask; 355 356 if (stat & AUART_STAT_BERR) { 357 flag = TTY_BREAK; 358 } else if (stat & AUART_STAT_PERR) 359 flag = TTY_PARITY; 360 else if (stat & AUART_STAT_FERR) 361 flag = TTY_FRAME; 362 363 if (stat & AUART_STAT_OERR) 364 s->port.icount.overrun++; 365 366 if (uart_handle_sysrq_char(&s->port, c)) 367 goto out; 368 369 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); 370 out: 371 writel(stat, s->port.membase + AUART_STAT); 372 } 373 374 static void mxs_auart_rx_chars(struct mxs_auart_port *s) 375 { 376 u32 stat = 0; 377 378 for (;;) { 379 stat = readl(s->port.membase + AUART_STAT); 380 if (stat & AUART_STAT_RXFE) 381 break; 382 mxs_auart_rx_char(s); 383 } 384 385 writel(stat, s->port.membase + AUART_STAT); 386 tty_flip_buffer_push(&s->port.state->port); 387 } 388 389 static int mxs_auart_request_port(struct uart_port *u) 390 { 391 return 0; 392 } 393 394 static int mxs_auart_verify_port(struct uart_port *u, 395 struct serial_struct *ser) 396 { 397 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) 398 return -EINVAL; 399 return 0; 400 } 401 402 static void mxs_auart_config_port(struct uart_port *u, int flags) 403 { 404 } 405 406 static const char *mxs_auart_type(struct uart_port *u) 407 { 408 struct mxs_auart_port *s = to_auart_port(u); 409 410 return dev_name(s->dev); 411 } 412 413 static void mxs_auart_release_port(struct uart_port *u) 414 { 415 } 416 417 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) 418 { 419 struct mxs_auart_port *s = to_auart_port(u); 420 421 u32 ctrl = readl(u->membase + AUART_CTRL2); 422 423 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS); 424 if (mctrl & TIOCM_RTS) { 425 if (uart_cts_enabled(u)) 426 ctrl |= AUART_CTRL2_RTSEN; 427 else 428 ctrl |= AUART_CTRL2_RTS; 429 } 430 431 writel(ctrl, u->membase + AUART_CTRL2); 432 433 mctrl_gpio_set(s->gpios, mctrl); 434 } 435 436 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS) 437 static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl) 438 { 439 u32 mctrl_diff; 440 441 mctrl_diff = mctrl ^ s->mctrl_prev; 442 s->mctrl_prev = mctrl; 443 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled && 444 s->port.state != NULL) { 445 if (mctrl_diff & TIOCM_RI) 446 s->port.icount.rng++; 447 if (mctrl_diff & TIOCM_DSR) 448 s->port.icount.dsr++; 449 if (mctrl_diff & TIOCM_CD) 450 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD); 451 if (mctrl_diff & TIOCM_CTS) 452 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS); 453 454 wake_up_interruptible(&s->port.state->port.delta_msr_wait); 455 } 456 return mctrl; 457 } 458 459 static u32 mxs_auart_get_mctrl(struct uart_port *u) 460 { 461 struct mxs_auart_port *s = to_auart_port(u); 462 u32 stat = readl(u->membase + AUART_STAT); 463 u32 mctrl = 0; 464 465 if (stat & AUART_STAT_CTS) 466 mctrl |= TIOCM_CTS; 467 468 return mctrl_gpio_get(s->gpios, &mctrl); 469 } 470 471 /* 472 * Enable modem status interrupts 473 */ 474 static void mxs_auart_enable_ms(struct uart_port *port) 475 { 476 struct mxs_auart_port *s = to_auart_port(port); 477 478 /* 479 * Interrupt should not be enabled twice 480 */ 481 if (s->ms_irq_enabled) 482 return; 483 484 s->ms_irq_enabled = true; 485 486 if (s->gpio_irq[UART_GPIO_CTS] >= 0) 487 enable_irq(s->gpio_irq[UART_GPIO_CTS]); 488 /* TODO: enable AUART_INTR_CTSMIEN otherwise */ 489 490 if (s->gpio_irq[UART_GPIO_DSR] >= 0) 491 enable_irq(s->gpio_irq[UART_GPIO_DSR]); 492 493 if (s->gpio_irq[UART_GPIO_RI] >= 0) 494 enable_irq(s->gpio_irq[UART_GPIO_RI]); 495 496 if (s->gpio_irq[UART_GPIO_DCD] >= 0) 497 enable_irq(s->gpio_irq[UART_GPIO_DCD]); 498 } 499 500 /* 501 * Disable modem status interrupts 502 */ 503 static void mxs_auart_disable_ms(struct uart_port *port) 504 { 505 struct mxs_auart_port *s = to_auart_port(port); 506 507 /* 508 * Interrupt should not be disabled twice 509 */ 510 if (!s->ms_irq_enabled) 511 return; 512 513 s->ms_irq_enabled = false; 514 515 if (s->gpio_irq[UART_GPIO_CTS] >= 0) 516 disable_irq(s->gpio_irq[UART_GPIO_CTS]); 517 /* TODO: disable AUART_INTR_CTSMIEN otherwise */ 518 519 if (s->gpio_irq[UART_GPIO_DSR] >= 0) 520 disable_irq(s->gpio_irq[UART_GPIO_DSR]); 521 522 if (s->gpio_irq[UART_GPIO_RI] >= 0) 523 disable_irq(s->gpio_irq[UART_GPIO_RI]); 524 525 if (s->gpio_irq[UART_GPIO_DCD] >= 0) 526 disable_irq(s->gpio_irq[UART_GPIO_DCD]); 527 } 528 529 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); 530 static void dma_rx_callback(void *arg) 531 { 532 struct mxs_auart_port *s = (struct mxs_auart_port *) arg; 533 struct tty_port *port = &s->port.state->port; 534 int count; 535 u32 stat; 536 537 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); 538 539 stat = readl(s->port.membase + AUART_STAT); 540 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | 541 AUART_STAT_PERR | AUART_STAT_FERR); 542 543 count = stat & AUART_STAT_RXCOUNT_MASK; 544 tty_insert_flip_string(port, s->rx_dma_buf, count); 545 546 writel(stat, s->port.membase + AUART_STAT); 547 tty_flip_buffer_push(port); 548 549 /* start the next DMA for RX. */ 550 mxs_auart_dma_prep_rx(s); 551 } 552 553 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) 554 { 555 struct dma_async_tx_descriptor *desc; 556 struct scatterlist *sgl = &s->rx_sgl; 557 struct dma_chan *channel = s->rx_dma_chan; 558 u32 pio[1]; 559 560 /* [1] : send PIO */ 561 pio[0] = AUART_CTRL0_RXTO_ENABLE 562 | AUART_CTRL0_RXTIMEOUT(0x80) 563 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); 564 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, 565 1, DMA_TRANS_NONE, 0); 566 if (!desc) { 567 dev_err(s->dev, "step 1 error\n"); 568 return -EINVAL; 569 } 570 571 /* [2] : send DMA request */ 572 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); 573 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); 574 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, 575 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 576 if (!desc) { 577 dev_err(s->dev, "step 2 error\n"); 578 return -1; 579 } 580 581 /* [3] : submit the DMA, but do not issue it. */ 582 desc->callback = dma_rx_callback; 583 desc->callback_param = s; 584 dmaengine_submit(desc); 585 dma_async_issue_pending(channel); 586 return 0; 587 } 588 589 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) 590 { 591 if (s->tx_dma_chan) { 592 dma_release_channel(s->tx_dma_chan); 593 s->tx_dma_chan = NULL; 594 } 595 if (s->rx_dma_chan) { 596 dma_release_channel(s->rx_dma_chan); 597 s->rx_dma_chan = NULL; 598 } 599 600 kfree(s->tx_dma_buf); 601 kfree(s->rx_dma_buf); 602 s->tx_dma_buf = NULL; 603 s->rx_dma_buf = NULL; 604 } 605 606 static void mxs_auart_dma_exit(struct mxs_auart_port *s) 607 { 608 609 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, 610 s->port.membase + AUART_CTRL2_CLR); 611 612 mxs_auart_dma_exit_channel(s); 613 s->flags &= ~MXS_AUART_DMA_ENABLED; 614 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 615 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); 616 } 617 618 static int mxs_auart_dma_init(struct mxs_auart_port *s) 619 { 620 if (auart_dma_enabled(s)) 621 return 0; 622 623 /* init for RX */ 624 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx"); 625 if (!s->rx_dma_chan) 626 goto err_out; 627 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 628 if (!s->rx_dma_buf) 629 goto err_out; 630 631 /* init for TX */ 632 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx"); 633 if (!s->tx_dma_chan) 634 goto err_out; 635 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 636 if (!s->tx_dma_buf) 637 goto err_out; 638 639 /* set the flags */ 640 s->flags |= MXS_AUART_DMA_ENABLED; 641 dev_dbg(s->dev, "enabled the DMA support."); 642 643 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 644 s->port.fifosize = UART_XMIT_SIZE; 645 646 return 0; 647 648 err_out: 649 mxs_auart_dma_exit_channel(s); 650 return -EINVAL; 651 652 } 653 654 #define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \ 655 UART_GPIO_RTS)) 656 #define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \ 657 UART_GPIO_CTS)) 658 static void mxs_auart_settermios(struct uart_port *u, 659 struct ktermios *termios, 660 struct ktermios *old) 661 { 662 struct mxs_auart_port *s = to_auart_port(u); 663 u32 bm, ctrl, ctrl2, div; 664 unsigned int cflag, baud; 665 666 cflag = termios->c_cflag; 667 668 ctrl = AUART_LINECTRL_FEN; 669 ctrl2 = readl(u->membase + AUART_CTRL2); 670 671 /* byte size */ 672 switch (cflag & CSIZE) { 673 case CS5: 674 bm = 0; 675 break; 676 case CS6: 677 bm = 1; 678 break; 679 case CS7: 680 bm = 2; 681 break; 682 case CS8: 683 bm = 3; 684 break; 685 default: 686 return; 687 } 688 689 ctrl |= AUART_LINECTRL_WLEN(bm); 690 691 /* parity */ 692 if (cflag & PARENB) { 693 ctrl |= AUART_LINECTRL_PEN; 694 if ((cflag & PARODD) == 0) 695 ctrl |= AUART_LINECTRL_EPS; 696 } 697 698 u->read_status_mask = 0; 699 700 if (termios->c_iflag & INPCK) 701 u->read_status_mask |= AUART_STAT_PERR; 702 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 703 u->read_status_mask |= AUART_STAT_BERR; 704 705 /* 706 * Characters to ignore 707 */ 708 u->ignore_status_mask = 0; 709 if (termios->c_iflag & IGNPAR) 710 u->ignore_status_mask |= AUART_STAT_PERR; 711 if (termios->c_iflag & IGNBRK) { 712 u->ignore_status_mask |= AUART_STAT_BERR; 713 /* 714 * If we're ignoring parity and break indicators, 715 * ignore overruns too (for real raw support). 716 */ 717 if (termios->c_iflag & IGNPAR) 718 u->ignore_status_mask |= AUART_STAT_OERR; 719 } 720 721 /* 722 * ignore all characters if CREAD is not set 723 */ 724 if (cflag & CREAD) 725 ctrl2 |= AUART_CTRL2_RXE; 726 else 727 ctrl2 &= ~AUART_CTRL2_RXE; 728 729 /* figure out the stop bits requested */ 730 if (cflag & CSTOPB) 731 ctrl |= AUART_LINECTRL_STP2; 732 733 /* figure out the hardware flow control settings */ 734 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); 735 if (cflag & CRTSCTS) { 736 /* 737 * The DMA has a bug(see errata:2836) in mx23. 738 * So we can not implement the DMA for auart in mx23, 739 * we can only implement the DMA support for auart 740 * in mx28. 741 */ 742 if (is_imx28_auart(s) 743 && test_bit(MXS_AUART_RTSCTS, &s->flags)) { 744 if (!mxs_auart_dma_init(s)) 745 /* enable DMA tranfer */ 746 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE 747 | AUART_CTRL2_DMAONERR; 748 } 749 /* Even if RTS is GPIO line RTSEN can be enabled because 750 * the pinctrl configuration decides about RTS pin function */ 751 ctrl2 |= AUART_CTRL2_RTSEN; 752 if (CTS_AT_AUART()) 753 ctrl2 |= AUART_CTRL2_CTSEN; 754 } 755 756 /* set baud rate */ 757 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); 758 div = u->uartclk * 32 / baud; 759 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); 760 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); 761 762 writel(ctrl, u->membase + AUART_LINECTRL); 763 writel(ctrl2, u->membase + AUART_CTRL2); 764 765 uart_update_timeout(u, termios->c_cflag, baud); 766 767 /* prepare for the DMA RX. */ 768 if (auart_dma_enabled(s) && 769 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { 770 if (!mxs_auart_dma_prep_rx(s)) { 771 /* Disable the normal RX interrupt. */ 772 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN, 773 u->membase + AUART_INTR_CLR); 774 } else { 775 mxs_auart_dma_exit(s); 776 dev_err(s->dev, "We can not start up the DMA.\n"); 777 } 778 } 779 780 /* CTS flow-control and modem-status interrupts */ 781 if (UART_ENABLE_MS(u, termios->c_cflag)) 782 mxs_auart_enable_ms(u); 783 else 784 mxs_auart_disable_ms(u); 785 } 786 787 static void mxs_auart_set_ldisc(struct uart_port *port, 788 struct ktermios *termios) 789 { 790 if (termios->c_line == N_PPS) { 791 port->flags |= UPF_HARDPPS_CD; 792 mxs_auart_enable_ms(port); 793 } else { 794 port->flags &= ~UPF_HARDPPS_CD; 795 } 796 } 797 798 static irqreturn_t mxs_auart_irq_handle(int irq, void *context) 799 { 800 u32 istat; 801 struct mxs_auart_port *s = context; 802 u32 mctrl_temp = s->mctrl_prev; 803 u32 stat = readl(s->port.membase + AUART_STAT); 804 805 istat = readl(s->port.membase + AUART_INTR); 806 807 /* ack irq */ 808 writel(istat & (AUART_INTR_RTIS 809 | AUART_INTR_TXIS 810 | AUART_INTR_RXIS 811 | AUART_INTR_CTSMIS), 812 s->port.membase + AUART_INTR_CLR); 813 814 /* 815 * Dealing with GPIO interrupt 816 */ 817 if (irq == s->gpio_irq[UART_GPIO_CTS] || 818 irq == s->gpio_irq[UART_GPIO_DCD] || 819 irq == s->gpio_irq[UART_GPIO_DSR] || 820 irq == s->gpio_irq[UART_GPIO_RI]) 821 mxs_auart_modem_status(s, 822 mctrl_gpio_get(s->gpios, &mctrl_temp)); 823 824 if (istat & AUART_INTR_CTSMIS) { 825 if (CTS_AT_AUART() && s->ms_irq_enabled) 826 uart_handle_cts_change(&s->port, 827 stat & AUART_STAT_CTS); 828 writel(AUART_INTR_CTSMIS, 829 s->port.membase + AUART_INTR_CLR); 830 istat &= ~AUART_INTR_CTSMIS; 831 } 832 833 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { 834 if (!auart_dma_enabled(s)) 835 mxs_auart_rx_chars(s); 836 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); 837 } 838 839 if (istat & AUART_INTR_TXIS) { 840 mxs_auart_tx_chars(s); 841 istat &= ~AUART_INTR_TXIS; 842 } 843 844 return IRQ_HANDLED; 845 } 846 847 static void mxs_auart_reset(struct uart_port *u) 848 { 849 int i; 850 unsigned int reg; 851 852 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR); 853 854 for (i = 0; i < 10000; i++) { 855 reg = readl(u->membase + AUART_CTRL0); 856 if (!(reg & AUART_CTRL0_SFTRST)) 857 break; 858 udelay(3); 859 } 860 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 861 } 862 863 static int mxs_auart_startup(struct uart_port *u) 864 { 865 int ret; 866 struct mxs_auart_port *s = to_auart_port(u); 867 868 ret = clk_prepare_enable(s->clk); 869 if (ret) 870 return ret; 871 872 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 873 874 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET); 875 876 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 877 u->membase + AUART_INTR); 878 879 /* Reset FIFO size (it could have changed if DMA was enabled) */ 880 u->fifosize = MXS_AUART_FIFO_SIZE; 881 882 /* 883 * Enable fifo so all four bytes of a DMA word are written to 884 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) 885 */ 886 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET); 887 888 /* get initial status of modem lines */ 889 mctrl_gpio_get(s->gpios, &s->mctrl_prev); 890 891 s->ms_irq_enabled = false; 892 return 0; 893 } 894 895 static void mxs_auart_shutdown(struct uart_port *u) 896 { 897 struct mxs_auart_port *s = to_auart_port(u); 898 899 mxs_auart_disable_ms(u); 900 901 if (auart_dma_enabled(s)) 902 mxs_auart_dma_exit(s); 903 904 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); 905 906 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 907 u->membase + AUART_INTR_CLR); 908 909 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET); 910 911 clk_disable_unprepare(s->clk); 912 } 913 914 static unsigned int mxs_auart_tx_empty(struct uart_port *u) 915 { 916 if ((readl(u->membase + AUART_STAT) & 917 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE) 918 return TIOCSER_TEMT; 919 920 return 0; 921 } 922 923 static void mxs_auart_start_tx(struct uart_port *u) 924 { 925 struct mxs_auart_port *s = to_auart_port(u); 926 927 /* enable transmitter */ 928 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET); 929 930 mxs_auart_tx_chars(s); 931 } 932 933 static void mxs_auart_stop_tx(struct uart_port *u) 934 { 935 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR); 936 } 937 938 static void mxs_auart_stop_rx(struct uart_port *u) 939 { 940 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR); 941 } 942 943 static void mxs_auart_break_ctl(struct uart_port *u, int ctl) 944 { 945 if (ctl) 946 writel(AUART_LINECTRL_BRK, 947 u->membase + AUART_LINECTRL_SET); 948 else 949 writel(AUART_LINECTRL_BRK, 950 u->membase + AUART_LINECTRL_CLR); 951 } 952 953 static struct uart_ops mxs_auart_ops = { 954 .tx_empty = mxs_auart_tx_empty, 955 .start_tx = mxs_auart_start_tx, 956 .stop_tx = mxs_auart_stop_tx, 957 .stop_rx = mxs_auart_stop_rx, 958 .enable_ms = mxs_auart_enable_ms, 959 .break_ctl = mxs_auart_break_ctl, 960 .set_mctrl = mxs_auart_set_mctrl, 961 .get_mctrl = mxs_auart_get_mctrl, 962 .startup = mxs_auart_startup, 963 .shutdown = mxs_auart_shutdown, 964 .set_termios = mxs_auart_settermios, 965 .set_ldisc = mxs_auart_set_ldisc, 966 .type = mxs_auart_type, 967 .release_port = mxs_auart_release_port, 968 .request_port = mxs_auart_request_port, 969 .config_port = mxs_auart_config_port, 970 .verify_port = mxs_auart_verify_port, 971 }; 972 973 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; 974 975 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 976 static void mxs_auart_console_putchar(struct uart_port *port, int ch) 977 { 978 unsigned int to = 1000; 979 980 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) { 981 if (!to--) 982 break; 983 udelay(1); 984 } 985 986 writel(ch, port->membase + AUART_DATA); 987 } 988 989 static void 990 auart_console_write(struct console *co, const char *str, unsigned int count) 991 { 992 struct mxs_auart_port *s; 993 struct uart_port *port; 994 unsigned int old_ctrl0, old_ctrl2; 995 unsigned int to = 20000; 996 997 if (co->index >= MXS_AUART_PORTS || co->index < 0) 998 return; 999 1000 s = auart_port[co->index]; 1001 port = &s->port; 1002 1003 clk_enable(s->clk); 1004 1005 /* First save the CR then disable the interrupts */ 1006 old_ctrl2 = readl(port->membase + AUART_CTRL2); 1007 old_ctrl0 = readl(port->membase + AUART_CTRL0); 1008 1009 writel(AUART_CTRL0_CLKGATE, 1010 port->membase + AUART_CTRL0_CLR); 1011 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, 1012 port->membase + AUART_CTRL2_SET); 1013 1014 uart_console_write(port, str, count, mxs_auart_console_putchar); 1015 1016 /* Finally, wait for transmitter to become empty ... */ 1017 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) { 1018 udelay(1); 1019 if (!to--) 1020 break; 1021 } 1022 1023 /* 1024 * ... and restore the TCR if we waited long enough for the transmitter 1025 * to be idle. This might keep the transmitter enabled although it is 1026 * unused, but that is better than to disable it while it is still 1027 * transmitting. 1028 */ 1029 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) { 1030 writel(old_ctrl0, port->membase + AUART_CTRL0); 1031 writel(old_ctrl2, port->membase + AUART_CTRL2); 1032 } 1033 1034 clk_disable(s->clk); 1035 } 1036 1037 static void __init 1038 auart_console_get_options(struct uart_port *port, int *baud, 1039 int *parity, int *bits) 1040 { 1041 unsigned int lcr_h, quot; 1042 1043 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN)) 1044 return; 1045 1046 lcr_h = readl(port->membase + AUART_LINECTRL); 1047 1048 *parity = 'n'; 1049 if (lcr_h & AUART_LINECTRL_PEN) { 1050 if (lcr_h & AUART_LINECTRL_EPS) 1051 *parity = 'e'; 1052 else 1053 *parity = 'o'; 1054 } 1055 1056 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) 1057 *bits = 7; 1058 else 1059 *bits = 8; 1060 1061 quot = ((readl(port->membase + AUART_LINECTRL) 1062 & AUART_LINECTRL_BAUD_DIVINT_MASK)) 1063 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); 1064 quot |= ((readl(port->membase + AUART_LINECTRL) 1065 & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) 1066 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; 1067 if (quot == 0) 1068 quot = 1; 1069 1070 *baud = (port->uartclk << 2) / quot; 1071 } 1072 1073 static int __init 1074 auart_console_setup(struct console *co, char *options) 1075 { 1076 struct mxs_auart_port *s; 1077 int baud = 9600; 1078 int bits = 8; 1079 int parity = 'n'; 1080 int flow = 'n'; 1081 int ret; 1082 1083 /* 1084 * Check whether an invalid uart number has been specified, and 1085 * if so, search for the first available port that does have 1086 * console support. 1087 */ 1088 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) 1089 co->index = 0; 1090 s = auart_port[co->index]; 1091 if (!s) 1092 return -ENODEV; 1093 1094 ret = clk_prepare_enable(s->clk); 1095 if (ret) 1096 return ret; 1097 1098 if (options) 1099 uart_parse_options(options, &baud, &parity, &bits, &flow); 1100 else 1101 auart_console_get_options(&s->port, &baud, &parity, &bits); 1102 1103 ret = uart_set_options(&s->port, co, baud, parity, bits, flow); 1104 1105 clk_disable_unprepare(s->clk); 1106 1107 return ret; 1108 } 1109 1110 static struct console auart_console = { 1111 .name = "ttyAPP", 1112 .write = auart_console_write, 1113 .device = uart_console_device, 1114 .setup = auart_console_setup, 1115 .flags = CON_PRINTBUFFER, 1116 .index = -1, 1117 .data = &auart_driver, 1118 }; 1119 #endif 1120 1121 static struct uart_driver auart_driver = { 1122 .owner = THIS_MODULE, 1123 .driver_name = "ttyAPP", 1124 .dev_name = "ttyAPP", 1125 .major = 0, 1126 .minor = 0, 1127 .nr = MXS_AUART_PORTS, 1128 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 1129 .cons = &auart_console, 1130 #endif 1131 }; 1132 1133 /* 1134 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it 1135 * could successfully get all information from dt or a negative errno. 1136 */ 1137 static int serial_mxs_probe_dt(struct mxs_auart_port *s, 1138 struct platform_device *pdev) 1139 { 1140 struct device_node *np = pdev->dev.of_node; 1141 int ret; 1142 1143 if (!np) 1144 /* no device tree device */ 1145 return 1; 1146 1147 ret = of_alias_get_id(np, "serial"); 1148 if (ret < 0) { 1149 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); 1150 return ret; 1151 } 1152 s->port.line = ret; 1153 1154 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1155 set_bit(MXS_AUART_RTSCTS, &s->flags); 1156 1157 return 0; 1158 } 1159 1160 static bool mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) 1161 { 1162 enum mctrl_gpio_idx i; 1163 struct gpio_desc *gpiod; 1164 1165 s->gpios = mctrl_gpio_init(dev, 0); 1166 if (IS_ERR_OR_NULL(s->gpios)) 1167 return false; 1168 1169 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */ 1170 if (!RTS_AT_AUART() || !CTS_AT_AUART()) { 1171 if (test_bit(MXS_AUART_RTSCTS, &s->flags)) 1172 dev_warn(dev, 1173 "DMA and flow control via gpio may cause some problems. DMA disabled!\n"); 1174 clear_bit(MXS_AUART_RTSCTS, &s->flags); 1175 } 1176 1177 for (i = 0; i < UART_GPIO_MAX; i++) { 1178 gpiod = mctrl_gpio_to_gpiod(s->gpios, i); 1179 if (gpiod && (gpiod_get_direction(gpiod) == GPIOF_DIR_IN)) 1180 s->gpio_irq[i] = gpiod_to_irq(gpiod); 1181 else 1182 s->gpio_irq[i] = -EINVAL; 1183 } 1184 1185 return true; 1186 } 1187 1188 static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) 1189 { 1190 enum mctrl_gpio_idx i; 1191 1192 for (i = 0; i < UART_GPIO_MAX; i++) 1193 if (s->gpio_irq[i] >= 0) 1194 free_irq(s->gpio_irq[i], s); 1195 } 1196 1197 static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s) 1198 { 1199 int *irq = s->gpio_irq; 1200 enum mctrl_gpio_idx i; 1201 int err = 0; 1202 1203 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1204 if (irq[i] < 0) 1205 continue; 1206 1207 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1208 err = request_irq(irq[i], mxs_auart_irq_handle, 1209 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s); 1210 if (err) 1211 dev_err(s->dev, "%s - Can't get %d irq\n", 1212 __func__, irq[i]); 1213 } 1214 1215 /* 1216 * If something went wrong, rollback. 1217 */ 1218 while (err && (--i >= 0)) 1219 if (irq[i] >= 0) 1220 free_irq(irq[i], s); 1221 1222 return err; 1223 } 1224 1225 static int mxs_auart_probe(struct platform_device *pdev) 1226 { 1227 const struct of_device_id *of_id = 1228 of_match_device(mxs_auart_dt_ids, &pdev->dev); 1229 struct mxs_auart_port *s; 1230 u32 version; 1231 int ret = 0; 1232 struct resource *r; 1233 1234 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); 1235 if (!s) { 1236 ret = -ENOMEM; 1237 goto out; 1238 } 1239 1240 ret = serial_mxs_probe_dt(s, pdev); 1241 if (ret > 0) 1242 s->port.line = pdev->id < 0 ? 0 : pdev->id; 1243 else if (ret < 0) 1244 goto out_free; 1245 1246 if (of_id) { 1247 pdev->id_entry = of_id->data; 1248 s->devtype = pdev->id_entry->driver_data; 1249 } 1250 1251 s->clk = clk_get(&pdev->dev, NULL); 1252 if (IS_ERR(s->clk)) { 1253 ret = PTR_ERR(s->clk); 1254 goto out_free; 1255 } 1256 1257 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1258 if (!r) { 1259 ret = -ENXIO; 1260 goto out_free_clk; 1261 } 1262 1263 s->port.mapbase = r->start; 1264 s->port.membase = ioremap(r->start, resource_size(r)); 1265 s->port.ops = &mxs_auart_ops; 1266 s->port.iotype = UPIO_MEM; 1267 s->port.fifosize = MXS_AUART_FIFO_SIZE; 1268 s->port.uartclk = clk_get_rate(s->clk); 1269 s->port.type = PORT_IMX; 1270 s->port.dev = s->dev = &pdev->dev; 1271 1272 s->mctrl_prev = 0; 1273 1274 s->irq = platform_get_irq(pdev, 0); 1275 s->port.irq = s->irq; 1276 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s); 1277 if (ret) 1278 goto out_free_clk; 1279 1280 platform_set_drvdata(pdev, s); 1281 1282 if (!mxs_auart_init_gpios(s, &pdev->dev)) 1283 dev_err(&pdev->dev, 1284 "Failed to initialize GPIOs. The serial port may not work as expected\n"); 1285 1286 /* 1287 * Get the GPIO lines IRQ 1288 */ 1289 ret = mxs_auart_request_gpio_irq(s); 1290 if (ret) 1291 goto out_free_irq; 1292 1293 auart_port[s->port.line] = s; 1294 1295 mxs_auart_reset(&s->port); 1296 1297 ret = uart_add_one_port(&auart_driver, &s->port); 1298 if (ret) 1299 goto out_free_gpio_irq; 1300 1301 version = readl(s->port.membase + AUART_VERSION); 1302 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", 1303 (version >> 24) & 0xff, 1304 (version >> 16) & 0xff, version & 0xffff); 1305 1306 return 0; 1307 1308 out_free_gpio_irq: 1309 mxs_auart_free_gpio_irq(s); 1310 out_free_irq: 1311 auart_port[pdev->id] = NULL; 1312 free_irq(s->irq, s); 1313 out_free_clk: 1314 clk_put(s->clk); 1315 out_free: 1316 kfree(s); 1317 out: 1318 return ret; 1319 } 1320 1321 static int mxs_auart_remove(struct platform_device *pdev) 1322 { 1323 struct mxs_auart_port *s = platform_get_drvdata(pdev); 1324 1325 uart_remove_one_port(&auart_driver, &s->port); 1326 1327 auart_port[pdev->id] = NULL; 1328 1329 mxs_auart_free_gpio_irq(s); 1330 clk_put(s->clk); 1331 free_irq(s->irq, s); 1332 kfree(s); 1333 1334 return 0; 1335 } 1336 1337 static struct platform_driver mxs_auart_driver = { 1338 .probe = mxs_auart_probe, 1339 .remove = mxs_auart_remove, 1340 .driver = { 1341 .name = "mxs-auart", 1342 .of_match_table = mxs_auart_dt_ids, 1343 }, 1344 }; 1345 1346 static int __init mxs_auart_init(void) 1347 { 1348 int r; 1349 1350 r = uart_register_driver(&auart_driver); 1351 if (r) 1352 goto out; 1353 1354 r = platform_driver_register(&mxs_auart_driver); 1355 if (r) 1356 goto out_err; 1357 1358 return 0; 1359 out_err: 1360 uart_unregister_driver(&auart_driver); 1361 out: 1362 return r; 1363 } 1364 1365 static void __exit mxs_auart_exit(void) 1366 { 1367 platform_driver_unregister(&mxs_auart_driver); 1368 uart_unregister_driver(&auart_driver); 1369 } 1370 1371 module_init(mxs_auart_init); 1372 module_exit(mxs_auart_exit); 1373 MODULE_LICENSE("GPL"); 1374 MODULE_DESCRIPTION("Freescale MXS application uart driver"); 1375 MODULE_ALIAS("platform:mxs-auart"); 1376