1 /* 2 * Freescale STMP37XX/STMP378X Application UART driver 3 * 4 * Author: dmitry pervushin <dimka@embeddedalley.com> 5 * 6 * Copyright 2008-2010 Freescale Semiconductor, Inc. 7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 8 * 9 * The code contained herein is licensed under the GNU General Public 10 * License. You may obtain a copy of the GNU General Public License 11 * Version 2 or later at the following locations: 12 * 13 * http://www.opensource.org/licenses/gpl-license.html 14 * http://www.gnu.org/copyleft/gpl.html 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/console.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/slab.h> 24 #include <linux/wait.h> 25 #include <linux/tty.h> 26 #include <linux/tty_driver.h> 27 #include <linux/tty_flip.h> 28 #include <linux/serial.h> 29 #include <linux/serial_core.h> 30 #include <linux/platform_device.h> 31 #include <linux/device.h> 32 #include <linux/clk.h> 33 #include <linux/delay.h> 34 #include <linux/io.h> 35 #include <linux/of_device.h> 36 #include <linux/dma-mapping.h> 37 #include <linux/dmaengine.h> 38 39 #include <asm/cacheflush.h> 40 41 #define MXS_AUART_PORTS 5 42 43 #define AUART_CTRL0 0x00000000 44 #define AUART_CTRL0_SET 0x00000004 45 #define AUART_CTRL0_CLR 0x00000008 46 #define AUART_CTRL0_TOG 0x0000000c 47 #define AUART_CTRL1 0x00000010 48 #define AUART_CTRL1_SET 0x00000014 49 #define AUART_CTRL1_CLR 0x00000018 50 #define AUART_CTRL1_TOG 0x0000001c 51 #define AUART_CTRL2 0x00000020 52 #define AUART_CTRL2_SET 0x00000024 53 #define AUART_CTRL2_CLR 0x00000028 54 #define AUART_CTRL2_TOG 0x0000002c 55 #define AUART_LINECTRL 0x00000030 56 #define AUART_LINECTRL_SET 0x00000034 57 #define AUART_LINECTRL_CLR 0x00000038 58 #define AUART_LINECTRL_TOG 0x0000003c 59 #define AUART_LINECTRL2 0x00000040 60 #define AUART_LINECTRL2_SET 0x00000044 61 #define AUART_LINECTRL2_CLR 0x00000048 62 #define AUART_LINECTRL2_TOG 0x0000004c 63 #define AUART_INTR 0x00000050 64 #define AUART_INTR_SET 0x00000054 65 #define AUART_INTR_CLR 0x00000058 66 #define AUART_INTR_TOG 0x0000005c 67 #define AUART_DATA 0x00000060 68 #define AUART_STAT 0x00000070 69 #define AUART_DEBUG 0x00000080 70 #define AUART_VERSION 0x00000090 71 #define AUART_AUTOBAUD 0x000000a0 72 73 #define AUART_CTRL0_SFTRST (1 << 31) 74 #define AUART_CTRL0_CLKGATE (1 << 30) 75 #define AUART_CTRL0_RXTO_ENABLE (1 << 27) 76 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) 77 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) 78 79 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) 80 81 #define AUART_CTRL2_DMAONERR (1 << 26) 82 #define AUART_CTRL2_TXDMAE (1 << 25) 83 #define AUART_CTRL2_RXDMAE (1 << 24) 84 85 #define AUART_CTRL2_CTSEN (1 << 15) 86 #define AUART_CTRL2_RTSEN (1 << 14) 87 #define AUART_CTRL2_RTS (1 << 11) 88 #define AUART_CTRL2_RXE (1 << 9) 89 #define AUART_CTRL2_TXE (1 << 8) 90 #define AUART_CTRL2_UARTEN (1 << 0) 91 92 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 93 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 94 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) 95 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 96 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 97 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) 98 #define AUART_LINECTRL_WLEN_MASK 0x00000060 99 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) 100 #define AUART_LINECTRL_FEN (1 << 4) 101 #define AUART_LINECTRL_STP2 (1 << 3) 102 #define AUART_LINECTRL_EPS (1 << 2) 103 #define AUART_LINECTRL_PEN (1 << 1) 104 #define AUART_LINECTRL_BRK (1 << 0) 105 106 #define AUART_INTR_RTIEN (1 << 22) 107 #define AUART_INTR_TXIEN (1 << 21) 108 #define AUART_INTR_RXIEN (1 << 20) 109 #define AUART_INTR_CTSMIEN (1 << 17) 110 #define AUART_INTR_RTIS (1 << 6) 111 #define AUART_INTR_TXIS (1 << 5) 112 #define AUART_INTR_RXIS (1 << 4) 113 #define AUART_INTR_CTSMIS (1 << 1) 114 115 #define AUART_STAT_BUSY (1 << 29) 116 #define AUART_STAT_CTS (1 << 28) 117 #define AUART_STAT_TXFE (1 << 27) 118 #define AUART_STAT_TXFF (1 << 25) 119 #define AUART_STAT_RXFE (1 << 24) 120 #define AUART_STAT_OERR (1 << 19) 121 #define AUART_STAT_BERR (1 << 18) 122 #define AUART_STAT_PERR (1 << 17) 123 #define AUART_STAT_FERR (1 << 16) 124 #define AUART_STAT_RXCOUNT_MASK 0xffff 125 126 static struct uart_driver auart_driver; 127 128 enum mxs_auart_type { 129 IMX23_AUART, 130 IMX28_AUART, 131 }; 132 133 struct mxs_auart_port { 134 struct uart_port port; 135 136 #define MXS_AUART_DMA_ENABLED 0x2 137 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ 138 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ 139 #define MXS_AUART_RTSCTS 4 /* bit 4 */ 140 unsigned long flags; 141 unsigned int ctrl; 142 enum mxs_auart_type devtype; 143 144 unsigned int irq; 145 146 struct clk *clk; 147 struct device *dev; 148 149 /* for DMA */ 150 struct scatterlist tx_sgl; 151 struct dma_chan *tx_dma_chan; 152 void *tx_dma_buf; 153 154 struct scatterlist rx_sgl; 155 struct dma_chan *rx_dma_chan; 156 void *rx_dma_buf; 157 }; 158 159 static struct platform_device_id mxs_auart_devtype[] = { 160 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART }, 161 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART }, 162 { /* sentinel */ } 163 }; 164 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); 165 166 static struct of_device_id mxs_auart_dt_ids[] = { 167 { 168 .compatible = "fsl,imx28-auart", 169 .data = &mxs_auart_devtype[IMX28_AUART] 170 }, { 171 .compatible = "fsl,imx23-auart", 172 .data = &mxs_auart_devtype[IMX23_AUART] 173 }, { /* sentinel */ } 174 }; 175 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); 176 177 static inline int is_imx28_auart(struct mxs_auart_port *s) 178 { 179 return s->devtype == IMX28_AUART; 180 } 181 182 static inline bool auart_dma_enabled(struct mxs_auart_port *s) 183 { 184 return s->flags & MXS_AUART_DMA_ENABLED; 185 } 186 187 static void mxs_auart_stop_tx(struct uart_port *u); 188 189 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) 190 191 static void mxs_auart_tx_chars(struct mxs_auart_port *s); 192 193 static void dma_tx_callback(void *param) 194 { 195 struct mxs_auart_port *s = param; 196 struct circ_buf *xmit = &s->port.state->xmit; 197 198 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); 199 200 /* clear the bit used to serialize the DMA tx. */ 201 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 202 smp_mb__after_clear_bit(); 203 204 /* wake up the possible processes. */ 205 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 206 uart_write_wakeup(&s->port); 207 208 mxs_auart_tx_chars(s); 209 } 210 211 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) 212 { 213 struct dma_async_tx_descriptor *desc; 214 struct scatterlist *sgl = &s->tx_sgl; 215 struct dma_chan *channel = s->tx_dma_chan; 216 u32 pio; 217 218 /* [1] : send PIO. Note, the first pio word is CTRL1. */ 219 pio = AUART_CTRL1_XFER_COUNT(size); 220 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, 221 1, DMA_TRANS_NONE, 0); 222 if (!desc) { 223 dev_err(s->dev, "step 1 error\n"); 224 return -EINVAL; 225 } 226 227 /* [2] : set DMA buffer. */ 228 sg_init_one(sgl, s->tx_dma_buf, size); 229 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); 230 desc = dmaengine_prep_slave_sg(channel, sgl, 231 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 232 if (!desc) { 233 dev_err(s->dev, "step 2 error\n"); 234 return -EINVAL; 235 } 236 237 /* [3] : submit the DMA */ 238 desc->callback = dma_tx_callback; 239 desc->callback_param = s; 240 dmaengine_submit(desc); 241 dma_async_issue_pending(channel); 242 return 0; 243 } 244 245 static void mxs_auart_tx_chars(struct mxs_auart_port *s) 246 { 247 struct circ_buf *xmit = &s->port.state->xmit; 248 249 if (auart_dma_enabled(s)) { 250 u32 i = 0; 251 int size; 252 void *buffer = s->tx_dma_buf; 253 254 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) 255 return; 256 257 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 258 size = min_t(u32, UART_XMIT_SIZE - i, 259 CIRC_CNT_TO_END(xmit->head, 260 xmit->tail, 261 UART_XMIT_SIZE)); 262 memcpy(buffer + i, xmit->buf + xmit->tail, size); 263 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); 264 265 i += size; 266 if (i >= UART_XMIT_SIZE) 267 break; 268 } 269 270 if (uart_tx_stopped(&s->port)) 271 mxs_auart_stop_tx(&s->port); 272 273 if (i) { 274 mxs_auart_dma_tx(s, i); 275 } else { 276 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 277 smp_mb__after_clear_bit(); 278 } 279 return; 280 } 281 282 283 while (!(readl(s->port.membase + AUART_STAT) & 284 AUART_STAT_TXFF)) { 285 if (s->port.x_char) { 286 s->port.icount.tx++; 287 writel(s->port.x_char, 288 s->port.membase + AUART_DATA); 289 s->port.x_char = 0; 290 continue; 291 } 292 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 293 s->port.icount.tx++; 294 writel(xmit->buf[xmit->tail], 295 s->port.membase + AUART_DATA); 296 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 297 } else 298 break; 299 } 300 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 301 uart_write_wakeup(&s->port); 302 303 if (uart_circ_empty(&(s->port.state->xmit))) 304 writel(AUART_INTR_TXIEN, 305 s->port.membase + AUART_INTR_CLR); 306 else 307 writel(AUART_INTR_TXIEN, 308 s->port.membase + AUART_INTR_SET); 309 310 if (uart_tx_stopped(&s->port)) 311 mxs_auart_stop_tx(&s->port); 312 } 313 314 static void mxs_auart_rx_char(struct mxs_auart_port *s) 315 { 316 int flag; 317 u32 stat; 318 u8 c; 319 320 c = readl(s->port.membase + AUART_DATA); 321 stat = readl(s->port.membase + AUART_STAT); 322 323 flag = TTY_NORMAL; 324 s->port.icount.rx++; 325 326 if (stat & AUART_STAT_BERR) { 327 s->port.icount.brk++; 328 if (uart_handle_break(&s->port)) 329 goto out; 330 } else if (stat & AUART_STAT_PERR) { 331 s->port.icount.parity++; 332 } else if (stat & AUART_STAT_FERR) { 333 s->port.icount.frame++; 334 } 335 336 /* 337 * Mask off conditions which should be ingored. 338 */ 339 stat &= s->port.read_status_mask; 340 341 if (stat & AUART_STAT_BERR) { 342 flag = TTY_BREAK; 343 } else if (stat & AUART_STAT_PERR) 344 flag = TTY_PARITY; 345 else if (stat & AUART_STAT_FERR) 346 flag = TTY_FRAME; 347 348 if (stat & AUART_STAT_OERR) 349 s->port.icount.overrun++; 350 351 if (uart_handle_sysrq_char(&s->port, c)) 352 goto out; 353 354 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); 355 out: 356 writel(stat, s->port.membase + AUART_STAT); 357 } 358 359 static void mxs_auart_rx_chars(struct mxs_auart_port *s) 360 { 361 u32 stat = 0; 362 363 for (;;) { 364 stat = readl(s->port.membase + AUART_STAT); 365 if (stat & AUART_STAT_RXFE) 366 break; 367 mxs_auart_rx_char(s); 368 } 369 370 writel(stat, s->port.membase + AUART_STAT); 371 tty_flip_buffer_push(&s->port.state->port); 372 } 373 374 static int mxs_auart_request_port(struct uart_port *u) 375 { 376 return 0; 377 } 378 379 static int mxs_auart_verify_port(struct uart_port *u, 380 struct serial_struct *ser) 381 { 382 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) 383 return -EINVAL; 384 return 0; 385 } 386 387 static void mxs_auart_config_port(struct uart_port *u, int flags) 388 { 389 } 390 391 static const char *mxs_auart_type(struct uart_port *u) 392 { 393 struct mxs_auart_port *s = to_auart_port(u); 394 395 return dev_name(s->dev); 396 } 397 398 static void mxs_auart_release_port(struct uart_port *u) 399 { 400 } 401 402 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) 403 { 404 struct mxs_auart_port *s = to_auart_port(u); 405 406 u32 ctrl = readl(u->membase + AUART_CTRL2); 407 408 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS); 409 if (mctrl & TIOCM_RTS) { 410 if (tty_port_cts_enabled(&u->state->port)) 411 ctrl |= AUART_CTRL2_RTSEN; 412 else 413 ctrl |= AUART_CTRL2_RTS; 414 } 415 416 s->ctrl = mctrl; 417 writel(ctrl, u->membase + AUART_CTRL2); 418 } 419 420 static u32 mxs_auart_get_mctrl(struct uart_port *u) 421 { 422 struct mxs_auart_port *s = to_auart_port(u); 423 u32 stat = readl(u->membase + AUART_STAT); 424 int ctrl2 = readl(u->membase + AUART_CTRL2); 425 u32 mctrl = s->ctrl; 426 427 mctrl &= ~TIOCM_CTS; 428 if (stat & AUART_STAT_CTS) 429 mctrl |= TIOCM_CTS; 430 431 if (ctrl2 & AUART_CTRL2_RTS) 432 mctrl |= TIOCM_RTS; 433 434 return mctrl; 435 } 436 437 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); 438 static void dma_rx_callback(void *arg) 439 { 440 struct mxs_auart_port *s = (struct mxs_auart_port *) arg; 441 struct tty_port *port = &s->port.state->port; 442 int count; 443 u32 stat; 444 445 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); 446 447 stat = readl(s->port.membase + AUART_STAT); 448 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | 449 AUART_STAT_PERR | AUART_STAT_FERR); 450 451 count = stat & AUART_STAT_RXCOUNT_MASK; 452 tty_insert_flip_string(port, s->rx_dma_buf, count); 453 454 writel(stat, s->port.membase + AUART_STAT); 455 tty_flip_buffer_push(port); 456 457 /* start the next DMA for RX. */ 458 mxs_auart_dma_prep_rx(s); 459 } 460 461 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) 462 { 463 struct dma_async_tx_descriptor *desc; 464 struct scatterlist *sgl = &s->rx_sgl; 465 struct dma_chan *channel = s->rx_dma_chan; 466 u32 pio[1]; 467 468 /* [1] : send PIO */ 469 pio[0] = AUART_CTRL0_RXTO_ENABLE 470 | AUART_CTRL0_RXTIMEOUT(0x80) 471 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); 472 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, 473 1, DMA_TRANS_NONE, 0); 474 if (!desc) { 475 dev_err(s->dev, "step 1 error\n"); 476 return -EINVAL; 477 } 478 479 /* [2] : send DMA request */ 480 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); 481 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); 482 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, 483 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 484 if (!desc) { 485 dev_err(s->dev, "step 2 error\n"); 486 return -1; 487 } 488 489 /* [3] : submit the DMA, but do not issue it. */ 490 desc->callback = dma_rx_callback; 491 desc->callback_param = s; 492 dmaengine_submit(desc); 493 dma_async_issue_pending(channel); 494 return 0; 495 } 496 497 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) 498 { 499 if (s->tx_dma_chan) { 500 dma_release_channel(s->tx_dma_chan); 501 s->tx_dma_chan = NULL; 502 } 503 if (s->rx_dma_chan) { 504 dma_release_channel(s->rx_dma_chan); 505 s->rx_dma_chan = NULL; 506 } 507 508 kfree(s->tx_dma_buf); 509 kfree(s->rx_dma_buf); 510 s->tx_dma_buf = NULL; 511 s->rx_dma_buf = NULL; 512 } 513 514 static void mxs_auart_dma_exit(struct mxs_auart_port *s) 515 { 516 517 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, 518 s->port.membase + AUART_CTRL2_CLR); 519 520 mxs_auart_dma_exit_channel(s); 521 s->flags &= ~MXS_AUART_DMA_ENABLED; 522 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 523 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); 524 } 525 526 static int mxs_auart_dma_init(struct mxs_auart_port *s) 527 { 528 if (auart_dma_enabled(s)) 529 return 0; 530 531 /* init for RX */ 532 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx"); 533 if (!s->rx_dma_chan) 534 goto err_out; 535 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 536 if (!s->rx_dma_buf) 537 goto err_out; 538 539 /* init for TX */ 540 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx"); 541 if (!s->tx_dma_chan) 542 goto err_out; 543 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 544 if (!s->tx_dma_buf) 545 goto err_out; 546 547 /* set the flags */ 548 s->flags |= MXS_AUART_DMA_ENABLED; 549 dev_dbg(s->dev, "enabled the DMA support."); 550 551 return 0; 552 553 err_out: 554 mxs_auart_dma_exit_channel(s); 555 return -EINVAL; 556 557 } 558 559 static void mxs_auart_settermios(struct uart_port *u, 560 struct ktermios *termios, 561 struct ktermios *old) 562 { 563 struct mxs_auart_port *s = to_auart_port(u); 564 u32 bm, ctrl, ctrl2, div; 565 unsigned int cflag, baud; 566 567 cflag = termios->c_cflag; 568 569 ctrl = AUART_LINECTRL_FEN; 570 ctrl2 = readl(u->membase + AUART_CTRL2); 571 572 /* byte size */ 573 switch (cflag & CSIZE) { 574 case CS5: 575 bm = 0; 576 break; 577 case CS6: 578 bm = 1; 579 break; 580 case CS7: 581 bm = 2; 582 break; 583 case CS8: 584 bm = 3; 585 break; 586 default: 587 return; 588 } 589 590 ctrl |= AUART_LINECTRL_WLEN(bm); 591 592 /* parity */ 593 if (cflag & PARENB) { 594 ctrl |= AUART_LINECTRL_PEN; 595 if ((cflag & PARODD) == 0) 596 ctrl |= AUART_LINECTRL_EPS; 597 } 598 599 u->read_status_mask = 0; 600 601 if (termios->c_iflag & INPCK) 602 u->read_status_mask |= AUART_STAT_PERR; 603 if (termios->c_iflag & (BRKINT | PARMRK)) 604 u->read_status_mask |= AUART_STAT_BERR; 605 606 /* 607 * Characters to ignore 608 */ 609 u->ignore_status_mask = 0; 610 if (termios->c_iflag & IGNPAR) 611 u->ignore_status_mask |= AUART_STAT_PERR; 612 if (termios->c_iflag & IGNBRK) { 613 u->ignore_status_mask |= AUART_STAT_BERR; 614 /* 615 * If we're ignoring parity and break indicators, 616 * ignore overruns too (for real raw support). 617 */ 618 if (termios->c_iflag & IGNPAR) 619 u->ignore_status_mask |= AUART_STAT_OERR; 620 } 621 622 /* 623 * ignore all characters if CREAD is not set 624 */ 625 if (cflag & CREAD) 626 ctrl2 |= AUART_CTRL2_RXE; 627 else 628 ctrl2 &= ~AUART_CTRL2_RXE; 629 630 /* figure out the stop bits requested */ 631 if (cflag & CSTOPB) 632 ctrl |= AUART_LINECTRL_STP2; 633 634 /* figure out the hardware flow control settings */ 635 if (cflag & CRTSCTS) { 636 /* 637 * The DMA has a bug(see errata:2836) in mx23. 638 * So we can not implement the DMA for auart in mx23, 639 * we can only implement the DMA support for auart 640 * in mx28. 641 */ 642 if (is_imx28_auart(s) 643 && test_bit(MXS_AUART_RTSCTS, &s->flags)) { 644 if (!mxs_auart_dma_init(s)) 645 /* enable DMA tranfer */ 646 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE 647 | AUART_CTRL2_DMAONERR; 648 } 649 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN; 650 } else { 651 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); 652 } 653 654 /* set baud rate */ 655 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); 656 div = u->uartclk * 32 / baud; 657 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); 658 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); 659 660 writel(ctrl, u->membase + AUART_LINECTRL); 661 writel(ctrl2, u->membase + AUART_CTRL2); 662 663 uart_update_timeout(u, termios->c_cflag, baud); 664 665 /* prepare for the DMA RX. */ 666 if (auart_dma_enabled(s) && 667 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { 668 if (!mxs_auart_dma_prep_rx(s)) { 669 /* Disable the normal RX interrupt. */ 670 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN, 671 u->membase + AUART_INTR_CLR); 672 } else { 673 mxs_auart_dma_exit(s); 674 dev_err(s->dev, "We can not start up the DMA.\n"); 675 } 676 } 677 } 678 679 static irqreturn_t mxs_auart_irq_handle(int irq, void *context) 680 { 681 u32 istat; 682 struct mxs_auart_port *s = context; 683 u32 stat = readl(s->port.membase + AUART_STAT); 684 685 istat = readl(s->port.membase + AUART_INTR); 686 687 /* ack irq */ 688 writel(istat & (AUART_INTR_RTIS 689 | AUART_INTR_TXIS 690 | AUART_INTR_RXIS 691 | AUART_INTR_CTSMIS), 692 s->port.membase + AUART_INTR_CLR); 693 694 if (istat & AUART_INTR_CTSMIS) { 695 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS); 696 writel(AUART_INTR_CTSMIS, 697 s->port.membase + AUART_INTR_CLR); 698 istat &= ~AUART_INTR_CTSMIS; 699 } 700 701 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { 702 if (!auart_dma_enabled(s)) 703 mxs_auart_rx_chars(s); 704 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); 705 } 706 707 if (istat & AUART_INTR_TXIS) { 708 mxs_auart_tx_chars(s); 709 istat &= ~AUART_INTR_TXIS; 710 } 711 712 return IRQ_HANDLED; 713 } 714 715 static void mxs_auart_reset(struct uart_port *u) 716 { 717 int i; 718 unsigned int reg; 719 720 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR); 721 722 for (i = 0; i < 10000; i++) { 723 reg = readl(u->membase + AUART_CTRL0); 724 if (!(reg & AUART_CTRL0_SFTRST)) 725 break; 726 udelay(3); 727 } 728 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 729 } 730 731 static int mxs_auart_startup(struct uart_port *u) 732 { 733 struct mxs_auart_port *s = to_auart_port(u); 734 735 clk_prepare_enable(s->clk); 736 737 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 738 739 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET); 740 741 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 742 u->membase + AUART_INTR); 743 744 /* 745 * Enable fifo so all four bytes of a DMA word are written to 746 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) 747 */ 748 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET); 749 750 return 0; 751 } 752 753 static void mxs_auart_shutdown(struct uart_port *u) 754 { 755 struct mxs_auart_port *s = to_auart_port(u); 756 757 if (auart_dma_enabled(s)) 758 mxs_auart_dma_exit(s); 759 760 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); 761 762 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 763 u->membase + AUART_INTR_CLR); 764 765 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET); 766 767 clk_disable_unprepare(s->clk); 768 } 769 770 static unsigned int mxs_auart_tx_empty(struct uart_port *u) 771 { 772 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE) 773 return TIOCSER_TEMT; 774 else 775 return 0; 776 } 777 778 static void mxs_auart_start_tx(struct uart_port *u) 779 { 780 struct mxs_auart_port *s = to_auart_port(u); 781 782 /* enable transmitter */ 783 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET); 784 785 mxs_auart_tx_chars(s); 786 } 787 788 static void mxs_auart_stop_tx(struct uart_port *u) 789 { 790 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR); 791 } 792 793 static void mxs_auart_stop_rx(struct uart_port *u) 794 { 795 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR); 796 } 797 798 static void mxs_auart_break_ctl(struct uart_port *u, int ctl) 799 { 800 if (ctl) 801 writel(AUART_LINECTRL_BRK, 802 u->membase + AUART_LINECTRL_SET); 803 else 804 writel(AUART_LINECTRL_BRK, 805 u->membase + AUART_LINECTRL_CLR); 806 } 807 808 static void mxs_auart_enable_ms(struct uart_port *port) 809 { 810 /* just empty */ 811 } 812 813 static struct uart_ops mxs_auart_ops = { 814 .tx_empty = mxs_auart_tx_empty, 815 .start_tx = mxs_auart_start_tx, 816 .stop_tx = mxs_auart_stop_tx, 817 .stop_rx = mxs_auart_stop_rx, 818 .enable_ms = mxs_auart_enable_ms, 819 .break_ctl = mxs_auart_break_ctl, 820 .set_mctrl = mxs_auart_set_mctrl, 821 .get_mctrl = mxs_auart_get_mctrl, 822 .startup = mxs_auart_startup, 823 .shutdown = mxs_auart_shutdown, 824 .set_termios = mxs_auart_settermios, 825 .type = mxs_auart_type, 826 .release_port = mxs_auart_release_port, 827 .request_port = mxs_auart_request_port, 828 .config_port = mxs_auart_config_port, 829 .verify_port = mxs_auart_verify_port, 830 }; 831 832 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; 833 834 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 835 static void mxs_auart_console_putchar(struct uart_port *port, int ch) 836 { 837 unsigned int to = 1000; 838 839 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) { 840 if (!to--) 841 break; 842 udelay(1); 843 } 844 845 writel(ch, port->membase + AUART_DATA); 846 } 847 848 static void 849 auart_console_write(struct console *co, const char *str, unsigned int count) 850 { 851 struct mxs_auart_port *s; 852 struct uart_port *port; 853 unsigned int old_ctrl0, old_ctrl2; 854 unsigned int to = 20000; 855 856 if (co->index >= MXS_AUART_PORTS || co->index < 0) 857 return; 858 859 s = auart_port[co->index]; 860 port = &s->port; 861 862 clk_enable(s->clk); 863 864 /* First save the CR then disable the interrupts */ 865 old_ctrl2 = readl(port->membase + AUART_CTRL2); 866 old_ctrl0 = readl(port->membase + AUART_CTRL0); 867 868 writel(AUART_CTRL0_CLKGATE, 869 port->membase + AUART_CTRL0_CLR); 870 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, 871 port->membase + AUART_CTRL2_SET); 872 873 uart_console_write(port, str, count, mxs_auart_console_putchar); 874 875 /* Finally, wait for transmitter to become empty ... */ 876 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) { 877 udelay(1); 878 if (!to--) 879 break; 880 } 881 882 /* 883 * ... and restore the TCR if we waited long enough for the transmitter 884 * to be idle. This might keep the transmitter enabled although it is 885 * unused, but that is better than to disable it while it is still 886 * transmitting. 887 */ 888 if (!(readl(port->membase + AUART_STAT) & AUART_STAT_BUSY)) { 889 writel(old_ctrl0, port->membase + AUART_CTRL0); 890 writel(old_ctrl2, port->membase + AUART_CTRL2); 891 } 892 893 clk_disable(s->clk); 894 } 895 896 static void __init 897 auart_console_get_options(struct uart_port *port, int *baud, 898 int *parity, int *bits) 899 { 900 unsigned int lcr_h, quot; 901 902 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN)) 903 return; 904 905 lcr_h = readl(port->membase + AUART_LINECTRL); 906 907 *parity = 'n'; 908 if (lcr_h & AUART_LINECTRL_PEN) { 909 if (lcr_h & AUART_LINECTRL_EPS) 910 *parity = 'e'; 911 else 912 *parity = 'o'; 913 } 914 915 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) 916 *bits = 7; 917 else 918 *bits = 8; 919 920 quot = ((readl(port->membase + AUART_LINECTRL) 921 & AUART_LINECTRL_BAUD_DIVINT_MASK)) 922 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); 923 quot |= ((readl(port->membase + AUART_LINECTRL) 924 & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) 925 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; 926 if (quot == 0) 927 quot = 1; 928 929 *baud = (port->uartclk << 2) / quot; 930 } 931 932 static int __init 933 auart_console_setup(struct console *co, char *options) 934 { 935 struct mxs_auart_port *s; 936 int baud = 9600; 937 int bits = 8; 938 int parity = 'n'; 939 int flow = 'n'; 940 int ret; 941 942 /* 943 * Check whether an invalid uart number has been specified, and 944 * if so, search for the first available port that does have 945 * console support. 946 */ 947 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) 948 co->index = 0; 949 s = auart_port[co->index]; 950 if (!s) 951 return -ENODEV; 952 953 clk_prepare_enable(s->clk); 954 955 if (options) 956 uart_parse_options(options, &baud, &parity, &bits, &flow); 957 else 958 auart_console_get_options(&s->port, &baud, &parity, &bits); 959 960 ret = uart_set_options(&s->port, co, baud, parity, bits, flow); 961 962 clk_disable_unprepare(s->clk); 963 964 return ret; 965 } 966 967 static struct console auart_console = { 968 .name = "ttyAPP", 969 .write = auart_console_write, 970 .device = uart_console_device, 971 .setup = auart_console_setup, 972 .flags = CON_PRINTBUFFER, 973 .index = -1, 974 .data = &auart_driver, 975 }; 976 #endif 977 978 static struct uart_driver auart_driver = { 979 .owner = THIS_MODULE, 980 .driver_name = "ttyAPP", 981 .dev_name = "ttyAPP", 982 .major = 0, 983 .minor = 0, 984 .nr = MXS_AUART_PORTS, 985 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 986 .cons = &auart_console, 987 #endif 988 }; 989 990 /* 991 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it 992 * could successfully get all information from dt or a negative errno. 993 */ 994 static int serial_mxs_probe_dt(struct mxs_auart_port *s, 995 struct platform_device *pdev) 996 { 997 struct device_node *np = pdev->dev.of_node; 998 int ret; 999 1000 if (!np) 1001 /* no device tree device */ 1002 return 1; 1003 1004 ret = of_alias_get_id(np, "serial"); 1005 if (ret < 0) { 1006 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); 1007 return ret; 1008 } 1009 s->port.line = ret; 1010 1011 if (of_get_property(np, "fsl,uart-has-rtscts", NULL)) 1012 set_bit(MXS_AUART_RTSCTS, &s->flags); 1013 1014 return 0; 1015 } 1016 1017 static int mxs_auart_probe(struct platform_device *pdev) 1018 { 1019 const struct of_device_id *of_id = 1020 of_match_device(mxs_auart_dt_ids, &pdev->dev); 1021 struct mxs_auart_port *s; 1022 u32 version; 1023 int ret = 0; 1024 struct resource *r; 1025 1026 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); 1027 if (!s) { 1028 ret = -ENOMEM; 1029 goto out; 1030 } 1031 1032 ret = serial_mxs_probe_dt(s, pdev); 1033 if (ret > 0) 1034 s->port.line = pdev->id < 0 ? 0 : pdev->id; 1035 else if (ret < 0) 1036 goto out_free; 1037 1038 if (of_id) { 1039 pdev->id_entry = of_id->data; 1040 s->devtype = pdev->id_entry->driver_data; 1041 } 1042 1043 s->clk = clk_get(&pdev->dev, NULL); 1044 if (IS_ERR(s->clk)) { 1045 ret = PTR_ERR(s->clk); 1046 goto out_free; 1047 } 1048 1049 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1050 if (!r) { 1051 ret = -ENXIO; 1052 goto out_free_clk; 1053 } 1054 1055 s->port.mapbase = r->start; 1056 s->port.membase = ioremap(r->start, resource_size(r)); 1057 s->port.ops = &mxs_auart_ops; 1058 s->port.iotype = UPIO_MEM; 1059 s->port.fifosize = 16; 1060 s->port.uartclk = clk_get_rate(s->clk); 1061 s->port.type = PORT_IMX; 1062 s->port.dev = s->dev = &pdev->dev; 1063 1064 s->ctrl = 0; 1065 1066 s->irq = platform_get_irq(pdev, 0); 1067 s->port.irq = s->irq; 1068 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s); 1069 if (ret) 1070 goto out_free_clk; 1071 1072 platform_set_drvdata(pdev, s); 1073 1074 auart_port[s->port.line] = s; 1075 1076 mxs_auart_reset(&s->port); 1077 1078 ret = uart_add_one_port(&auart_driver, &s->port); 1079 if (ret) 1080 goto out_free_irq; 1081 1082 version = readl(s->port.membase + AUART_VERSION); 1083 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", 1084 (version >> 24) & 0xff, 1085 (version >> 16) & 0xff, version & 0xffff); 1086 1087 return 0; 1088 1089 out_free_irq: 1090 auart_port[pdev->id] = NULL; 1091 free_irq(s->irq, s); 1092 out_free_clk: 1093 clk_put(s->clk); 1094 out_free: 1095 kfree(s); 1096 out: 1097 return ret; 1098 } 1099 1100 static int mxs_auart_remove(struct platform_device *pdev) 1101 { 1102 struct mxs_auart_port *s = platform_get_drvdata(pdev); 1103 1104 uart_remove_one_port(&auart_driver, &s->port); 1105 1106 auart_port[pdev->id] = NULL; 1107 1108 clk_put(s->clk); 1109 free_irq(s->irq, s); 1110 kfree(s); 1111 1112 return 0; 1113 } 1114 1115 static struct platform_driver mxs_auart_driver = { 1116 .probe = mxs_auart_probe, 1117 .remove = mxs_auart_remove, 1118 .driver = { 1119 .name = "mxs-auart", 1120 .owner = THIS_MODULE, 1121 .of_match_table = mxs_auart_dt_ids, 1122 }, 1123 }; 1124 1125 static int __init mxs_auart_init(void) 1126 { 1127 int r; 1128 1129 r = uart_register_driver(&auart_driver); 1130 if (r) 1131 goto out; 1132 1133 r = platform_driver_register(&mxs_auart_driver); 1134 if (r) 1135 goto out_err; 1136 1137 return 0; 1138 out_err: 1139 uart_unregister_driver(&auart_driver); 1140 out: 1141 return r; 1142 } 1143 1144 static void __exit mxs_auart_exit(void) 1145 { 1146 platform_driver_unregister(&mxs_auart_driver); 1147 uart_unregister_driver(&auart_driver); 1148 } 1149 1150 module_init(mxs_auart_init); 1151 module_exit(mxs_auart_exit); 1152 MODULE_LICENSE("GPL"); 1153 MODULE_DESCRIPTION("Freescale MXS application uart driver"); 1154 MODULE_ALIAS("platform:mxs-auart"); 1155