1 /* 2 * Freescale STMP37XX/STMP378X Application UART driver 3 * 4 * Author: dmitry pervushin <dimka@embeddedalley.com> 5 * 6 * Copyright 2008-2010 Freescale Semiconductor, Inc. 7 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 8 * 9 * The code contained herein is licensed under the GNU General Public 10 * License. You may obtain a copy of the GNU General Public License 11 * Version 2 or later at the following locations: 12 * 13 * http://www.opensource.org/licenses/gpl-license.html 14 * http://www.gnu.org/copyleft/gpl.html 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/console.h> 21 #include <linux/interrupt.h> 22 #include <linux/module.h> 23 #include <linux/slab.h> 24 #include <linux/wait.h> 25 #include <linux/tty.h> 26 #include <linux/tty_driver.h> 27 #include <linux/tty_flip.h> 28 #include <linux/serial.h> 29 #include <linux/serial_core.h> 30 #include <linux/platform_device.h> 31 #include <linux/device.h> 32 #include <linux/clk.h> 33 #include <linux/delay.h> 34 #include <linux/io.h> 35 #include <linux/pinctrl/consumer.h> 36 #include <linux/of_device.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/fsl/mxs-dma.h> 39 40 #include <asm/cacheflush.h> 41 42 #define MXS_AUART_PORTS 5 43 44 #define AUART_CTRL0 0x00000000 45 #define AUART_CTRL0_SET 0x00000004 46 #define AUART_CTRL0_CLR 0x00000008 47 #define AUART_CTRL0_TOG 0x0000000c 48 #define AUART_CTRL1 0x00000010 49 #define AUART_CTRL1_SET 0x00000014 50 #define AUART_CTRL1_CLR 0x00000018 51 #define AUART_CTRL1_TOG 0x0000001c 52 #define AUART_CTRL2 0x00000020 53 #define AUART_CTRL2_SET 0x00000024 54 #define AUART_CTRL2_CLR 0x00000028 55 #define AUART_CTRL2_TOG 0x0000002c 56 #define AUART_LINECTRL 0x00000030 57 #define AUART_LINECTRL_SET 0x00000034 58 #define AUART_LINECTRL_CLR 0x00000038 59 #define AUART_LINECTRL_TOG 0x0000003c 60 #define AUART_LINECTRL2 0x00000040 61 #define AUART_LINECTRL2_SET 0x00000044 62 #define AUART_LINECTRL2_CLR 0x00000048 63 #define AUART_LINECTRL2_TOG 0x0000004c 64 #define AUART_INTR 0x00000050 65 #define AUART_INTR_SET 0x00000054 66 #define AUART_INTR_CLR 0x00000058 67 #define AUART_INTR_TOG 0x0000005c 68 #define AUART_DATA 0x00000060 69 #define AUART_STAT 0x00000070 70 #define AUART_DEBUG 0x00000080 71 #define AUART_VERSION 0x00000090 72 #define AUART_AUTOBAUD 0x000000a0 73 74 #define AUART_CTRL0_SFTRST (1 << 31) 75 #define AUART_CTRL0_CLKGATE (1 << 30) 76 #define AUART_CTRL0_RXTO_ENABLE (1 << 27) 77 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) 78 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) 79 80 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) 81 82 #define AUART_CTRL2_DMAONERR (1 << 26) 83 #define AUART_CTRL2_TXDMAE (1 << 25) 84 #define AUART_CTRL2_RXDMAE (1 << 24) 85 86 #define AUART_CTRL2_CTSEN (1 << 15) 87 #define AUART_CTRL2_RTSEN (1 << 14) 88 #define AUART_CTRL2_RTS (1 << 11) 89 #define AUART_CTRL2_RXE (1 << 9) 90 #define AUART_CTRL2_TXE (1 << 8) 91 #define AUART_CTRL2_UARTEN (1 << 0) 92 93 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 94 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 95 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) 96 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 97 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 98 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) 99 #define AUART_LINECTRL_WLEN_MASK 0x00000060 100 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) 101 #define AUART_LINECTRL_FEN (1 << 4) 102 #define AUART_LINECTRL_STP2 (1 << 3) 103 #define AUART_LINECTRL_EPS (1 << 2) 104 #define AUART_LINECTRL_PEN (1 << 1) 105 #define AUART_LINECTRL_BRK (1 << 0) 106 107 #define AUART_INTR_RTIEN (1 << 22) 108 #define AUART_INTR_TXIEN (1 << 21) 109 #define AUART_INTR_RXIEN (1 << 20) 110 #define AUART_INTR_CTSMIEN (1 << 17) 111 #define AUART_INTR_RTIS (1 << 6) 112 #define AUART_INTR_TXIS (1 << 5) 113 #define AUART_INTR_RXIS (1 << 4) 114 #define AUART_INTR_CTSMIS (1 << 1) 115 116 #define AUART_STAT_BUSY (1 << 29) 117 #define AUART_STAT_CTS (1 << 28) 118 #define AUART_STAT_TXFE (1 << 27) 119 #define AUART_STAT_TXFF (1 << 25) 120 #define AUART_STAT_RXFE (1 << 24) 121 #define AUART_STAT_OERR (1 << 19) 122 #define AUART_STAT_BERR (1 << 18) 123 #define AUART_STAT_PERR (1 << 17) 124 #define AUART_STAT_FERR (1 << 16) 125 #define AUART_STAT_RXCOUNT_MASK 0xffff 126 127 static struct uart_driver auart_driver; 128 129 enum mxs_auart_type { 130 IMX23_AUART, 131 IMX28_AUART, 132 }; 133 134 struct mxs_auart_port { 135 struct uart_port port; 136 137 #define MXS_AUART_DMA_CONFIG 0x1 138 #define MXS_AUART_DMA_ENABLED 0x2 139 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ 140 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ 141 unsigned long flags; 142 unsigned int ctrl; 143 enum mxs_auart_type devtype; 144 145 unsigned int irq; 146 147 struct clk *clk; 148 struct device *dev; 149 150 /* for DMA */ 151 struct mxs_dma_data dma_data; 152 int dma_channel_rx, dma_channel_tx; 153 int dma_irq_rx, dma_irq_tx; 154 int dma_channel; 155 156 struct scatterlist tx_sgl; 157 struct dma_chan *tx_dma_chan; 158 void *tx_dma_buf; 159 160 struct scatterlist rx_sgl; 161 struct dma_chan *rx_dma_chan; 162 void *rx_dma_buf; 163 }; 164 165 static struct platform_device_id mxs_auart_devtype[] = { 166 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART }, 167 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART }, 168 { /* sentinel */ } 169 }; 170 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); 171 172 static struct of_device_id mxs_auart_dt_ids[] = { 173 { 174 .compatible = "fsl,imx28-auart", 175 .data = &mxs_auart_devtype[IMX28_AUART] 176 }, { 177 .compatible = "fsl,imx23-auart", 178 .data = &mxs_auart_devtype[IMX23_AUART] 179 }, { /* sentinel */ } 180 }; 181 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); 182 183 static inline int is_imx28_auart(struct mxs_auart_port *s) 184 { 185 return s->devtype == IMX28_AUART; 186 } 187 188 static inline bool auart_dma_enabled(struct mxs_auart_port *s) 189 { 190 return s->flags & MXS_AUART_DMA_ENABLED; 191 } 192 193 static void mxs_auart_stop_tx(struct uart_port *u); 194 195 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) 196 197 static void mxs_auart_tx_chars(struct mxs_auart_port *s); 198 199 static void dma_tx_callback(void *param) 200 { 201 struct mxs_auart_port *s = param; 202 struct circ_buf *xmit = &s->port.state->xmit; 203 204 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); 205 206 /* clear the bit used to serialize the DMA tx. */ 207 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 208 smp_mb__after_clear_bit(); 209 210 /* wake up the possible processes. */ 211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 212 uart_write_wakeup(&s->port); 213 214 mxs_auart_tx_chars(s); 215 } 216 217 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) 218 { 219 struct dma_async_tx_descriptor *desc; 220 struct scatterlist *sgl = &s->tx_sgl; 221 struct dma_chan *channel = s->tx_dma_chan; 222 u32 pio; 223 224 /* [1] : send PIO. Note, the first pio word is CTRL1. */ 225 pio = AUART_CTRL1_XFER_COUNT(size); 226 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, 227 1, DMA_TRANS_NONE, 0); 228 if (!desc) { 229 dev_err(s->dev, "step 1 error\n"); 230 return -EINVAL; 231 } 232 233 /* [2] : set DMA buffer. */ 234 sg_init_one(sgl, s->tx_dma_buf, size); 235 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); 236 desc = dmaengine_prep_slave_sg(channel, sgl, 237 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 238 if (!desc) { 239 dev_err(s->dev, "step 2 error\n"); 240 return -EINVAL; 241 } 242 243 /* [3] : submit the DMA */ 244 desc->callback = dma_tx_callback; 245 desc->callback_param = s; 246 dmaengine_submit(desc); 247 dma_async_issue_pending(channel); 248 return 0; 249 } 250 251 static void mxs_auart_tx_chars(struct mxs_auart_port *s) 252 { 253 struct circ_buf *xmit = &s->port.state->xmit; 254 255 if (auart_dma_enabled(s)) { 256 u32 i = 0; 257 int size; 258 void *buffer = s->tx_dma_buf; 259 260 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) 261 return; 262 263 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 264 size = min_t(u32, UART_XMIT_SIZE - i, 265 CIRC_CNT_TO_END(xmit->head, 266 xmit->tail, 267 UART_XMIT_SIZE)); 268 memcpy(buffer + i, xmit->buf + xmit->tail, size); 269 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); 270 271 i += size; 272 if (i >= UART_XMIT_SIZE) 273 break; 274 } 275 276 if (uart_tx_stopped(&s->port)) 277 mxs_auart_stop_tx(&s->port); 278 279 if (i) { 280 mxs_auart_dma_tx(s, i); 281 } else { 282 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 283 smp_mb__after_clear_bit(); 284 } 285 return; 286 } 287 288 289 while (!(readl(s->port.membase + AUART_STAT) & 290 AUART_STAT_TXFF)) { 291 if (s->port.x_char) { 292 s->port.icount.tx++; 293 writel(s->port.x_char, 294 s->port.membase + AUART_DATA); 295 s->port.x_char = 0; 296 continue; 297 } 298 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 299 s->port.icount.tx++; 300 writel(xmit->buf[xmit->tail], 301 s->port.membase + AUART_DATA); 302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 303 } else 304 break; 305 } 306 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 307 uart_write_wakeup(&s->port); 308 309 if (uart_circ_empty(&(s->port.state->xmit))) 310 writel(AUART_INTR_TXIEN, 311 s->port.membase + AUART_INTR_CLR); 312 else 313 writel(AUART_INTR_TXIEN, 314 s->port.membase + AUART_INTR_SET); 315 316 if (uart_tx_stopped(&s->port)) 317 mxs_auart_stop_tx(&s->port); 318 } 319 320 static void mxs_auart_rx_char(struct mxs_auart_port *s) 321 { 322 int flag; 323 u32 stat; 324 u8 c; 325 326 c = readl(s->port.membase + AUART_DATA); 327 stat = readl(s->port.membase + AUART_STAT); 328 329 flag = TTY_NORMAL; 330 s->port.icount.rx++; 331 332 if (stat & AUART_STAT_BERR) { 333 s->port.icount.brk++; 334 if (uart_handle_break(&s->port)) 335 goto out; 336 } else if (stat & AUART_STAT_PERR) { 337 s->port.icount.parity++; 338 } else if (stat & AUART_STAT_FERR) { 339 s->port.icount.frame++; 340 } 341 342 /* 343 * Mask off conditions which should be ingored. 344 */ 345 stat &= s->port.read_status_mask; 346 347 if (stat & AUART_STAT_BERR) { 348 flag = TTY_BREAK; 349 } else if (stat & AUART_STAT_PERR) 350 flag = TTY_PARITY; 351 else if (stat & AUART_STAT_FERR) 352 flag = TTY_FRAME; 353 354 if (stat & AUART_STAT_OERR) 355 s->port.icount.overrun++; 356 357 if (uart_handle_sysrq_char(&s->port, c)) 358 goto out; 359 360 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); 361 out: 362 writel(stat, s->port.membase + AUART_STAT); 363 } 364 365 static void mxs_auart_rx_chars(struct mxs_auart_port *s) 366 { 367 struct tty_struct *tty = s->port.state->port.tty; 368 u32 stat = 0; 369 370 for (;;) { 371 stat = readl(s->port.membase + AUART_STAT); 372 if (stat & AUART_STAT_RXFE) 373 break; 374 mxs_auart_rx_char(s); 375 } 376 377 writel(stat, s->port.membase + AUART_STAT); 378 tty_flip_buffer_push(tty); 379 } 380 381 static int mxs_auart_request_port(struct uart_port *u) 382 { 383 return 0; 384 } 385 386 static int mxs_auart_verify_port(struct uart_port *u, 387 struct serial_struct *ser) 388 { 389 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) 390 return -EINVAL; 391 return 0; 392 } 393 394 static void mxs_auart_config_port(struct uart_port *u, int flags) 395 { 396 } 397 398 static const char *mxs_auart_type(struct uart_port *u) 399 { 400 struct mxs_auart_port *s = to_auart_port(u); 401 402 return dev_name(s->dev); 403 } 404 405 static void mxs_auart_release_port(struct uart_port *u) 406 { 407 } 408 409 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) 410 { 411 struct mxs_auart_port *s = to_auart_port(u); 412 413 u32 ctrl = readl(u->membase + AUART_CTRL2); 414 415 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS); 416 if (mctrl & TIOCM_RTS) { 417 if (tty_port_cts_enabled(&u->state->port)) 418 ctrl |= AUART_CTRL2_RTSEN; 419 else 420 ctrl |= AUART_CTRL2_RTS; 421 } 422 423 s->ctrl = mctrl; 424 writel(ctrl, u->membase + AUART_CTRL2); 425 } 426 427 static u32 mxs_auart_get_mctrl(struct uart_port *u) 428 { 429 struct mxs_auart_port *s = to_auart_port(u); 430 u32 stat = readl(u->membase + AUART_STAT); 431 int ctrl2 = readl(u->membase + AUART_CTRL2); 432 u32 mctrl = s->ctrl; 433 434 mctrl &= ~TIOCM_CTS; 435 if (stat & AUART_STAT_CTS) 436 mctrl |= TIOCM_CTS; 437 438 if (ctrl2 & AUART_CTRL2_RTS) 439 mctrl |= TIOCM_RTS; 440 441 return mctrl; 442 } 443 444 static bool mxs_auart_dma_filter(struct dma_chan *chan, void *param) 445 { 446 struct mxs_auart_port *s = param; 447 448 if (!mxs_dma_is_apbx(chan)) 449 return false; 450 451 if (s->dma_channel == chan->chan_id) { 452 chan->private = &s->dma_data; 453 return true; 454 } 455 return false; 456 } 457 458 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); 459 static void dma_rx_callback(void *arg) 460 { 461 struct mxs_auart_port *s = (struct mxs_auart_port *) arg; 462 struct tty_struct *tty = s->port.state->port.tty; 463 int count; 464 u32 stat; 465 466 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); 467 468 stat = readl(s->port.membase + AUART_STAT); 469 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | 470 AUART_STAT_PERR | AUART_STAT_FERR); 471 472 count = stat & AUART_STAT_RXCOUNT_MASK; 473 tty_insert_flip_string(tty, s->rx_dma_buf, count); 474 475 writel(stat, s->port.membase + AUART_STAT); 476 tty_flip_buffer_push(tty); 477 478 /* start the next DMA for RX. */ 479 mxs_auart_dma_prep_rx(s); 480 } 481 482 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) 483 { 484 struct dma_async_tx_descriptor *desc; 485 struct scatterlist *sgl = &s->rx_sgl; 486 struct dma_chan *channel = s->rx_dma_chan; 487 u32 pio[1]; 488 489 /* [1] : send PIO */ 490 pio[0] = AUART_CTRL0_RXTO_ENABLE 491 | AUART_CTRL0_RXTIMEOUT(0x80) 492 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); 493 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, 494 1, DMA_TRANS_NONE, 0); 495 if (!desc) { 496 dev_err(s->dev, "step 1 error\n"); 497 return -EINVAL; 498 } 499 500 /* [2] : send DMA request */ 501 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); 502 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); 503 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, 504 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 505 if (!desc) { 506 dev_err(s->dev, "step 2 error\n"); 507 return -1; 508 } 509 510 /* [3] : submit the DMA, but do not issue it. */ 511 desc->callback = dma_rx_callback; 512 desc->callback_param = s; 513 dmaengine_submit(desc); 514 dma_async_issue_pending(channel); 515 return 0; 516 } 517 518 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) 519 { 520 if (s->tx_dma_chan) { 521 dma_release_channel(s->tx_dma_chan); 522 s->tx_dma_chan = NULL; 523 } 524 if (s->rx_dma_chan) { 525 dma_release_channel(s->rx_dma_chan); 526 s->rx_dma_chan = NULL; 527 } 528 529 kfree(s->tx_dma_buf); 530 kfree(s->rx_dma_buf); 531 s->tx_dma_buf = NULL; 532 s->rx_dma_buf = NULL; 533 } 534 535 static void mxs_auart_dma_exit(struct mxs_auart_port *s) 536 { 537 538 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, 539 s->port.membase + AUART_CTRL2_CLR); 540 541 mxs_auart_dma_exit_channel(s); 542 s->flags &= ~MXS_AUART_DMA_ENABLED; 543 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 544 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); 545 } 546 547 static int mxs_auart_dma_init(struct mxs_auart_port *s) 548 { 549 dma_cap_mask_t mask; 550 551 if (auart_dma_enabled(s)) 552 return 0; 553 554 /* We do not get the right DMA channels. */ 555 if (s->dma_channel_rx == -1 || s->dma_channel_rx == -1) 556 return -EINVAL; 557 558 /* init for RX */ 559 dma_cap_zero(mask); 560 dma_cap_set(DMA_SLAVE, mask); 561 s->dma_channel = s->dma_channel_rx; 562 s->dma_data.chan_irq = s->dma_irq_rx; 563 s->rx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s); 564 if (!s->rx_dma_chan) 565 goto err_out; 566 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 567 if (!s->rx_dma_buf) 568 goto err_out; 569 570 /* init for TX */ 571 s->dma_channel = s->dma_channel_tx; 572 s->dma_data.chan_irq = s->dma_irq_tx; 573 s->tx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s); 574 if (!s->tx_dma_chan) 575 goto err_out; 576 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 577 if (!s->tx_dma_buf) 578 goto err_out; 579 580 /* set the flags */ 581 s->flags |= MXS_AUART_DMA_ENABLED; 582 dev_dbg(s->dev, "enabled the DMA support."); 583 584 return 0; 585 586 err_out: 587 mxs_auart_dma_exit_channel(s); 588 return -EINVAL; 589 590 } 591 592 static void mxs_auart_settermios(struct uart_port *u, 593 struct ktermios *termios, 594 struct ktermios *old) 595 { 596 struct mxs_auart_port *s = to_auart_port(u); 597 u32 bm, ctrl, ctrl2, div; 598 unsigned int cflag, baud; 599 600 cflag = termios->c_cflag; 601 602 ctrl = AUART_LINECTRL_FEN; 603 ctrl2 = readl(u->membase + AUART_CTRL2); 604 605 /* byte size */ 606 switch (cflag & CSIZE) { 607 case CS5: 608 bm = 0; 609 break; 610 case CS6: 611 bm = 1; 612 break; 613 case CS7: 614 bm = 2; 615 break; 616 case CS8: 617 bm = 3; 618 break; 619 default: 620 return; 621 } 622 623 ctrl |= AUART_LINECTRL_WLEN(bm); 624 625 /* parity */ 626 if (cflag & PARENB) { 627 ctrl |= AUART_LINECTRL_PEN; 628 if ((cflag & PARODD) == 0) 629 ctrl |= AUART_LINECTRL_EPS; 630 } 631 632 u->read_status_mask = 0; 633 634 if (termios->c_iflag & INPCK) 635 u->read_status_mask |= AUART_STAT_PERR; 636 if (termios->c_iflag & (BRKINT | PARMRK)) 637 u->read_status_mask |= AUART_STAT_BERR; 638 639 /* 640 * Characters to ignore 641 */ 642 u->ignore_status_mask = 0; 643 if (termios->c_iflag & IGNPAR) 644 u->ignore_status_mask |= AUART_STAT_PERR; 645 if (termios->c_iflag & IGNBRK) { 646 u->ignore_status_mask |= AUART_STAT_BERR; 647 /* 648 * If we're ignoring parity and break indicators, 649 * ignore overruns too (for real raw support). 650 */ 651 if (termios->c_iflag & IGNPAR) 652 u->ignore_status_mask |= AUART_STAT_OERR; 653 } 654 655 /* 656 * ignore all characters if CREAD is not set 657 */ 658 if (cflag & CREAD) 659 ctrl2 |= AUART_CTRL2_RXE; 660 else 661 ctrl2 &= ~AUART_CTRL2_RXE; 662 663 /* figure out the stop bits requested */ 664 if (cflag & CSTOPB) 665 ctrl |= AUART_LINECTRL_STP2; 666 667 /* figure out the hardware flow control settings */ 668 if (cflag & CRTSCTS) { 669 /* 670 * The DMA has a bug(see errata:2836) in mx23. 671 * So we can not implement the DMA for auart in mx23, 672 * we can only implement the DMA support for auart 673 * in mx28. 674 */ 675 if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)) { 676 if (!mxs_auart_dma_init(s)) 677 /* enable DMA tranfer */ 678 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE 679 | AUART_CTRL2_DMAONERR; 680 } 681 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN; 682 } else { 683 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); 684 } 685 686 /* set baud rate */ 687 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk); 688 div = u->uartclk * 32 / baud; 689 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); 690 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); 691 692 writel(ctrl, u->membase + AUART_LINECTRL); 693 writel(ctrl2, u->membase + AUART_CTRL2); 694 695 uart_update_timeout(u, termios->c_cflag, baud); 696 697 /* prepare for the DMA RX. */ 698 if (auart_dma_enabled(s) && 699 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { 700 if (!mxs_auart_dma_prep_rx(s)) { 701 /* Disable the normal RX interrupt. */ 702 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN, 703 u->membase + AUART_INTR_CLR); 704 } else { 705 mxs_auart_dma_exit(s); 706 dev_err(s->dev, "We can not start up the DMA.\n"); 707 } 708 } 709 } 710 711 static irqreturn_t mxs_auart_irq_handle(int irq, void *context) 712 { 713 u32 istatus, istat; 714 struct mxs_auart_port *s = context; 715 u32 stat = readl(s->port.membase + AUART_STAT); 716 717 istatus = istat = readl(s->port.membase + AUART_INTR); 718 719 if (istat & AUART_INTR_CTSMIS) { 720 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS); 721 writel(AUART_INTR_CTSMIS, 722 s->port.membase + AUART_INTR_CLR); 723 istat &= ~AUART_INTR_CTSMIS; 724 } 725 726 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { 727 if (!auart_dma_enabled(s)) 728 mxs_auart_rx_chars(s); 729 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); 730 } 731 732 if (istat & AUART_INTR_TXIS) { 733 mxs_auart_tx_chars(s); 734 istat &= ~AUART_INTR_TXIS; 735 } 736 737 writel(istatus & (AUART_INTR_RTIS 738 | AUART_INTR_TXIS 739 | AUART_INTR_RXIS 740 | AUART_INTR_CTSMIS), 741 s->port.membase + AUART_INTR_CLR); 742 743 return IRQ_HANDLED; 744 } 745 746 static void mxs_auart_reset(struct uart_port *u) 747 { 748 int i; 749 unsigned int reg; 750 751 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR); 752 753 for (i = 0; i < 10000; i++) { 754 reg = readl(u->membase + AUART_CTRL0); 755 if (!(reg & AUART_CTRL0_SFTRST)) 756 break; 757 udelay(3); 758 } 759 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 760 } 761 762 static int mxs_auart_startup(struct uart_port *u) 763 { 764 struct mxs_auart_port *s = to_auart_port(u); 765 766 clk_prepare_enable(s->clk); 767 768 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR); 769 770 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET); 771 772 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 773 u->membase + AUART_INTR); 774 775 /* 776 * Enable fifo so all four bytes of a DMA word are written to 777 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) 778 */ 779 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET); 780 781 return 0; 782 } 783 784 static void mxs_auart_shutdown(struct uart_port *u) 785 { 786 struct mxs_auart_port *s = to_auart_port(u); 787 788 if (auart_dma_enabled(s)) 789 mxs_auart_dma_exit(s); 790 791 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR); 792 793 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 794 u->membase + AUART_INTR_CLR); 795 796 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET); 797 798 clk_disable_unprepare(s->clk); 799 } 800 801 static unsigned int mxs_auart_tx_empty(struct uart_port *u) 802 { 803 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE) 804 return TIOCSER_TEMT; 805 else 806 return 0; 807 } 808 809 static void mxs_auart_start_tx(struct uart_port *u) 810 { 811 struct mxs_auart_port *s = to_auart_port(u); 812 813 /* enable transmitter */ 814 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET); 815 816 mxs_auart_tx_chars(s); 817 } 818 819 static void mxs_auart_stop_tx(struct uart_port *u) 820 { 821 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR); 822 } 823 824 static void mxs_auart_stop_rx(struct uart_port *u) 825 { 826 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR); 827 } 828 829 static void mxs_auart_break_ctl(struct uart_port *u, int ctl) 830 { 831 if (ctl) 832 writel(AUART_LINECTRL_BRK, 833 u->membase + AUART_LINECTRL_SET); 834 else 835 writel(AUART_LINECTRL_BRK, 836 u->membase + AUART_LINECTRL_CLR); 837 } 838 839 static void mxs_auart_enable_ms(struct uart_port *port) 840 { 841 /* just empty */ 842 } 843 844 static struct uart_ops mxs_auart_ops = { 845 .tx_empty = mxs_auart_tx_empty, 846 .start_tx = mxs_auart_start_tx, 847 .stop_tx = mxs_auart_stop_tx, 848 .stop_rx = mxs_auart_stop_rx, 849 .enable_ms = mxs_auart_enable_ms, 850 .break_ctl = mxs_auart_break_ctl, 851 .set_mctrl = mxs_auart_set_mctrl, 852 .get_mctrl = mxs_auart_get_mctrl, 853 .startup = mxs_auart_startup, 854 .shutdown = mxs_auart_shutdown, 855 .set_termios = mxs_auart_settermios, 856 .type = mxs_auart_type, 857 .release_port = mxs_auart_release_port, 858 .request_port = mxs_auart_request_port, 859 .config_port = mxs_auart_config_port, 860 .verify_port = mxs_auart_verify_port, 861 }; 862 863 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; 864 865 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 866 static void mxs_auart_console_putchar(struct uart_port *port, int ch) 867 { 868 unsigned int to = 1000; 869 870 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) { 871 if (!to--) 872 break; 873 udelay(1); 874 } 875 876 writel(ch, port->membase + AUART_DATA); 877 } 878 879 static void 880 auart_console_write(struct console *co, const char *str, unsigned int count) 881 { 882 struct mxs_auart_port *s; 883 struct uart_port *port; 884 unsigned int old_ctrl0, old_ctrl2; 885 unsigned int to = 1000; 886 887 if (co->index > MXS_AUART_PORTS || co->index < 0) 888 return; 889 890 s = auart_port[co->index]; 891 port = &s->port; 892 893 clk_enable(s->clk); 894 895 /* First save the CR then disable the interrupts */ 896 old_ctrl2 = readl(port->membase + AUART_CTRL2); 897 old_ctrl0 = readl(port->membase + AUART_CTRL0); 898 899 writel(AUART_CTRL0_CLKGATE, 900 port->membase + AUART_CTRL0_CLR); 901 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, 902 port->membase + AUART_CTRL2_SET); 903 904 uart_console_write(port, str, count, mxs_auart_console_putchar); 905 906 /* 907 * Finally, wait for transmitter to become empty 908 * and restore the TCR 909 */ 910 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) { 911 if (!to--) 912 break; 913 udelay(1); 914 } 915 916 writel(old_ctrl0, port->membase + AUART_CTRL0); 917 writel(old_ctrl2, port->membase + AUART_CTRL2); 918 919 clk_disable(s->clk); 920 } 921 922 static void __init 923 auart_console_get_options(struct uart_port *port, int *baud, 924 int *parity, int *bits) 925 { 926 unsigned int lcr_h, quot; 927 928 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN)) 929 return; 930 931 lcr_h = readl(port->membase + AUART_LINECTRL); 932 933 *parity = 'n'; 934 if (lcr_h & AUART_LINECTRL_PEN) { 935 if (lcr_h & AUART_LINECTRL_EPS) 936 *parity = 'e'; 937 else 938 *parity = 'o'; 939 } 940 941 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) 942 *bits = 7; 943 else 944 *bits = 8; 945 946 quot = ((readl(port->membase + AUART_LINECTRL) 947 & AUART_LINECTRL_BAUD_DIVINT_MASK)) 948 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); 949 quot |= ((readl(port->membase + AUART_LINECTRL) 950 & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) 951 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; 952 if (quot == 0) 953 quot = 1; 954 955 *baud = (port->uartclk << 2) / quot; 956 } 957 958 static int __init 959 auart_console_setup(struct console *co, char *options) 960 { 961 struct mxs_auart_port *s; 962 int baud = 9600; 963 int bits = 8; 964 int parity = 'n'; 965 int flow = 'n'; 966 int ret; 967 968 /* 969 * Check whether an invalid uart number has been specified, and 970 * if so, search for the first available port that does have 971 * console support. 972 */ 973 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) 974 co->index = 0; 975 s = auart_port[co->index]; 976 if (!s) 977 return -ENODEV; 978 979 clk_prepare_enable(s->clk); 980 981 if (options) 982 uart_parse_options(options, &baud, &parity, &bits, &flow); 983 else 984 auart_console_get_options(&s->port, &baud, &parity, &bits); 985 986 ret = uart_set_options(&s->port, co, baud, parity, bits, flow); 987 988 clk_disable_unprepare(s->clk); 989 990 return ret; 991 } 992 993 static struct console auart_console = { 994 .name = "ttyAPP", 995 .write = auart_console_write, 996 .device = uart_console_device, 997 .setup = auart_console_setup, 998 .flags = CON_PRINTBUFFER, 999 .index = -1, 1000 .data = &auart_driver, 1001 }; 1002 #endif 1003 1004 static struct uart_driver auart_driver = { 1005 .owner = THIS_MODULE, 1006 .driver_name = "ttyAPP", 1007 .dev_name = "ttyAPP", 1008 .major = 0, 1009 .minor = 0, 1010 .nr = MXS_AUART_PORTS, 1011 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 1012 .cons = &auart_console, 1013 #endif 1014 }; 1015 1016 /* 1017 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it 1018 * could successfully get all information from dt or a negative errno. 1019 */ 1020 static int serial_mxs_probe_dt(struct mxs_auart_port *s, 1021 struct platform_device *pdev) 1022 { 1023 struct device_node *np = pdev->dev.of_node; 1024 u32 dma_channel[2]; 1025 int ret; 1026 1027 if (!np) 1028 /* no device tree device */ 1029 return 1; 1030 1031 ret = of_alias_get_id(np, "serial"); 1032 if (ret < 0) { 1033 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); 1034 return ret; 1035 } 1036 s->port.line = ret; 1037 1038 s->dma_irq_rx = platform_get_irq(pdev, 1); 1039 s->dma_irq_tx = platform_get_irq(pdev, 2); 1040 1041 ret = of_property_read_u32_array(np, "fsl,auart-dma-channel", 1042 dma_channel, 2); 1043 if (ret == 0) { 1044 s->dma_channel_rx = dma_channel[0]; 1045 s->dma_channel_tx = dma_channel[1]; 1046 1047 s->flags |= MXS_AUART_DMA_CONFIG; 1048 } else { 1049 s->dma_channel_rx = -1; 1050 s->dma_channel_tx = -1; 1051 } 1052 return 0; 1053 } 1054 1055 static int mxs_auart_probe(struct platform_device *pdev) 1056 { 1057 const struct of_device_id *of_id = 1058 of_match_device(mxs_auart_dt_ids, &pdev->dev); 1059 struct mxs_auart_port *s; 1060 u32 version; 1061 int ret = 0; 1062 struct resource *r; 1063 struct pinctrl *pinctrl; 1064 1065 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); 1066 if (!s) { 1067 ret = -ENOMEM; 1068 goto out; 1069 } 1070 1071 ret = serial_mxs_probe_dt(s, pdev); 1072 if (ret > 0) 1073 s->port.line = pdev->id < 0 ? 0 : pdev->id; 1074 else if (ret < 0) 1075 goto out_free; 1076 1077 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1078 if (IS_ERR(pinctrl)) { 1079 ret = PTR_ERR(pinctrl); 1080 goto out_free; 1081 } 1082 1083 if (of_id) { 1084 pdev->id_entry = of_id->data; 1085 s->devtype = pdev->id_entry->driver_data; 1086 } 1087 1088 s->clk = clk_get(&pdev->dev, NULL); 1089 if (IS_ERR(s->clk)) { 1090 ret = PTR_ERR(s->clk); 1091 goto out_free; 1092 } 1093 1094 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1095 if (!r) { 1096 ret = -ENXIO; 1097 goto out_free_clk; 1098 } 1099 1100 s->port.mapbase = r->start; 1101 s->port.membase = ioremap(r->start, resource_size(r)); 1102 s->port.ops = &mxs_auart_ops; 1103 s->port.iotype = UPIO_MEM; 1104 s->port.fifosize = 16; 1105 s->port.uartclk = clk_get_rate(s->clk); 1106 s->port.type = PORT_IMX; 1107 s->port.dev = s->dev = get_device(&pdev->dev); 1108 1109 s->ctrl = 0; 1110 1111 s->irq = platform_get_irq(pdev, 0); 1112 s->port.irq = s->irq; 1113 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s); 1114 if (ret) 1115 goto out_free_clk; 1116 1117 platform_set_drvdata(pdev, s); 1118 1119 auart_port[s->port.line] = s; 1120 1121 mxs_auart_reset(&s->port); 1122 1123 ret = uart_add_one_port(&auart_driver, &s->port); 1124 if (ret) 1125 goto out_free_irq; 1126 1127 version = readl(s->port.membase + AUART_VERSION); 1128 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", 1129 (version >> 24) & 0xff, 1130 (version >> 16) & 0xff, version & 0xffff); 1131 1132 return 0; 1133 1134 out_free_irq: 1135 auart_port[pdev->id] = NULL; 1136 free_irq(s->irq, s); 1137 out_free_clk: 1138 put_device(s->dev); 1139 clk_put(s->clk); 1140 out_free: 1141 kfree(s); 1142 out: 1143 return ret; 1144 } 1145 1146 static int mxs_auart_remove(struct platform_device *pdev) 1147 { 1148 struct mxs_auart_port *s = platform_get_drvdata(pdev); 1149 1150 uart_remove_one_port(&auart_driver, &s->port); 1151 1152 auart_port[pdev->id] = NULL; 1153 1154 put_device(s->dev); 1155 clk_put(s->clk); 1156 free_irq(s->irq, s); 1157 kfree(s); 1158 1159 return 0; 1160 } 1161 1162 static struct platform_driver mxs_auart_driver = { 1163 .probe = mxs_auart_probe, 1164 .remove = mxs_auart_remove, 1165 .driver = { 1166 .name = "mxs-auart", 1167 .owner = THIS_MODULE, 1168 .of_match_table = mxs_auart_dt_ids, 1169 }, 1170 }; 1171 1172 static int __init mxs_auart_init(void) 1173 { 1174 int r; 1175 1176 r = uart_register_driver(&auart_driver); 1177 if (r) 1178 goto out; 1179 1180 r = platform_driver_register(&mxs_auart_driver); 1181 if (r) 1182 goto out_err; 1183 1184 return 0; 1185 out_err: 1186 uart_unregister_driver(&auart_driver); 1187 out: 1188 return r; 1189 } 1190 1191 static void __exit mxs_auart_exit(void) 1192 { 1193 platform_driver_unregister(&mxs_auart_driver); 1194 uart_unregister_driver(&auart_driver); 1195 } 1196 1197 module_init(mxs_auart_init); 1198 module_exit(mxs_auart_exit); 1199 MODULE_LICENSE("GPL"); 1200 MODULE_DESCRIPTION("Freescale MXS application uart driver"); 1201 MODULE_ALIAS("platform:mxs-auart"); 1202