1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Application UART driver for: 4 * Freescale STMP37XX/STMP378X 5 * Alphascale ASM9260 6 * 7 * Author: dmitry pervushin <dimka@embeddedalley.com> 8 * 9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de> 10 * Provide Alphascale ASM9260 support. 11 * Copyright 2008-2010 Freescale Semiconductor, Inc. 12 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. 13 */ 14 15 #if defined(CONFIG_SERIAL_MXS_AUART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 16 #define SUPPORT_SYSRQ 17 #endif 18 19 #include <linux/kernel.h> 20 #include <linux/errno.h> 21 #include <linux/init.h> 22 #include <linux/console.h> 23 #include <linux/interrupt.h> 24 #include <linux/module.h> 25 #include <linux/slab.h> 26 #include <linux/wait.h> 27 #include <linux/tty.h> 28 #include <linux/tty_driver.h> 29 #include <linux/tty_flip.h> 30 #include <linux/serial.h> 31 #include <linux/serial_core.h> 32 #include <linux/platform_device.h> 33 #include <linux/device.h> 34 #include <linux/clk.h> 35 #include <linux/delay.h> 36 #include <linux/io.h> 37 #include <linux/of_device.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/dmaengine.h> 40 41 #include <asm/cacheflush.h> 42 43 #include <linux/gpio/consumer.h> 44 #include <linux/err.h> 45 #include <linux/irq.h> 46 #include "serial_mctrl_gpio.h" 47 48 #define MXS_AUART_PORTS 5 49 #define MXS_AUART_FIFO_SIZE 16 50 51 #define SET_REG 0x4 52 #define CLR_REG 0x8 53 #define TOG_REG 0xc 54 55 #define AUART_CTRL0 0x00000000 56 #define AUART_CTRL1 0x00000010 57 #define AUART_CTRL2 0x00000020 58 #define AUART_LINECTRL 0x00000030 59 #define AUART_LINECTRL2 0x00000040 60 #define AUART_INTR 0x00000050 61 #define AUART_DATA 0x00000060 62 #define AUART_STAT 0x00000070 63 #define AUART_DEBUG 0x00000080 64 #define AUART_VERSION 0x00000090 65 #define AUART_AUTOBAUD 0x000000a0 66 67 #define AUART_CTRL0_SFTRST (1 << 31) 68 #define AUART_CTRL0_CLKGATE (1 << 30) 69 #define AUART_CTRL0_RXTO_ENABLE (1 << 27) 70 #define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16) 71 #define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff) 72 73 #define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff) 74 75 #define AUART_CTRL2_DMAONERR (1 << 26) 76 #define AUART_CTRL2_TXDMAE (1 << 25) 77 #define AUART_CTRL2_RXDMAE (1 << 24) 78 79 #define AUART_CTRL2_CTSEN (1 << 15) 80 #define AUART_CTRL2_RTSEN (1 << 14) 81 #define AUART_CTRL2_RTS (1 << 11) 82 #define AUART_CTRL2_RXE (1 << 9) 83 #define AUART_CTRL2_TXE (1 << 8) 84 #define AUART_CTRL2_UARTEN (1 << 0) 85 86 #define AUART_LINECTRL_BAUD_DIV_MAX 0x003fffc0 87 #define AUART_LINECTRL_BAUD_DIV_MIN 0x000000ec 88 #define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16 89 #define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000 90 #define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16) 91 #define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8 92 #define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00 93 #define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8) 94 #define AUART_LINECTRL_SPS (1 << 7) 95 #define AUART_LINECTRL_WLEN_MASK 0x00000060 96 #define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5) 97 #define AUART_LINECTRL_FEN (1 << 4) 98 #define AUART_LINECTRL_STP2 (1 << 3) 99 #define AUART_LINECTRL_EPS (1 << 2) 100 #define AUART_LINECTRL_PEN (1 << 1) 101 #define AUART_LINECTRL_BRK (1 << 0) 102 103 #define AUART_INTR_RTIEN (1 << 22) 104 #define AUART_INTR_TXIEN (1 << 21) 105 #define AUART_INTR_RXIEN (1 << 20) 106 #define AUART_INTR_CTSMIEN (1 << 17) 107 #define AUART_INTR_RTIS (1 << 6) 108 #define AUART_INTR_TXIS (1 << 5) 109 #define AUART_INTR_RXIS (1 << 4) 110 #define AUART_INTR_CTSMIS (1 << 1) 111 112 #define AUART_STAT_BUSY (1 << 29) 113 #define AUART_STAT_CTS (1 << 28) 114 #define AUART_STAT_TXFE (1 << 27) 115 #define AUART_STAT_TXFF (1 << 25) 116 #define AUART_STAT_RXFE (1 << 24) 117 #define AUART_STAT_OERR (1 << 19) 118 #define AUART_STAT_BERR (1 << 18) 119 #define AUART_STAT_PERR (1 << 17) 120 #define AUART_STAT_FERR (1 << 16) 121 #define AUART_STAT_RXCOUNT_MASK 0xffff 122 123 /* 124 * Start of Alphascale asm9260 defines 125 * This list contains only differences of existing bits 126 * between imx2x and asm9260 127 */ 128 #define ASM9260_HW_CTRL0 0x0000 129 /* 130 * RW. Tell the UART to execute the RX DMA Command. The 131 * UART will clear this bit at the end of receive execution. 132 */ 133 #define ASM9260_BM_CTRL0_RXDMA_RUN BIT(28) 134 /* RW. 0 use FIFO for status register; 1 use DMA */ 135 #define ASM9260_BM_CTRL0_RXTO_SOURCE_STATUS BIT(25) 136 /* 137 * RW. RX TIMEOUT Enable. Valid for FIFO and DMA. 138 * Warning: If this bit is set to 0, the RX timeout will not affect receive DMA 139 * operation. If this bit is set to 1, a receive timeout will cause the receive 140 * DMA logic to terminate by filling the remaining DMA bytes with garbage data. 141 */ 142 #define ASM9260_BM_CTRL0_RXTO_ENABLE BIT(24) 143 /* 144 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before 145 * asserting timeout on the RX input. If the RXFIFO is not empty and the RX 146 * input is idle, then the watchdog counter will decrement each bit-time. Note 147 * 7-bit-time is added to the programmed value, so a value of zero will set 148 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also 149 * note that the counter is reloaded at the end of each frame, so if the frame 150 * is 10 bits long and the timeout counter value is zero, then timeout will 151 * occur (when FIFO is not empty) even if the RX input is not idle. The default 152 * value is 0x3 (31 bit-time). 153 */ 154 #define ASM9260_BM_CTRL0_RXTO_MASK (0xff << 16) 155 /* TIMEOUT = (100*7+1)*(1/BAUD) */ 156 #define ASM9260_BM_CTRL0_DEFAULT_RXTIMEOUT (20 << 16) 157 158 /* TX ctrl register */ 159 #define ASM9260_HW_CTRL1 0x0010 160 /* 161 * RW. Tell the UART to execute the TX DMA Command. The 162 * UART will clear this bit at the end of transmit execution. 163 */ 164 #define ASM9260_BM_CTRL1_TXDMA_RUN BIT(28) 165 166 #define ASM9260_HW_CTRL2 0x0020 167 /* 168 * RW. Receive Interrupt FIFO Level Select. 169 * The trigger points for the receive interrupt are as follows: 170 * ONE_EIGHTHS = 0x0 Trigger on FIFO full to at least 2 of 16 entries. 171 * ONE_QUARTER = 0x1 Trigger on FIFO full to at least 4 of 16 entries. 172 * ONE_HALF = 0x2 Trigger on FIFO full to at least 8 of 16 entries. 173 * THREE_QUARTERS = 0x3 Trigger on FIFO full to at least 12 of 16 entries. 174 * SEVEN_EIGHTHS = 0x4 Trigger on FIFO full to at least 14 of 16 entries. 175 */ 176 #define ASM9260_BM_CTRL2_RXIFLSEL (7 << 20) 177 #define ASM9260_BM_CTRL2_DEFAULT_RXIFLSEL (3 << 20) 178 /* RW. Same as RXIFLSEL */ 179 #define ASM9260_BM_CTRL2_TXIFLSEL (7 << 16) 180 #define ASM9260_BM_CTRL2_DEFAULT_TXIFLSEL (2 << 16) 181 /* RW. Set DTR. When this bit is 1, the output is 0. */ 182 #define ASM9260_BM_CTRL2_DTR BIT(10) 183 /* RW. Loop Back Enable */ 184 #define ASM9260_BM_CTRL2_LBE BIT(7) 185 #define ASM9260_BM_CTRL2_PORT_ENABLE BIT(0) 186 187 #define ASM9260_HW_LINECTRL 0x0030 188 /* 189 * RW. Stick Parity Select. When bits 1, 2, and 7 of this register are set, the 190 * parity bit is transmitted and checked as a 0. When bits 1 and 7 are set, 191 * and bit 2 is 0, the parity bit is transmitted and checked as a 1. When this 192 * bit is cleared stick parity is disabled. 193 */ 194 #define ASM9260_BM_LCTRL_SPS BIT(7) 195 /* RW. Word length */ 196 #define ASM9260_BM_LCTRL_WLEN (3 << 5) 197 #define ASM9260_BM_LCTRL_CHRL_5 (0 << 5) 198 #define ASM9260_BM_LCTRL_CHRL_6 (1 << 5) 199 #define ASM9260_BM_LCTRL_CHRL_7 (2 << 5) 200 #define ASM9260_BM_LCTRL_CHRL_8 (3 << 5) 201 202 /* 203 * Interrupt register. 204 * contains the interrupt enables and the interrupt status bits 205 */ 206 #define ASM9260_HW_INTR 0x0040 207 /* Tx FIFO EMPTY Raw Interrupt enable */ 208 #define ASM9260_BM_INTR_TFEIEN BIT(27) 209 /* Overrun Error Interrupt Enable. */ 210 #define ASM9260_BM_INTR_OEIEN BIT(26) 211 /* Break Error Interrupt Enable. */ 212 #define ASM9260_BM_INTR_BEIEN BIT(25) 213 /* Parity Error Interrupt Enable. */ 214 #define ASM9260_BM_INTR_PEIEN BIT(24) 215 /* Framing Error Interrupt Enable. */ 216 #define ASM9260_BM_INTR_FEIEN BIT(23) 217 218 /* nUARTDSR Modem Interrupt Enable. */ 219 #define ASM9260_BM_INTR_DSRMIEN BIT(19) 220 /* nUARTDCD Modem Interrupt Enable. */ 221 #define ASM9260_BM_INTR_DCDMIEN BIT(18) 222 /* nUARTRI Modem Interrupt Enable. */ 223 #define ASM9260_BM_INTR_RIMIEN BIT(16) 224 /* Auto-Boud Timeout */ 225 #define ASM9260_BM_INTR_ABTO BIT(13) 226 #define ASM9260_BM_INTR_ABEO BIT(12) 227 /* Tx FIFO EMPTY Raw Interrupt state */ 228 #define ASM9260_BM_INTR_TFEIS BIT(11) 229 /* Overrun Error */ 230 #define ASM9260_BM_INTR_OEIS BIT(10) 231 /* Break Error */ 232 #define ASM9260_BM_INTR_BEIS BIT(9) 233 /* Parity Error */ 234 #define ASM9260_BM_INTR_PEIS BIT(8) 235 /* Framing Error */ 236 #define ASM9260_BM_INTR_FEIS BIT(7) 237 #define ASM9260_BM_INTR_DSRMIS BIT(3) 238 #define ASM9260_BM_INTR_DCDMIS BIT(2) 239 #define ASM9260_BM_INTR_RIMIS BIT(0) 240 241 /* 242 * RW. In DMA mode, up to 4 Received/Transmit characters can be accessed at a 243 * time. In PIO mode, only one character can be accessed at a time. The status 244 * register contains the receive data flags and valid bits. 245 */ 246 #define ASM9260_HW_DATA 0x0050 247 248 #define ASM9260_HW_STAT 0x0060 249 /* RO. If 1, UARTAPP is present in this product. */ 250 #define ASM9260_BM_STAT_PRESENT BIT(31) 251 /* RO. If 1, HISPEED is present in this product. */ 252 #define ASM9260_BM_STAT_HISPEED BIT(30) 253 /* RO. Receive FIFO Full. */ 254 #define ASM9260_BM_STAT_RXFULL BIT(26) 255 256 /* RO. The UART Debug Register contains the state of the DMA signals. */ 257 #define ASM9260_HW_DEBUG 0x0070 258 /* DMA Command Run Status */ 259 #define ASM9260_BM_DEBUG_TXDMARUN BIT(5) 260 #define ASM9260_BM_DEBUG_RXDMARUN BIT(4) 261 /* DMA Command End Status */ 262 #define ASM9260_BM_DEBUG_TXCMDEND BIT(3) 263 #define ASM9260_BM_DEBUG_RXCMDEND BIT(2) 264 /* DMA Request Status */ 265 #define ASM9260_BM_DEBUG_TXDMARQ BIT(1) 266 #define ASM9260_BM_DEBUG_RXDMARQ BIT(0) 267 268 #define ASM9260_HW_ILPR 0x0080 269 270 #define ASM9260_HW_RS485CTRL 0x0090 271 /* 272 * RW. This bit reverses the polarity of the direction control signal on the RTS 273 * (or DTR) pin. 274 * If 0, The direction control pin will be driven to logic ‘0’ when the 275 * transmitter has data to be sent. It will be driven to logic ‘1’ after the 276 * last bit of data has been transmitted. 277 */ 278 #define ASM9260_BM_RS485CTRL_ONIV BIT(5) 279 /* RW. Enable Auto Direction Control. */ 280 #define ASM9260_BM_RS485CTRL_DIR_CTRL BIT(4) 281 /* 282 * RW. If 0 and DIR_CTRL = 1, pin RTS is used for direction control. 283 * If 1 and DIR_CTRL = 1, pin DTR is used for direction control. 284 */ 285 #define ASM9260_BM_RS485CTRL_PINSEL BIT(3) 286 /* RW. Enable Auto Address Detect (AAD). */ 287 #define ASM9260_BM_RS485CTRL_AADEN BIT(2) 288 /* RW. Disable receiver. */ 289 #define ASM9260_BM_RS485CTRL_RXDIS BIT(1) 290 /* RW. Enable RS-485/EIA-485 Normal Multidrop Mode (NMM) */ 291 #define ASM9260_BM_RS485CTRL_RS485EN BIT(0) 292 293 #define ASM9260_HW_RS485ADRMATCH 0x00a0 294 /* Contains the address match value. */ 295 #define ASM9260_BM_RS485ADRMATCH_MASK (0xff << 0) 296 297 #define ASM9260_HW_RS485DLY 0x00b0 298 /* 299 * RW. Contains the direction control (RTS or DTR) delay value. This delay time 300 * is in periods of the baud clock. 301 */ 302 #define ASM9260_BM_RS485DLY_MASK (0xff << 0) 303 304 #define ASM9260_HW_AUTOBAUD 0x00c0 305 /* WO. Auto-baud time-out interrupt clear bit. */ 306 #define ASM9260_BM_AUTOBAUD_TO_INT_CLR BIT(9) 307 /* WO. End of auto-baud interrupt clear bit. */ 308 #define ASM9260_BM_AUTOBAUD_EO_INT_CLR BIT(8) 309 /* Restart in case of timeout (counter restarts at next UART Rx falling edge) */ 310 #define ASM9260_BM_AUTOBAUD_AUTORESTART BIT(2) 311 /* Auto-baud mode select bit. 0 - Mode 0, 1 - Mode 1. */ 312 #define ASM9260_BM_AUTOBAUD_MODE BIT(1) 313 /* 314 * Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is 315 * automatically cleared after auto-baud completion. 316 */ 317 #define ASM9260_BM_AUTOBAUD_START BIT(0) 318 319 #define ASM9260_HW_CTRL3 0x00d0 320 #define ASM9260_BM_CTRL3_OUTCLK_DIV_MASK (0xffff << 16) 321 /* 322 * RW. Provide clk over OUTCLK pin. In case of asm9260 it can be configured on 323 * pins 137 and 144. 324 */ 325 #define ASM9260_BM_CTRL3_MASTERMODE BIT(6) 326 /* RW. Baud Rate Mode: 1 - Enable sync mode. 0 - async mode. */ 327 #define ASM9260_BM_CTRL3_SYNCMODE BIT(4) 328 /* RW. 1 - MSB bit send frist; 0 - LSB bit frist. */ 329 #define ASM9260_BM_CTRL3_MSBF BIT(2) 330 /* RW. 1 - sample rate = 8 x Baudrate; 0 - sample rate = 16 x Baudrate. */ 331 #define ASM9260_BM_CTRL3_BAUD8 BIT(1) 332 /* RW. 1 - Set word length to 9bit. 0 - use ASM9260_BM_LCTRL_WLEN */ 333 #define ASM9260_BM_CTRL3_9BIT BIT(0) 334 335 #define ASM9260_HW_ISO7816_CTRL 0x00e0 336 /* RW. Enable High Speed mode. */ 337 #define ASM9260_BM_ISO7816CTRL_HS BIT(12) 338 /* Disable Successive Receive NACK */ 339 #define ASM9260_BM_ISO7816CTRL_DS_NACK BIT(8) 340 #define ASM9260_BM_ISO7816CTRL_MAX_ITER_MASK (0xff << 4) 341 /* Receive NACK Inhibit */ 342 #define ASM9260_BM_ISO7816CTRL_INACK BIT(3) 343 #define ASM9260_BM_ISO7816CTRL_NEG_DATA BIT(2) 344 /* RW. 1 - ISO7816 mode; 0 - USART mode */ 345 #define ASM9260_BM_ISO7816CTRL_ENABLE BIT(0) 346 347 #define ASM9260_HW_ISO7816_ERRCNT 0x00f0 348 /* Parity error counter. Will be cleared after reading */ 349 #define ASM9260_BM_ISO7816_NB_ERRORS_MASK (0xff << 0) 350 351 #define ASM9260_HW_ISO7816_STATUS 0x0100 352 /* Max number of Repetitions Reached */ 353 #define ASM9260_BM_ISO7816_STAT_ITERATION BIT(0) 354 355 /* End of Alphascale asm9260 defines */ 356 357 static struct uart_driver auart_driver; 358 359 enum mxs_auart_type { 360 IMX23_AUART, 361 IMX28_AUART, 362 ASM9260_AUART, 363 }; 364 365 struct vendor_data { 366 const u16 *reg_offset; 367 }; 368 369 enum { 370 REG_CTRL0, 371 REG_CTRL1, 372 REG_CTRL2, 373 REG_LINECTRL, 374 REG_LINECTRL2, 375 REG_INTR, 376 REG_DATA, 377 REG_STAT, 378 REG_DEBUG, 379 REG_VERSION, 380 REG_AUTOBAUD, 381 382 /* The size of the array - must be last */ 383 REG_ARRAY_SIZE, 384 }; 385 386 static const u16 mxs_asm9260_offsets[REG_ARRAY_SIZE] = { 387 [REG_CTRL0] = ASM9260_HW_CTRL0, 388 [REG_CTRL1] = ASM9260_HW_CTRL1, 389 [REG_CTRL2] = ASM9260_HW_CTRL2, 390 [REG_LINECTRL] = ASM9260_HW_LINECTRL, 391 [REG_INTR] = ASM9260_HW_INTR, 392 [REG_DATA] = ASM9260_HW_DATA, 393 [REG_STAT] = ASM9260_HW_STAT, 394 [REG_DEBUG] = ASM9260_HW_DEBUG, 395 [REG_AUTOBAUD] = ASM9260_HW_AUTOBAUD, 396 }; 397 398 static const u16 mxs_stmp37xx_offsets[REG_ARRAY_SIZE] = { 399 [REG_CTRL0] = AUART_CTRL0, 400 [REG_CTRL1] = AUART_CTRL1, 401 [REG_CTRL2] = AUART_CTRL2, 402 [REG_LINECTRL] = AUART_LINECTRL, 403 [REG_LINECTRL2] = AUART_LINECTRL2, 404 [REG_INTR] = AUART_INTR, 405 [REG_DATA] = AUART_DATA, 406 [REG_STAT] = AUART_STAT, 407 [REG_DEBUG] = AUART_DEBUG, 408 [REG_VERSION] = AUART_VERSION, 409 [REG_AUTOBAUD] = AUART_AUTOBAUD, 410 }; 411 412 static const struct vendor_data vendor_alphascale_asm9260 = { 413 .reg_offset = mxs_asm9260_offsets, 414 }; 415 416 static const struct vendor_data vendor_freescale_stmp37xx = { 417 .reg_offset = mxs_stmp37xx_offsets, 418 }; 419 420 struct mxs_auart_port { 421 struct uart_port port; 422 423 #define MXS_AUART_DMA_ENABLED 0x2 424 #define MXS_AUART_DMA_TX_SYNC 2 /* bit 2 */ 425 #define MXS_AUART_DMA_RX_READY 3 /* bit 3 */ 426 #define MXS_AUART_RTSCTS 4 /* bit 4 */ 427 unsigned long flags; 428 unsigned int mctrl_prev; 429 enum mxs_auart_type devtype; 430 const struct vendor_data *vendor; 431 432 struct clk *clk; 433 struct clk *clk_ahb; 434 struct device *dev; 435 436 /* for DMA */ 437 struct scatterlist tx_sgl; 438 struct dma_chan *tx_dma_chan; 439 void *tx_dma_buf; 440 441 struct scatterlist rx_sgl; 442 struct dma_chan *rx_dma_chan; 443 void *rx_dma_buf; 444 445 struct mctrl_gpios *gpios; 446 int gpio_irq[UART_GPIO_MAX]; 447 bool ms_irq_enabled; 448 }; 449 450 static const struct platform_device_id mxs_auart_devtype[] = { 451 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART }, 452 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART }, 453 { .name = "as-auart-asm9260", .driver_data = ASM9260_AUART }, 454 { /* sentinel */ } 455 }; 456 MODULE_DEVICE_TABLE(platform, mxs_auart_devtype); 457 458 static const struct of_device_id mxs_auart_dt_ids[] = { 459 { 460 .compatible = "fsl,imx28-auart", 461 .data = &mxs_auart_devtype[IMX28_AUART] 462 }, { 463 .compatible = "fsl,imx23-auart", 464 .data = &mxs_auart_devtype[IMX23_AUART] 465 }, { 466 .compatible = "alphascale,asm9260-auart", 467 .data = &mxs_auart_devtype[ASM9260_AUART] 468 }, { /* sentinel */ } 469 }; 470 MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids); 471 472 static inline int is_imx28_auart(struct mxs_auart_port *s) 473 { 474 return s->devtype == IMX28_AUART; 475 } 476 477 static inline int is_asm9260_auart(struct mxs_auart_port *s) 478 { 479 return s->devtype == ASM9260_AUART; 480 } 481 482 static inline bool auart_dma_enabled(struct mxs_auart_port *s) 483 { 484 return s->flags & MXS_AUART_DMA_ENABLED; 485 } 486 487 static unsigned int mxs_reg_to_offset(const struct mxs_auart_port *uap, 488 unsigned int reg) 489 { 490 return uap->vendor->reg_offset[reg]; 491 } 492 493 static unsigned int mxs_read(const struct mxs_auart_port *uap, 494 unsigned int reg) 495 { 496 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 497 498 return readl_relaxed(addr); 499 } 500 501 static void mxs_write(unsigned int val, struct mxs_auart_port *uap, 502 unsigned int reg) 503 { 504 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 505 506 writel_relaxed(val, addr); 507 } 508 509 static void mxs_set(unsigned int val, struct mxs_auart_port *uap, 510 unsigned int reg) 511 { 512 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 513 514 writel_relaxed(val, addr + SET_REG); 515 } 516 517 static void mxs_clr(unsigned int val, struct mxs_auart_port *uap, 518 unsigned int reg) 519 { 520 void __iomem *addr = uap->port.membase + mxs_reg_to_offset(uap, reg); 521 522 writel_relaxed(val, addr + CLR_REG); 523 } 524 525 static void mxs_auart_stop_tx(struct uart_port *u); 526 527 #define to_auart_port(u) container_of(u, struct mxs_auart_port, port) 528 529 static void mxs_auart_tx_chars(struct mxs_auart_port *s); 530 531 static void dma_tx_callback(void *param) 532 { 533 struct mxs_auart_port *s = param; 534 struct circ_buf *xmit = &s->port.state->xmit; 535 536 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE); 537 538 /* clear the bit used to serialize the DMA tx. */ 539 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 540 smp_mb__after_atomic(); 541 542 /* wake up the possible processes. */ 543 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 544 uart_write_wakeup(&s->port); 545 546 mxs_auart_tx_chars(s); 547 } 548 549 static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size) 550 { 551 struct dma_async_tx_descriptor *desc; 552 struct scatterlist *sgl = &s->tx_sgl; 553 struct dma_chan *channel = s->tx_dma_chan; 554 u32 pio; 555 556 /* [1] : send PIO. Note, the first pio word is CTRL1. */ 557 pio = AUART_CTRL1_XFER_COUNT(size); 558 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio, 559 1, DMA_TRANS_NONE, 0); 560 if (!desc) { 561 dev_err(s->dev, "step 1 error\n"); 562 return -EINVAL; 563 } 564 565 /* [2] : set DMA buffer. */ 566 sg_init_one(sgl, s->tx_dma_buf, size); 567 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE); 568 desc = dmaengine_prep_slave_sg(channel, sgl, 569 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 570 if (!desc) { 571 dev_err(s->dev, "step 2 error\n"); 572 return -EINVAL; 573 } 574 575 /* [3] : submit the DMA */ 576 desc->callback = dma_tx_callback; 577 desc->callback_param = s; 578 dmaengine_submit(desc); 579 dma_async_issue_pending(channel); 580 return 0; 581 } 582 583 static void mxs_auart_tx_chars(struct mxs_auart_port *s) 584 { 585 struct circ_buf *xmit = &s->port.state->xmit; 586 587 if (auart_dma_enabled(s)) { 588 u32 i = 0; 589 int size; 590 void *buffer = s->tx_dma_buf; 591 592 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags)) 593 return; 594 595 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 596 size = min_t(u32, UART_XMIT_SIZE - i, 597 CIRC_CNT_TO_END(xmit->head, 598 xmit->tail, 599 UART_XMIT_SIZE)); 600 memcpy(buffer + i, xmit->buf + xmit->tail, size); 601 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1); 602 603 i += size; 604 if (i >= UART_XMIT_SIZE) 605 break; 606 } 607 608 if (uart_tx_stopped(&s->port)) 609 mxs_auart_stop_tx(&s->port); 610 611 if (i) { 612 mxs_auart_dma_tx(s, i); 613 } else { 614 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 615 smp_mb__after_atomic(); 616 } 617 return; 618 } 619 620 621 while (!(mxs_read(s, REG_STAT) & AUART_STAT_TXFF)) { 622 if (s->port.x_char) { 623 s->port.icount.tx++; 624 mxs_write(s->port.x_char, s, REG_DATA); 625 s->port.x_char = 0; 626 continue; 627 } 628 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) { 629 s->port.icount.tx++; 630 mxs_write(xmit->buf[xmit->tail], s, REG_DATA); 631 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 632 } else 633 break; 634 } 635 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 636 uart_write_wakeup(&s->port); 637 638 if (uart_circ_empty(&(s->port.state->xmit))) 639 mxs_clr(AUART_INTR_TXIEN, s, REG_INTR); 640 else 641 mxs_set(AUART_INTR_TXIEN, s, REG_INTR); 642 643 if (uart_tx_stopped(&s->port)) 644 mxs_auart_stop_tx(&s->port); 645 } 646 647 static void mxs_auart_rx_char(struct mxs_auart_port *s) 648 { 649 int flag; 650 u32 stat; 651 u8 c; 652 653 c = mxs_read(s, REG_DATA); 654 stat = mxs_read(s, REG_STAT); 655 656 flag = TTY_NORMAL; 657 s->port.icount.rx++; 658 659 if (stat & AUART_STAT_BERR) { 660 s->port.icount.brk++; 661 if (uart_handle_break(&s->port)) 662 goto out; 663 } else if (stat & AUART_STAT_PERR) { 664 s->port.icount.parity++; 665 } else if (stat & AUART_STAT_FERR) { 666 s->port.icount.frame++; 667 } 668 669 /* 670 * Mask off conditions which should be ingored. 671 */ 672 stat &= s->port.read_status_mask; 673 674 if (stat & AUART_STAT_BERR) { 675 flag = TTY_BREAK; 676 } else if (stat & AUART_STAT_PERR) 677 flag = TTY_PARITY; 678 else if (stat & AUART_STAT_FERR) 679 flag = TTY_FRAME; 680 681 if (stat & AUART_STAT_OERR) 682 s->port.icount.overrun++; 683 684 if (uart_handle_sysrq_char(&s->port, c)) 685 goto out; 686 687 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag); 688 out: 689 mxs_write(stat, s, REG_STAT); 690 } 691 692 static void mxs_auart_rx_chars(struct mxs_auart_port *s) 693 { 694 u32 stat = 0; 695 696 for (;;) { 697 stat = mxs_read(s, REG_STAT); 698 if (stat & AUART_STAT_RXFE) 699 break; 700 mxs_auart_rx_char(s); 701 } 702 703 mxs_write(stat, s, REG_STAT); 704 tty_flip_buffer_push(&s->port.state->port); 705 } 706 707 static int mxs_auart_request_port(struct uart_port *u) 708 { 709 return 0; 710 } 711 712 static int mxs_auart_verify_port(struct uart_port *u, 713 struct serial_struct *ser) 714 { 715 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX) 716 return -EINVAL; 717 return 0; 718 } 719 720 static void mxs_auart_config_port(struct uart_port *u, int flags) 721 { 722 } 723 724 static const char *mxs_auart_type(struct uart_port *u) 725 { 726 struct mxs_auart_port *s = to_auart_port(u); 727 728 return dev_name(s->dev); 729 } 730 731 static void mxs_auart_release_port(struct uart_port *u) 732 { 733 } 734 735 static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl) 736 { 737 struct mxs_auart_port *s = to_auart_port(u); 738 739 u32 ctrl = mxs_read(s, REG_CTRL2); 740 741 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS); 742 if (mctrl & TIOCM_RTS) { 743 if (uart_cts_enabled(u)) 744 ctrl |= AUART_CTRL2_RTSEN; 745 else 746 ctrl |= AUART_CTRL2_RTS; 747 } 748 749 mxs_write(ctrl, s, REG_CTRL2); 750 751 mctrl_gpio_set(s->gpios, mctrl); 752 } 753 754 #define MCTRL_ANY_DELTA (TIOCM_RI | TIOCM_DSR | TIOCM_CD | TIOCM_CTS) 755 static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl) 756 { 757 u32 mctrl_diff; 758 759 mctrl_diff = mctrl ^ s->mctrl_prev; 760 s->mctrl_prev = mctrl; 761 if (mctrl_diff & MCTRL_ANY_DELTA && s->ms_irq_enabled && 762 s->port.state != NULL) { 763 if (mctrl_diff & TIOCM_RI) 764 s->port.icount.rng++; 765 if (mctrl_diff & TIOCM_DSR) 766 s->port.icount.dsr++; 767 if (mctrl_diff & TIOCM_CD) 768 uart_handle_dcd_change(&s->port, mctrl & TIOCM_CD); 769 if (mctrl_diff & TIOCM_CTS) 770 uart_handle_cts_change(&s->port, mctrl & TIOCM_CTS); 771 772 wake_up_interruptible(&s->port.state->port.delta_msr_wait); 773 } 774 return mctrl; 775 } 776 777 static u32 mxs_auart_get_mctrl(struct uart_port *u) 778 { 779 struct mxs_auart_port *s = to_auart_port(u); 780 u32 stat = mxs_read(s, REG_STAT); 781 u32 mctrl = 0; 782 783 if (stat & AUART_STAT_CTS) 784 mctrl |= TIOCM_CTS; 785 786 return mctrl_gpio_get(s->gpios, &mctrl); 787 } 788 789 /* 790 * Enable modem status interrupts 791 */ 792 static void mxs_auart_enable_ms(struct uart_port *port) 793 { 794 struct mxs_auart_port *s = to_auart_port(port); 795 796 /* 797 * Interrupt should not be enabled twice 798 */ 799 if (s->ms_irq_enabled) 800 return; 801 802 s->ms_irq_enabled = true; 803 804 if (s->gpio_irq[UART_GPIO_CTS] >= 0) 805 enable_irq(s->gpio_irq[UART_GPIO_CTS]); 806 /* TODO: enable AUART_INTR_CTSMIEN otherwise */ 807 808 if (s->gpio_irq[UART_GPIO_DSR] >= 0) 809 enable_irq(s->gpio_irq[UART_GPIO_DSR]); 810 811 if (s->gpio_irq[UART_GPIO_RI] >= 0) 812 enable_irq(s->gpio_irq[UART_GPIO_RI]); 813 814 if (s->gpio_irq[UART_GPIO_DCD] >= 0) 815 enable_irq(s->gpio_irq[UART_GPIO_DCD]); 816 } 817 818 /* 819 * Disable modem status interrupts 820 */ 821 static void mxs_auart_disable_ms(struct uart_port *port) 822 { 823 struct mxs_auart_port *s = to_auart_port(port); 824 825 /* 826 * Interrupt should not be disabled twice 827 */ 828 if (!s->ms_irq_enabled) 829 return; 830 831 s->ms_irq_enabled = false; 832 833 if (s->gpio_irq[UART_GPIO_CTS] >= 0) 834 disable_irq(s->gpio_irq[UART_GPIO_CTS]); 835 /* TODO: disable AUART_INTR_CTSMIEN otherwise */ 836 837 if (s->gpio_irq[UART_GPIO_DSR] >= 0) 838 disable_irq(s->gpio_irq[UART_GPIO_DSR]); 839 840 if (s->gpio_irq[UART_GPIO_RI] >= 0) 841 disable_irq(s->gpio_irq[UART_GPIO_RI]); 842 843 if (s->gpio_irq[UART_GPIO_DCD] >= 0) 844 disable_irq(s->gpio_irq[UART_GPIO_DCD]); 845 } 846 847 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s); 848 static void dma_rx_callback(void *arg) 849 { 850 struct mxs_auart_port *s = (struct mxs_auart_port *) arg; 851 struct tty_port *port = &s->port.state->port; 852 int count; 853 u32 stat; 854 855 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE); 856 857 stat = mxs_read(s, REG_STAT); 858 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR | 859 AUART_STAT_PERR | AUART_STAT_FERR); 860 861 count = stat & AUART_STAT_RXCOUNT_MASK; 862 tty_insert_flip_string(port, s->rx_dma_buf, count); 863 864 mxs_write(stat, s, REG_STAT); 865 tty_flip_buffer_push(port); 866 867 /* start the next DMA for RX. */ 868 mxs_auart_dma_prep_rx(s); 869 } 870 871 static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s) 872 { 873 struct dma_async_tx_descriptor *desc; 874 struct scatterlist *sgl = &s->rx_sgl; 875 struct dma_chan *channel = s->rx_dma_chan; 876 u32 pio[1]; 877 878 /* [1] : send PIO */ 879 pio[0] = AUART_CTRL0_RXTO_ENABLE 880 | AUART_CTRL0_RXTIMEOUT(0x80) 881 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE); 882 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio, 883 1, DMA_TRANS_NONE, 0); 884 if (!desc) { 885 dev_err(s->dev, "step 1 error\n"); 886 return -EINVAL; 887 } 888 889 /* [2] : send DMA request */ 890 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE); 891 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE); 892 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM, 893 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 894 if (!desc) { 895 dev_err(s->dev, "step 2 error\n"); 896 return -1; 897 } 898 899 /* [3] : submit the DMA, but do not issue it. */ 900 desc->callback = dma_rx_callback; 901 desc->callback_param = s; 902 dmaengine_submit(desc); 903 dma_async_issue_pending(channel); 904 return 0; 905 } 906 907 static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s) 908 { 909 if (s->tx_dma_chan) { 910 dma_release_channel(s->tx_dma_chan); 911 s->tx_dma_chan = NULL; 912 } 913 if (s->rx_dma_chan) { 914 dma_release_channel(s->rx_dma_chan); 915 s->rx_dma_chan = NULL; 916 } 917 918 kfree(s->tx_dma_buf); 919 kfree(s->rx_dma_buf); 920 s->tx_dma_buf = NULL; 921 s->rx_dma_buf = NULL; 922 } 923 924 static void mxs_auart_dma_exit(struct mxs_auart_port *s) 925 { 926 927 mxs_clr(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, 928 s, REG_CTRL2); 929 930 mxs_auart_dma_exit_channel(s); 931 s->flags &= ~MXS_AUART_DMA_ENABLED; 932 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags); 933 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags); 934 } 935 936 static int mxs_auart_dma_init(struct mxs_auart_port *s) 937 { 938 if (auart_dma_enabled(s)) 939 return 0; 940 941 /* init for RX */ 942 s->rx_dma_chan = dma_request_slave_channel(s->dev, "rx"); 943 if (!s->rx_dma_chan) 944 goto err_out; 945 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 946 if (!s->rx_dma_buf) 947 goto err_out; 948 949 /* init for TX */ 950 s->tx_dma_chan = dma_request_slave_channel(s->dev, "tx"); 951 if (!s->tx_dma_chan) 952 goto err_out; 953 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA); 954 if (!s->tx_dma_buf) 955 goto err_out; 956 957 /* set the flags */ 958 s->flags |= MXS_AUART_DMA_ENABLED; 959 dev_dbg(s->dev, "enabled the DMA support."); 960 961 /* The DMA buffer is now the FIFO the TTY subsystem can use */ 962 s->port.fifosize = UART_XMIT_SIZE; 963 964 return 0; 965 966 err_out: 967 mxs_auart_dma_exit_channel(s); 968 return -EINVAL; 969 970 } 971 972 #define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS) 973 #define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS) 974 static void mxs_auart_settermios(struct uart_port *u, 975 struct ktermios *termios, 976 struct ktermios *old) 977 { 978 struct mxs_auart_port *s = to_auart_port(u); 979 u32 bm, ctrl, ctrl2, div; 980 unsigned int cflag, baud, baud_min, baud_max; 981 982 cflag = termios->c_cflag; 983 984 ctrl = AUART_LINECTRL_FEN; 985 ctrl2 = mxs_read(s, REG_CTRL2); 986 987 /* byte size */ 988 switch (cflag & CSIZE) { 989 case CS5: 990 bm = 0; 991 break; 992 case CS6: 993 bm = 1; 994 break; 995 case CS7: 996 bm = 2; 997 break; 998 case CS8: 999 bm = 3; 1000 break; 1001 default: 1002 return; 1003 } 1004 1005 ctrl |= AUART_LINECTRL_WLEN(bm); 1006 1007 /* parity */ 1008 if (cflag & PARENB) { 1009 ctrl |= AUART_LINECTRL_PEN; 1010 if ((cflag & PARODD) == 0) 1011 ctrl |= AUART_LINECTRL_EPS; 1012 if (cflag & CMSPAR) 1013 ctrl |= AUART_LINECTRL_SPS; 1014 } 1015 1016 u->read_status_mask = AUART_STAT_OERR; 1017 1018 if (termios->c_iflag & INPCK) 1019 u->read_status_mask |= AUART_STAT_PERR; 1020 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1021 u->read_status_mask |= AUART_STAT_BERR; 1022 1023 /* 1024 * Characters to ignore 1025 */ 1026 u->ignore_status_mask = 0; 1027 if (termios->c_iflag & IGNPAR) 1028 u->ignore_status_mask |= AUART_STAT_PERR; 1029 if (termios->c_iflag & IGNBRK) { 1030 u->ignore_status_mask |= AUART_STAT_BERR; 1031 /* 1032 * If we're ignoring parity and break indicators, 1033 * ignore overruns too (for real raw support). 1034 */ 1035 if (termios->c_iflag & IGNPAR) 1036 u->ignore_status_mask |= AUART_STAT_OERR; 1037 } 1038 1039 /* 1040 * ignore all characters if CREAD is not set 1041 */ 1042 if (cflag & CREAD) 1043 ctrl2 |= AUART_CTRL2_RXE; 1044 else 1045 ctrl2 &= ~AUART_CTRL2_RXE; 1046 1047 /* figure out the stop bits requested */ 1048 if (cflag & CSTOPB) 1049 ctrl |= AUART_LINECTRL_STP2; 1050 1051 /* figure out the hardware flow control settings */ 1052 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN); 1053 if (cflag & CRTSCTS) { 1054 /* 1055 * The DMA has a bug(see errata:2836) in mx23. 1056 * So we can not implement the DMA for auart in mx23, 1057 * we can only implement the DMA support for auart 1058 * in mx28. 1059 */ 1060 if (is_imx28_auart(s) 1061 && test_bit(MXS_AUART_RTSCTS, &s->flags)) { 1062 if (!mxs_auart_dma_init(s)) 1063 /* enable DMA tranfer */ 1064 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE 1065 | AUART_CTRL2_DMAONERR; 1066 } 1067 /* Even if RTS is GPIO line RTSEN can be enabled because 1068 * the pinctrl configuration decides about RTS pin function */ 1069 ctrl2 |= AUART_CTRL2_RTSEN; 1070 if (CTS_AT_AUART()) 1071 ctrl2 |= AUART_CTRL2_CTSEN; 1072 } 1073 1074 /* set baud rate */ 1075 if (is_asm9260_auart(s)) { 1076 baud = uart_get_baud_rate(u, termios, old, 1077 u->uartclk * 4 / 0x3FFFFF, 1078 u->uartclk / 16); 1079 div = u->uartclk * 4 / baud; 1080 } else { 1081 baud_min = DIV_ROUND_UP(u->uartclk * 32, 1082 AUART_LINECTRL_BAUD_DIV_MAX); 1083 baud_max = u->uartclk * 32 / AUART_LINECTRL_BAUD_DIV_MIN; 1084 baud = uart_get_baud_rate(u, termios, old, baud_min, baud_max); 1085 div = DIV_ROUND_CLOSEST(u->uartclk * 32, baud); 1086 } 1087 1088 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F); 1089 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6); 1090 mxs_write(ctrl, s, REG_LINECTRL); 1091 1092 mxs_write(ctrl2, s, REG_CTRL2); 1093 1094 uart_update_timeout(u, termios->c_cflag, baud); 1095 1096 /* prepare for the DMA RX. */ 1097 if (auart_dma_enabled(s) && 1098 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) { 1099 if (!mxs_auart_dma_prep_rx(s)) { 1100 /* Disable the normal RX interrupt. */ 1101 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN, 1102 s, REG_INTR); 1103 } else { 1104 mxs_auart_dma_exit(s); 1105 dev_err(s->dev, "We can not start up the DMA.\n"); 1106 } 1107 } 1108 1109 /* CTS flow-control and modem-status interrupts */ 1110 if (UART_ENABLE_MS(u, termios->c_cflag)) 1111 mxs_auart_enable_ms(u); 1112 else 1113 mxs_auart_disable_ms(u); 1114 } 1115 1116 static void mxs_auart_set_ldisc(struct uart_port *port, 1117 struct ktermios *termios) 1118 { 1119 if (termios->c_line == N_PPS) { 1120 port->flags |= UPF_HARDPPS_CD; 1121 mxs_auart_enable_ms(port); 1122 } else { 1123 port->flags &= ~UPF_HARDPPS_CD; 1124 } 1125 } 1126 1127 static irqreturn_t mxs_auart_irq_handle(int irq, void *context) 1128 { 1129 u32 istat; 1130 struct mxs_auart_port *s = context; 1131 u32 mctrl_temp = s->mctrl_prev; 1132 u32 stat = mxs_read(s, REG_STAT); 1133 1134 istat = mxs_read(s, REG_INTR); 1135 1136 /* ack irq */ 1137 mxs_clr(istat & (AUART_INTR_RTIS | AUART_INTR_TXIS | AUART_INTR_RXIS 1138 | AUART_INTR_CTSMIS), s, REG_INTR); 1139 1140 /* 1141 * Dealing with GPIO interrupt 1142 */ 1143 if (irq == s->gpio_irq[UART_GPIO_CTS] || 1144 irq == s->gpio_irq[UART_GPIO_DCD] || 1145 irq == s->gpio_irq[UART_GPIO_DSR] || 1146 irq == s->gpio_irq[UART_GPIO_RI]) 1147 mxs_auart_modem_status(s, 1148 mctrl_gpio_get(s->gpios, &mctrl_temp)); 1149 1150 if (istat & AUART_INTR_CTSMIS) { 1151 if (CTS_AT_AUART() && s->ms_irq_enabled) 1152 uart_handle_cts_change(&s->port, 1153 stat & AUART_STAT_CTS); 1154 mxs_clr(AUART_INTR_CTSMIS, s, REG_INTR); 1155 istat &= ~AUART_INTR_CTSMIS; 1156 } 1157 1158 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) { 1159 if (!auart_dma_enabled(s)) 1160 mxs_auart_rx_chars(s); 1161 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS); 1162 } 1163 1164 if (istat & AUART_INTR_TXIS) { 1165 mxs_auart_tx_chars(s); 1166 istat &= ~AUART_INTR_TXIS; 1167 } 1168 1169 return IRQ_HANDLED; 1170 } 1171 1172 static void mxs_auart_reset_deassert(struct mxs_auart_port *s) 1173 { 1174 int i; 1175 unsigned int reg; 1176 1177 mxs_clr(AUART_CTRL0_SFTRST, s, REG_CTRL0); 1178 1179 for (i = 0; i < 10000; i++) { 1180 reg = mxs_read(s, REG_CTRL0); 1181 if (!(reg & AUART_CTRL0_SFTRST)) 1182 break; 1183 udelay(3); 1184 } 1185 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1186 } 1187 1188 static void mxs_auart_reset_assert(struct mxs_auart_port *s) 1189 { 1190 int i; 1191 u32 reg; 1192 1193 reg = mxs_read(s, REG_CTRL0); 1194 /* if already in reset state, keep it untouched */ 1195 if (reg & AUART_CTRL0_SFTRST) 1196 return; 1197 1198 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1199 mxs_set(AUART_CTRL0_SFTRST, s, REG_CTRL0); 1200 1201 for (i = 0; i < 1000; i++) { 1202 reg = mxs_read(s, REG_CTRL0); 1203 /* reset is finished when the clock is gated */ 1204 if (reg & AUART_CTRL0_CLKGATE) 1205 return; 1206 udelay(10); 1207 } 1208 1209 dev_err(s->dev, "Failed to reset the unit."); 1210 } 1211 1212 static int mxs_auart_startup(struct uart_port *u) 1213 { 1214 int ret; 1215 struct mxs_auart_port *s = to_auart_port(u); 1216 1217 ret = clk_prepare_enable(s->clk); 1218 if (ret) 1219 return ret; 1220 1221 if (uart_console(u)) { 1222 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1223 } else { 1224 /* reset the unit to a well known state */ 1225 mxs_auart_reset_assert(s); 1226 mxs_auart_reset_deassert(s); 1227 } 1228 1229 mxs_set(AUART_CTRL2_UARTEN, s, REG_CTRL2); 1230 1231 mxs_write(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN, 1232 s, REG_INTR); 1233 1234 /* Reset FIFO size (it could have changed if DMA was enabled) */ 1235 u->fifosize = MXS_AUART_FIFO_SIZE; 1236 1237 /* 1238 * Enable fifo so all four bytes of a DMA word are written to 1239 * output (otherwise, only the LSB is written, ie. 1 in 4 bytes) 1240 */ 1241 mxs_set(AUART_LINECTRL_FEN, s, REG_LINECTRL); 1242 1243 /* get initial status of modem lines */ 1244 mctrl_gpio_get(s->gpios, &s->mctrl_prev); 1245 1246 s->ms_irq_enabled = false; 1247 return 0; 1248 } 1249 1250 static void mxs_auart_shutdown(struct uart_port *u) 1251 { 1252 struct mxs_auart_port *s = to_auart_port(u); 1253 1254 mxs_auart_disable_ms(u); 1255 1256 if (auart_dma_enabled(s)) 1257 mxs_auart_dma_exit(s); 1258 1259 if (uart_console(u)) { 1260 mxs_clr(AUART_CTRL2_UARTEN, s, REG_CTRL2); 1261 1262 mxs_clr(AUART_INTR_RXIEN | AUART_INTR_RTIEN | 1263 AUART_INTR_CTSMIEN, s, REG_INTR); 1264 mxs_set(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1265 } else { 1266 mxs_auart_reset_assert(s); 1267 } 1268 1269 clk_disable_unprepare(s->clk); 1270 } 1271 1272 static unsigned int mxs_auart_tx_empty(struct uart_port *u) 1273 { 1274 struct mxs_auart_port *s = to_auart_port(u); 1275 1276 if ((mxs_read(s, REG_STAT) & 1277 (AUART_STAT_TXFE | AUART_STAT_BUSY)) == AUART_STAT_TXFE) 1278 return TIOCSER_TEMT; 1279 1280 return 0; 1281 } 1282 1283 static void mxs_auart_start_tx(struct uart_port *u) 1284 { 1285 struct mxs_auart_port *s = to_auart_port(u); 1286 1287 /* enable transmitter */ 1288 mxs_set(AUART_CTRL2_TXE, s, REG_CTRL2); 1289 1290 mxs_auart_tx_chars(s); 1291 } 1292 1293 static void mxs_auart_stop_tx(struct uart_port *u) 1294 { 1295 struct mxs_auart_port *s = to_auart_port(u); 1296 1297 mxs_clr(AUART_CTRL2_TXE, s, REG_CTRL2); 1298 } 1299 1300 static void mxs_auart_stop_rx(struct uart_port *u) 1301 { 1302 struct mxs_auart_port *s = to_auart_port(u); 1303 1304 mxs_clr(AUART_CTRL2_RXE, s, REG_CTRL2); 1305 } 1306 1307 static void mxs_auart_break_ctl(struct uart_port *u, int ctl) 1308 { 1309 struct mxs_auart_port *s = to_auart_port(u); 1310 1311 if (ctl) 1312 mxs_set(AUART_LINECTRL_BRK, s, REG_LINECTRL); 1313 else 1314 mxs_clr(AUART_LINECTRL_BRK, s, REG_LINECTRL); 1315 } 1316 1317 static const struct uart_ops mxs_auart_ops = { 1318 .tx_empty = mxs_auart_tx_empty, 1319 .start_tx = mxs_auart_start_tx, 1320 .stop_tx = mxs_auart_stop_tx, 1321 .stop_rx = mxs_auart_stop_rx, 1322 .enable_ms = mxs_auart_enable_ms, 1323 .break_ctl = mxs_auart_break_ctl, 1324 .set_mctrl = mxs_auart_set_mctrl, 1325 .get_mctrl = mxs_auart_get_mctrl, 1326 .startup = mxs_auart_startup, 1327 .shutdown = mxs_auart_shutdown, 1328 .set_termios = mxs_auart_settermios, 1329 .set_ldisc = mxs_auart_set_ldisc, 1330 .type = mxs_auart_type, 1331 .release_port = mxs_auart_release_port, 1332 .request_port = mxs_auart_request_port, 1333 .config_port = mxs_auart_config_port, 1334 .verify_port = mxs_auart_verify_port, 1335 }; 1336 1337 static struct mxs_auart_port *auart_port[MXS_AUART_PORTS]; 1338 1339 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 1340 static void mxs_auart_console_putchar(struct uart_port *port, int ch) 1341 { 1342 struct mxs_auart_port *s = to_auart_port(port); 1343 unsigned int to = 1000; 1344 1345 while (mxs_read(s, REG_STAT) & AUART_STAT_TXFF) { 1346 if (!to--) 1347 break; 1348 udelay(1); 1349 } 1350 1351 mxs_write(ch, s, REG_DATA); 1352 } 1353 1354 static void 1355 auart_console_write(struct console *co, const char *str, unsigned int count) 1356 { 1357 struct mxs_auart_port *s; 1358 struct uart_port *port; 1359 unsigned int old_ctrl0, old_ctrl2; 1360 unsigned int to = 20000; 1361 1362 if (co->index >= MXS_AUART_PORTS || co->index < 0) 1363 return; 1364 1365 s = auart_port[co->index]; 1366 port = &s->port; 1367 1368 clk_enable(s->clk); 1369 1370 /* First save the CR then disable the interrupts */ 1371 old_ctrl2 = mxs_read(s, REG_CTRL2); 1372 old_ctrl0 = mxs_read(s, REG_CTRL0); 1373 1374 mxs_clr(AUART_CTRL0_CLKGATE, s, REG_CTRL0); 1375 mxs_set(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE, s, REG_CTRL2); 1376 1377 uart_console_write(port, str, count, mxs_auart_console_putchar); 1378 1379 /* Finally, wait for transmitter to become empty ... */ 1380 while (mxs_read(s, REG_STAT) & AUART_STAT_BUSY) { 1381 udelay(1); 1382 if (!to--) 1383 break; 1384 } 1385 1386 /* 1387 * ... and restore the TCR if we waited long enough for the transmitter 1388 * to be idle. This might keep the transmitter enabled although it is 1389 * unused, but that is better than to disable it while it is still 1390 * transmitting. 1391 */ 1392 if (!(mxs_read(s, REG_STAT) & AUART_STAT_BUSY)) { 1393 mxs_write(old_ctrl0, s, REG_CTRL0); 1394 mxs_write(old_ctrl2, s, REG_CTRL2); 1395 } 1396 1397 clk_disable(s->clk); 1398 } 1399 1400 static void __init 1401 auart_console_get_options(struct mxs_auart_port *s, int *baud, 1402 int *parity, int *bits) 1403 { 1404 struct uart_port *port = &s->port; 1405 unsigned int lcr_h, quot; 1406 1407 if (!(mxs_read(s, REG_CTRL2) & AUART_CTRL2_UARTEN)) 1408 return; 1409 1410 lcr_h = mxs_read(s, REG_LINECTRL); 1411 1412 *parity = 'n'; 1413 if (lcr_h & AUART_LINECTRL_PEN) { 1414 if (lcr_h & AUART_LINECTRL_EPS) 1415 *parity = 'e'; 1416 else 1417 *parity = 'o'; 1418 } 1419 1420 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2)) 1421 *bits = 7; 1422 else 1423 *bits = 8; 1424 1425 quot = ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVINT_MASK)) 1426 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6); 1427 quot |= ((mxs_read(s, REG_LINECTRL) & AUART_LINECTRL_BAUD_DIVFRAC_MASK)) 1428 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT; 1429 if (quot == 0) 1430 quot = 1; 1431 1432 *baud = (port->uartclk << 2) / quot; 1433 } 1434 1435 static int __init 1436 auart_console_setup(struct console *co, char *options) 1437 { 1438 struct mxs_auart_port *s; 1439 int baud = 9600; 1440 int bits = 8; 1441 int parity = 'n'; 1442 int flow = 'n'; 1443 int ret; 1444 1445 /* 1446 * Check whether an invalid uart number has been specified, and 1447 * if so, search for the first available port that does have 1448 * console support. 1449 */ 1450 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port)) 1451 co->index = 0; 1452 s = auart_port[co->index]; 1453 if (!s) 1454 return -ENODEV; 1455 1456 ret = clk_prepare_enable(s->clk); 1457 if (ret) 1458 return ret; 1459 1460 if (options) 1461 uart_parse_options(options, &baud, &parity, &bits, &flow); 1462 else 1463 auart_console_get_options(s, &baud, &parity, &bits); 1464 1465 ret = uart_set_options(&s->port, co, baud, parity, bits, flow); 1466 1467 clk_disable_unprepare(s->clk); 1468 1469 return ret; 1470 } 1471 1472 static struct console auart_console = { 1473 .name = "ttyAPP", 1474 .write = auart_console_write, 1475 .device = uart_console_device, 1476 .setup = auart_console_setup, 1477 .flags = CON_PRINTBUFFER, 1478 .index = -1, 1479 .data = &auart_driver, 1480 }; 1481 #endif 1482 1483 static struct uart_driver auart_driver = { 1484 .owner = THIS_MODULE, 1485 .driver_name = "ttyAPP", 1486 .dev_name = "ttyAPP", 1487 .major = 0, 1488 .minor = 0, 1489 .nr = MXS_AUART_PORTS, 1490 #ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE 1491 .cons = &auart_console, 1492 #endif 1493 }; 1494 1495 static void mxs_init_regs(struct mxs_auart_port *s) 1496 { 1497 if (is_asm9260_auart(s)) 1498 s->vendor = &vendor_alphascale_asm9260; 1499 else 1500 s->vendor = &vendor_freescale_stmp37xx; 1501 } 1502 1503 static int mxs_get_clks(struct mxs_auart_port *s, 1504 struct platform_device *pdev) 1505 { 1506 int err; 1507 1508 if (!is_asm9260_auart(s)) { 1509 s->clk = devm_clk_get(&pdev->dev, NULL); 1510 return PTR_ERR_OR_ZERO(s->clk); 1511 } 1512 1513 s->clk = devm_clk_get(s->dev, "mod"); 1514 if (IS_ERR(s->clk)) { 1515 dev_err(s->dev, "Failed to get \"mod\" clk\n"); 1516 return PTR_ERR(s->clk); 1517 } 1518 1519 s->clk_ahb = devm_clk_get(s->dev, "ahb"); 1520 if (IS_ERR(s->clk_ahb)) { 1521 dev_err(s->dev, "Failed to get \"ahb\" clk\n"); 1522 return PTR_ERR(s->clk_ahb); 1523 } 1524 1525 err = clk_prepare_enable(s->clk_ahb); 1526 if (err) { 1527 dev_err(s->dev, "Failed to enable ahb_clk!\n"); 1528 return err; 1529 } 1530 1531 err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb)); 1532 if (err) { 1533 dev_err(s->dev, "Failed to set rate!\n"); 1534 goto disable_clk_ahb; 1535 } 1536 1537 err = clk_prepare_enable(s->clk); 1538 if (err) { 1539 dev_err(s->dev, "Failed to enable clk!\n"); 1540 goto disable_clk_ahb; 1541 } 1542 1543 return 0; 1544 1545 disable_clk_ahb: 1546 clk_disable_unprepare(s->clk_ahb); 1547 return err; 1548 } 1549 1550 /* 1551 * This function returns 1 if pdev isn't a device instatiated by dt, 0 if it 1552 * could successfully get all information from dt or a negative errno. 1553 */ 1554 static int serial_mxs_probe_dt(struct mxs_auart_port *s, 1555 struct platform_device *pdev) 1556 { 1557 struct device_node *np = pdev->dev.of_node; 1558 int ret; 1559 1560 if (!np) 1561 /* no device tree device */ 1562 return 1; 1563 1564 ret = of_alias_get_id(np, "serial"); 1565 if (ret < 0) { 1566 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret); 1567 return ret; 1568 } 1569 s->port.line = ret; 1570 1571 if (of_get_property(np, "uart-has-rtscts", NULL) || 1572 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */) 1573 set_bit(MXS_AUART_RTSCTS, &s->flags); 1574 1575 return 0; 1576 } 1577 1578 static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev) 1579 { 1580 enum mctrl_gpio_idx i; 1581 struct gpio_desc *gpiod; 1582 1583 s->gpios = mctrl_gpio_init_noauto(dev, 0); 1584 if (IS_ERR(s->gpios)) 1585 return PTR_ERR(s->gpios); 1586 1587 /* Block (enabled before) DMA option if RTS or CTS is GPIO line */ 1588 if (!RTS_AT_AUART() || !CTS_AT_AUART()) { 1589 if (test_bit(MXS_AUART_RTSCTS, &s->flags)) 1590 dev_warn(dev, 1591 "DMA and flow control via gpio may cause some problems. DMA disabled!\n"); 1592 clear_bit(MXS_AUART_RTSCTS, &s->flags); 1593 } 1594 1595 for (i = 0; i < UART_GPIO_MAX; i++) { 1596 gpiod = mctrl_gpio_to_gpiod(s->gpios, i); 1597 if (gpiod && (gpiod_get_direction(gpiod) == 1)) 1598 s->gpio_irq[i] = gpiod_to_irq(gpiod); 1599 else 1600 s->gpio_irq[i] = -EINVAL; 1601 } 1602 1603 return 0; 1604 } 1605 1606 static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s) 1607 { 1608 enum mctrl_gpio_idx i; 1609 1610 for (i = 0; i < UART_GPIO_MAX; i++) 1611 if (s->gpio_irq[i] >= 0) 1612 free_irq(s->gpio_irq[i], s); 1613 } 1614 1615 static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s) 1616 { 1617 int *irq = s->gpio_irq; 1618 enum mctrl_gpio_idx i; 1619 int err = 0; 1620 1621 for (i = 0; (i < UART_GPIO_MAX) && !err; i++) { 1622 if (irq[i] < 0) 1623 continue; 1624 1625 irq_set_status_flags(irq[i], IRQ_NOAUTOEN); 1626 err = request_irq(irq[i], mxs_auart_irq_handle, 1627 IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s); 1628 if (err) 1629 dev_err(s->dev, "%s - Can't get %d irq\n", 1630 __func__, irq[i]); 1631 } 1632 1633 /* 1634 * If something went wrong, rollback. 1635 * Be careful: i may be unsigned. 1636 */ 1637 while (err && (i-- > 0)) 1638 if (irq[i] >= 0) 1639 free_irq(irq[i], s); 1640 1641 return err; 1642 } 1643 1644 static int mxs_auart_probe(struct platform_device *pdev) 1645 { 1646 const struct of_device_id *of_id = 1647 of_match_device(mxs_auart_dt_ids, &pdev->dev); 1648 struct mxs_auart_port *s; 1649 u32 version; 1650 int ret, irq; 1651 struct resource *r; 1652 1653 s = devm_kzalloc(&pdev->dev, sizeof(*s), GFP_KERNEL); 1654 if (!s) 1655 return -ENOMEM; 1656 1657 s->port.dev = &pdev->dev; 1658 s->dev = &pdev->dev; 1659 1660 ret = serial_mxs_probe_dt(s, pdev); 1661 if (ret > 0) 1662 s->port.line = pdev->id < 0 ? 0 : pdev->id; 1663 else if (ret < 0) 1664 return ret; 1665 if (s->port.line >= ARRAY_SIZE(auart_port)) { 1666 dev_err(&pdev->dev, "serial%d out of range\n", s->port.line); 1667 return -EINVAL; 1668 } 1669 1670 if (of_id) { 1671 pdev->id_entry = of_id->data; 1672 s->devtype = pdev->id_entry->driver_data; 1673 } 1674 1675 ret = mxs_get_clks(s, pdev); 1676 if (ret) 1677 return ret; 1678 1679 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1680 if (!r) { 1681 ret = -ENXIO; 1682 goto out_disable_clks; 1683 } 1684 1685 s->port.mapbase = r->start; 1686 s->port.membase = ioremap(r->start, resource_size(r)); 1687 if (!s->port.membase) { 1688 ret = -ENOMEM; 1689 goto out_disable_clks; 1690 } 1691 s->port.ops = &mxs_auart_ops; 1692 s->port.iotype = UPIO_MEM; 1693 s->port.fifosize = MXS_AUART_FIFO_SIZE; 1694 s->port.uartclk = clk_get_rate(s->clk); 1695 s->port.type = PORT_IMX; 1696 1697 mxs_init_regs(s); 1698 1699 s->mctrl_prev = 0; 1700 1701 irq = platform_get_irq(pdev, 0); 1702 if (irq < 0) { 1703 ret = irq; 1704 goto out_disable_clks; 1705 } 1706 1707 s->port.irq = irq; 1708 ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0, 1709 dev_name(&pdev->dev), s); 1710 if (ret) 1711 goto out_disable_clks; 1712 1713 platform_set_drvdata(pdev, s); 1714 1715 ret = mxs_auart_init_gpios(s, &pdev->dev); 1716 if (ret) { 1717 dev_err(&pdev->dev, "Failed to initialize GPIOs.\n"); 1718 goto out_disable_clks; 1719 } 1720 1721 /* 1722 * Get the GPIO lines IRQ 1723 */ 1724 ret = mxs_auart_request_gpio_irq(s); 1725 if (ret) 1726 goto out_disable_clks; 1727 1728 auart_port[s->port.line] = s; 1729 1730 mxs_auart_reset_deassert(s); 1731 1732 ret = uart_add_one_port(&auart_driver, &s->port); 1733 if (ret) 1734 goto out_free_qpio_irq; 1735 1736 /* ASM9260 don't have version reg */ 1737 if (is_asm9260_auart(s)) { 1738 dev_info(&pdev->dev, "Found APPUART ASM9260\n"); 1739 } else { 1740 version = mxs_read(s, REG_VERSION); 1741 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n", 1742 (version >> 24) & 0xff, 1743 (version >> 16) & 0xff, version & 0xffff); 1744 } 1745 1746 return 0; 1747 1748 out_free_qpio_irq: 1749 mxs_auart_free_gpio_irq(s); 1750 auart_port[pdev->id] = NULL; 1751 1752 out_disable_clks: 1753 if (is_asm9260_auart(s)) { 1754 clk_disable_unprepare(s->clk); 1755 clk_disable_unprepare(s->clk_ahb); 1756 } 1757 return ret; 1758 } 1759 1760 static int mxs_auart_remove(struct platform_device *pdev) 1761 { 1762 struct mxs_auart_port *s = platform_get_drvdata(pdev); 1763 1764 uart_remove_one_port(&auart_driver, &s->port); 1765 auart_port[pdev->id] = NULL; 1766 mxs_auart_free_gpio_irq(s); 1767 if (is_asm9260_auart(s)) { 1768 clk_disable_unprepare(s->clk); 1769 clk_disable_unprepare(s->clk_ahb); 1770 } 1771 1772 return 0; 1773 } 1774 1775 static struct platform_driver mxs_auart_driver = { 1776 .probe = mxs_auart_probe, 1777 .remove = mxs_auart_remove, 1778 .driver = { 1779 .name = "mxs-auart", 1780 .of_match_table = mxs_auart_dt_ids, 1781 }, 1782 }; 1783 1784 static int __init mxs_auart_init(void) 1785 { 1786 int r; 1787 1788 r = uart_register_driver(&auart_driver); 1789 if (r) 1790 goto out; 1791 1792 r = platform_driver_register(&mxs_auart_driver); 1793 if (r) 1794 goto out_err; 1795 1796 return 0; 1797 out_err: 1798 uart_unregister_driver(&auart_driver); 1799 out: 1800 return r; 1801 } 1802 1803 static void __exit mxs_auart_exit(void) 1804 { 1805 platform_driver_unregister(&mxs_auart_driver); 1806 uart_unregister_driver(&auart_driver); 1807 } 1808 1809 module_init(mxs_auart_init); 1810 module_exit(mxs_auart_exit); 1811 MODULE_LICENSE("GPL"); 1812 MODULE_DESCRIPTION("Freescale MXS application uart driver"); 1813 MODULE_ALIAS("platform:mxs-auart"); 1814