1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * *************************************************************************** 4 * Marvell Armada-3700 Serial Driver 5 * Author: Wilson Ding <dingwei@marvell.com> 6 * Copyright (C) 2015 Marvell International Ltd. 7 * *************************************************************************** 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 12 #include <linux/console.h> 13 #include <linux/delay.h> 14 #include <linux/device.h> 15 #include <linux/init.h> 16 #include <linux/io.h> 17 #include <linux/iopoll.h> 18 #include <linux/math64.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_device.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/serial.h> 26 #include <linux/serial_core.h> 27 #include <linux/slab.h> 28 #include <linux/tty.h> 29 #include <linux/tty_flip.h> 30 31 /* Register Map */ 32 #define UART_STD_RBR 0x00 33 #define UART_EXT_RBR 0x18 34 35 #define UART_STD_TSH 0x04 36 #define UART_EXT_TSH 0x1C 37 38 #define UART_STD_CTRL1 0x08 39 #define UART_EXT_CTRL1 0x04 40 #define CTRL_SOFT_RST BIT(31) 41 #define CTRL_TXFIFO_RST BIT(15) 42 #define CTRL_RXFIFO_RST BIT(14) 43 #define CTRL_SND_BRK_SEQ BIT(11) 44 #define CTRL_BRK_DET_INT BIT(3) 45 #define CTRL_FRM_ERR_INT BIT(2) 46 #define CTRL_PAR_ERR_INT BIT(1) 47 #define CTRL_OVR_ERR_INT BIT(0) 48 #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \ 49 CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) 50 51 #define UART_STD_CTRL2 UART_STD_CTRL1 52 #define UART_EXT_CTRL2 0x20 53 #define CTRL_STD_TX_RDY_INT BIT(5) 54 #define CTRL_EXT_TX_RDY_INT BIT(6) 55 #define CTRL_STD_RX_RDY_INT BIT(4) 56 #define CTRL_EXT_RX_RDY_INT BIT(5) 57 58 #define UART_STAT 0x0C 59 #define STAT_TX_FIFO_EMP BIT(13) 60 #define STAT_TX_FIFO_FUL BIT(11) 61 #define STAT_TX_EMP BIT(6) 62 #define STAT_STD_TX_RDY BIT(5) 63 #define STAT_EXT_TX_RDY BIT(15) 64 #define STAT_STD_RX_RDY BIT(4) 65 #define STAT_EXT_RX_RDY BIT(14) 66 #define STAT_BRK_DET BIT(3) 67 #define STAT_FRM_ERR BIT(2) 68 #define STAT_PAR_ERR BIT(1) 69 #define STAT_OVR_ERR BIT(0) 70 #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \ 71 | STAT_PAR_ERR | STAT_OVR_ERR) 72 73 /* 74 * Marvell Armada 3700 Functional Specifications describes that bit 21 of UART 75 * Clock Control register controls UART1 and bit 20 controls UART2. But in 76 * reality bit 21 controls UART2 and bit 20 controls UART1. This seems to be an 77 * error in Marvell's documentation. Hence following CLK_DIS macros are swapped. 78 */ 79 80 #define UART_BRDV 0x10 81 /* These bits are located in UART1 address space and control UART2 */ 82 #define UART2_CLK_DIS BIT(21) 83 /* These bits are located in UART1 address space and control UART1 */ 84 #define UART1_CLK_DIS BIT(20) 85 /* These bits are located in UART1 address space and control both UARTs */ 86 #define CLK_NO_XTAL BIT(19) 87 #define CLK_TBG_DIV1_SHIFT 15 88 #define CLK_TBG_DIV1_MASK 0x7 89 #define CLK_TBG_DIV1_MAX 6 90 #define CLK_TBG_DIV2_SHIFT 12 91 #define CLK_TBG_DIV2_MASK 0x7 92 #define CLK_TBG_DIV2_MAX 6 93 #define CLK_TBG_SEL_SHIFT 10 94 #define CLK_TBG_SEL_MASK 0x3 95 /* These bits are located in both UARTs address space */ 96 #define BRDV_BAUD_MASK 0x3FF 97 #define BRDV_BAUD_MAX BRDV_BAUD_MASK 98 99 #define UART_OSAMP 0x14 100 #define OSAMP_DEFAULT_DIVISOR 16 101 #define OSAMP_DIVISORS_MASK 0x3F3F3F3F 102 #define OSAMP_MAX_DIVISOR 63 103 104 #define MVEBU_NR_UARTS 2 105 106 #define MVEBU_UART_TYPE "mvebu-uart" 107 #define DRIVER_NAME "mvebu_serial" 108 109 enum { 110 /* Either there is only one summed IRQ... */ 111 UART_IRQ_SUM = 0, 112 /* ...or there are two separate IRQ for RX and TX */ 113 UART_RX_IRQ = 0, 114 UART_TX_IRQ, 115 UART_IRQ_COUNT 116 }; 117 118 /* Diverging register offsets */ 119 struct uart_regs_layout { 120 unsigned int rbr; 121 unsigned int tsh; 122 unsigned int ctrl; 123 unsigned int intr; 124 }; 125 126 /* Diverging flags */ 127 struct uart_flags { 128 unsigned int ctrl_tx_rdy_int; 129 unsigned int ctrl_rx_rdy_int; 130 unsigned int stat_tx_rdy; 131 unsigned int stat_rx_rdy; 132 }; 133 134 /* Driver data, a structure for each UART port */ 135 struct mvebu_uart_driver_data { 136 bool is_ext; 137 struct uart_regs_layout regs; 138 struct uart_flags flags; 139 }; 140 141 /* Saved registers during suspend */ 142 struct mvebu_uart_pm_regs { 143 unsigned int rbr; 144 unsigned int tsh; 145 unsigned int ctrl; 146 unsigned int intr; 147 unsigned int stat; 148 unsigned int brdv; 149 unsigned int osamp; 150 }; 151 152 /* MVEBU UART driver structure */ 153 struct mvebu_uart { 154 struct uart_port *port; 155 struct clk *clk; 156 int irq[UART_IRQ_COUNT]; 157 struct mvebu_uart_driver_data *data; 158 #if defined(CONFIG_PM) 159 struct mvebu_uart_pm_regs pm_regs; 160 #endif /* CONFIG_PM */ 161 }; 162 163 static struct mvebu_uart *to_mvuart(struct uart_port *port) 164 { 165 return (struct mvebu_uart *)port->private_data; 166 } 167 168 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext) 169 170 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr) 171 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh) 172 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl) 173 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) 174 175 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int) 176 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int) 177 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy) 178 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy) 179 180 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; 181 182 static DEFINE_SPINLOCK(mvebu_uart_lock); 183 184 /* Core UART Driver Operations */ 185 static unsigned int mvebu_uart_tx_empty(struct uart_port *port) 186 { 187 unsigned long flags; 188 unsigned int st; 189 190 spin_lock_irqsave(&port->lock, flags); 191 st = readl(port->membase + UART_STAT); 192 spin_unlock_irqrestore(&port->lock, flags); 193 194 return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0; 195 } 196 197 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port) 198 { 199 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 200 } 201 202 static void mvebu_uart_set_mctrl(struct uart_port *port, 203 unsigned int mctrl) 204 { 205 /* 206 * Even if we do not support configuring the modem control lines, this 207 * function must be proided to the serial core 208 */ 209 } 210 211 static void mvebu_uart_stop_tx(struct uart_port *port) 212 { 213 unsigned int ctl = readl(port->membase + UART_INTR(port)); 214 215 ctl &= ~CTRL_TX_RDY_INT(port); 216 writel(ctl, port->membase + UART_INTR(port)); 217 } 218 219 static void mvebu_uart_start_tx(struct uart_port *port) 220 { 221 unsigned int ctl; 222 struct circ_buf *xmit = &port->state->xmit; 223 224 if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { 225 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 226 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 227 port->icount.tx++; 228 } 229 230 ctl = readl(port->membase + UART_INTR(port)); 231 ctl |= CTRL_TX_RDY_INT(port); 232 writel(ctl, port->membase + UART_INTR(port)); 233 } 234 235 static void mvebu_uart_stop_rx(struct uart_port *port) 236 { 237 unsigned int ctl; 238 239 ctl = readl(port->membase + UART_CTRL(port)); 240 ctl &= ~CTRL_BRK_INT; 241 writel(ctl, port->membase + UART_CTRL(port)); 242 243 ctl = readl(port->membase + UART_INTR(port)); 244 ctl &= ~CTRL_RX_RDY_INT(port); 245 writel(ctl, port->membase + UART_INTR(port)); 246 } 247 248 static void mvebu_uart_break_ctl(struct uart_port *port, int brk) 249 { 250 unsigned int ctl; 251 unsigned long flags; 252 253 spin_lock_irqsave(&port->lock, flags); 254 ctl = readl(port->membase + UART_CTRL(port)); 255 if (brk == -1) 256 ctl |= CTRL_SND_BRK_SEQ; 257 else 258 ctl &= ~CTRL_SND_BRK_SEQ; 259 writel(ctl, port->membase + UART_CTRL(port)); 260 spin_unlock_irqrestore(&port->lock, flags); 261 } 262 263 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) 264 { 265 struct tty_port *tport = &port->state->port; 266 unsigned char ch = 0; 267 char flag = 0; 268 269 do { 270 if (status & STAT_RX_RDY(port)) { 271 ch = readl(port->membase + UART_RBR(port)); 272 ch &= 0xff; 273 flag = TTY_NORMAL; 274 port->icount.rx++; 275 276 if (status & STAT_PAR_ERR) 277 port->icount.parity++; 278 } 279 280 if (status & STAT_BRK_DET) { 281 port->icount.brk++; 282 status &= ~(STAT_FRM_ERR | STAT_PAR_ERR); 283 if (uart_handle_break(port)) 284 goto ignore_char; 285 } 286 287 if (status & STAT_OVR_ERR) 288 port->icount.overrun++; 289 290 if (status & STAT_FRM_ERR) 291 port->icount.frame++; 292 293 if (uart_handle_sysrq_char(port, ch)) 294 goto ignore_char; 295 296 if (status & port->ignore_status_mask & STAT_PAR_ERR) 297 status &= ~STAT_RX_RDY(port); 298 299 status &= port->read_status_mask; 300 301 if (status & STAT_PAR_ERR) 302 flag = TTY_PARITY; 303 304 status &= ~port->ignore_status_mask; 305 306 if (status & STAT_RX_RDY(port)) 307 tty_insert_flip_char(tport, ch, flag); 308 309 if (status & STAT_BRK_DET) 310 tty_insert_flip_char(tport, 0, TTY_BREAK); 311 312 if (status & STAT_FRM_ERR) 313 tty_insert_flip_char(tport, 0, TTY_FRAME); 314 315 if (status & STAT_OVR_ERR) 316 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 317 318 ignore_char: 319 status = readl(port->membase + UART_STAT); 320 } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET)); 321 322 tty_flip_buffer_push(tport); 323 } 324 325 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) 326 { 327 struct circ_buf *xmit = &port->state->xmit; 328 unsigned int count; 329 unsigned int st; 330 331 if (port->x_char) { 332 writel(port->x_char, port->membase + UART_TSH(port)); 333 port->icount.tx++; 334 port->x_char = 0; 335 return; 336 } 337 338 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 339 mvebu_uart_stop_tx(port); 340 return; 341 } 342 343 for (count = 0; count < port->fifosize; count++) { 344 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 345 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 346 port->icount.tx++; 347 348 if (uart_circ_empty(xmit)) 349 break; 350 351 st = readl(port->membase + UART_STAT); 352 if (st & STAT_TX_FIFO_FUL) 353 break; 354 } 355 356 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 357 uart_write_wakeup(port); 358 359 if (uart_circ_empty(xmit)) 360 mvebu_uart_stop_tx(port); 361 } 362 363 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) 364 { 365 struct uart_port *port = (struct uart_port *)dev_id; 366 unsigned int st = readl(port->membase + UART_STAT); 367 368 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 369 STAT_BRK_DET)) 370 mvebu_uart_rx_chars(port, st); 371 372 if (st & STAT_TX_RDY(port)) 373 mvebu_uart_tx_chars(port, st); 374 375 return IRQ_HANDLED; 376 } 377 378 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id) 379 { 380 struct uart_port *port = (struct uart_port *)dev_id; 381 unsigned int st = readl(port->membase + UART_STAT); 382 383 if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 384 STAT_BRK_DET)) 385 mvebu_uart_rx_chars(port, st); 386 387 return IRQ_HANDLED; 388 } 389 390 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id) 391 { 392 struct uart_port *port = (struct uart_port *)dev_id; 393 unsigned int st = readl(port->membase + UART_STAT); 394 395 if (st & STAT_TX_RDY(port)) 396 mvebu_uart_tx_chars(port, st); 397 398 return IRQ_HANDLED; 399 } 400 401 static int mvebu_uart_startup(struct uart_port *port) 402 { 403 struct mvebu_uart *mvuart = to_mvuart(port); 404 unsigned int ctl; 405 int ret; 406 407 writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST, 408 port->membase + UART_CTRL(port)); 409 udelay(1); 410 411 /* Clear the error bits of state register before IRQ request */ 412 ret = readl(port->membase + UART_STAT); 413 ret |= STAT_BRK_ERR; 414 writel(ret, port->membase + UART_STAT); 415 416 writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); 417 418 ctl = readl(port->membase + UART_INTR(port)); 419 ctl |= CTRL_RX_RDY_INT(port); 420 writel(ctl, port->membase + UART_INTR(port)); 421 422 if (!mvuart->irq[UART_TX_IRQ]) { 423 /* Old bindings with just one interrupt (UART0 only) */ 424 ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], 425 mvebu_uart_isr, port->irqflags, 426 dev_name(port->dev), port); 427 if (ret) { 428 dev_err(port->dev, "unable to request IRQ %d\n", 429 mvuart->irq[UART_IRQ_SUM]); 430 return ret; 431 } 432 } else { 433 /* New bindings with an IRQ for RX and TX (both UART) */ 434 ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], 435 mvebu_uart_rx_isr, port->irqflags, 436 dev_name(port->dev), port); 437 if (ret) { 438 dev_err(port->dev, "unable to request IRQ %d\n", 439 mvuart->irq[UART_RX_IRQ]); 440 return ret; 441 } 442 443 ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], 444 mvebu_uart_tx_isr, port->irqflags, 445 dev_name(port->dev), 446 port); 447 if (ret) { 448 dev_err(port->dev, "unable to request IRQ %d\n", 449 mvuart->irq[UART_TX_IRQ]); 450 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], 451 port); 452 return ret; 453 } 454 } 455 456 return 0; 457 } 458 459 static void mvebu_uart_shutdown(struct uart_port *port) 460 { 461 struct mvebu_uart *mvuart = to_mvuart(port); 462 463 writel(0, port->membase + UART_INTR(port)); 464 465 if (!mvuart->irq[UART_TX_IRQ]) { 466 devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port); 467 } else { 468 devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port); 469 devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port); 470 } 471 } 472 473 static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) 474 { 475 unsigned int d_divisor, m_divisor; 476 unsigned long flags; 477 u32 brdv, osamp; 478 479 if (!port->uartclk) 480 return -EOPNOTSUPP; 481 482 /* 483 * The baudrate is derived from the UART clock thanks to divisors: 484 * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6 485 * > D ("baud generator"): can divide the clock from 1 to 1023 486 * > M ("fractional divisor"): allows a better accuracy (from 1 to 63) 487 * 488 * Exact formulas for calculating baudrate: 489 * 490 * with default x16 scheme: 491 * baudrate = xtal / (d * 16) 492 * baudrate = tbg / (d1 * d2 * d * 16) 493 * 494 * with fractional divisor: 495 * baudrate = 10 * xtal / (d * (3 * (m1 + m2) + 2 * (m3 + m4))) 496 * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4))) 497 * 498 * Oversampling value: 499 * osamp = (m1 << 0) | (m2 << 8) | (m3 << 16) | (m4 << 24); 500 * 501 * Where m1 controls number of clock cycles per bit for bits 1,2,3; 502 * m2 for bits 4,5,6; m3 for bits 7,8 and m4 for bits 9,10. 503 * 504 * To simplify baudrate setup set all the M prescalers to the same 505 * value. For baudrates 9600 Bd and higher, it is enough to use the 506 * default (x16) divisor or fractional divisor with M = 63, so there 507 * is no need to use real fractional support (where the M prescalers 508 * are not equal). 509 * 510 * When all the M prescalers are zeroed then default (x16) divisor is 511 * used. Default x16 scheme is more stable than M (fractional divisor), 512 * so use M only when D divisor is not enough to derive baudrate. 513 * 514 * Member port->uartclk is either xtal clock rate or TBG clock rate 515 * divided by (d1 * d2). So d1 and d2 are already set by the UART clock 516 * driver (and UART driver itself cannot change them). Moreover they are 517 * shared between both UARTs. 518 */ 519 520 m_divisor = OSAMP_DEFAULT_DIVISOR; 521 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); 522 523 if (d_divisor > BRDV_BAUD_MAX) { 524 /* 525 * Experiments show that small M divisors are unstable. 526 * Use maximal possible M = 63 and calculate D divisor. 527 */ 528 m_divisor = OSAMP_MAX_DIVISOR; 529 d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); 530 } 531 532 if (d_divisor < 1) 533 d_divisor = 1; 534 else if (d_divisor > BRDV_BAUD_MAX) 535 d_divisor = BRDV_BAUD_MAX; 536 537 spin_lock_irqsave(&mvebu_uart_lock, flags); 538 brdv = readl(port->membase + UART_BRDV); 539 brdv &= ~BRDV_BAUD_MASK; 540 brdv |= d_divisor; 541 writel(brdv, port->membase + UART_BRDV); 542 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 543 544 osamp = readl(port->membase + UART_OSAMP); 545 osamp &= ~OSAMP_DIVISORS_MASK; 546 if (m_divisor != OSAMP_DEFAULT_DIVISOR) 547 osamp |= (m_divisor << 0) | (m_divisor << 8) | 548 (m_divisor << 16) | (m_divisor << 24); 549 writel(osamp, port->membase + UART_OSAMP); 550 551 return 0; 552 } 553 554 static void mvebu_uart_set_termios(struct uart_port *port, 555 struct ktermios *termios, 556 struct ktermios *old) 557 { 558 unsigned long flags; 559 unsigned int baud, min_baud, max_baud; 560 561 spin_lock_irqsave(&port->lock, flags); 562 563 port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | 564 STAT_TX_RDY(port) | STAT_TX_FIFO_FUL; 565 566 if (termios->c_iflag & INPCK) 567 port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; 568 569 port->ignore_status_mask = 0; 570 if (termios->c_iflag & IGNPAR) 571 port->ignore_status_mask |= 572 STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR; 573 574 if ((termios->c_cflag & CREAD) == 0) 575 port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; 576 577 /* 578 * Maximal divisor is 1023 and maximal fractional divisor is 63. And 579 * experiments show that baudrates above 1/80 of parent clock rate are 580 * not stable. So disallow baudrates above 1/80 of the parent clock 581 * rate. If port->uartclk is not available, then 582 * mvebu_uart_baud_rate_set() fails, so values min_baud and max_baud 583 * in this case do not matter. 584 */ 585 min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX * 586 OSAMP_MAX_DIVISOR); 587 max_baud = port->uartclk / 80; 588 589 baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud); 590 if (mvebu_uart_baud_rate_set(port, baud)) { 591 /* No clock available, baudrate cannot be changed */ 592 if (old) 593 baud = uart_get_baud_rate(port, old, NULL, 594 min_baud, max_baud); 595 } else { 596 tty_termios_encode_baud_rate(termios, baud, baud); 597 uart_update_timeout(port, termios->c_cflag, baud); 598 } 599 600 /* Only the following flag changes are supported */ 601 if (old) { 602 termios->c_iflag &= INPCK | IGNPAR; 603 termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); 604 termios->c_cflag &= CREAD | CBAUD; 605 termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); 606 termios->c_cflag |= CS8; 607 } 608 609 spin_unlock_irqrestore(&port->lock, flags); 610 } 611 612 static const char *mvebu_uart_type(struct uart_port *port) 613 { 614 return MVEBU_UART_TYPE; 615 } 616 617 static void mvebu_uart_release_port(struct uart_port *port) 618 { 619 /* Nothing to do here */ 620 } 621 622 static int mvebu_uart_request_port(struct uart_port *port) 623 { 624 return 0; 625 } 626 627 #ifdef CONFIG_CONSOLE_POLL 628 static int mvebu_uart_get_poll_char(struct uart_port *port) 629 { 630 unsigned int st = readl(port->membase + UART_STAT); 631 632 if (!(st & STAT_RX_RDY(port))) 633 return NO_POLL_CHAR; 634 635 return readl(port->membase + UART_RBR(port)); 636 } 637 638 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) 639 { 640 unsigned int st; 641 642 for (;;) { 643 st = readl(port->membase + UART_STAT); 644 645 if (!(st & STAT_TX_FIFO_FUL)) 646 break; 647 648 udelay(1); 649 } 650 651 writel(c, port->membase + UART_TSH(port)); 652 } 653 #endif 654 655 static const struct uart_ops mvebu_uart_ops = { 656 .tx_empty = mvebu_uart_tx_empty, 657 .set_mctrl = mvebu_uart_set_mctrl, 658 .get_mctrl = mvebu_uart_get_mctrl, 659 .stop_tx = mvebu_uart_stop_tx, 660 .start_tx = mvebu_uart_start_tx, 661 .stop_rx = mvebu_uart_stop_rx, 662 .break_ctl = mvebu_uart_break_ctl, 663 .startup = mvebu_uart_startup, 664 .shutdown = mvebu_uart_shutdown, 665 .set_termios = mvebu_uart_set_termios, 666 .type = mvebu_uart_type, 667 .release_port = mvebu_uart_release_port, 668 .request_port = mvebu_uart_request_port, 669 #ifdef CONFIG_CONSOLE_POLL 670 .poll_get_char = mvebu_uart_get_poll_char, 671 .poll_put_char = mvebu_uart_put_poll_char, 672 #endif 673 }; 674 675 /* Console Driver Operations */ 676 677 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE 678 /* Early Console */ 679 static void mvebu_uart_putc(struct uart_port *port, unsigned char c) 680 { 681 unsigned int st; 682 683 for (;;) { 684 st = readl(port->membase + UART_STAT); 685 if (!(st & STAT_TX_FIFO_FUL)) 686 break; 687 } 688 689 /* At early stage, DT is not parsed yet, only use UART0 */ 690 writel(c, port->membase + UART_STD_TSH); 691 692 for (;;) { 693 st = readl(port->membase + UART_STAT); 694 if (st & STAT_TX_FIFO_EMP) 695 break; 696 } 697 } 698 699 static void mvebu_uart_putc_early_write(struct console *con, 700 const char *s, 701 unsigned int n) 702 { 703 struct earlycon_device *dev = con->data; 704 705 uart_console_write(&dev->port, s, n, mvebu_uart_putc); 706 } 707 708 static int __init 709 mvebu_uart_early_console_setup(struct earlycon_device *device, 710 const char *opt) 711 { 712 if (!device->port.membase) 713 return -ENODEV; 714 715 device->con->write = mvebu_uart_putc_early_write; 716 717 return 0; 718 } 719 720 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup); 721 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart", 722 mvebu_uart_early_console_setup); 723 724 static void wait_for_xmitr(struct uart_port *port) 725 { 726 u32 val; 727 728 readl_poll_timeout_atomic(port->membase + UART_STAT, val, 729 (val & STAT_TX_RDY(port)), 1, 10000); 730 } 731 732 static void wait_for_xmite(struct uart_port *port) 733 { 734 u32 val; 735 736 readl_poll_timeout_atomic(port->membase + UART_STAT, val, 737 (val & STAT_TX_EMP), 1, 10000); 738 } 739 740 static void mvebu_uart_console_putchar(struct uart_port *port, unsigned char ch) 741 { 742 wait_for_xmitr(port); 743 writel(ch, port->membase + UART_TSH(port)); 744 } 745 746 static void mvebu_uart_console_write(struct console *co, const char *s, 747 unsigned int count) 748 { 749 struct uart_port *port = &mvebu_uart_ports[co->index]; 750 unsigned long flags; 751 unsigned int ier, intr, ctl; 752 int locked = 1; 753 754 if (oops_in_progress) 755 locked = spin_trylock_irqsave(&port->lock, flags); 756 else 757 spin_lock_irqsave(&port->lock, flags); 758 759 ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; 760 intr = readl(port->membase + UART_INTR(port)) & 761 (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port)); 762 writel(0, port->membase + UART_CTRL(port)); 763 writel(0, port->membase + UART_INTR(port)); 764 765 uart_console_write(port, s, count, mvebu_uart_console_putchar); 766 767 wait_for_xmite(port); 768 769 if (ier) 770 writel(ier, port->membase + UART_CTRL(port)); 771 772 if (intr) { 773 ctl = intr | readl(port->membase + UART_INTR(port)); 774 writel(ctl, port->membase + UART_INTR(port)); 775 } 776 777 if (locked) 778 spin_unlock_irqrestore(&port->lock, flags); 779 } 780 781 static int mvebu_uart_console_setup(struct console *co, char *options) 782 { 783 struct uart_port *port; 784 int baud = 9600; 785 int bits = 8; 786 int parity = 'n'; 787 int flow = 'n'; 788 789 if (co->index < 0 || co->index >= MVEBU_NR_UARTS) 790 return -EINVAL; 791 792 port = &mvebu_uart_ports[co->index]; 793 794 if (!port->mapbase || !port->membase) { 795 pr_debug("console on ttyMV%i not present\n", co->index); 796 return -ENODEV; 797 } 798 799 if (options) 800 uart_parse_options(options, &baud, &parity, &bits, &flow); 801 802 return uart_set_options(port, co, baud, parity, bits, flow); 803 } 804 805 static struct uart_driver mvebu_uart_driver; 806 807 static struct console mvebu_uart_console = { 808 .name = "ttyMV", 809 .write = mvebu_uart_console_write, 810 .device = uart_console_device, 811 .setup = mvebu_uart_console_setup, 812 .flags = CON_PRINTBUFFER, 813 .index = -1, 814 .data = &mvebu_uart_driver, 815 }; 816 817 static int __init mvebu_uart_console_init(void) 818 { 819 register_console(&mvebu_uart_console); 820 return 0; 821 } 822 823 console_initcall(mvebu_uart_console_init); 824 825 826 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */ 827 828 static struct uart_driver mvebu_uart_driver = { 829 .owner = THIS_MODULE, 830 .driver_name = DRIVER_NAME, 831 .dev_name = "ttyMV", 832 .nr = MVEBU_NR_UARTS, 833 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE 834 .cons = &mvebu_uart_console, 835 #endif 836 }; 837 838 #if defined(CONFIG_PM) 839 static int mvebu_uart_suspend(struct device *dev) 840 { 841 struct mvebu_uart *mvuart = dev_get_drvdata(dev); 842 struct uart_port *port = mvuart->port; 843 unsigned long flags; 844 845 uart_suspend_port(&mvebu_uart_driver, port); 846 847 mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); 848 mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); 849 mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); 850 mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); 851 mvuart->pm_regs.stat = readl(port->membase + UART_STAT); 852 spin_lock_irqsave(&mvebu_uart_lock, flags); 853 mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); 854 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 855 mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); 856 857 device_set_wakeup_enable(dev, true); 858 859 return 0; 860 } 861 862 static int mvebu_uart_resume(struct device *dev) 863 { 864 struct mvebu_uart *mvuart = dev_get_drvdata(dev); 865 struct uart_port *port = mvuart->port; 866 unsigned long flags; 867 868 writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); 869 writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); 870 writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); 871 writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); 872 writel(mvuart->pm_regs.stat, port->membase + UART_STAT); 873 spin_lock_irqsave(&mvebu_uart_lock, flags); 874 writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); 875 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 876 writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); 877 878 uart_resume_port(&mvebu_uart_driver, port); 879 880 return 0; 881 } 882 883 static const struct dev_pm_ops mvebu_uart_pm_ops = { 884 .suspend = mvebu_uart_suspend, 885 .resume = mvebu_uart_resume, 886 }; 887 #endif /* CONFIG_PM */ 888 889 static const struct of_device_id mvebu_uart_of_match[]; 890 891 /* Counter to keep track of each UART port id when not using CONFIG_OF */ 892 static int uart_num_counter; 893 894 static int mvebu_uart_probe(struct platform_device *pdev) 895 { 896 struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 897 const struct of_device_id *match = of_match_device(mvebu_uart_of_match, 898 &pdev->dev); 899 struct uart_port *port; 900 struct mvebu_uart *mvuart; 901 int id, irq; 902 903 if (!reg) { 904 dev_err(&pdev->dev, "no registers defined\n"); 905 return -EINVAL; 906 } 907 908 /* Assume that all UART ports have a DT alias or none has */ 909 id = of_alias_get_id(pdev->dev.of_node, "serial"); 910 if (!pdev->dev.of_node || id < 0) 911 pdev->id = uart_num_counter++; 912 else 913 pdev->id = id; 914 915 if (pdev->id >= MVEBU_NR_UARTS) { 916 dev_err(&pdev->dev, "cannot have more than %d UART ports\n", 917 MVEBU_NR_UARTS); 918 return -EINVAL; 919 } 920 921 port = &mvebu_uart_ports[pdev->id]; 922 923 spin_lock_init(&port->lock); 924 925 port->dev = &pdev->dev; 926 port->type = PORT_MVEBU; 927 port->ops = &mvebu_uart_ops; 928 port->regshift = 0; 929 930 port->fifosize = 32; 931 port->iotype = UPIO_MEM32; 932 port->flags = UPF_FIXED_PORT; 933 port->line = pdev->id; 934 935 /* 936 * IRQ number is not stored in this structure because we may have two of 937 * them per port (RX and TX). Instead, use the driver UART structure 938 * array so called ->irq[]. 939 */ 940 port->irq = 0; 941 port->irqflags = 0; 942 port->mapbase = reg->start; 943 944 port->membase = devm_ioremap_resource(&pdev->dev, reg); 945 if (IS_ERR(port->membase)) 946 return PTR_ERR(port->membase); 947 948 mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), 949 GFP_KERNEL); 950 if (!mvuart) 951 return -ENOMEM; 952 953 /* Get controller data depending on the compatible string */ 954 mvuart->data = (struct mvebu_uart_driver_data *)match->data; 955 mvuart->port = port; 956 957 port->private_data = mvuart; 958 platform_set_drvdata(pdev, mvuart); 959 960 /* Get fixed clock frequency */ 961 mvuart->clk = devm_clk_get(&pdev->dev, NULL); 962 if (IS_ERR(mvuart->clk)) { 963 if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) 964 return PTR_ERR(mvuart->clk); 965 966 if (IS_EXTENDED(port)) { 967 dev_err(&pdev->dev, "unable to get UART clock\n"); 968 return PTR_ERR(mvuart->clk); 969 } 970 } else { 971 if (!clk_prepare_enable(mvuart->clk)) 972 port->uartclk = clk_get_rate(mvuart->clk); 973 } 974 975 /* Manage interrupts */ 976 if (platform_irq_count(pdev) == 1) { 977 /* Old bindings: no name on the single unamed UART0 IRQ */ 978 irq = platform_get_irq(pdev, 0); 979 if (irq < 0) 980 return irq; 981 982 mvuart->irq[UART_IRQ_SUM] = irq; 983 } else { 984 /* 985 * New bindings: named interrupts (RX, TX) for both UARTS, 986 * only make use of uart-rx and uart-tx interrupts, do not use 987 * uart-sum of UART0 port. 988 */ 989 irq = platform_get_irq_byname(pdev, "uart-rx"); 990 if (irq < 0) 991 return irq; 992 993 mvuart->irq[UART_RX_IRQ] = irq; 994 995 irq = platform_get_irq_byname(pdev, "uart-tx"); 996 if (irq < 0) 997 return irq; 998 999 mvuart->irq[UART_TX_IRQ] = irq; 1000 } 1001 1002 /* UART Soft Reset*/ 1003 writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); 1004 udelay(1); 1005 writel(0, port->membase + UART_CTRL(port)); 1006 1007 return uart_add_one_port(&mvebu_uart_driver, port); 1008 } 1009 1010 static struct mvebu_uart_driver_data uart_std_driver_data = { 1011 .is_ext = false, 1012 .regs.rbr = UART_STD_RBR, 1013 .regs.tsh = UART_STD_TSH, 1014 .regs.ctrl = UART_STD_CTRL1, 1015 .regs.intr = UART_STD_CTRL2, 1016 .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT, 1017 .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT, 1018 .flags.stat_tx_rdy = STAT_STD_TX_RDY, 1019 .flags.stat_rx_rdy = STAT_STD_RX_RDY, 1020 }; 1021 1022 static struct mvebu_uart_driver_data uart_ext_driver_data = { 1023 .is_ext = true, 1024 .regs.rbr = UART_EXT_RBR, 1025 .regs.tsh = UART_EXT_TSH, 1026 .regs.ctrl = UART_EXT_CTRL1, 1027 .regs.intr = UART_EXT_CTRL2, 1028 .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT, 1029 .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT, 1030 .flags.stat_tx_rdy = STAT_EXT_TX_RDY, 1031 .flags.stat_rx_rdy = STAT_EXT_RX_RDY, 1032 }; 1033 1034 /* Match table for of_platform binding */ 1035 static const struct of_device_id mvebu_uart_of_match[] = { 1036 { 1037 .compatible = "marvell,armada-3700-uart", 1038 .data = (void *)&uart_std_driver_data, 1039 }, 1040 { 1041 .compatible = "marvell,armada-3700-uart-ext", 1042 .data = (void *)&uart_ext_driver_data, 1043 }, 1044 {} 1045 }; 1046 1047 static struct platform_driver mvebu_uart_platform_driver = { 1048 .probe = mvebu_uart_probe, 1049 .driver = { 1050 .name = "mvebu-uart", 1051 .of_match_table = of_match_ptr(mvebu_uart_of_match), 1052 .suppress_bind_attrs = true, 1053 #if defined(CONFIG_PM) 1054 .pm = &mvebu_uart_pm_ops, 1055 #endif /* CONFIG_PM */ 1056 }, 1057 }; 1058 1059 /* This code is based on clk-fixed-factor.c driver and modified. */ 1060 1061 struct mvebu_uart_clock { 1062 struct clk_hw clk_hw; 1063 int clock_idx; 1064 u32 pm_context_reg1; 1065 u32 pm_context_reg2; 1066 }; 1067 1068 struct mvebu_uart_clock_base { 1069 struct mvebu_uart_clock clocks[2]; 1070 unsigned int parent_rates[5]; 1071 int parent_idx; 1072 unsigned int div; 1073 void __iomem *reg1; 1074 void __iomem *reg2; 1075 bool configured; 1076 }; 1077 1078 #define PARENT_CLOCK_XTAL 4 1079 1080 #define to_uart_clock(hw) container_of(hw, struct mvebu_uart_clock, clk_hw) 1081 #define to_uart_clock_base(uart_clock) container_of(uart_clock, \ 1082 struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx]) 1083 1084 static int mvebu_uart_clock_prepare(struct clk_hw *hw) 1085 { 1086 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1087 struct mvebu_uart_clock_base *uart_clock_base = 1088 to_uart_clock_base(uart_clock); 1089 unsigned int prev_clock_idx, prev_clock_rate, prev_d1d2; 1090 unsigned int parent_clock_idx, parent_clock_rate; 1091 unsigned long flags; 1092 unsigned int d1, d2; 1093 u64 divisor; 1094 u32 val; 1095 1096 /* 1097 * This function just reconfigures UART Clock Control register (located 1098 * in UART1 address space which controls both UART1 and UART2) to 1099 * selected UART base clock and recalculates current UART1/UART2 1100 * divisors in their address spaces, so that final baudrate will not be 1101 * changed by switching UART parent clock. This is required for 1102 * otherwise kernel's boot log stops working - we need to ensure that 1103 * UART baudrate does not change during this setup. It is a one time 1104 * operation, it will execute only once and set `configured` to true, 1105 * and be skipped on subsequent calls. Because this UART Clock Control 1106 * register (UART_BRDV) is shared between UART1 baudrate function, 1107 * UART1 clock selector and UART2 clock selector, every access to 1108 * UART_BRDV (reg1) needs to be protected by a lock. 1109 */ 1110 1111 spin_lock_irqsave(&mvebu_uart_lock, flags); 1112 1113 if (uart_clock_base->configured) { 1114 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1115 return 0; 1116 } 1117 1118 parent_clock_idx = uart_clock_base->parent_idx; 1119 parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx]; 1120 1121 val = readl(uart_clock_base->reg1); 1122 1123 if (uart_clock_base->div > CLK_TBG_DIV1_MAX) { 1124 d1 = CLK_TBG_DIV1_MAX; 1125 d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; 1126 } else { 1127 d1 = uart_clock_base->div; 1128 d2 = 1; 1129 } 1130 1131 if (val & CLK_NO_XTAL) { 1132 prev_clock_idx = (val >> CLK_TBG_SEL_SHIFT) & CLK_TBG_SEL_MASK; 1133 prev_d1d2 = ((val >> CLK_TBG_DIV1_SHIFT) & CLK_TBG_DIV1_MASK) * 1134 ((val >> CLK_TBG_DIV2_SHIFT) & CLK_TBG_DIV2_MASK); 1135 } else { 1136 prev_clock_idx = PARENT_CLOCK_XTAL; 1137 prev_d1d2 = 1; 1138 } 1139 1140 /* Note that uart_clock_base->parent_rates[i] may not be available */ 1141 prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx]; 1142 1143 /* Recalculate UART1 divisor so UART1 baudrate does not change */ 1144 if (prev_clock_rate) { 1145 divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) * 1146 parent_clock_rate * prev_d1d2, 1147 prev_clock_rate * d1 * d2); 1148 if (divisor < 1) 1149 divisor = 1; 1150 else if (divisor > BRDV_BAUD_MAX) 1151 divisor = BRDV_BAUD_MAX; 1152 val = (val & ~BRDV_BAUD_MASK) | divisor; 1153 } 1154 1155 if (parent_clock_idx != PARENT_CLOCK_XTAL) { 1156 /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */ 1157 val |= CLK_NO_XTAL; 1158 val &= ~(CLK_TBG_DIV1_MASK << CLK_TBG_DIV1_SHIFT); 1159 val |= d1 << CLK_TBG_DIV1_SHIFT; 1160 val &= ~(CLK_TBG_DIV2_MASK << CLK_TBG_DIV2_SHIFT); 1161 val |= d2 << CLK_TBG_DIV2_SHIFT; 1162 val &= ~(CLK_TBG_SEL_MASK << CLK_TBG_SEL_SHIFT); 1163 val |= parent_clock_idx << CLK_TBG_SEL_SHIFT; 1164 } else { 1165 /* Use XTAL, TBG bits are then ignored */ 1166 val &= ~CLK_NO_XTAL; 1167 } 1168 1169 writel(val, uart_clock_base->reg1); 1170 1171 /* Recalculate UART2 divisor so UART2 baudrate does not change */ 1172 if (prev_clock_rate) { 1173 val = readl(uart_clock_base->reg2); 1174 divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) * 1175 parent_clock_rate * prev_d1d2, 1176 prev_clock_rate * d1 * d2); 1177 if (divisor < 1) 1178 divisor = 1; 1179 else if (divisor > BRDV_BAUD_MAX) 1180 divisor = BRDV_BAUD_MAX; 1181 val = (val & ~BRDV_BAUD_MASK) | divisor; 1182 writel(val, uart_clock_base->reg2); 1183 } 1184 1185 uart_clock_base->configured = true; 1186 1187 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1188 1189 return 0; 1190 } 1191 1192 static int mvebu_uart_clock_enable(struct clk_hw *hw) 1193 { 1194 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1195 struct mvebu_uart_clock_base *uart_clock_base = 1196 to_uart_clock_base(uart_clock); 1197 unsigned long flags; 1198 u32 val; 1199 1200 spin_lock_irqsave(&mvebu_uart_lock, flags); 1201 1202 val = readl(uart_clock_base->reg1); 1203 1204 if (uart_clock->clock_idx == 0) 1205 val &= ~UART1_CLK_DIS; 1206 else 1207 val &= ~UART2_CLK_DIS; 1208 1209 writel(val, uart_clock_base->reg1); 1210 1211 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1212 1213 return 0; 1214 } 1215 1216 static void mvebu_uart_clock_disable(struct clk_hw *hw) 1217 { 1218 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1219 struct mvebu_uart_clock_base *uart_clock_base = 1220 to_uart_clock_base(uart_clock); 1221 unsigned long flags; 1222 u32 val; 1223 1224 spin_lock_irqsave(&mvebu_uart_lock, flags); 1225 1226 val = readl(uart_clock_base->reg1); 1227 1228 if (uart_clock->clock_idx == 0) 1229 val |= UART1_CLK_DIS; 1230 else 1231 val |= UART2_CLK_DIS; 1232 1233 writel(val, uart_clock_base->reg1); 1234 1235 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1236 } 1237 1238 static int mvebu_uart_clock_is_enabled(struct clk_hw *hw) 1239 { 1240 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1241 struct mvebu_uart_clock_base *uart_clock_base = 1242 to_uart_clock_base(uart_clock); 1243 u32 val; 1244 1245 val = readl(uart_clock_base->reg1); 1246 1247 if (uart_clock->clock_idx == 0) 1248 return !(val & UART1_CLK_DIS); 1249 else 1250 return !(val & UART2_CLK_DIS); 1251 } 1252 1253 static int mvebu_uart_clock_save_context(struct clk_hw *hw) 1254 { 1255 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1256 struct mvebu_uart_clock_base *uart_clock_base = 1257 to_uart_clock_base(uart_clock); 1258 unsigned long flags; 1259 1260 spin_lock_irqsave(&mvebu_uart_lock, flags); 1261 uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1); 1262 uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2); 1263 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1264 1265 return 0; 1266 } 1267 1268 static void mvebu_uart_clock_restore_context(struct clk_hw *hw) 1269 { 1270 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1271 struct mvebu_uart_clock_base *uart_clock_base = 1272 to_uart_clock_base(uart_clock); 1273 unsigned long flags; 1274 1275 spin_lock_irqsave(&mvebu_uart_lock, flags); 1276 writel(uart_clock->pm_context_reg1, uart_clock_base->reg1); 1277 writel(uart_clock->pm_context_reg2, uart_clock_base->reg2); 1278 spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1279 } 1280 1281 static unsigned long mvebu_uart_clock_recalc_rate(struct clk_hw *hw, 1282 unsigned long parent_rate) 1283 { 1284 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1285 struct mvebu_uart_clock_base *uart_clock_base = 1286 to_uart_clock_base(uart_clock); 1287 1288 return parent_rate / uart_clock_base->div; 1289 } 1290 1291 static long mvebu_uart_clock_round_rate(struct clk_hw *hw, unsigned long rate, 1292 unsigned long *parent_rate) 1293 { 1294 struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1295 struct mvebu_uart_clock_base *uart_clock_base = 1296 to_uart_clock_base(uart_clock); 1297 1298 return *parent_rate / uart_clock_base->div; 1299 } 1300 1301 static int mvebu_uart_clock_set_rate(struct clk_hw *hw, unsigned long rate, 1302 unsigned long parent_rate) 1303 { 1304 /* 1305 * We must report success but we can do so unconditionally because 1306 * mvebu_uart_clock_round_rate returns values that ensure this call is a 1307 * nop. 1308 */ 1309 1310 return 0; 1311 } 1312 1313 static const struct clk_ops mvebu_uart_clock_ops = { 1314 .prepare = mvebu_uart_clock_prepare, 1315 .enable = mvebu_uart_clock_enable, 1316 .disable = mvebu_uart_clock_disable, 1317 .is_enabled = mvebu_uart_clock_is_enabled, 1318 .save_context = mvebu_uart_clock_save_context, 1319 .restore_context = mvebu_uart_clock_restore_context, 1320 .round_rate = mvebu_uart_clock_round_rate, 1321 .set_rate = mvebu_uart_clock_set_rate, 1322 .recalc_rate = mvebu_uart_clock_recalc_rate, 1323 }; 1324 1325 static int mvebu_uart_clock_register(struct device *dev, 1326 struct mvebu_uart_clock *uart_clock, 1327 const char *name, 1328 const char *parent_name) 1329 { 1330 struct clk_init_data init = { }; 1331 1332 uart_clock->clk_hw.init = &init; 1333 1334 init.name = name; 1335 init.ops = &mvebu_uart_clock_ops; 1336 init.flags = 0; 1337 init.num_parents = 1; 1338 init.parent_names = &parent_name; 1339 1340 return devm_clk_hw_register(dev, &uart_clock->clk_hw); 1341 } 1342 1343 static int mvebu_uart_clock_probe(struct platform_device *pdev) 1344 { 1345 static const char *const uart_clk_names[] = { "uart_1", "uart_2" }; 1346 static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P", 1347 "TBG-A-S", "TBG-B-S", 1348 "xtal" }; 1349 struct clk *parent_clks[ARRAY_SIZE(parent_clk_names)]; 1350 struct mvebu_uart_clock_base *uart_clock_base; 1351 struct clk_hw_onecell_data *hw_clk_data; 1352 struct device *dev = &pdev->dev; 1353 int i, parent_clk_idx, ret; 1354 unsigned long div, rate; 1355 struct resource *res; 1356 unsigned int d1, d2; 1357 1358 BUILD_BUG_ON(ARRAY_SIZE(uart_clk_names) != 1359 ARRAY_SIZE(uart_clock_base->clocks)); 1360 BUILD_BUG_ON(ARRAY_SIZE(parent_clk_names) != 1361 ARRAY_SIZE(uart_clock_base->parent_rates)); 1362 1363 uart_clock_base = devm_kzalloc(dev, 1364 sizeof(*uart_clock_base), 1365 GFP_KERNEL); 1366 if (!uart_clock_base) 1367 return -ENOMEM; 1368 1369 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1370 if (!res) { 1371 dev_err(dev, "Couldn't get first register\n"); 1372 return -ENOENT; 1373 } 1374 1375 /* 1376 * UART Clock Control register (reg1 / UART_BRDV) is in the address 1377 * space of UART1 (standard UART variant), controls parent clock and 1378 * dividers for both UART1 and UART2 and is supplied via DT as the first 1379 * resource. Therefore use ioremap() rather than ioremap_resource() to 1380 * avoid conflicts with UART1 driver. Access to UART_BRDV is protected 1381 * by a lock shared between clock and UART driver. 1382 */ 1383 uart_clock_base->reg1 = devm_ioremap(dev, res->start, 1384 resource_size(res)); 1385 if (!uart_clock_base->reg1) 1386 return -ENOMEM; 1387 1388 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1389 if (!res) { 1390 dev_err(dev, "Couldn't get second register\n"); 1391 return -ENOENT; 1392 } 1393 1394 /* 1395 * UART 2 Baud Rate Divisor register (reg2 / UART_BRDV) is in address 1396 * space of UART2 (extended UART variant), controls only one UART2 1397 * specific divider and is supplied via DT as second resource. 1398 * Therefore use ioremap() rather than ioremap_resource() to avoid 1399 * conflicts with UART2 driver. Access to UART_BRDV is protected by a 1400 * by lock shared between clock and UART driver. 1401 */ 1402 uart_clock_base->reg2 = devm_ioremap(dev, res->start, 1403 resource_size(res)); 1404 if (!uart_clock_base->reg2) 1405 return -ENOMEM; 1406 1407 hw_clk_data = devm_kzalloc(dev, 1408 struct_size(hw_clk_data, hws, 1409 ARRAY_SIZE(uart_clk_names)), 1410 GFP_KERNEL); 1411 if (!hw_clk_data) 1412 return -ENOMEM; 1413 1414 hw_clk_data->num = ARRAY_SIZE(uart_clk_names); 1415 for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) { 1416 hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw; 1417 uart_clock_base->clocks[i].clock_idx = i; 1418 } 1419 1420 parent_clk_idx = -1; 1421 1422 for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) { 1423 parent_clks[i] = devm_clk_get(dev, parent_clk_names[i]); 1424 if (IS_ERR(parent_clks[i])) { 1425 if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER) 1426 return -EPROBE_DEFER; 1427 dev_warn(dev, "Couldn't get the parent clock %s: %ld\n", 1428 parent_clk_names[i], PTR_ERR(parent_clks[i])); 1429 continue; 1430 } 1431 1432 ret = clk_prepare_enable(parent_clks[i]); 1433 if (ret) { 1434 dev_warn(dev, "Couldn't enable parent clock %s: %d\n", 1435 parent_clk_names[i], ret); 1436 continue; 1437 } 1438 rate = clk_get_rate(parent_clks[i]); 1439 uart_clock_base->parent_rates[i] = rate; 1440 1441 if (i != PARENT_CLOCK_XTAL) { 1442 /* 1443 * Calculate the smallest TBG d1 and d2 divisors that 1444 * still can provide 9600 baudrate. 1445 */ 1446 d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * 1447 BRDV_BAUD_MAX); 1448 if (d1 < 1) 1449 d1 = 1; 1450 else if (d1 > CLK_TBG_DIV1_MAX) 1451 d1 = CLK_TBG_DIV1_MAX; 1452 1453 d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * 1454 BRDV_BAUD_MAX * d1); 1455 if (d2 < 1) 1456 d2 = 1; 1457 else if (d2 > CLK_TBG_DIV2_MAX) 1458 d2 = CLK_TBG_DIV2_MAX; 1459 } else { 1460 /* 1461 * When UART clock uses XTAL clock as a source then it 1462 * is not possible to use d1 and d2 divisors. 1463 */ 1464 d1 = d2 = 1; 1465 } 1466 1467 /* Skip clock source which cannot provide 9600 baudrate */ 1468 if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2) 1469 continue; 1470 1471 /* 1472 * Choose TBG clock source with the smallest divisors. Use XTAL 1473 * clock source only in case TBG is not available as XTAL cannot 1474 * be used for baudrates higher than 230400. 1475 */ 1476 if (parent_clk_idx == -1 || 1477 (i != PARENT_CLOCK_XTAL && div > d1 * d2)) { 1478 parent_clk_idx = i; 1479 div = d1 * d2; 1480 } 1481 } 1482 1483 for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) { 1484 if (i == parent_clk_idx || IS_ERR(parent_clks[i])) 1485 continue; 1486 clk_disable_unprepare(parent_clks[i]); 1487 devm_clk_put(dev, parent_clks[i]); 1488 } 1489 1490 if (parent_clk_idx == -1) { 1491 dev_err(dev, "No usable parent clock\n"); 1492 return -ENOENT; 1493 } 1494 1495 uart_clock_base->parent_idx = parent_clk_idx; 1496 uart_clock_base->div = div; 1497 1498 dev_notice(dev, "Using parent clock %s as base UART clock\n", 1499 __clk_get_name(parent_clks[parent_clk_idx])); 1500 1501 for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) { 1502 ret = mvebu_uart_clock_register(dev, 1503 &uart_clock_base->clocks[i], 1504 uart_clk_names[i], 1505 __clk_get_name(parent_clks[parent_clk_idx])); 1506 if (ret) { 1507 dev_err(dev, "Can't register UART clock %d: %d\n", 1508 i, ret); 1509 return ret; 1510 } 1511 } 1512 1513 return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1514 hw_clk_data); 1515 } 1516 1517 static const struct of_device_id mvebu_uart_clock_of_match[] = { 1518 { .compatible = "marvell,armada-3700-uart-clock", }, 1519 { } 1520 }; 1521 1522 static struct platform_driver mvebu_uart_clock_platform_driver = { 1523 .probe = mvebu_uart_clock_probe, 1524 .driver = { 1525 .name = "mvebu-uart-clock", 1526 .of_match_table = mvebu_uart_clock_of_match, 1527 }, 1528 }; 1529 1530 static int __init mvebu_uart_init(void) 1531 { 1532 int ret; 1533 1534 ret = uart_register_driver(&mvebu_uart_driver); 1535 if (ret) 1536 return ret; 1537 1538 ret = platform_driver_register(&mvebu_uart_clock_platform_driver); 1539 if (ret) { 1540 uart_unregister_driver(&mvebu_uart_driver); 1541 return ret; 1542 } 1543 1544 ret = platform_driver_register(&mvebu_uart_platform_driver); 1545 if (ret) { 1546 platform_driver_unregister(&mvebu_uart_clock_platform_driver); 1547 uart_unregister_driver(&mvebu_uart_driver); 1548 return ret; 1549 } 1550 1551 return 0; 1552 } 1553 arch_initcall(mvebu_uart_init); 1554