xref: /openbmc/linux/drivers/tty/serial/mvebu-uart.c (revision 9fb29c73)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * ***************************************************************************
4 * Marvell Armada-3700 Serial Driver
5 * Author: Wilson Ding <dingwei@marvell.com>
6 * Copyright (C) 2015 Marvell International Ltd.
7 * ***************************************************************************
8 */
9 
10 #include <linux/clk.h>
11 #include <linux/console.h>
12 #include <linux/delay.h>
13 #include <linux/device.h>
14 #include <linux/init.h>
15 #include <linux/io.h>
16 #include <linux/iopoll.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/platform_device.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 
29 /* Register Map */
30 #define UART_STD_RBR		0x00
31 #define UART_EXT_RBR		0x18
32 
33 #define UART_STD_TSH		0x04
34 #define UART_EXT_TSH		0x1C
35 
36 #define UART_STD_CTRL1		0x08
37 #define UART_EXT_CTRL1		0x04
38 #define  CTRL_SOFT_RST		BIT(31)
39 #define  CTRL_TXFIFO_RST	BIT(15)
40 #define  CTRL_RXFIFO_RST	BIT(14)
41 #define  CTRL_SND_BRK_SEQ	BIT(11)
42 #define  CTRL_BRK_DET_INT	BIT(3)
43 #define  CTRL_FRM_ERR_INT	BIT(2)
44 #define  CTRL_PAR_ERR_INT	BIT(1)
45 #define  CTRL_OVR_ERR_INT	BIT(0)
46 #define  CTRL_BRK_INT		(CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \
47 				CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT)
48 
49 #define UART_STD_CTRL2		UART_STD_CTRL1
50 #define UART_EXT_CTRL2		0x20
51 #define  CTRL_STD_TX_RDY_INT	BIT(5)
52 #define  CTRL_EXT_TX_RDY_INT	BIT(6)
53 #define  CTRL_STD_RX_RDY_INT	BIT(4)
54 #define  CTRL_EXT_RX_RDY_INT	BIT(5)
55 
56 #define UART_STAT		0x0C
57 #define  STAT_TX_FIFO_EMP	BIT(13)
58 #define  STAT_TX_FIFO_FUL	BIT(11)
59 #define  STAT_TX_EMP		BIT(6)
60 #define  STAT_STD_TX_RDY	BIT(5)
61 #define  STAT_EXT_TX_RDY	BIT(15)
62 #define  STAT_STD_RX_RDY	BIT(4)
63 #define  STAT_EXT_RX_RDY	BIT(14)
64 #define  STAT_BRK_DET		BIT(3)
65 #define  STAT_FRM_ERR		BIT(2)
66 #define  STAT_PAR_ERR		BIT(1)
67 #define  STAT_OVR_ERR		BIT(0)
68 #define  STAT_BRK_ERR		(STAT_BRK_DET | STAT_FRM_ERR \
69 				 | STAT_PAR_ERR | STAT_OVR_ERR)
70 
71 #define UART_BRDV		0x10
72 #define  BRDV_BAUD_MASK         0x3FF
73 
74 #define UART_OSAMP		0x14
75 #define  OSAMP_DEFAULT_DIVISOR	16
76 #define  OSAMP_DIVISORS_MASK	0x3F3F3F3F
77 
78 #define MVEBU_NR_UARTS		2
79 
80 #define MVEBU_UART_TYPE		"mvebu-uart"
81 #define DRIVER_NAME		"mvebu_serial"
82 
83 enum {
84 	/* Either there is only one summed IRQ... */
85 	UART_IRQ_SUM = 0,
86 	/* ...or there are two separate IRQ for RX and TX */
87 	UART_RX_IRQ = 0,
88 	UART_TX_IRQ,
89 	UART_IRQ_COUNT
90 };
91 
92 /* Diverging register offsets */
93 struct uart_regs_layout {
94 	unsigned int rbr;
95 	unsigned int tsh;
96 	unsigned int ctrl;
97 	unsigned int intr;
98 };
99 
100 /* Diverging flags */
101 struct uart_flags {
102 	unsigned int ctrl_tx_rdy_int;
103 	unsigned int ctrl_rx_rdy_int;
104 	unsigned int stat_tx_rdy;
105 	unsigned int stat_rx_rdy;
106 };
107 
108 /* Driver data, a structure for each UART port */
109 struct mvebu_uart_driver_data {
110 	bool is_ext;
111 	struct uart_regs_layout regs;
112 	struct uart_flags flags;
113 };
114 
115 /* Saved registers during suspend */
116 struct mvebu_uart_pm_regs {
117 	unsigned int rbr;
118 	unsigned int tsh;
119 	unsigned int ctrl;
120 	unsigned int intr;
121 	unsigned int stat;
122 	unsigned int brdv;
123 	unsigned int osamp;
124 };
125 
126 /* MVEBU UART driver structure */
127 struct mvebu_uart {
128 	struct uart_port *port;
129 	struct clk *clk;
130 	int irq[UART_IRQ_COUNT];
131 	unsigned char __iomem *nb;
132 	struct mvebu_uart_driver_data *data;
133 #if defined(CONFIG_PM)
134 	struct mvebu_uart_pm_regs pm_regs;
135 #endif /* CONFIG_PM */
136 };
137 
138 static struct mvebu_uart *to_mvuart(struct uart_port *port)
139 {
140 	return (struct mvebu_uart *)port->private_data;
141 }
142 
143 #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext)
144 
145 #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr)
146 #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh)
147 #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl)
148 #define UART_INTR(port) (to_mvuart(port)->data->regs.intr)
149 
150 #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int)
151 #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int)
152 #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy)
153 #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy)
154 
155 static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS];
156 
157 /* Core UART Driver Operations */
158 static unsigned int mvebu_uart_tx_empty(struct uart_port *port)
159 {
160 	unsigned long flags;
161 	unsigned int st;
162 
163 	spin_lock_irqsave(&port->lock, flags);
164 	st = readl(port->membase + UART_STAT);
165 	spin_unlock_irqrestore(&port->lock, flags);
166 
167 	return (st & STAT_TX_FIFO_EMP) ? TIOCSER_TEMT : 0;
168 }
169 
170 static unsigned int mvebu_uart_get_mctrl(struct uart_port *port)
171 {
172 	return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
173 }
174 
175 static void mvebu_uart_set_mctrl(struct uart_port *port,
176 				 unsigned int mctrl)
177 {
178 /*
179  * Even if we do not support configuring the modem control lines, this
180  * function must be proided to the serial core
181  */
182 }
183 
184 static void mvebu_uart_stop_tx(struct uart_port *port)
185 {
186 	unsigned int ctl = readl(port->membase + UART_INTR(port));
187 
188 	ctl &= ~CTRL_TX_RDY_INT(port);
189 	writel(ctl, port->membase + UART_INTR(port));
190 }
191 
192 static void mvebu_uart_start_tx(struct uart_port *port)
193 {
194 	unsigned int ctl;
195 	struct circ_buf *xmit = &port->state->xmit;
196 
197 	if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
198 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
199 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
200 		port->icount.tx++;
201 	}
202 
203 	ctl = readl(port->membase + UART_INTR(port));
204 	ctl |= CTRL_TX_RDY_INT(port);
205 	writel(ctl, port->membase + UART_INTR(port));
206 }
207 
208 static void mvebu_uart_stop_rx(struct uart_port *port)
209 {
210 	unsigned int ctl;
211 
212 	ctl = readl(port->membase + UART_CTRL(port));
213 	ctl &= ~CTRL_BRK_INT;
214 	writel(ctl, port->membase + UART_CTRL(port));
215 
216 	ctl = readl(port->membase + UART_INTR(port));
217 	ctl &= ~CTRL_RX_RDY_INT(port);
218 	writel(ctl, port->membase + UART_INTR(port));
219 }
220 
221 static void mvebu_uart_break_ctl(struct uart_port *port, int brk)
222 {
223 	unsigned int ctl;
224 	unsigned long flags;
225 
226 	spin_lock_irqsave(&port->lock, flags);
227 	ctl = readl(port->membase + UART_CTRL(port));
228 	if (brk == -1)
229 		ctl |= CTRL_SND_BRK_SEQ;
230 	else
231 		ctl &= ~CTRL_SND_BRK_SEQ;
232 	writel(ctl, port->membase + UART_CTRL(port));
233 	spin_unlock_irqrestore(&port->lock, flags);
234 }
235 
236 static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status)
237 {
238 	struct tty_port *tport = &port->state->port;
239 	unsigned char ch = 0;
240 	char flag = 0;
241 
242 	do {
243 		if (status & STAT_RX_RDY(port)) {
244 			ch = readl(port->membase + UART_RBR(port));
245 			ch &= 0xff;
246 			flag = TTY_NORMAL;
247 			port->icount.rx++;
248 
249 			if (status & STAT_PAR_ERR)
250 				port->icount.parity++;
251 		}
252 
253 		if (status & STAT_BRK_DET) {
254 			port->icount.brk++;
255 			status &= ~(STAT_FRM_ERR | STAT_PAR_ERR);
256 			if (uart_handle_break(port))
257 				goto ignore_char;
258 		}
259 
260 		if (status & STAT_OVR_ERR)
261 			port->icount.overrun++;
262 
263 		if (status & STAT_FRM_ERR)
264 			port->icount.frame++;
265 
266 		if (uart_handle_sysrq_char(port, ch))
267 			goto ignore_char;
268 
269 		if (status & port->ignore_status_mask & STAT_PAR_ERR)
270 			status &= ~STAT_RX_RDY(port);
271 
272 		status &= port->read_status_mask;
273 
274 		if (status & STAT_PAR_ERR)
275 			flag = TTY_PARITY;
276 
277 		status &= ~port->ignore_status_mask;
278 
279 		if (status & STAT_RX_RDY(port))
280 			tty_insert_flip_char(tport, ch, flag);
281 
282 		if (status & STAT_BRK_DET)
283 			tty_insert_flip_char(tport, 0, TTY_BREAK);
284 
285 		if (status & STAT_FRM_ERR)
286 			tty_insert_flip_char(tport, 0, TTY_FRAME);
287 
288 		if (status & STAT_OVR_ERR)
289 			tty_insert_flip_char(tport, 0, TTY_OVERRUN);
290 
291 ignore_char:
292 		status = readl(port->membase + UART_STAT);
293 	} while (status & (STAT_RX_RDY(port) | STAT_BRK_DET));
294 
295 	tty_flip_buffer_push(tport);
296 }
297 
298 static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status)
299 {
300 	struct circ_buf *xmit = &port->state->xmit;
301 	unsigned int count;
302 	unsigned int st;
303 
304 	if (port->x_char) {
305 		writel(port->x_char, port->membase + UART_TSH(port));
306 		port->icount.tx++;
307 		port->x_char = 0;
308 		return;
309 	}
310 
311 	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
312 		mvebu_uart_stop_tx(port);
313 		return;
314 	}
315 
316 	for (count = 0; count < port->fifosize; count++) {
317 		writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
318 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
319 		port->icount.tx++;
320 
321 		if (uart_circ_empty(xmit))
322 			break;
323 
324 		st = readl(port->membase + UART_STAT);
325 		if (st & STAT_TX_FIFO_FUL)
326 			break;
327 	}
328 
329 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
330 		uart_write_wakeup(port);
331 
332 	if (uart_circ_empty(xmit))
333 		mvebu_uart_stop_tx(port);
334 }
335 
336 static irqreturn_t mvebu_uart_isr(int irq, void *dev_id)
337 {
338 	struct uart_port *port = (struct uart_port *)dev_id;
339 	unsigned int st = readl(port->membase + UART_STAT);
340 
341 	if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
342 		  STAT_BRK_DET))
343 		mvebu_uart_rx_chars(port, st);
344 
345 	if (st & STAT_TX_RDY(port))
346 		mvebu_uart_tx_chars(port, st);
347 
348 	return IRQ_HANDLED;
349 }
350 
351 static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id)
352 {
353 	struct uart_port *port = (struct uart_port *)dev_id;
354 	unsigned int st = readl(port->membase + UART_STAT);
355 
356 	if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR |
357 			STAT_BRK_DET))
358 		mvebu_uart_rx_chars(port, st);
359 
360 	return IRQ_HANDLED;
361 }
362 
363 static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id)
364 {
365 	struct uart_port *port = (struct uart_port *)dev_id;
366 	unsigned int st = readl(port->membase + UART_STAT);
367 
368 	if (st & STAT_TX_RDY(port))
369 		mvebu_uart_tx_chars(port, st);
370 
371 	return IRQ_HANDLED;
372 }
373 
374 static int mvebu_uart_startup(struct uart_port *port)
375 {
376 	struct mvebu_uart *mvuart = to_mvuart(port);
377 	unsigned int ctl;
378 	int ret;
379 
380 	writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
381 	       port->membase + UART_CTRL(port));
382 	udelay(1);
383 
384 	/* Clear the error bits of state register before IRQ request */
385 	ret = readl(port->membase + UART_STAT);
386 	ret |= STAT_BRK_ERR;
387 	writel(ret, port->membase + UART_STAT);
388 
389 	writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
390 
391 	ctl = readl(port->membase + UART_INTR(port));
392 	ctl |= CTRL_RX_RDY_INT(port);
393 	writel(ctl, port->membase + UART_INTR(port));
394 
395 	if (!mvuart->irq[UART_TX_IRQ]) {
396 		/* Old bindings with just one interrupt (UART0 only) */
397 		ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM],
398 				       mvebu_uart_isr, port->irqflags,
399 				       dev_name(port->dev), port);
400 		if (ret) {
401 			dev_err(port->dev, "unable to request IRQ %d\n",
402 				mvuart->irq[UART_IRQ_SUM]);
403 			return ret;
404 		}
405 	} else {
406 		/* New bindings with an IRQ for RX and TX (both UART) */
407 		ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ],
408 				       mvebu_uart_rx_isr, port->irqflags,
409 				       dev_name(port->dev), port);
410 		if (ret) {
411 			dev_err(port->dev, "unable to request IRQ %d\n",
412 				mvuart->irq[UART_RX_IRQ]);
413 			return ret;
414 		}
415 
416 		ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ],
417 				       mvebu_uart_tx_isr, port->irqflags,
418 				       dev_name(port->dev),
419 				       port);
420 		if (ret) {
421 			dev_err(port->dev, "unable to request IRQ %d\n",
422 				mvuart->irq[UART_TX_IRQ]);
423 			devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ],
424 				      port);
425 			return ret;
426 		}
427 	}
428 
429 	return 0;
430 }
431 
432 static void mvebu_uart_shutdown(struct uart_port *port)
433 {
434 	struct mvebu_uart *mvuart = to_mvuart(port);
435 
436 	writel(0, port->membase + UART_INTR(port));
437 
438 	if (!mvuart->irq[UART_TX_IRQ]) {
439 		devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port);
440 	} else {
441 		devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port);
442 		devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port);
443 	}
444 }
445 
446 static int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud)
447 {
448 	struct mvebu_uart *mvuart = to_mvuart(port);
449 	unsigned int d_divisor, m_divisor;
450 	u32 brdv, osamp;
451 
452 	if (IS_ERR(mvuart->clk))
453 		return -PTR_ERR(mvuart->clk);
454 
455 	/*
456 	 * The baudrate is derived from the UART clock thanks to two divisors:
457 	 *   > D ("baud generator"): can divide the clock from 2 to 2^10 - 1.
458 	 *   > M ("fractional divisor"): allows a better accuracy for
459 	 *     baudrates higher than 230400.
460 	 *
461 	 * As the derivation of M is rather complicated, the code sticks to its
462 	 * default value (x16) when all the prescalers are zeroed, and only
463 	 * makes use of D to configure the desired baudrate.
464 	 */
465 	m_divisor = OSAMP_DEFAULT_DIVISOR;
466 	d_divisor = DIV_ROUND_UP(port->uartclk, baud * m_divisor);
467 
468 	brdv = readl(port->membase + UART_BRDV);
469 	brdv &= ~BRDV_BAUD_MASK;
470 	brdv |= d_divisor;
471 	writel(brdv, port->membase + UART_BRDV);
472 
473 	osamp = readl(port->membase + UART_OSAMP);
474 	osamp &= ~OSAMP_DIVISORS_MASK;
475 	writel(osamp, port->membase + UART_OSAMP);
476 
477 	return 0;
478 }
479 
480 static void mvebu_uart_set_termios(struct uart_port *port,
481 				   struct ktermios *termios,
482 				   struct ktermios *old)
483 {
484 	unsigned long flags;
485 	unsigned int baud;
486 
487 	spin_lock_irqsave(&port->lock, flags);
488 
489 	port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR |
490 		STAT_TX_RDY(port) | STAT_TX_FIFO_FUL;
491 
492 	if (termios->c_iflag & INPCK)
493 		port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
494 
495 	port->ignore_status_mask = 0;
496 	if (termios->c_iflag & IGNPAR)
497 		port->ignore_status_mask |=
498 			STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
499 
500 	if ((termios->c_cflag & CREAD) == 0)
501 		port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR;
502 
503 	/*
504 	 * Maximum achievable frequency with simple baudrate divisor is 230400.
505 	 * Since the error per bit frame would be of more than 15%, achieving
506 	 * higher frequencies would require to implement the fractional divisor
507 	 * feature.
508 	 */
509 	baud = uart_get_baud_rate(port, termios, old, 0, 230400);
510 	if (mvebu_uart_baud_rate_set(port, baud)) {
511 		/* No clock available, baudrate cannot be changed */
512 		if (old)
513 			baud = uart_get_baud_rate(port, old, NULL, 0, 230400);
514 	} else {
515 		tty_termios_encode_baud_rate(termios, baud, baud);
516 		uart_update_timeout(port, termios->c_cflag, baud);
517 	}
518 
519 	/* Only the following flag changes are supported */
520 	if (old) {
521 		termios->c_iflag &= INPCK | IGNPAR;
522 		termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR);
523 		termios->c_cflag &= CREAD | CBAUD;
524 		termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD);
525 		termios->c_cflag |= CS8;
526 	}
527 
528 	spin_unlock_irqrestore(&port->lock, flags);
529 }
530 
531 static const char *mvebu_uart_type(struct uart_port *port)
532 {
533 	return MVEBU_UART_TYPE;
534 }
535 
536 static void mvebu_uart_release_port(struct uart_port *port)
537 {
538 	/* Nothing to do here */
539 }
540 
541 static int mvebu_uart_request_port(struct uart_port *port)
542 {
543 	return 0;
544 }
545 
546 #ifdef CONFIG_CONSOLE_POLL
547 static int mvebu_uart_get_poll_char(struct uart_port *port)
548 {
549 	unsigned int st = readl(port->membase + UART_STAT);
550 
551 	if (!(st & STAT_RX_RDY(port)))
552 		return NO_POLL_CHAR;
553 
554 	return readl(port->membase + UART_RBR(port));
555 }
556 
557 static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c)
558 {
559 	unsigned int st;
560 
561 	for (;;) {
562 		st = readl(port->membase + UART_STAT);
563 
564 		if (!(st & STAT_TX_FIFO_FUL))
565 			break;
566 
567 		udelay(1);
568 	}
569 
570 	writel(c, port->membase + UART_TSH(port));
571 }
572 #endif
573 
574 static const struct uart_ops mvebu_uart_ops = {
575 	.tx_empty	= mvebu_uart_tx_empty,
576 	.set_mctrl	= mvebu_uart_set_mctrl,
577 	.get_mctrl	= mvebu_uart_get_mctrl,
578 	.stop_tx	= mvebu_uart_stop_tx,
579 	.start_tx	= mvebu_uart_start_tx,
580 	.stop_rx	= mvebu_uart_stop_rx,
581 	.break_ctl	= mvebu_uart_break_ctl,
582 	.startup	= mvebu_uart_startup,
583 	.shutdown	= mvebu_uart_shutdown,
584 	.set_termios	= mvebu_uart_set_termios,
585 	.type		= mvebu_uart_type,
586 	.release_port	= mvebu_uart_release_port,
587 	.request_port	= mvebu_uart_request_port,
588 #ifdef CONFIG_CONSOLE_POLL
589 	.poll_get_char	= mvebu_uart_get_poll_char,
590 	.poll_put_char	= mvebu_uart_put_poll_char,
591 #endif
592 };
593 
594 /* Console Driver Operations  */
595 
596 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
597 /* Early Console */
598 static void mvebu_uart_putc(struct uart_port *port, int c)
599 {
600 	unsigned int st;
601 
602 	for (;;) {
603 		st = readl(port->membase + UART_STAT);
604 		if (!(st & STAT_TX_FIFO_FUL))
605 			break;
606 	}
607 
608 	/* At early stage, DT is not parsed yet, only use UART0 */
609 	writel(c, port->membase + UART_STD_TSH);
610 
611 	for (;;) {
612 		st = readl(port->membase + UART_STAT);
613 		if (st & STAT_TX_FIFO_EMP)
614 			break;
615 	}
616 }
617 
618 static void mvebu_uart_putc_early_write(struct console *con,
619 					const char *s,
620 					unsigned n)
621 {
622 	struct earlycon_device *dev = con->data;
623 
624 	uart_console_write(&dev->port, s, n, mvebu_uart_putc);
625 }
626 
627 static int __init
628 mvebu_uart_early_console_setup(struct earlycon_device *device,
629 			       const char *opt)
630 {
631 	if (!device->port.membase)
632 		return -ENODEV;
633 
634 	device->con->write = mvebu_uart_putc_early_write;
635 
636 	return 0;
637 }
638 
639 EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup);
640 OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart",
641 		    mvebu_uart_early_console_setup);
642 
643 static void wait_for_xmitr(struct uart_port *port)
644 {
645 	u32 val;
646 
647 	readl_poll_timeout_atomic(port->membase + UART_STAT, val,
648 				  (val & STAT_TX_RDY(port)), 1, 10000);
649 }
650 
651 static void mvebu_uart_console_putchar(struct uart_port *port, int ch)
652 {
653 	wait_for_xmitr(port);
654 	writel(ch, port->membase + UART_TSH(port));
655 }
656 
657 static void mvebu_uart_console_write(struct console *co, const char *s,
658 				     unsigned int count)
659 {
660 	struct uart_port *port = &mvebu_uart_ports[co->index];
661 	unsigned long flags;
662 	unsigned int ier, intr, ctl;
663 	int locked = 1;
664 
665 	if (oops_in_progress)
666 		locked = spin_trylock_irqsave(&port->lock, flags);
667 	else
668 		spin_lock_irqsave(&port->lock, flags);
669 
670 	ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT;
671 	intr = readl(port->membase + UART_INTR(port)) &
672 		(CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port));
673 	writel(0, port->membase + UART_CTRL(port));
674 	writel(0, port->membase + UART_INTR(port));
675 
676 	uart_console_write(port, s, count, mvebu_uart_console_putchar);
677 
678 	wait_for_xmitr(port);
679 
680 	if (ier)
681 		writel(ier, port->membase + UART_CTRL(port));
682 
683 	if (intr) {
684 		ctl = intr | readl(port->membase + UART_INTR(port));
685 		writel(ctl, port->membase + UART_INTR(port));
686 	}
687 
688 	if (locked)
689 		spin_unlock_irqrestore(&port->lock, flags);
690 }
691 
692 static int mvebu_uart_console_setup(struct console *co, char *options)
693 {
694 	struct uart_port *port;
695 	int baud = 9600;
696 	int bits = 8;
697 	int parity = 'n';
698 	int flow = 'n';
699 
700 	if (co->index < 0 || co->index >= MVEBU_NR_UARTS)
701 		return -EINVAL;
702 
703 	port = &mvebu_uart_ports[co->index];
704 
705 	if (!port->mapbase || !port->membase) {
706 		pr_debug("console on ttyMV%i not present\n", co->index);
707 		return -ENODEV;
708 	}
709 
710 	if (options)
711 		uart_parse_options(options, &baud, &parity, &bits, &flow);
712 
713 	return uart_set_options(port, co, baud, parity, bits, flow);
714 }
715 
716 static struct uart_driver mvebu_uart_driver;
717 
718 static struct console mvebu_uart_console = {
719 	.name	= "ttyMV",
720 	.write	= mvebu_uart_console_write,
721 	.device	= uart_console_device,
722 	.setup	= mvebu_uart_console_setup,
723 	.flags	= CON_PRINTBUFFER,
724 	.index	= -1,
725 	.data	= &mvebu_uart_driver,
726 };
727 
728 static int __init mvebu_uart_console_init(void)
729 {
730 	register_console(&mvebu_uart_console);
731 	return 0;
732 }
733 
734 console_initcall(mvebu_uart_console_init);
735 
736 
737 #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */
738 
739 static struct uart_driver mvebu_uart_driver = {
740 	.owner			= THIS_MODULE,
741 	.driver_name		= DRIVER_NAME,
742 	.dev_name		= "ttyMV",
743 	.nr			= MVEBU_NR_UARTS,
744 #ifdef CONFIG_SERIAL_MVEBU_CONSOLE
745 	.cons			= &mvebu_uart_console,
746 #endif
747 };
748 
749 #if defined(CONFIG_PM)
750 static int mvebu_uart_suspend(struct device *dev)
751 {
752 	struct mvebu_uart *mvuart = dev_get_drvdata(dev);
753 	struct uart_port *port = mvuart->port;
754 
755 	uart_suspend_port(&mvebu_uart_driver, port);
756 
757 	mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port));
758 	mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port));
759 	mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port));
760 	mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port));
761 	mvuart->pm_regs.stat = readl(port->membase + UART_STAT);
762 	mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV);
763 	mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP);
764 
765 	device_set_wakeup_enable(dev, true);
766 
767 	return 0;
768 }
769 
770 static int mvebu_uart_resume(struct device *dev)
771 {
772 	struct mvebu_uart *mvuart = dev_get_drvdata(dev);
773 	struct uart_port *port = mvuart->port;
774 
775 	writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port));
776 	writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port));
777 	writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port));
778 	writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port));
779 	writel(mvuart->pm_regs.stat, port->membase + UART_STAT);
780 	writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV);
781 	writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP);
782 
783 	uart_resume_port(&mvebu_uart_driver, port);
784 
785 	return 0;
786 }
787 
788 static const struct dev_pm_ops mvebu_uart_pm_ops = {
789 	.suspend        = mvebu_uart_suspend,
790 	.resume         = mvebu_uart_resume,
791 };
792 #endif /* CONFIG_PM */
793 
794 static const struct of_device_id mvebu_uart_of_match[];
795 
796 /* Counter to keep track of each UART port id when not using CONFIG_OF */
797 static int uart_num_counter;
798 
799 static int mvebu_uart_probe(struct platform_device *pdev)
800 {
801 	struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
802 	const struct of_device_id *match = of_match_device(mvebu_uart_of_match,
803 							   &pdev->dev);
804 	struct uart_port *port;
805 	struct mvebu_uart *mvuart;
806 	int ret, id, irq;
807 
808 	if (!reg) {
809 		dev_err(&pdev->dev, "no registers defined\n");
810 		return -EINVAL;
811 	}
812 
813 	/* Assume that all UART ports have a DT alias or none has */
814 	id = of_alias_get_id(pdev->dev.of_node, "serial");
815 	if (!pdev->dev.of_node || id < 0)
816 		pdev->id = uart_num_counter++;
817 	else
818 		pdev->id = id;
819 
820 	if (pdev->id >= MVEBU_NR_UARTS) {
821 		dev_err(&pdev->dev, "cannot have more than %d UART ports\n",
822 			MVEBU_NR_UARTS);
823 		return -EINVAL;
824 	}
825 
826 	port = &mvebu_uart_ports[pdev->id];
827 
828 	spin_lock_init(&port->lock);
829 
830 	port->dev        = &pdev->dev;
831 	port->type       = PORT_MVEBU;
832 	port->ops        = &mvebu_uart_ops;
833 	port->regshift   = 0;
834 
835 	port->fifosize   = 32;
836 	port->iotype     = UPIO_MEM32;
837 	port->flags      = UPF_FIXED_PORT;
838 	port->line       = pdev->id;
839 
840 	/*
841 	 * IRQ number is not stored in this structure because we may have two of
842 	 * them per port (RX and TX). Instead, use the driver UART structure
843 	 * array so called ->irq[].
844 	 */
845 	port->irq        = 0;
846 	port->irqflags   = 0;
847 	port->mapbase    = reg->start;
848 
849 	port->membase = devm_ioremap_resource(&pdev->dev, reg);
850 	if (IS_ERR(port->membase))
851 		return -PTR_ERR(port->membase);
852 
853 	mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart),
854 			      GFP_KERNEL);
855 	if (!mvuart)
856 		return -ENOMEM;
857 
858 	/* Get controller data depending on the compatible string */
859 	mvuart->data = (struct mvebu_uart_driver_data *)match->data;
860 	mvuart->port = port;
861 
862 	port->private_data = mvuart;
863 	platform_set_drvdata(pdev, mvuart);
864 
865 	/* Get fixed clock frequency */
866 	mvuart->clk = devm_clk_get(&pdev->dev, NULL);
867 	if (IS_ERR(mvuart->clk)) {
868 		if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER)
869 			return PTR_ERR(mvuart->clk);
870 
871 		if (IS_EXTENDED(port)) {
872 			dev_err(&pdev->dev, "unable to get UART clock\n");
873 			return PTR_ERR(mvuart->clk);
874 		}
875 	} else {
876 		if (!clk_prepare_enable(mvuart->clk))
877 			port->uartclk = clk_get_rate(mvuart->clk);
878 	}
879 
880 	/* Manage interrupts */
881 	if (platform_irq_count(pdev) == 1) {
882 		/* Old bindings: no name on the single unamed UART0 IRQ */
883 		irq = platform_get_irq(pdev, 0);
884 		if (irq < 0) {
885 			dev_err(&pdev->dev, "unable to get UART IRQ\n");
886 			return irq;
887 		}
888 
889 		mvuart->irq[UART_IRQ_SUM] = irq;
890 	} else {
891 		/*
892 		 * New bindings: named interrupts (RX, TX) for both UARTS,
893 		 * only make use of uart-rx and uart-tx interrupts, do not use
894 		 * uart-sum of UART0 port.
895 		 */
896 		irq = platform_get_irq_byname(pdev, "uart-rx");
897 		if (irq < 0) {
898 			dev_err(&pdev->dev, "unable to get 'uart-rx' IRQ\n");
899 			return irq;
900 		}
901 
902 		mvuart->irq[UART_RX_IRQ] = irq;
903 
904 		irq = platform_get_irq_byname(pdev, "uart-tx");
905 		if (irq < 0) {
906 			dev_err(&pdev->dev, "unable to get 'uart-tx' IRQ\n");
907 			return irq;
908 		}
909 
910 		mvuart->irq[UART_TX_IRQ] = irq;
911 	}
912 
913 	/* UART Soft Reset*/
914 	writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port));
915 	udelay(1);
916 	writel(0, port->membase + UART_CTRL(port));
917 
918 	ret = uart_add_one_port(&mvebu_uart_driver, port);
919 	if (ret)
920 		return ret;
921 	return 0;
922 }
923 
924 static struct mvebu_uart_driver_data uart_std_driver_data = {
925 	.is_ext = false,
926 	.regs.rbr = UART_STD_RBR,
927 	.regs.tsh = UART_STD_TSH,
928 	.regs.ctrl = UART_STD_CTRL1,
929 	.regs.intr = UART_STD_CTRL2,
930 	.flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT,
931 	.flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT,
932 	.flags.stat_tx_rdy = STAT_STD_TX_RDY,
933 	.flags.stat_rx_rdy = STAT_STD_RX_RDY,
934 };
935 
936 static struct mvebu_uart_driver_data uart_ext_driver_data = {
937 	.is_ext = true,
938 	.regs.rbr = UART_EXT_RBR,
939 	.regs.tsh = UART_EXT_TSH,
940 	.regs.ctrl = UART_EXT_CTRL1,
941 	.regs.intr = UART_EXT_CTRL2,
942 	.flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT,
943 	.flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT,
944 	.flags.stat_tx_rdy = STAT_EXT_TX_RDY,
945 	.flags.stat_rx_rdy = STAT_EXT_RX_RDY,
946 };
947 
948 /* Match table for of_platform binding */
949 static const struct of_device_id mvebu_uart_of_match[] = {
950 	{
951 		.compatible = "marvell,armada-3700-uart",
952 		.data = (void *)&uart_std_driver_data,
953 	},
954 	{
955 		.compatible = "marvell,armada-3700-uart-ext",
956 		.data = (void *)&uart_ext_driver_data,
957 	},
958 	{}
959 };
960 
961 static struct platform_driver mvebu_uart_platform_driver = {
962 	.probe	= mvebu_uart_probe,
963 	.driver	= {
964 		.name  = "mvebu-uart",
965 		.of_match_table = of_match_ptr(mvebu_uart_of_match),
966 		.suppress_bind_attrs = true,
967 #if defined(CONFIG_PM)
968 		.pm	= &mvebu_uart_pm_ops,
969 #endif /* CONFIG_PM */
970 	},
971 };
972 
973 static int __init mvebu_uart_init(void)
974 {
975 	int ret;
976 
977 	ret = uart_register_driver(&mvebu_uart_driver);
978 	if (ret)
979 		return ret;
980 
981 	ret = platform_driver_register(&mvebu_uart_platform_driver);
982 	if (ret)
983 		uart_unregister_driver(&mvebu_uart_driver);
984 
985 	return ret;
986 }
987 arch_initcall(mvebu_uart_init);
988