1e3b3d0f5SGreg Kroah-Hartman // SPDX-License-Identifier: GPL-2.0+ 230530791SWilson Ding /* 330530791SWilson Ding * *************************************************************************** 489ebc274SPaul Gortmaker * Marvell Armada-3700 Serial Driver 589ebc274SPaul Gortmaker * Author: Wilson Ding <dingwei@marvell.com> 630530791SWilson Ding * Copyright (C) 2015 Marvell International Ltd. 730530791SWilson Ding * *************************************************************************** 830530791SWilson Ding */ 930530791SWilson Ding 1030530791SWilson Ding #include <linux/clk.h> 11b7e2b536SPali Rohár #include <linux/clk-provider.h> 1230530791SWilson Ding #include <linux/console.h> 1330530791SWilson Ding #include <linux/delay.h> 1430530791SWilson Ding #include <linux/device.h> 1530530791SWilson Ding #include <linux/init.h> 1630530791SWilson Ding #include <linux/io.h> 1730530791SWilson Ding #include <linux/iopoll.h> 18b7e2b536SPali Rohár #include <linux/math64.h> 1930530791SWilson Ding #include <linux/of.h> 2030530791SWilson Ding #include <linux/of_address.h> 2130530791SWilson Ding #include <linux/of_device.h> 2230530791SWilson Ding #include <linux/of_irq.h> 2330530791SWilson Ding #include <linux/of_platform.h> 2430530791SWilson Ding #include <linux/platform_device.h> 2530530791SWilson Ding #include <linux/serial.h> 2630530791SWilson Ding #include <linux/serial_core.h> 2730530791SWilson Ding #include <linux/slab.h> 2830530791SWilson Ding #include <linux/tty.h> 2930530791SWilson Ding #include <linux/tty_flip.h> 3030530791SWilson Ding 3130530791SWilson Ding /* Register Map */ 325218d769SMiquel Raynal #define UART_STD_RBR 0x00 3353501e02SMiquel Raynal #define UART_EXT_RBR 0x18 3430530791SWilson Ding 355218d769SMiquel Raynal #define UART_STD_TSH 0x04 3653501e02SMiquel Raynal #define UART_EXT_TSH 0x1C 3730530791SWilson Ding 385218d769SMiquel Raynal #define UART_STD_CTRL1 0x08 3953501e02SMiquel Raynal #define UART_EXT_CTRL1 0x04 4030530791SWilson Ding #define CTRL_SOFT_RST BIT(31) 4130530791SWilson Ding #define CTRL_TXFIFO_RST BIT(15) 4230530791SWilson Ding #define CTRL_RXFIFO_RST BIT(14) 4330530791SWilson Ding #define CTRL_SND_BRK_SEQ BIT(11) 4430530791SWilson Ding #define CTRL_BRK_DET_INT BIT(3) 4530530791SWilson Ding #define CTRL_FRM_ERR_INT BIT(2) 4630530791SWilson Ding #define CTRL_PAR_ERR_INT BIT(1) 4730530791SWilson Ding #define CTRL_OVR_ERR_INT BIT(0) 485218d769SMiquel Raynal #define CTRL_BRK_INT (CTRL_BRK_DET_INT | CTRL_FRM_ERR_INT | \ 495218d769SMiquel Raynal CTRL_PAR_ERR_INT | CTRL_OVR_ERR_INT) 5030530791SWilson Ding 515218d769SMiquel Raynal #define UART_STD_CTRL2 UART_STD_CTRL1 5253501e02SMiquel Raynal #define UART_EXT_CTRL2 0x20 535218d769SMiquel Raynal #define CTRL_STD_TX_RDY_INT BIT(5) 5453501e02SMiquel Raynal #define CTRL_EXT_TX_RDY_INT BIT(6) 555218d769SMiquel Raynal #define CTRL_STD_RX_RDY_INT BIT(4) 5653501e02SMiquel Raynal #define CTRL_EXT_RX_RDY_INT BIT(5) 575218d769SMiquel Raynal 585218d769SMiquel Raynal #define UART_STAT 0x0C 5930530791SWilson Ding #define STAT_TX_FIFO_EMP BIT(13) 6030530791SWilson Ding #define STAT_TX_FIFO_FUL BIT(11) 6130530791SWilson Ding #define STAT_TX_EMP BIT(6) 625218d769SMiquel Raynal #define STAT_STD_TX_RDY BIT(5) 6353501e02SMiquel Raynal #define STAT_EXT_TX_RDY BIT(15) 645218d769SMiquel Raynal #define STAT_STD_RX_RDY BIT(4) 6553501e02SMiquel Raynal #define STAT_EXT_RX_RDY BIT(14) 6630530791SWilson Ding #define STAT_BRK_DET BIT(3) 6730530791SWilson Ding #define STAT_FRM_ERR BIT(2) 6830530791SWilson Ding #define STAT_PAR_ERR BIT(1) 6930530791SWilson Ding #define STAT_OVR_ERR BIT(0) 700ef5a6e0SColin Ian King #define STAT_BRK_ERR (STAT_BRK_DET | STAT_FRM_ERR \ 7130530791SWilson Ding | STAT_PAR_ERR | STAT_OVR_ERR) 7230530791SWilson Ding 73b7e2b536SPali Rohár /* 74b7e2b536SPali Rohár * Marvell Armada 3700 Functional Specifications describes that bit 21 of UART 75b7e2b536SPali Rohár * Clock Control register controls UART1 and bit 20 controls UART2. But in 76b7e2b536SPali Rohár * reality bit 21 controls UART2 and bit 20 controls UART1. This seems to be an 77b7e2b536SPali Rohár * error in Marvell's documentation. Hence following CLK_DIS macros are swapped. 78b7e2b536SPali Rohár */ 79b7e2b536SPali Rohár 8030530791SWilson Ding #define UART_BRDV 0x10 81b7e2b536SPali Rohár /* These bits are located in UART1 address space and control UART2 */ 82b7e2b536SPali Rohár #define UART2_CLK_DIS BIT(21) 83b7e2b536SPali Rohár /* These bits are located in UART1 address space and control UART1 */ 84b7e2b536SPali Rohár #define UART1_CLK_DIS BIT(20) 85b7e2b536SPali Rohár /* These bits are located in UART1 address space and control both UARTs */ 86b7e2b536SPali Rohár #define CLK_NO_XTAL BIT(19) 87b7e2b536SPali Rohár #define CLK_TBG_DIV1_SHIFT 15 88b7e2b536SPali Rohár #define CLK_TBG_DIV1_MASK 0x7 89b7e2b536SPali Rohár #define CLK_TBG_DIV1_MAX 6 90b7e2b536SPali Rohár #define CLK_TBG_DIV2_SHIFT 12 91b7e2b536SPali Rohár #define CLK_TBG_DIV2_MASK 0x7 92b7e2b536SPali Rohár #define CLK_TBG_DIV2_MAX 6 93b7e2b536SPali Rohár #define CLK_TBG_SEL_SHIFT 10 94b7e2b536SPali Rohár #define CLK_TBG_SEL_MASK 0x3 95b7e2b536SPali Rohár /* These bits are located in both UARTs address space */ 9668a0db1dSAllen Yan #define BRDV_BAUD_MASK 0x3FF 97b7e2b536SPali Rohár #define BRDV_BAUD_MAX BRDV_BAUD_MASK 9830530791SWilson Ding 99394e8351SMiquel Raynal #define UART_OSAMP 0x14 1000e4cf69eSMiquel Raynal #define OSAMP_DEFAULT_DIVISOR 16 10135d7a58aSMiquel Raynal #define OSAMP_DIVISORS_MASK 0x3F3F3F3F 102694b7112SPali Rohár #define OSAMP_MAX_DIVISOR 63 103394e8351SMiquel Raynal 1043a75e91bSMiquel Raynal #define MVEBU_NR_UARTS 2 10530530791SWilson Ding 10630530791SWilson Ding #define MVEBU_UART_TYPE "mvebu-uart" 10702c33330SYehuda Yitschak #define DRIVER_NAME "mvebu_serial" 10830530791SWilson Ding 10995f78768SMiquel Raynal enum { 11095f78768SMiquel Raynal /* Either there is only one summed IRQ... */ 11195f78768SMiquel Raynal UART_IRQ_SUM = 0, 11295f78768SMiquel Raynal /* ...or there are two separate IRQ for RX and TX */ 11395f78768SMiquel Raynal UART_RX_IRQ = 0, 11495f78768SMiquel Raynal UART_TX_IRQ, 11595f78768SMiquel Raynal UART_IRQ_COUNT 11695f78768SMiquel Raynal }; 11795f78768SMiquel Raynal 11895f78768SMiquel Raynal /* Diverging register offsets */ 1195218d769SMiquel Raynal struct uart_regs_layout { 1205218d769SMiquel Raynal unsigned int rbr; 1215218d769SMiquel Raynal unsigned int tsh; 1225218d769SMiquel Raynal unsigned int ctrl; 1235218d769SMiquel Raynal unsigned int intr; 1245218d769SMiquel Raynal }; 12530530791SWilson Ding 1265218d769SMiquel Raynal /* Diverging flags */ 1275218d769SMiquel Raynal struct uart_flags { 1285218d769SMiquel Raynal unsigned int ctrl_tx_rdy_int; 1295218d769SMiquel Raynal unsigned int ctrl_rx_rdy_int; 1305218d769SMiquel Raynal unsigned int stat_tx_rdy; 1315218d769SMiquel Raynal unsigned int stat_rx_rdy; 1325218d769SMiquel Raynal }; 1335218d769SMiquel Raynal 1345218d769SMiquel Raynal /* Driver data, a structure for each UART port */ 1355218d769SMiquel Raynal struct mvebu_uart_driver_data { 1365218d769SMiquel Raynal bool is_ext; 1375218d769SMiquel Raynal struct uart_regs_layout regs; 1385218d769SMiquel Raynal struct uart_flags flags; 1395218d769SMiquel Raynal }; 1405218d769SMiquel Raynal 141394e8351SMiquel Raynal /* Saved registers during suspend */ 142394e8351SMiquel Raynal struct mvebu_uart_pm_regs { 143394e8351SMiquel Raynal unsigned int rbr; 144394e8351SMiquel Raynal unsigned int tsh; 145394e8351SMiquel Raynal unsigned int ctrl; 146394e8351SMiquel Raynal unsigned int intr; 147394e8351SMiquel Raynal unsigned int stat; 148394e8351SMiquel Raynal unsigned int brdv; 149394e8351SMiquel Raynal unsigned int osamp; 150394e8351SMiquel Raynal }; 151394e8351SMiquel Raynal 1525218d769SMiquel Raynal /* MVEBU UART driver structure */ 1535218d769SMiquel Raynal struct mvebu_uart { 15430530791SWilson Ding struct uart_port *port; 15530530791SWilson Ding struct clk *clk; 15695f78768SMiquel Raynal int irq[UART_IRQ_COUNT]; 1575218d769SMiquel Raynal struct mvebu_uart_driver_data *data; 158394e8351SMiquel Raynal #if defined(CONFIG_PM) 159394e8351SMiquel Raynal struct mvebu_uart_pm_regs pm_regs; 160394e8351SMiquel Raynal #endif /* CONFIG_PM */ 16130530791SWilson Ding }; 16230530791SWilson Ding 1635218d769SMiquel Raynal static struct mvebu_uart *to_mvuart(struct uart_port *port) 1645218d769SMiquel Raynal { 1655218d769SMiquel Raynal return (struct mvebu_uart *)port->private_data; 1665218d769SMiquel Raynal } 1675218d769SMiquel Raynal 1685218d769SMiquel Raynal #define IS_EXTENDED(port) (to_mvuart(port)->data->is_ext) 1695218d769SMiquel Raynal 1705218d769SMiquel Raynal #define UART_RBR(port) (to_mvuart(port)->data->regs.rbr) 1715218d769SMiquel Raynal #define UART_TSH(port) (to_mvuart(port)->data->regs.tsh) 1725218d769SMiquel Raynal #define UART_CTRL(port) (to_mvuart(port)->data->regs.ctrl) 1735218d769SMiquel Raynal #define UART_INTR(port) (to_mvuart(port)->data->regs.intr) 1745218d769SMiquel Raynal 1755218d769SMiquel Raynal #define CTRL_TX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_tx_rdy_int) 1765218d769SMiquel Raynal #define CTRL_RX_RDY_INT(port) (to_mvuart(port)->data->flags.ctrl_rx_rdy_int) 1775218d769SMiquel Raynal #define STAT_TX_RDY(port) (to_mvuart(port)->data->flags.stat_tx_rdy) 1785218d769SMiquel Raynal #define STAT_RX_RDY(port) (to_mvuart(port)->data->flags.stat_rx_rdy) 1795218d769SMiquel Raynal 1805218d769SMiquel Raynal static struct uart_port mvebu_uart_ports[MVEBU_NR_UARTS]; 1815218d769SMiquel Raynal 182b7e2b536SPali Rohár static DEFINE_SPINLOCK(mvebu_uart_lock); 183b7e2b536SPali Rohár 18430530791SWilson Ding /* Core UART Driver Operations */ 18530530791SWilson Ding static unsigned int mvebu_uart_tx_empty(struct uart_port *port) 18630530791SWilson Ding { 18730530791SWilson Ding unsigned long flags; 18830530791SWilson Ding unsigned int st; 18930530791SWilson Ding 19030530791SWilson Ding spin_lock_irqsave(&port->lock, flags); 19130530791SWilson Ding st = readl(port->membase + UART_STAT); 19230530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags); 19330530791SWilson Ding 19474e1eb3bSPali Rohár return (st & STAT_TX_EMP) ? TIOCSER_TEMT : 0; 19530530791SWilson Ding } 19630530791SWilson Ding 19730530791SWilson Ding static unsigned int mvebu_uart_get_mctrl(struct uart_port *port) 19830530791SWilson Ding { 19930530791SWilson Ding return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; 20030530791SWilson Ding } 20130530791SWilson Ding 20230530791SWilson Ding static void mvebu_uart_set_mctrl(struct uart_port *port, 20330530791SWilson Ding unsigned int mctrl) 20430530791SWilson Ding { 20530530791SWilson Ding /* 20630530791SWilson Ding * Even if we do not support configuring the modem control lines, this 20730530791SWilson Ding * function must be proided to the serial core 20830530791SWilson Ding */ 20930530791SWilson Ding } 21030530791SWilson Ding 21130530791SWilson Ding static void mvebu_uart_stop_tx(struct uart_port *port) 21230530791SWilson Ding { 2135218d769SMiquel Raynal unsigned int ctl = readl(port->membase + UART_INTR(port)); 21430530791SWilson Ding 2155218d769SMiquel Raynal ctl &= ~CTRL_TX_RDY_INT(port); 2165218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port)); 21730530791SWilson Ding } 21830530791SWilson Ding 21930530791SWilson Ding static void mvebu_uart_start_tx(struct uart_port *port) 22030530791SWilson Ding { 22130434b07SAllen Yan unsigned int ctl; 22230434b07SAllen Yan struct circ_buf *xmit = &port->state->xmit; 22330530791SWilson Ding 22430434b07SAllen Yan if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) { 22530434b07SAllen Yan writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); 22630434b07SAllen Yan xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 22730434b07SAllen Yan port->icount.tx++; 22830434b07SAllen Yan } 22930434b07SAllen Yan 23030434b07SAllen Yan ctl = readl(port->membase + UART_INTR(port)); 2315218d769SMiquel Raynal ctl |= CTRL_TX_RDY_INT(port); 2325218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port)); 23330530791SWilson Ding } 23430530791SWilson Ding 23530530791SWilson Ding static void mvebu_uart_stop_rx(struct uart_port *port) 23630530791SWilson Ding { 2375218d769SMiquel Raynal unsigned int ctl; 23830530791SWilson Ding 2395218d769SMiquel Raynal ctl = readl(port->membase + UART_CTRL(port)); 2405218d769SMiquel Raynal ctl &= ~CTRL_BRK_INT; 2415218d769SMiquel Raynal writel(ctl, port->membase + UART_CTRL(port)); 2425218d769SMiquel Raynal 2435218d769SMiquel Raynal ctl = readl(port->membase + UART_INTR(port)); 2445218d769SMiquel Raynal ctl &= ~CTRL_RX_RDY_INT(port); 2455218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port)); 24630530791SWilson Ding } 24730530791SWilson Ding 24830530791SWilson Ding static void mvebu_uart_break_ctl(struct uart_port *port, int brk) 24930530791SWilson Ding { 25030530791SWilson Ding unsigned int ctl; 25130530791SWilson Ding unsigned long flags; 25230530791SWilson Ding 25330530791SWilson Ding spin_lock_irqsave(&port->lock, flags); 2545218d769SMiquel Raynal ctl = readl(port->membase + UART_CTRL(port)); 25530530791SWilson Ding if (brk == -1) 25630530791SWilson Ding ctl |= CTRL_SND_BRK_SEQ; 25730530791SWilson Ding else 25830530791SWilson Ding ctl &= ~CTRL_SND_BRK_SEQ; 2595218d769SMiquel Raynal writel(ctl, port->membase + UART_CTRL(port)); 26030530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags); 26130530791SWilson Ding } 26230530791SWilson Ding 26330530791SWilson Ding static void mvebu_uart_rx_chars(struct uart_port *port, unsigned int status) 26430530791SWilson Ding { 26530530791SWilson Ding struct tty_port *tport = &port->state->port; 26630530791SWilson Ding unsigned char ch = 0; 26730530791SWilson Ding char flag = 0; 268a7209541SNarendra Hadke int ret; 26930530791SWilson Ding 27030530791SWilson Ding do { 2715218d769SMiquel Raynal if (status & STAT_RX_RDY(port)) { 2725218d769SMiquel Raynal ch = readl(port->membase + UART_RBR(port)); 27330530791SWilson Ding ch &= 0xff; 27430530791SWilson Ding flag = TTY_NORMAL; 27530530791SWilson Ding port->icount.rx++; 27630530791SWilson Ding 27730530791SWilson Ding if (status & STAT_PAR_ERR) 27830530791SWilson Ding port->icount.parity++; 27930530791SWilson Ding } 28030530791SWilson Ding 281a7209541SNarendra Hadke /* 282a7209541SNarendra Hadke * For UART2, error bits are not cleared on buffer read. 283a7209541SNarendra Hadke * This causes interrupt loop and system hang. 284a7209541SNarendra Hadke */ 285a7209541SNarendra Hadke if (IS_EXTENDED(port) && (status & STAT_BRK_ERR)) { 286a7209541SNarendra Hadke ret = readl(port->membase + UART_STAT); 287a7209541SNarendra Hadke ret |= STAT_BRK_ERR; 288a7209541SNarendra Hadke writel(ret, port->membase + UART_STAT); 289a7209541SNarendra Hadke } 290a7209541SNarendra Hadke 29130530791SWilson Ding if (status & STAT_BRK_DET) { 29230530791SWilson Ding port->icount.brk++; 29330530791SWilson Ding status &= ~(STAT_FRM_ERR | STAT_PAR_ERR); 29430530791SWilson Ding if (uart_handle_break(port)) 29530530791SWilson Ding goto ignore_char; 29630530791SWilson Ding } 29730530791SWilson Ding 29830530791SWilson Ding if (status & STAT_OVR_ERR) 29930530791SWilson Ding port->icount.overrun++; 30030530791SWilson Ding 30130530791SWilson Ding if (status & STAT_FRM_ERR) 30230530791SWilson Ding port->icount.frame++; 30330530791SWilson Ding 30430530791SWilson Ding if (uart_handle_sysrq_char(port, ch)) 30530530791SWilson Ding goto ignore_char; 30630530791SWilson Ding 30730530791SWilson Ding if (status & port->ignore_status_mask & STAT_PAR_ERR) 3085218d769SMiquel Raynal status &= ~STAT_RX_RDY(port); 30930530791SWilson Ding 31030530791SWilson Ding status &= port->read_status_mask; 31130530791SWilson Ding 31230530791SWilson Ding if (status & STAT_PAR_ERR) 31330530791SWilson Ding flag = TTY_PARITY; 31430530791SWilson Ding 31530530791SWilson Ding status &= ~port->ignore_status_mask; 31630530791SWilson Ding 3175218d769SMiquel Raynal if (status & STAT_RX_RDY(port)) 31830530791SWilson Ding tty_insert_flip_char(tport, ch, flag); 31930530791SWilson Ding 32030530791SWilson Ding if (status & STAT_BRK_DET) 32130530791SWilson Ding tty_insert_flip_char(tport, 0, TTY_BREAK); 32230530791SWilson Ding 32330530791SWilson Ding if (status & STAT_FRM_ERR) 32430530791SWilson Ding tty_insert_flip_char(tport, 0, TTY_FRAME); 32530530791SWilson Ding 32630530791SWilson Ding if (status & STAT_OVR_ERR) 32730530791SWilson Ding tty_insert_flip_char(tport, 0, TTY_OVERRUN); 32830530791SWilson Ding 32930530791SWilson Ding ignore_char: 33030530791SWilson Ding status = readl(port->membase + UART_STAT); 3315218d769SMiquel Raynal } while (status & (STAT_RX_RDY(port) | STAT_BRK_DET)); 33230530791SWilson Ding 33330530791SWilson Ding tty_flip_buffer_push(tport); 33430530791SWilson Ding } 33530530791SWilson Ding 33630530791SWilson Ding static void mvebu_uart_tx_chars(struct uart_port *port, unsigned int status) 33730530791SWilson Ding { 338*d11cc8c3SJiri Slaby (SUSE) u8 ch; 33930530791SWilson Ding 340*d11cc8c3SJiri Slaby (SUSE) uart_port_tx_limited(port, ch, port->fifosize, 341*d11cc8c3SJiri Slaby (SUSE) !(readl(port->membase + UART_STAT) & STAT_TX_FIFO_FUL), 342*d11cc8c3SJiri Slaby (SUSE) writel(ch, port->membase + UART_TSH(port)), 343*d11cc8c3SJiri Slaby (SUSE) ({})); 34430530791SWilson Ding } 34530530791SWilson Ding 34630530791SWilson Ding static irqreturn_t mvebu_uart_isr(int irq, void *dev_id) 34730530791SWilson Ding { 34830530791SWilson Ding struct uart_port *port = (struct uart_port *)dev_id; 34930530791SWilson Ding unsigned int st = readl(port->membase + UART_STAT); 35030530791SWilson Ding 3515218d769SMiquel Raynal if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 3525218d769SMiquel Raynal STAT_BRK_DET)) 35330530791SWilson Ding mvebu_uart_rx_chars(port, st); 35430530791SWilson Ding 3555218d769SMiquel Raynal if (st & STAT_TX_RDY(port)) 35630530791SWilson Ding mvebu_uart_tx_chars(port, st); 35730530791SWilson Ding 35830530791SWilson Ding return IRQ_HANDLED; 35930530791SWilson Ding } 36030530791SWilson Ding 36195f78768SMiquel Raynal static irqreturn_t mvebu_uart_rx_isr(int irq, void *dev_id) 36295f78768SMiquel Raynal { 36395f78768SMiquel Raynal struct uart_port *port = (struct uart_port *)dev_id; 36495f78768SMiquel Raynal unsigned int st = readl(port->membase + UART_STAT); 36595f78768SMiquel Raynal 36695f78768SMiquel Raynal if (st & (STAT_RX_RDY(port) | STAT_OVR_ERR | STAT_FRM_ERR | 36795f78768SMiquel Raynal STAT_BRK_DET)) 36895f78768SMiquel Raynal mvebu_uart_rx_chars(port, st); 36995f78768SMiquel Raynal 37095f78768SMiquel Raynal return IRQ_HANDLED; 37195f78768SMiquel Raynal } 37295f78768SMiquel Raynal 37395f78768SMiquel Raynal static irqreturn_t mvebu_uart_tx_isr(int irq, void *dev_id) 37495f78768SMiquel Raynal { 37595f78768SMiquel Raynal struct uart_port *port = (struct uart_port *)dev_id; 37695f78768SMiquel Raynal unsigned int st = readl(port->membase + UART_STAT); 37795f78768SMiquel Raynal 37895f78768SMiquel Raynal if (st & STAT_TX_RDY(port)) 37995f78768SMiquel Raynal mvebu_uart_tx_chars(port, st); 38095f78768SMiquel Raynal 38195f78768SMiquel Raynal return IRQ_HANDLED; 38295f78768SMiquel Raynal } 38395f78768SMiquel Raynal 38430530791SWilson Ding static int mvebu_uart_startup(struct uart_port *port) 38530530791SWilson Ding { 38695f78768SMiquel Raynal struct mvebu_uart *mvuart = to_mvuart(port); 3875218d769SMiquel Raynal unsigned int ctl; 38830530791SWilson Ding int ret; 38930530791SWilson Ding 39030530791SWilson Ding writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST, 3915218d769SMiquel Raynal port->membase + UART_CTRL(port)); 39230530791SWilson Ding udelay(1); 3932ff23c48SAllen Yan 3942ff23c48SAllen Yan /* Clear the error bits of state register before IRQ request */ 3952ff23c48SAllen Yan ret = readl(port->membase + UART_STAT); 3962ff23c48SAllen Yan ret |= STAT_BRK_ERR; 3972ff23c48SAllen Yan writel(ret, port->membase + UART_STAT); 3982ff23c48SAllen Yan 3995218d769SMiquel Raynal writel(CTRL_BRK_INT, port->membase + UART_CTRL(port)); 4005218d769SMiquel Raynal 4015218d769SMiquel Raynal ctl = readl(port->membase + UART_INTR(port)); 4025218d769SMiquel Raynal ctl |= CTRL_RX_RDY_INT(port); 4035218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port)); 40430530791SWilson Ding 40595f78768SMiquel Raynal if (!mvuart->irq[UART_TX_IRQ]) { 40695f78768SMiquel Raynal /* Old bindings with just one interrupt (UART0 only) */ 40795f78768SMiquel Raynal ret = devm_request_irq(port->dev, mvuart->irq[UART_IRQ_SUM], 40895f78768SMiquel Raynal mvebu_uart_isr, port->irqflags, 40995f78768SMiquel Raynal dev_name(port->dev), port); 41030530791SWilson Ding if (ret) { 41195f78768SMiquel Raynal dev_err(port->dev, "unable to request IRQ %d\n", 41295f78768SMiquel Raynal mvuart->irq[UART_IRQ_SUM]); 41330530791SWilson Ding return ret; 41430530791SWilson Ding } 41595f78768SMiquel Raynal } else { 41695f78768SMiquel Raynal /* New bindings with an IRQ for RX and TX (both UART) */ 41795f78768SMiquel Raynal ret = devm_request_irq(port->dev, mvuart->irq[UART_RX_IRQ], 41895f78768SMiquel Raynal mvebu_uart_rx_isr, port->irqflags, 41995f78768SMiquel Raynal dev_name(port->dev), port); 42095f78768SMiquel Raynal if (ret) { 42195f78768SMiquel Raynal dev_err(port->dev, "unable to request IRQ %d\n", 42295f78768SMiquel Raynal mvuart->irq[UART_RX_IRQ]); 42395f78768SMiquel Raynal return ret; 42495f78768SMiquel Raynal } 42595f78768SMiquel Raynal 42695f78768SMiquel Raynal ret = devm_request_irq(port->dev, mvuart->irq[UART_TX_IRQ], 42795f78768SMiquel Raynal mvebu_uart_tx_isr, port->irqflags, 42895f78768SMiquel Raynal dev_name(port->dev), 42995f78768SMiquel Raynal port); 43095f78768SMiquel Raynal if (ret) { 43195f78768SMiquel Raynal dev_err(port->dev, "unable to request IRQ %d\n", 43295f78768SMiquel Raynal mvuart->irq[UART_TX_IRQ]); 43395f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], 43495f78768SMiquel Raynal port); 43595f78768SMiquel Raynal return ret; 43695f78768SMiquel Raynal } 43795f78768SMiquel Raynal } 43830530791SWilson Ding 43930530791SWilson Ding return 0; 44030530791SWilson Ding } 44130530791SWilson Ding 44230530791SWilson Ding static void mvebu_uart_shutdown(struct uart_port *port) 44330530791SWilson Ding { 44495f78768SMiquel Raynal struct mvebu_uart *mvuart = to_mvuart(port); 44595f78768SMiquel Raynal 4465218d769SMiquel Raynal writel(0, port->membase + UART_INTR(port)); 447c2c1659bSThomas Petazzoni 44895f78768SMiquel Raynal if (!mvuart->irq[UART_TX_IRQ]) { 44995f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_IRQ_SUM], port); 45095f78768SMiquel Raynal } else { 45195f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_RX_IRQ], port); 45295f78768SMiquel Raynal devm_free_irq(port->dev, mvuart->irq[UART_TX_IRQ], port); 45395f78768SMiquel Raynal } 45430530791SWilson Ding } 45530530791SWilson Ding 4564f532c1eSPali Rohár static unsigned int mvebu_uart_baud_rate_set(struct uart_port *port, unsigned int baud) 45768a0db1dSAllen Yan { 4580e4cf69eSMiquel Raynal unsigned int d_divisor, m_divisor; 459b7e2b536SPali Rohár unsigned long flags; 46035d7a58aSMiquel Raynal u32 brdv, osamp; 46168a0db1dSAllen Yan 462ecd6b010SPali Rohár if (!port->uartclk) 4634f532c1eSPali Rohár return 0; 46468a0db1dSAllen Yan 46568a0db1dSAllen Yan /* 466694b7112SPali Rohár * The baudrate is derived from the UART clock thanks to divisors: 467694b7112SPali Rohár * > d1 * d2 ("TBG divisors"): can divide only TBG clock from 1 to 6 468694b7112SPali Rohár * > D ("baud generator"): can divide the clock from 1 to 1023 469694b7112SPali Rohár * > M ("fractional divisor"): allows a better accuracy (from 1 to 63) 4700e4cf69eSMiquel Raynal * 471694b7112SPali Rohár * Exact formulas for calculating baudrate: 472694b7112SPali Rohár * 473694b7112SPali Rohár * with default x16 scheme: 474694b7112SPali Rohár * baudrate = xtal / (d * 16) 475694b7112SPali Rohár * baudrate = tbg / (d1 * d2 * d * 16) 476694b7112SPali Rohár * 477694b7112SPali Rohár * with fractional divisor: 478694b7112SPali Rohár * baudrate = 10 * xtal / (d * (3 * (m1 + m2) + 2 * (m3 + m4))) 479694b7112SPali Rohár * baudrate = 10 * tbg / (d1*d2 * d * (3 * (m1 + m2) + 2 * (m3 + m4))) 480694b7112SPali Rohár * 481694b7112SPali Rohár * Oversampling value: 482694b7112SPali Rohár * osamp = (m1 << 0) | (m2 << 8) | (m3 << 16) | (m4 << 24); 483694b7112SPali Rohár * 484694b7112SPali Rohár * Where m1 controls number of clock cycles per bit for bits 1,2,3; 485694b7112SPali Rohár * m2 for bits 4,5,6; m3 for bits 7,8 and m4 for bits 9,10. 486694b7112SPali Rohár * 487694b7112SPali Rohár * To simplify baudrate setup set all the M prescalers to the same 488694b7112SPali Rohár * value. For baudrates 9600 Bd and higher, it is enough to use the 489694b7112SPali Rohár * default (x16) divisor or fractional divisor with M = 63, so there 490694b7112SPali Rohár * is no need to use real fractional support (where the M prescalers 491694b7112SPali Rohár * are not equal). 492694b7112SPali Rohár * 493694b7112SPali Rohár * When all the M prescalers are zeroed then default (x16) divisor is 494694b7112SPali Rohár * used. Default x16 scheme is more stable than M (fractional divisor), 495694b7112SPali Rohár * so use M only when D divisor is not enough to derive baudrate. 496694b7112SPali Rohár * 497694b7112SPali Rohár * Member port->uartclk is either xtal clock rate or TBG clock rate 498694b7112SPali Rohár * divided by (d1 * d2). So d1 and d2 are already set by the UART clock 499694b7112SPali Rohár * driver (and UART driver itself cannot change them). Moreover they are 500694b7112SPali Rohár * shared between both UARTs. 50168a0db1dSAllen Yan */ 502694b7112SPali Rohár 5030e4cf69eSMiquel Raynal m_divisor = OSAMP_DEFAULT_DIVISOR; 5049078204cSPali Rohár d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); 5050e4cf69eSMiquel Raynal 506694b7112SPali Rohár if (d_divisor > BRDV_BAUD_MAX) { 507694b7112SPali Rohár /* 508694b7112SPali Rohár * Experiments show that small M divisors are unstable. 509694b7112SPali Rohár * Use maximal possible M = 63 and calculate D divisor. 510694b7112SPali Rohár */ 511694b7112SPali Rohár m_divisor = OSAMP_MAX_DIVISOR; 512694b7112SPali Rohár d_divisor = DIV_ROUND_CLOSEST(port->uartclk, baud * m_divisor); 513694b7112SPali Rohár } 514694b7112SPali Rohár 515694b7112SPali Rohár if (d_divisor < 1) 516694b7112SPali Rohár d_divisor = 1; 517694b7112SPali Rohár else if (d_divisor > BRDV_BAUD_MAX) 518694b7112SPali Rohár d_divisor = BRDV_BAUD_MAX; 519694b7112SPali Rohár 520b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 52168a0db1dSAllen Yan brdv = readl(port->membase + UART_BRDV); 52268a0db1dSAllen Yan brdv &= ~BRDV_BAUD_MASK; 5230e4cf69eSMiquel Raynal brdv |= d_divisor; 52468a0db1dSAllen Yan writel(brdv, port->membase + UART_BRDV); 525b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 52668a0db1dSAllen Yan 52735d7a58aSMiquel Raynal osamp = readl(port->membase + UART_OSAMP); 52835d7a58aSMiquel Raynal osamp &= ~OSAMP_DIVISORS_MASK; 529694b7112SPali Rohár if (m_divisor != OSAMP_DEFAULT_DIVISOR) 530694b7112SPali Rohár osamp |= (m_divisor << 0) | (m_divisor << 8) | 531694b7112SPali Rohár (m_divisor << 16) | (m_divisor << 24); 53235d7a58aSMiquel Raynal writel(osamp, port->membase + UART_OSAMP); 53335d7a58aSMiquel Raynal 5344f532c1eSPali Rohár return DIV_ROUND_CLOSEST(port->uartclk, d_divisor * m_divisor); 53568a0db1dSAllen Yan } 53668a0db1dSAllen Yan 53730530791SWilson Ding static void mvebu_uart_set_termios(struct uart_port *port, 53830530791SWilson Ding struct ktermios *termios, 539bec5b814SIlpo Järvinen const struct ktermios *old) 54030530791SWilson Ding { 54130530791SWilson Ding unsigned long flags; 542deeaf963SPali Rohár unsigned int baud, min_baud, max_baud; 54330530791SWilson Ding 54430530791SWilson Ding spin_lock_irqsave(&port->lock, flags); 54530530791SWilson Ding 5465218d769SMiquel Raynal port->read_status_mask = STAT_RX_RDY(port) | STAT_OVR_ERR | 5475218d769SMiquel Raynal STAT_TX_RDY(port) | STAT_TX_FIFO_FUL; 54830530791SWilson Ding 54930530791SWilson Ding if (termios->c_iflag & INPCK) 55030530791SWilson Ding port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR; 55130530791SWilson Ding 55230530791SWilson Ding port->ignore_status_mask = 0; 55330530791SWilson Ding if (termios->c_iflag & IGNPAR) 55430530791SWilson Ding port->ignore_status_mask |= 55530530791SWilson Ding STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR; 55630530791SWilson Ding 55730530791SWilson Ding if ((termios->c_cflag & CREAD) == 0) 5585218d769SMiquel Raynal port->ignore_status_mask |= STAT_RX_RDY(port) | STAT_BRK_ERR; 55930530791SWilson Ding 56068a0db1dSAllen Yan /* 561694b7112SPali Rohár * Maximal divisor is 1023 and maximal fractional divisor is 63. And 562694b7112SPali Rohár * experiments show that baudrates above 1/80 of parent clock rate are 563694b7112SPali Rohár * not stable. So disallow baudrates above 1/80 of the parent clock 564694b7112SPali Rohár * rate. If port->uartclk is not available, then 565694b7112SPali Rohár * mvebu_uart_baud_rate_set() fails, so values min_baud and max_baud 566694b7112SPali Rohár * in this case do not matter. 56768a0db1dSAllen Yan */ 568694b7112SPali Rohár min_baud = DIV_ROUND_UP(port->uartclk, BRDV_BAUD_MAX * 569694b7112SPali Rohár OSAMP_MAX_DIVISOR); 570694b7112SPali Rohár max_baud = port->uartclk / 80; 571deeaf963SPali Rohár 572deeaf963SPali Rohár baud = uart_get_baud_rate(port, termios, old, min_baud, max_baud); 5734f532c1eSPali Rohár baud = mvebu_uart_baud_rate_set(port, baud); 5744f532c1eSPali Rohár 5754f532c1eSPali Rohár /* In case baudrate cannot be changed, report previous old value */ 5764f532c1eSPali Rohár if (baud == 0 && old) 5774f532c1eSPali Rohár baud = tty_termios_baud_rate(old); 57868a0db1dSAllen Yan 57968a0db1dSAllen Yan /* Only the following flag changes are supported */ 58068a0db1dSAllen Yan if (old) { 58168a0db1dSAllen Yan termios->c_iflag &= INPCK | IGNPAR; 58268a0db1dSAllen Yan termios->c_iflag |= old->c_iflag & ~(INPCK | IGNPAR); 58368a0db1dSAllen Yan termios->c_cflag &= CREAD | CBAUD; 58468a0db1dSAllen Yan termios->c_cflag |= old->c_cflag & ~(CREAD | CBAUD); 585e0bf2d49SJan Kiszka termios->c_cflag |= CS8; 58668a0db1dSAllen Yan } 58730530791SWilson Ding 5884f532c1eSPali Rohár if (baud != 0) { 5894f532c1eSPali Rohár tty_termios_encode_baud_rate(termios, baud, baud); 5904f532c1eSPali Rohár uart_update_timeout(port, termios->c_cflag, baud); 5914f532c1eSPali Rohár } 5924f532c1eSPali Rohár 59330530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags); 59430530791SWilson Ding } 59530530791SWilson Ding 59630530791SWilson Ding static const char *mvebu_uart_type(struct uart_port *port) 59730530791SWilson Ding { 59830530791SWilson Ding return MVEBU_UART_TYPE; 59930530791SWilson Ding } 60030530791SWilson Ding 60130530791SWilson Ding static void mvebu_uart_release_port(struct uart_port *port) 60230530791SWilson Ding { 60330530791SWilson Ding /* Nothing to do here */ 60430530791SWilson Ding } 60530530791SWilson Ding 60630530791SWilson Ding static int mvebu_uart_request_port(struct uart_port *port) 60730530791SWilson Ding { 60830530791SWilson Ding return 0; 60930530791SWilson Ding } 61030530791SWilson Ding 61130530791SWilson Ding #ifdef CONFIG_CONSOLE_POLL 61230530791SWilson Ding static int mvebu_uart_get_poll_char(struct uart_port *port) 61330530791SWilson Ding { 61430530791SWilson Ding unsigned int st = readl(port->membase + UART_STAT); 61530530791SWilson Ding 6165218d769SMiquel Raynal if (!(st & STAT_RX_RDY(port))) 61730530791SWilson Ding return NO_POLL_CHAR; 61830530791SWilson Ding 6195218d769SMiquel Raynal return readl(port->membase + UART_RBR(port)); 62030530791SWilson Ding } 62130530791SWilson Ding 62230530791SWilson Ding static void mvebu_uart_put_poll_char(struct uart_port *port, unsigned char c) 62330530791SWilson Ding { 62430530791SWilson Ding unsigned int st; 62530530791SWilson Ding 62630530791SWilson Ding for (;;) { 62730530791SWilson Ding st = readl(port->membase + UART_STAT); 62830530791SWilson Ding 62930530791SWilson Ding if (!(st & STAT_TX_FIFO_FUL)) 63030530791SWilson Ding break; 63130530791SWilson Ding 63230530791SWilson Ding udelay(1); 63330530791SWilson Ding } 63430530791SWilson Ding 6355218d769SMiquel Raynal writel(c, port->membase + UART_TSH(port)); 63630530791SWilson Ding } 63730530791SWilson Ding #endif 63830530791SWilson Ding 63930530791SWilson Ding static const struct uart_ops mvebu_uart_ops = { 64030530791SWilson Ding .tx_empty = mvebu_uart_tx_empty, 64130530791SWilson Ding .set_mctrl = mvebu_uart_set_mctrl, 64230530791SWilson Ding .get_mctrl = mvebu_uart_get_mctrl, 64330530791SWilson Ding .stop_tx = mvebu_uart_stop_tx, 64430530791SWilson Ding .start_tx = mvebu_uart_start_tx, 64530530791SWilson Ding .stop_rx = mvebu_uart_stop_rx, 64630530791SWilson Ding .break_ctl = mvebu_uart_break_ctl, 64730530791SWilson Ding .startup = mvebu_uart_startup, 64830530791SWilson Ding .shutdown = mvebu_uart_shutdown, 64930530791SWilson Ding .set_termios = mvebu_uart_set_termios, 65030530791SWilson Ding .type = mvebu_uart_type, 65130530791SWilson Ding .release_port = mvebu_uart_release_port, 65230530791SWilson Ding .request_port = mvebu_uart_request_port, 65330530791SWilson Ding #ifdef CONFIG_CONSOLE_POLL 65430530791SWilson Ding .poll_get_char = mvebu_uart_get_poll_char, 65530530791SWilson Ding .poll_put_char = mvebu_uart_put_poll_char, 65630530791SWilson Ding #endif 65730530791SWilson Ding }; 65830530791SWilson Ding 65930530791SWilson Ding /* Console Driver Operations */ 66030530791SWilson Ding 66130530791SWilson Ding #ifdef CONFIG_SERIAL_MVEBU_CONSOLE 66230530791SWilson Ding /* Early Console */ 6633f8bab17SJiri Slaby static void mvebu_uart_putc(struct uart_port *port, unsigned char c) 66430530791SWilson Ding { 66530530791SWilson Ding unsigned int st; 66630530791SWilson Ding 66730530791SWilson Ding for (;;) { 66830530791SWilson Ding st = readl(port->membase + UART_STAT); 66930530791SWilson Ding if (!(st & STAT_TX_FIFO_FUL)) 67030530791SWilson Ding break; 67130530791SWilson Ding } 67230530791SWilson Ding 6735218d769SMiquel Raynal /* At early stage, DT is not parsed yet, only use UART0 */ 6745218d769SMiquel Raynal writel(c, port->membase + UART_STD_TSH); 67530530791SWilson Ding 67630530791SWilson Ding for (;;) { 67730530791SWilson Ding st = readl(port->membase + UART_STAT); 67830530791SWilson Ding if (st & STAT_TX_FIFO_EMP) 67930530791SWilson Ding break; 68030530791SWilson Ding } 68130530791SWilson Ding } 68230530791SWilson Ding 68330530791SWilson Ding static void mvebu_uart_putc_early_write(struct console *con, 68430530791SWilson Ding const char *s, 6855607fa6cSJinchao Wang unsigned int n) 68630530791SWilson Ding { 68730530791SWilson Ding struct earlycon_device *dev = con->data; 68830530791SWilson Ding 68930530791SWilson Ding uart_console_write(&dev->port, s, n, mvebu_uart_putc); 69030530791SWilson Ding } 69130530791SWilson Ding 69230530791SWilson Ding static int __init 69330530791SWilson Ding mvebu_uart_early_console_setup(struct earlycon_device *device, 69430530791SWilson Ding const char *opt) 69530530791SWilson Ding { 69630530791SWilson Ding if (!device->port.membase) 69730530791SWilson Ding return -ENODEV; 69830530791SWilson Ding 69930530791SWilson Ding device->con->write = mvebu_uart_putc_early_write; 70030530791SWilson Ding 70130530791SWilson Ding return 0; 70230530791SWilson Ding } 70330530791SWilson Ding 70430530791SWilson Ding EARLYCON_DECLARE(ar3700_uart, mvebu_uart_early_console_setup); 70530530791SWilson Ding OF_EARLYCON_DECLARE(ar3700_uart, "marvell,armada-3700-uart", 70630530791SWilson Ding mvebu_uart_early_console_setup); 70730530791SWilson Ding 70830530791SWilson Ding static void wait_for_xmitr(struct uart_port *port) 70930530791SWilson Ding { 71030530791SWilson Ding u32 val; 71130530791SWilson Ding 71230530791SWilson Ding readl_poll_timeout_atomic(port->membase + UART_STAT, val, 713c685af11SGabriel Matni (val & STAT_TX_RDY(port)), 1, 10000); 71430530791SWilson Ding } 71530530791SWilson Ding 71654ca955bSPali Rohár static void wait_for_xmite(struct uart_port *port) 71754ca955bSPali Rohár { 71854ca955bSPali Rohár u32 val; 71954ca955bSPali Rohár 72054ca955bSPali Rohár readl_poll_timeout_atomic(port->membase + UART_STAT, val, 72154ca955bSPali Rohár (val & STAT_TX_EMP), 1, 10000); 72254ca955bSPali Rohár } 72354ca955bSPali Rohár 7243f8bab17SJiri Slaby static void mvebu_uart_console_putchar(struct uart_port *port, unsigned char ch) 72530530791SWilson Ding { 72630530791SWilson Ding wait_for_xmitr(port); 7275218d769SMiquel Raynal writel(ch, port->membase + UART_TSH(port)); 72830530791SWilson Ding } 72930530791SWilson Ding 73030530791SWilson Ding static void mvebu_uart_console_write(struct console *co, const char *s, 73130530791SWilson Ding unsigned int count) 73230530791SWilson Ding { 73330530791SWilson Ding struct uart_port *port = &mvebu_uart_ports[co->index]; 73430530791SWilson Ding unsigned long flags; 7355218d769SMiquel Raynal unsigned int ier, intr, ctl; 73630530791SWilson Ding int locked = 1; 73730530791SWilson Ding 73830530791SWilson Ding if (oops_in_progress) 73930530791SWilson Ding locked = spin_trylock_irqsave(&port->lock, flags); 74030530791SWilson Ding else 74130530791SWilson Ding spin_lock_irqsave(&port->lock, flags); 74230530791SWilson Ding 7435218d769SMiquel Raynal ier = readl(port->membase + UART_CTRL(port)) & CTRL_BRK_INT; 7445218d769SMiquel Raynal intr = readl(port->membase + UART_INTR(port)) & 7455218d769SMiquel Raynal (CTRL_RX_RDY_INT(port) | CTRL_TX_RDY_INT(port)); 7465218d769SMiquel Raynal writel(0, port->membase + UART_CTRL(port)); 7475218d769SMiquel Raynal writel(0, port->membase + UART_INTR(port)); 74830530791SWilson Ding 74930530791SWilson Ding uart_console_write(port, s, count, mvebu_uart_console_putchar); 75030530791SWilson Ding 75154ca955bSPali Rohár wait_for_xmite(port); 75230530791SWilson Ding 75330530791SWilson Ding if (ier) 7545218d769SMiquel Raynal writel(ier, port->membase + UART_CTRL(port)); 7555218d769SMiquel Raynal 7565218d769SMiquel Raynal if (intr) { 7575218d769SMiquel Raynal ctl = intr | readl(port->membase + UART_INTR(port)); 7585218d769SMiquel Raynal writel(ctl, port->membase + UART_INTR(port)); 7595218d769SMiquel Raynal } 76030530791SWilson Ding 76130530791SWilson Ding if (locked) 76230530791SWilson Ding spin_unlock_irqrestore(&port->lock, flags); 76330530791SWilson Ding } 76430530791SWilson Ding 76530530791SWilson Ding static int mvebu_uart_console_setup(struct console *co, char *options) 76630530791SWilson Ding { 76730530791SWilson Ding struct uart_port *port; 76830530791SWilson Ding int baud = 9600; 76930530791SWilson Ding int bits = 8; 77030530791SWilson Ding int parity = 'n'; 77130530791SWilson Ding int flow = 'n'; 77230530791SWilson Ding 77330530791SWilson Ding if (co->index < 0 || co->index >= MVEBU_NR_UARTS) 77430530791SWilson Ding return -EINVAL; 77530530791SWilson Ding 77630530791SWilson Ding port = &mvebu_uart_ports[co->index]; 77730530791SWilson Ding 77830530791SWilson Ding if (!port->mapbase || !port->membase) { 77930530791SWilson Ding pr_debug("console on ttyMV%i not present\n", co->index); 78030530791SWilson Ding return -ENODEV; 78130530791SWilson Ding } 78230530791SWilson Ding 78330530791SWilson Ding if (options) 78430530791SWilson Ding uart_parse_options(options, &baud, &parity, &bits, &flow); 78530530791SWilson Ding 78630530791SWilson Ding return uart_set_options(port, co, baud, parity, bits, flow); 78730530791SWilson Ding } 78830530791SWilson Ding 78930530791SWilson Ding static struct uart_driver mvebu_uart_driver; 79030530791SWilson Ding 79130530791SWilson Ding static struct console mvebu_uart_console = { 79230530791SWilson Ding .name = "ttyMV", 79330530791SWilson Ding .write = mvebu_uart_console_write, 79430530791SWilson Ding .device = uart_console_device, 79530530791SWilson Ding .setup = mvebu_uart_console_setup, 79630530791SWilson Ding .flags = CON_PRINTBUFFER, 79730530791SWilson Ding .index = -1, 79830530791SWilson Ding .data = &mvebu_uart_driver, 79930530791SWilson Ding }; 80030530791SWilson Ding 80130530791SWilson Ding static int __init mvebu_uart_console_init(void) 80230530791SWilson Ding { 80330530791SWilson Ding register_console(&mvebu_uart_console); 80430530791SWilson Ding return 0; 80530530791SWilson Ding } 80630530791SWilson Ding 80730530791SWilson Ding console_initcall(mvebu_uart_console_init); 80830530791SWilson Ding 80930530791SWilson Ding 81030530791SWilson Ding #endif /* CONFIG_SERIAL_MVEBU_CONSOLE */ 81130530791SWilson Ding 81230530791SWilson Ding static struct uart_driver mvebu_uart_driver = { 81330530791SWilson Ding .owner = THIS_MODULE, 81402c33330SYehuda Yitschak .driver_name = DRIVER_NAME, 81530530791SWilson Ding .dev_name = "ttyMV", 81630530791SWilson Ding .nr = MVEBU_NR_UARTS, 81730530791SWilson Ding #ifdef CONFIG_SERIAL_MVEBU_CONSOLE 81830530791SWilson Ding .cons = &mvebu_uart_console, 81930530791SWilson Ding #endif 82030530791SWilson Ding }; 82130530791SWilson Ding 822394e8351SMiquel Raynal #if defined(CONFIG_PM) 823394e8351SMiquel Raynal static int mvebu_uart_suspend(struct device *dev) 824394e8351SMiquel Raynal { 825394e8351SMiquel Raynal struct mvebu_uart *mvuart = dev_get_drvdata(dev); 826394e8351SMiquel Raynal struct uart_port *port = mvuart->port; 827b7e2b536SPali Rohár unsigned long flags; 828394e8351SMiquel Raynal 829394e8351SMiquel Raynal uart_suspend_port(&mvebu_uart_driver, port); 830394e8351SMiquel Raynal 831394e8351SMiquel Raynal mvuart->pm_regs.rbr = readl(port->membase + UART_RBR(port)); 832394e8351SMiquel Raynal mvuart->pm_regs.tsh = readl(port->membase + UART_TSH(port)); 833394e8351SMiquel Raynal mvuart->pm_regs.ctrl = readl(port->membase + UART_CTRL(port)); 834394e8351SMiquel Raynal mvuart->pm_regs.intr = readl(port->membase + UART_INTR(port)); 835394e8351SMiquel Raynal mvuart->pm_regs.stat = readl(port->membase + UART_STAT); 836b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 837394e8351SMiquel Raynal mvuart->pm_regs.brdv = readl(port->membase + UART_BRDV); 838b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 839394e8351SMiquel Raynal mvuart->pm_regs.osamp = readl(port->membase + UART_OSAMP); 840394e8351SMiquel Raynal 841394e8351SMiquel Raynal device_set_wakeup_enable(dev, true); 842394e8351SMiquel Raynal 843394e8351SMiquel Raynal return 0; 844394e8351SMiquel Raynal } 845394e8351SMiquel Raynal 846394e8351SMiquel Raynal static int mvebu_uart_resume(struct device *dev) 847394e8351SMiquel Raynal { 848394e8351SMiquel Raynal struct mvebu_uart *mvuart = dev_get_drvdata(dev); 849394e8351SMiquel Raynal struct uart_port *port = mvuart->port; 850b7e2b536SPali Rohár unsigned long flags; 851394e8351SMiquel Raynal 852394e8351SMiquel Raynal writel(mvuart->pm_regs.rbr, port->membase + UART_RBR(port)); 853394e8351SMiquel Raynal writel(mvuart->pm_regs.tsh, port->membase + UART_TSH(port)); 854394e8351SMiquel Raynal writel(mvuart->pm_regs.ctrl, port->membase + UART_CTRL(port)); 855394e8351SMiquel Raynal writel(mvuart->pm_regs.intr, port->membase + UART_INTR(port)); 856394e8351SMiquel Raynal writel(mvuart->pm_regs.stat, port->membase + UART_STAT); 857b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 858394e8351SMiquel Raynal writel(mvuart->pm_regs.brdv, port->membase + UART_BRDV); 859b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 860394e8351SMiquel Raynal writel(mvuart->pm_regs.osamp, port->membase + UART_OSAMP); 861394e8351SMiquel Raynal 862394e8351SMiquel Raynal uart_resume_port(&mvebu_uart_driver, port); 863394e8351SMiquel Raynal 864394e8351SMiquel Raynal return 0; 865394e8351SMiquel Raynal } 866394e8351SMiquel Raynal 867394e8351SMiquel Raynal static const struct dev_pm_ops mvebu_uart_pm_ops = { 868394e8351SMiquel Raynal .suspend = mvebu_uart_suspend, 869394e8351SMiquel Raynal .resume = mvebu_uart_resume, 870394e8351SMiquel Raynal }; 871394e8351SMiquel Raynal #endif /* CONFIG_PM */ 872394e8351SMiquel Raynal 8735218d769SMiquel Raynal static const struct of_device_id mvebu_uart_of_match[]; 8745218d769SMiquel Raynal 87594228f95SAllen Yan /* Counter to keep track of each UART port id when not using CONFIG_OF */ 87694228f95SAllen Yan static int uart_num_counter; 87794228f95SAllen Yan 87830530791SWilson Ding static int mvebu_uart_probe(struct platform_device *pdev) 87930530791SWilson Ding { 88030530791SWilson Ding struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 0); 8815218d769SMiquel Raynal const struct of_device_id *match = of_match_device(mvebu_uart_of_match, 8825218d769SMiquel Raynal &pdev->dev); 88330530791SWilson Ding struct uart_port *port; 8845218d769SMiquel Raynal struct mvebu_uart *mvuart; 88558e49346SQinglang Miao int id, irq; 88630530791SWilson Ding 88795f78768SMiquel Raynal if (!reg) { 88895f78768SMiquel Raynal dev_err(&pdev->dev, "no registers defined\n"); 88930530791SWilson Ding return -EINVAL; 89030530791SWilson Ding } 89130530791SWilson Ding 89294228f95SAllen Yan /* Assume that all UART ports have a DT alias or none has */ 89394228f95SAllen Yan id = of_alias_get_id(pdev->dev.of_node, "serial"); 89494228f95SAllen Yan if (!pdev->dev.of_node || id < 0) 89594228f95SAllen Yan pdev->id = uart_num_counter++; 89694228f95SAllen Yan else 89794228f95SAllen Yan pdev->id = id; 89894228f95SAllen Yan 89994228f95SAllen Yan if (pdev->id >= MVEBU_NR_UARTS) { 90094228f95SAllen Yan dev_err(&pdev->dev, "cannot have more than %d UART ports\n", 90194228f95SAllen Yan MVEBU_NR_UARTS); 90294228f95SAllen Yan return -EINVAL; 90394228f95SAllen Yan } 90494228f95SAllen Yan 90594228f95SAllen Yan port = &mvebu_uart_ports[pdev->id]; 90630530791SWilson Ding 90730530791SWilson Ding spin_lock_init(&port->lock); 90830530791SWilson Ding 90930530791SWilson Ding port->dev = &pdev->dev; 91030530791SWilson Ding port->type = PORT_MVEBU; 91130530791SWilson Ding port->ops = &mvebu_uart_ops; 91230530791SWilson Ding port->regshift = 0; 91330530791SWilson Ding 91430530791SWilson Ding port->fifosize = 32; 91530530791SWilson Ding port->iotype = UPIO_MEM32; 91630530791SWilson Ding port->flags = UPF_FIXED_PORT; 91794228f95SAllen Yan port->line = pdev->id; 91830530791SWilson Ding 91995f78768SMiquel Raynal /* 92095f78768SMiquel Raynal * IRQ number is not stored in this structure because we may have two of 92195f78768SMiquel Raynal * them per port (RX and TX). Instead, use the driver UART structure 92295f78768SMiquel Raynal * array so called ->irq[]. 92395f78768SMiquel Raynal */ 92495f78768SMiquel Raynal port->irq = 0; 92530530791SWilson Ding port->irqflags = 0; 92630530791SWilson Ding port->mapbase = reg->start; 92730530791SWilson Ding 92830530791SWilson Ding port->membase = devm_ioremap_resource(&pdev->dev, reg); 92930530791SWilson Ding if (IS_ERR(port->membase)) 9304a3e2084Stangbin return PTR_ERR(port->membase); 93130530791SWilson Ding 9325218d769SMiquel Raynal mvuart = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_uart), 93330530791SWilson Ding GFP_KERNEL); 9345218d769SMiquel Raynal if (!mvuart) 93530530791SWilson Ding return -ENOMEM; 93630530791SWilson Ding 93768a0db1dSAllen Yan /* Get controller data depending on the compatible string */ 9385218d769SMiquel Raynal mvuart->data = (struct mvebu_uart_driver_data *)match->data; 9395218d769SMiquel Raynal mvuart->port = port; 94030530791SWilson Ding 9415218d769SMiquel Raynal port->private_data = mvuart; 9425218d769SMiquel Raynal platform_set_drvdata(pdev, mvuart); 94330530791SWilson Ding 94468a0db1dSAllen Yan /* Get fixed clock frequency */ 94568a0db1dSAllen Yan mvuart->clk = devm_clk_get(&pdev->dev, NULL); 94668a0db1dSAllen Yan if (IS_ERR(mvuart->clk)) { 94768a0db1dSAllen Yan if (PTR_ERR(mvuart->clk) == -EPROBE_DEFER) 94868a0db1dSAllen Yan return PTR_ERR(mvuart->clk); 94968a0db1dSAllen Yan 95068a0db1dSAllen Yan if (IS_EXTENDED(port)) { 95168a0db1dSAllen Yan dev_err(&pdev->dev, "unable to get UART clock\n"); 95268a0db1dSAllen Yan return PTR_ERR(mvuart->clk); 95368a0db1dSAllen Yan } 95468a0db1dSAllen Yan } else { 95568a0db1dSAllen Yan if (!clk_prepare_enable(mvuart->clk)) 95668a0db1dSAllen Yan port->uartclk = clk_get_rate(mvuart->clk); 95768a0db1dSAllen Yan } 95868a0db1dSAllen Yan 95995f78768SMiquel Raynal /* Manage interrupts */ 96095f78768SMiquel Raynal if (platform_irq_count(pdev) == 1) { 96195f78768SMiquel Raynal /* Old bindings: no name on the single unamed UART0 IRQ */ 96295f78768SMiquel Raynal irq = platform_get_irq(pdev, 0); 9631df21786SStephen Boyd if (irq < 0) 96495f78768SMiquel Raynal return irq; 96595f78768SMiquel Raynal 96695f78768SMiquel Raynal mvuart->irq[UART_IRQ_SUM] = irq; 96795f78768SMiquel Raynal } else { 96895f78768SMiquel Raynal /* 96995f78768SMiquel Raynal * New bindings: named interrupts (RX, TX) for both UARTS, 97095f78768SMiquel Raynal * only make use of uart-rx and uart-tx interrupts, do not use 97195f78768SMiquel Raynal * uart-sum of UART0 port. 97295f78768SMiquel Raynal */ 97395f78768SMiquel Raynal irq = platform_get_irq_byname(pdev, "uart-rx"); 9741df21786SStephen Boyd if (irq < 0) 97595f78768SMiquel Raynal return irq; 97695f78768SMiquel Raynal 97795f78768SMiquel Raynal mvuart->irq[UART_RX_IRQ] = irq; 97895f78768SMiquel Raynal 97995f78768SMiquel Raynal irq = platform_get_irq_byname(pdev, "uart-tx"); 9801df21786SStephen Boyd if (irq < 0) 98195f78768SMiquel Raynal return irq; 98295f78768SMiquel Raynal 98395f78768SMiquel Raynal mvuart->irq[UART_TX_IRQ] = irq; 98495f78768SMiquel Raynal } 98595f78768SMiquel Raynal 9869c3d3ee1SAllen Yan /* UART Soft Reset*/ 9879c3d3ee1SAllen Yan writel(CTRL_SOFT_RST, port->membase + UART_CTRL(port)); 9889c3d3ee1SAllen Yan udelay(1); 9899c3d3ee1SAllen Yan writel(0, port->membase + UART_CTRL(port)); 9909c3d3ee1SAllen Yan 991b6353702SQinglang Miao return uart_add_one_port(&mvebu_uart_driver, port); 99230530791SWilson Ding } 99330530791SWilson Ding 9945218d769SMiquel Raynal static struct mvebu_uart_driver_data uart_std_driver_data = { 9955218d769SMiquel Raynal .is_ext = false, 9965218d769SMiquel Raynal .regs.rbr = UART_STD_RBR, 9975218d769SMiquel Raynal .regs.tsh = UART_STD_TSH, 9985218d769SMiquel Raynal .regs.ctrl = UART_STD_CTRL1, 9995218d769SMiquel Raynal .regs.intr = UART_STD_CTRL2, 10005218d769SMiquel Raynal .flags.ctrl_tx_rdy_int = CTRL_STD_TX_RDY_INT, 10015218d769SMiquel Raynal .flags.ctrl_rx_rdy_int = CTRL_STD_RX_RDY_INT, 10025218d769SMiquel Raynal .flags.stat_tx_rdy = STAT_STD_TX_RDY, 10035218d769SMiquel Raynal .flags.stat_rx_rdy = STAT_STD_RX_RDY, 10045218d769SMiquel Raynal }; 10055218d769SMiquel Raynal 100653501e02SMiquel Raynal static struct mvebu_uart_driver_data uart_ext_driver_data = { 100753501e02SMiquel Raynal .is_ext = true, 100853501e02SMiquel Raynal .regs.rbr = UART_EXT_RBR, 100953501e02SMiquel Raynal .regs.tsh = UART_EXT_TSH, 101053501e02SMiquel Raynal .regs.ctrl = UART_EXT_CTRL1, 101153501e02SMiquel Raynal .regs.intr = UART_EXT_CTRL2, 101253501e02SMiquel Raynal .flags.ctrl_tx_rdy_int = CTRL_EXT_TX_RDY_INT, 101353501e02SMiquel Raynal .flags.ctrl_rx_rdy_int = CTRL_EXT_RX_RDY_INT, 101453501e02SMiquel Raynal .flags.stat_tx_rdy = STAT_EXT_TX_RDY, 101553501e02SMiquel Raynal .flags.stat_rx_rdy = STAT_EXT_RX_RDY, 101653501e02SMiquel Raynal }; 101753501e02SMiquel Raynal 101830530791SWilson Ding /* Match table for of_platform binding */ 101930530791SWilson Ding static const struct of_device_id mvebu_uart_of_match[] = { 10205218d769SMiquel Raynal { 10215218d769SMiquel Raynal .compatible = "marvell,armada-3700-uart", 10225218d769SMiquel Raynal .data = (void *)&uart_std_driver_data, 10235218d769SMiquel Raynal }, 102453501e02SMiquel Raynal { 102553501e02SMiquel Raynal .compatible = "marvell,armada-3700-uart-ext", 102653501e02SMiquel Raynal .data = (void *)&uart_ext_driver_data, 102753501e02SMiquel Raynal }, 102830530791SWilson Ding {} 102930530791SWilson Ding }; 103030530791SWilson Ding 103130530791SWilson Ding static struct platform_driver mvebu_uart_platform_driver = { 103230530791SWilson Ding .probe = mvebu_uart_probe, 103330530791SWilson Ding .driver = { 103430530791SWilson Ding .name = "mvebu-uart", 103530530791SWilson Ding .of_match_table = of_match_ptr(mvebu_uart_of_match), 103689ebc274SPaul Gortmaker .suppress_bind_attrs = true, 1037394e8351SMiquel Raynal #if defined(CONFIG_PM) 1038394e8351SMiquel Raynal .pm = &mvebu_uart_pm_ops, 1039394e8351SMiquel Raynal #endif /* CONFIG_PM */ 104030530791SWilson Ding }, 104130530791SWilson Ding }; 104230530791SWilson Ding 1043b7e2b536SPali Rohár /* This code is based on clk-fixed-factor.c driver and modified. */ 1044b7e2b536SPali Rohár 1045b7e2b536SPali Rohár struct mvebu_uart_clock { 1046b7e2b536SPali Rohár struct clk_hw clk_hw; 1047b7e2b536SPali Rohár int clock_idx; 1048b7e2b536SPali Rohár u32 pm_context_reg1; 1049b7e2b536SPali Rohár u32 pm_context_reg2; 1050b7e2b536SPali Rohár }; 1051b7e2b536SPali Rohár 1052b7e2b536SPali Rohár struct mvebu_uart_clock_base { 1053b7e2b536SPali Rohár struct mvebu_uart_clock clocks[2]; 1054b7e2b536SPali Rohár unsigned int parent_rates[5]; 1055b7e2b536SPali Rohár int parent_idx; 1056b7e2b536SPali Rohár unsigned int div; 1057b7e2b536SPali Rohár void __iomem *reg1; 1058b7e2b536SPali Rohár void __iomem *reg2; 1059b7e2b536SPali Rohár bool configured; 1060b7e2b536SPali Rohár }; 1061b7e2b536SPali Rohár 1062b7e2b536SPali Rohár #define PARENT_CLOCK_XTAL 4 1063b7e2b536SPali Rohár 1064b7e2b536SPali Rohár #define to_uart_clock(hw) container_of(hw, struct mvebu_uart_clock, clk_hw) 1065b7e2b536SPali Rohár #define to_uart_clock_base(uart_clock) container_of(uart_clock, \ 1066b7e2b536SPali Rohár struct mvebu_uart_clock_base, clocks[uart_clock->clock_idx]) 1067b7e2b536SPali Rohár 1068b7e2b536SPali Rohár static int mvebu_uart_clock_prepare(struct clk_hw *hw) 1069b7e2b536SPali Rohár { 1070b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1071b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1072b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1073b7e2b536SPali Rohár unsigned int prev_clock_idx, prev_clock_rate, prev_d1d2; 1074b7e2b536SPali Rohár unsigned int parent_clock_idx, parent_clock_rate; 1075b7e2b536SPali Rohár unsigned long flags; 1076b7e2b536SPali Rohár unsigned int d1, d2; 1077b7e2b536SPali Rohár u64 divisor; 1078b7e2b536SPali Rohár u32 val; 1079b7e2b536SPali Rohár 1080b7e2b536SPali Rohár /* 1081b7e2b536SPali Rohár * This function just reconfigures UART Clock Control register (located 1082b7e2b536SPali Rohár * in UART1 address space which controls both UART1 and UART2) to 1083b7e2b536SPali Rohár * selected UART base clock and recalculates current UART1/UART2 1084b7e2b536SPali Rohár * divisors in their address spaces, so that final baudrate will not be 1085b7e2b536SPali Rohár * changed by switching UART parent clock. This is required for 1086b7e2b536SPali Rohár * otherwise kernel's boot log stops working - we need to ensure that 1087b7e2b536SPali Rohár * UART baudrate does not change during this setup. It is a one time 1088b7e2b536SPali Rohár * operation, it will execute only once and set `configured` to true, 1089b7e2b536SPali Rohár * and be skipped on subsequent calls. Because this UART Clock Control 1090b7e2b536SPali Rohár * register (UART_BRDV) is shared between UART1 baudrate function, 1091b7e2b536SPali Rohár * UART1 clock selector and UART2 clock selector, every access to 1092b7e2b536SPali Rohár * UART_BRDV (reg1) needs to be protected by a lock. 1093b7e2b536SPali Rohár */ 1094b7e2b536SPali Rohár 1095b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 1096b7e2b536SPali Rohár 1097b7e2b536SPali Rohár if (uart_clock_base->configured) { 1098b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1099b7e2b536SPali Rohár return 0; 1100b7e2b536SPali Rohár } 1101b7e2b536SPali Rohár 1102b7e2b536SPali Rohár parent_clock_idx = uart_clock_base->parent_idx; 1103b7e2b536SPali Rohár parent_clock_rate = uart_clock_base->parent_rates[parent_clock_idx]; 1104b7e2b536SPali Rohár 1105b7e2b536SPali Rohár val = readl(uart_clock_base->reg1); 1106b7e2b536SPali Rohár 1107b7e2b536SPali Rohár if (uart_clock_base->div > CLK_TBG_DIV1_MAX) { 1108b7e2b536SPali Rohár d1 = CLK_TBG_DIV1_MAX; 1109b7e2b536SPali Rohár d2 = uart_clock_base->div / CLK_TBG_DIV1_MAX; 1110b7e2b536SPali Rohár } else { 1111b7e2b536SPali Rohár d1 = uart_clock_base->div; 1112b7e2b536SPali Rohár d2 = 1; 1113b7e2b536SPali Rohár } 1114b7e2b536SPali Rohár 1115b7e2b536SPali Rohár if (val & CLK_NO_XTAL) { 1116b7e2b536SPali Rohár prev_clock_idx = (val >> CLK_TBG_SEL_SHIFT) & CLK_TBG_SEL_MASK; 1117b7e2b536SPali Rohár prev_d1d2 = ((val >> CLK_TBG_DIV1_SHIFT) & CLK_TBG_DIV1_MASK) * 1118b7e2b536SPali Rohár ((val >> CLK_TBG_DIV2_SHIFT) & CLK_TBG_DIV2_MASK); 1119b7e2b536SPali Rohár } else { 1120b7e2b536SPali Rohár prev_clock_idx = PARENT_CLOCK_XTAL; 1121b7e2b536SPali Rohár prev_d1d2 = 1; 1122b7e2b536SPali Rohár } 1123b7e2b536SPali Rohár 1124b7e2b536SPali Rohár /* Note that uart_clock_base->parent_rates[i] may not be available */ 1125b7e2b536SPali Rohár prev_clock_rate = uart_clock_base->parent_rates[prev_clock_idx]; 1126b7e2b536SPali Rohár 1127b7e2b536SPali Rohár /* Recalculate UART1 divisor so UART1 baudrate does not change */ 1128b7e2b536SPali Rohár if (prev_clock_rate) { 1129b7e2b536SPali Rohár divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) * 1130b7e2b536SPali Rohár parent_clock_rate * prev_d1d2, 1131b7e2b536SPali Rohár prev_clock_rate * d1 * d2); 1132b7e2b536SPali Rohár if (divisor < 1) 1133b7e2b536SPali Rohár divisor = 1; 1134b7e2b536SPali Rohár else if (divisor > BRDV_BAUD_MAX) 1135b7e2b536SPali Rohár divisor = BRDV_BAUD_MAX; 1136b7e2b536SPali Rohár val = (val & ~BRDV_BAUD_MASK) | divisor; 1137b7e2b536SPali Rohár } 1138b7e2b536SPali Rohár 1139b7e2b536SPali Rohár if (parent_clock_idx != PARENT_CLOCK_XTAL) { 1140b7e2b536SPali Rohár /* Do not use XTAL, select TBG clock and TBG d1 * d2 divisors */ 1141b7e2b536SPali Rohár val |= CLK_NO_XTAL; 1142b7e2b536SPali Rohár val &= ~(CLK_TBG_DIV1_MASK << CLK_TBG_DIV1_SHIFT); 1143b7e2b536SPali Rohár val |= d1 << CLK_TBG_DIV1_SHIFT; 1144b7e2b536SPali Rohár val &= ~(CLK_TBG_DIV2_MASK << CLK_TBG_DIV2_SHIFT); 1145b7e2b536SPali Rohár val |= d2 << CLK_TBG_DIV2_SHIFT; 1146b7e2b536SPali Rohár val &= ~(CLK_TBG_SEL_MASK << CLK_TBG_SEL_SHIFT); 1147b7e2b536SPali Rohár val |= parent_clock_idx << CLK_TBG_SEL_SHIFT; 1148b7e2b536SPali Rohár } else { 1149b7e2b536SPali Rohár /* Use XTAL, TBG bits are then ignored */ 1150b7e2b536SPali Rohár val &= ~CLK_NO_XTAL; 1151b7e2b536SPali Rohár } 1152b7e2b536SPali Rohár 1153b7e2b536SPali Rohár writel(val, uart_clock_base->reg1); 1154b7e2b536SPali Rohár 1155b7e2b536SPali Rohár /* Recalculate UART2 divisor so UART2 baudrate does not change */ 1156b7e2b536SPali Rohár if (prev_clock_rate) { 1157b7e2b536SPali Rohár val = readl(uart_clock_base->reg2); 1158b7e2b536SPali Rohár divisor = DIV_U64_ROUND_CLOSEST((u64)(val & BRDV_BAUD_MASK) * 1159b7e2b536SPali Rohár parent_clock_rate * prev_d1d2, 1160b7e2b536SPali Rohár prev_clock_rate * d1 * d2); 1161b7e2b536SPali Rohár if (divisor < 1) 1162b7e2b536SPali Rohár divisor = 1; 1163b7e2b536SPali Rohár else if (divisor > BRDV_BAUD_MAX) 1164b7e2b536SPali Rohár divisor = BRDV_BAUD_MAX; 1165b7e2b536SPali Rohár val = (val & ~BRDV_BAUD_MASK) | divisor; 1166b7e2b536SPali Rohár writel(val, uart_clock_base->reg2); 1167b7e2b536SPali Rohár } 1168b7e2b536SPali Rohár 1169b7e2b536SPali Rohár uart_clock_base->configured = true; 1170b7e2b536SPali Rohár 1171b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1172b7e2b536SPali Rohár 1173b7e2b536SPali Rohár return 0; 1174b7e2b536SPali Rohár } 1175b7e2b536SPali Rohár 1176b7e2b536SPali Rohár static int mvebu_uart_clock_enable(struct clk_hw *hw) 1177b7e2b536SPali Rohár { 1178b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1179b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1180b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1181b7e2b536SPali Rohár unsigned long flags; 1182b7e2b536SPali Rohár u32 val; 1183b7e2b536SPali Rohár 1184b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 1185b7e2b536SPali Rohár 1186b7e2b536SPali Rohár val = readl(uart_clock_base->reg1); 1187b7e2b536SPali Rohár 1188b7e2b536SPali Rohár if (uart_clock->clock_idx == 0) 1189b7e2b536SPali Rohár val &= ~UART1_CLK_DIS; 1190b7e2b536SPali Rohár else 1191b7e2b536SPali Rohár val &= ~UART2_CLK_DIS; 1192b7e2b536SPali Rohár 1193b7e2b536SPali Rohár writel(val, uart_clock_base->reg1); 1194b7e2b536SPali Rohár 1195b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1196b7e2b536SPali Rohár 1197b7e2b536SPali Rohár return 0; 1198b7e2b536SPali Rohár } 1199b7e2b536SPali Rohár 1200b7e2b536SPali Rohár static void mvebu_uart_clock_disable(struct clk_hw *hw) 1201b7e2b536SPali Rohár { 1202b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1203b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1204b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1205b7e2b536SPali Rohár unsigned long flags; 1206b7e2b536SPali Rohár u32 val; 1207b7e2b536SPali Rohár 1208b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 1209b7e2b536SPali Rohár 1210b7e2b536SPali Rohár val = readl(uart_clock_base->reg1); 1211b7e2b536SPali Rohár 1212b7e2b536SPali Rohár if (uart_clock->clock_idx == 0) 1213b7e2b536SPali Rohár val |= UART1_CLK_DIS; 1214b7e2b536SPali Rohár else 1215b7e2b536SPali Rohár val |= UART2_CLK_DIS; 1216b7e2b536SPali Rohár 1217b7e2b536SPali Rohár writel(val, uart_clock_base->reg1); 1218b7e2b536SPali Rohár 1219b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1220b7e2b536SPali Rohár } 1221b7e2b536SPali Rohár 1222b7e2b536SPali Rohár static int mvebu_uart_clock_is_enabled(struct clk_hw *hw) 1223b7e2b536SPali Rohár { 1224b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1225b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1226b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1227b7e2b536SPali Rohár u32 val; 1228b7e2b536SPali Rohár 1229b7e2b536SPali Rohár val = readl(uart_clock_base->reg1); 1230b7e2b536SPali Rohár 1231b7e2b536SPali Rohár if (uart_clock->clock_idx == 0) 1232b7e2b536SPali Rohár return !(val & UART1_CLK_DIS); 1233b7e2b536SPali Rohár else 1234b7e2b536SPali Rohár return !(val & UART2_CLK_DIS); 1235b7e2b536SPali Rohár } 1236b7e2b536SPali Rohár 1237b7e2b536SPali Rohár static int mvebu_uart_clock_save_context(struct clk_hw *hw) 1238b7e2b536SPali Rohár { 1239b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1240b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1241b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1242b7e2b536SPali Rohár unsigned long flags; 1243b7e2b536SPali Rohár 1244b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 1245b7e2b536SPali Rohár uart_clock->pm_context_reg1 = readl(uart_clock_base->reg1); 1246b7e2b536SPali Rohár uart_clock->pm_context_reg2 = readl(uart_clock_base->reg2); 1247b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1248b7e2b536SPali Rohár 1249b7e2b536SPali Rohár return 0; 1250b7e2b536SPali Rohár } 1251b7e2b536SPali Rohár 1252b7e2b536SPali Rohár static void mvebu_uart_clock_restore_context(struct clk_hw *hw) 1253b7e2b536SPali Rohár { 1254b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1255b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1256b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1257b7e2b536SPali Rohár unsigned long flags; 1258b7e2b536SPali Rohár 1259b7e2b536SPali Rohár spin_lock_irqsave(&mvebu_uart_lock, flags); 1260b7e2b536SPali Rohár writel(uart_clock->pm_context_reg1, uart_clock_base->reg1); 1261b7e2b536SPali Rohár writel(uart_clock->pm_context_reg2, uart_clock_base->reg2); 1262b7e2b536SPali Rohár spin_unlock_irqrestore(&mvebu_uart_lock, flags); 1263b7e2b536SPali Rohár } 1264b7e2b536SPali Rohár 1265b7e2b536SPali Rohár static unsigned long mvebu_uart_clock_recalc_rate(struct clk_hw *hw, 1266b7e2b536SPali Rohár unsigned long parent_rate) 1267b7e2b536SPali Rohár { 1268b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1269b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1270b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1271b7e2b536SPali Rohár 1272b7e2b536SPali Rohár return parent_rate / uart_clock_base->div; 1273b7e2b536SPali Rohár } 1274b7e2b536SPali Rohár 1275b7e2b536SPali Rohár static long mvebu_uart_clock_round_rate(struct clk_hw *hw, unsigned long rate, 1276b7e2b536SPali Rohár unsigned long *parent_rate) 1277b7e2b536SPali Rohár { 1278b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock = to_uart_clock(hw); 1279b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base = 1280b7e2b536SPali Rohár to_uart_clock_base(uart_clock); 1281b7e2b536SPali Rohár 1282b7e2b536SPali Rohár return *parent_rate / uart_clock_base->div; 1283b7e2b536SPali Rohár } 1284b7e2b536SPali Rohár 1285b7e2b536SPali Rohár static int mvebu_uart_clock_set_rate(struct clk_hw *hw, unsigned long rate, 1286b7e2b536SPali Rohár unsigned long parent_rate) 1287b7e2b536SPali Rohár { 1288b7e2b536SPali Rohár /* 1289b7e2b536SPali Rohár * We must report success but we can do so unconditionally because 1290b7e2b536SPali Rohár * mvebu_uart_clock_round_rate returns values that ensure this call is a 1291b7e2b536SPali Rohár * nop. 1292b7e2b536SPali Rohár */ 1293b7e2b536SPali Rohár 1294b7e2b536SPali Rohár return 0; 1295b7e2b536SPali Rohár } 1296b7e2b536SPali Rohár 1297b7e2b536SPali Rohár static const struct clk_ops mvebu_uart_clock_ops = { 1298b7e2b536SPali Rohár .prepare = mvebu_uart_clock_prepare, 1299b7e2b536SPali Rohár .enable = mvebu_uart_clock_enable, 1300b7e2b536SPali Rohár .disable = mvebu_uart_clock_disable, 1301b7e2b536SPali Rohár .is_enabled = mvebu_uart_clock_is_enabled, 1302b7e2b536SPali Rohár .save_context = mvebu_uart_clock_save_context, 1303b7e2b536SPali Rohár .restore_context = mvebu_uart_clock_restore_context, 1304b7e2b536SPali Rohár .round_rate = mvebu_uart_clock_round_rate, 1305b7e2b536SPali Rohár .set_rate = mvebu_uart_clock_set_rate, 1306b7e2b536SPali Rohár .recalc_rate = mvebu_uart_clock_recalc_rate, 1307b7e2b536SPali Rohár }; 1308b7e2b536SPali Rohár 1309b7e2b536SPali Rohár static int mvebu_uart_clock_register(struct device *dev, 1310b7e2b536SPali Rohár struct mvebu_uart_clock *uart_clock, 1311b7e2b536SPali Rohár const char *name, 1312b7e2b536SPali Rohár const char *parent_name) 1313b7e2b536SPali Rohár { 1314b7e2b536SPali Rohár struct clk_init_data init = { }; 1315b7e2b536SPali Rohár 1316b7e2b536SPali Rohár uart_clock->clk_hw.init = &init; 1317b7e2b536SPali Rohár 1318b7e2b536SPali Rohár init.name = name; 1319b7e2b536SPali Rohár init.ops = &mvebu_uart_clock_ops; 1320b7e2b536SPali Rohár init.flags = 0; 1321b7e2b536SPali Rohár init.num_parents = 1; 1322b7e2b536SPali Rohár init.parent_names = &parent_name; 1323b7e2b536SPali Rohár 1324b7e2b536SPali Rohár return devm_clk_hw_register(dev, &uart_clock->clk_hw); 1325b7e2b536SPali Rohár } 1326b7e2b536SPali Rohár 1327b7e2b536SPali Rohár static int mvebu_uart_clock_probe(struct platform_device *pdev) 1328b7e2b536SPali Rohár { 1329b7e2b536SPali Rohár static const char *const uart_clk_names[] = { "uart_1", "uart_2" }; 1330b7e2b536SPali Rohár static const char *const parent_clk_names[] = { "TBG-A-P", "TBG-B-P", 1331b7e2b536SPali Rohár "TBG-A-S", "TBG-B-S", 1332b7e2b536SPali Rohár "xtal" }; 1333b7e2b536SPali Rohár struct clk *parent_clks[ARRAY_SIZE(parent_clk_names)]; 1334b7e2b536SPali Rohár struct mvebu_uart_clock_base *uart_clock_base; 1335b7e2b536SPali Rohár struct clk_hw_onecell_data *hw_clk_data; 1336b7e2b536SPali Rohár struct device *dev = &pdev->dev; 1337b7e2b536SPali Rohár int i, parent_clk_idx, ret; 1338b7e2b536SPali Rohár unsigned long div, rate; 1339b7e2b536SPali Rohár struct resource *res; 1340b7e2b536SPali Rohár unsigned int d1, d2; 1341b7e2b536SPali Rohár 1342b7e2b536SPali Rohár BUILD_BUG_ON(ARRAY_SIZE(uart_clk_names) != 1343b7e2b536SPali Rohár ARRAY_SIZE(uart_clock_base->clocks)); 1344b7e2b536SPali Rohár BUILD_BUG_ON(ARRAY_SIZE(parent_clk_names) != 1345b7e2b536SPali Rohár ARRAY_SIZE(uart_clock_base->parent_rates)); 1346b7e2b536SPali Rohár 1347b7e2b536SPali Rohár uart_clock_base = devm_kzalloc(dev, 1348b7e2b536SPali Rohár sizeof(*uart_clock_base), 1349b7e2b536SPali Rohár GFP_KERNEL); 1350b7e2b536SPali Rohár if (!uart_clock_base) 1351b7e2b536SPali Rohár return -ENOMEM; 1352b7e2b536SPali Rohár 1353b7e2b536SPali Rohár res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1354b7e2b536SPali Rohár if (!res) { 1355b7e2b536SPali Rohár dev_err(dev, "Couldn't get first register\n"); 1356b7e2b536SPali Rohár return -ENOENT; 1357b7e2b536SPali Rohár } 1358b7e2b536SPali Rohár 1359b7e2b536SPali Rohár /* 1360b7e2b536SPali Rohár * UART Clock Control register (reg1 / UART_BRDV) is in the address 1361b7e2b536SPali Rohár * space of UART1 (standard UART variant), controls parent clock and 1362b7e2b536SPali Rohár * dividers for both UART1 and UART2 and is supplied via DT as the first 1363b7e2b536SPali Rohár * resource. Therefore use ioremap() rather than ioremap_resource() to 1364b7e2b536SPali Rohár * avoid conflicts with UART1 driver. Access to UART_BRDV is protected 1365b7e2b536SPali Rohár * by a lock shared between clock and UART driver. 1366b7e2b536SPali Rohár */ 1367b7e2b536SPali Rohár uart_clock_base->reg1 = devm_ioremap(dev, res->start, 1368b7e2b536SPali Rohár resource_size(res)); 136947b95e8aSWei Yongjun if (!uart_clock_base->reg1) 137047b95e8aSWei Yongjun return -ENOMEM; 1371b7e2b536SPali Rohár 1372b7e2b536SPali Rohár res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1373b7e2b536SPali Rohár if (!res) { 1374b7e2b536SPali Rohár dev_err(dev, "Couldn't get second register\n"); 1375b7e2b536SPali Rohár return -ENOENT; 1376b7e2b536SPali Rohár } 1377b7e2b536SPali Rohár 1378b7e2b536SPali Rohár /* 1379b7e2b536SPali Rohár * UART 2 Baud Rate Divisor register (reg2 / UART_BRDV) is in address 1380b7e2b536SPali Rohár * space of UART2 (extended UART variant), controls only one UART2 1381b7e2b536SPali Rohár * specific divider and is supplied via DT as second resource. 1382b7e2b536SPali Rohár * Therefore use ioremap() rather than ioremap_resource() to avoid 1383b7e2b536SPali Rohár * conflicts with UART2 driver. Access to UART_BRDV is protected by a 1384b7e2b536SPali Rohár * by lock shared between clock and UART driver. 1385b7e2b536SPali Rohár */ 1386b7e2b536SPali Rohár uart_clock_base->reg2 = devm_ioremap(dev, res->start, 1387b7e2b536SPali Rohár resource_size(res)); 138847b95e8aSWei Yongjun if (!uart_clock_base->reg2) 138947b95e8aSWei Yongjun return -ENOMEM; 1390b7e2b536SPali Rohár 1391b7e2b536SPali Rohár hw_clk_data = devm_kzalloc(dev, 1392b7e2b536SPali Rohár struct_size(hw_clk_data, hws, 1393b7e2b536SPali Rohár ARRAY_SIZE(uart_clk_names)), 1394b7e2b536SPali Rohár GFP_KERNEL); 1395b7e2b536SPali Rohár if (!hw_clk_data) 1396b7e2b536SPali Rohár return -ENOMEM; 1397b7e2b536SPali Rohár 1398b7e2b536SPali Rohár hw_clk_data->num = ARRAY_SIZE(uart_clk_names); 1399b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) { 1400b7e2b536SPali Rohár hw_clk_data->hws[i] = &uart_clock_base->clocks[i].clk_hw; 1401b7e2b536SPali Rohár uart_clock_base->clocks[i].clock_idx = i; 1402b7e2b536SPali Rohár } 1403b7e2b536SPali Rohár 1404b7e2b536SPali Rohár parent_clk_idx = -1; 1405b7e2b536SPali Rohár 1406b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) { 1407b7e2b536SPali Rohár parent_clks[i] = devm_clk_get(dev, parent_clk_names[i]); 1408b7e2b536SPali Rohár if (IS_ERR(parent_clks[i])) { 1409b7e2b536SPali Rohár if (PTR_ERR(parent_clks[i]) == -EPROBE_DEFER) 1410b7e2b536SPali Rohár return -EPROBE_DEFER; 1411b7e2b536SPali Rohár dev_warn(dev, "Couldn't get the parent clock %s: %ld\n", 1412b7e2b536SPali Rohár parent_clk_names[i], PTR_ERR(parent_clks[i])); 1413b7e2b536SPali Rohár continue; 1414b7e2b536SPali Rohár } 1415b7e2b536SPali Rohár 1416b7e2b536SPali Rohár ret = clk_prepare_enable(parent_clks[i]); 1417b7e2b536SPali Rohár if (ret) { 1418b7e2b536SPali Rohár dev_warn(dev, "Couldn't enable parent clock %s: %d\n", 1419b7e2b536SPali Rohár parent_clk_names[i], ret); 1420b7e2b536SPali Rohár continue; 1421b7e2b536SPali Rohár } 1422b7e2b536SPali Rohár rate = clk_get_rate(parent_clks[i]); 1423b7e2b536SPali Rohár uart_clock_base->parent_rates[i] = rate; 1424b7e2b536SPali Rohár 1425b7e2b536SPali Rohár if (i != PARENT_CLOCK_XTAL) { 1426b7e2b536SPali Rohár /* 1427b7e2b536SPali Rohár * Calculate the smallest TBG d1 and d2 divisors that 1428b7e2b536SPali Rohár * still can provide 9600 baudrate. 1429b7e2b536SPali Rohár */ 1430694b7112SPali Rohár d1 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * 1431b7e2b536SPali Rohár BRDV_BAUD_MAX); 1432b7e2b536SPali Rohár if (d1 < 1) 1433b7e2b536SPali Rohár d1 = 1; 1434b7e2b536SPali Rohár else if (d1 > CLK_TBG_DIV1_MAX) 1435b7e2b536SPali Rohár d1 = CLK_TBG_DIV1_MAX; 1436b7e2b536SPali Rohár 1437694b7112SPali Rohár d2 = DIV_ROUND_UP(rate, 9600 * OSAMP_MAX_DIVISOR * 1438b7e2b536SPali Rohár BRDV_BAUD_MAX * d1); 1439b7e2b536SPali Rohár if (d2 < 1) 1440b7e2b536SPali Rohár d2 = 1; 1441b7e2b536SPali Rohár else if (d2 > CLK_TBG_DIV2_MAX) 1442b7e2b536SPali Rohár d2 = CLK_TBG_DIV2_MAX; 1443b7e2b536SPali Rohár } else { 1444b7e2b536SPali Rohár /* 1445b7e2b536SPali Rohár * When UART clock uses XTAL clock as a source then it 1446b7e2b536SPali Rohár * is not possible to use d1 and d2 divisors. 1447b7e2b536SPali Rohár */ 1448b7e2b536SPali Rohár d1 = d2 = 1; 1449b7e2b536SPali Rohár } 1450b7e2b536SPali Rohár 1451b7e2b536SPali Rohár /* Skip clock source which cannot provide 9600 baudrate */ 1452694b7112SPali Rohár if (rate > 9600 * OSAMP_MAX_DIVISOR * BRDV_BAUD_MAX * d1 * d2) 1453b7e2b536SPali Rohár continue; 1454b7e2b536SPali Rohár 1455b7e2b536SPali Rohár /* 1456b7e2b536SPali Rohár * Choose TBG clock source with the smallest divisors. Use XTAL 1457b7e2b536SPali Rohár * clock source only in case TBG is not available as XTAL cannot 1458b7e2b536SPali Rohár * be used for baudrates higher than 230400. 1459b7e2b536SPali Rohár */ 1460b7e2b536SPali Rohár if (parent_clk_idx == -1 || 1461b7e2b536SPali Rohár (i != PARENT_CLOCK_XTAL && div > d1 * d2)) { 1462b7e2b536SPali Rohár parent_clk_idx = i; 1463b7e2b536SPali Rohár div = d1 * d2; 1464b7e2b536SPali Rohár } 1465b7e2b536SPali Rohár } 1466b7e2b536SPali Rohár 1467b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(parent_clk_names); i++) { 1468b7e2b536SPali Rohár if (i == parent_clk_idx || IS_ERR(parent_clks[i])) 1469b7e2b536SPali Rohár continue; 1470b7e2b536SPali Rohár clk_disable_unprepare(parent_clks[i]); 1471b7e2b536SPali Rohár devm_clk_put(dev, parent_clks[i]); 1472b7e2b536SPali Rohár } 1473b7e2b536SPali Rohár 1474b7e2b536SPali Rohár if (parent_clk_idx == -1) { 1475b7e2b536SPali Rohár dev_err(dev, "No usable parent clock\n"); 1476b7e2b536SPali Rohár return -ENOENT; 1477b7e2b536SPali Rohár } 1478b7e2b536SPali Rohár 1479b7e2b536SPali Rohár uart_clock_base->parent_idx = parent_clk_idx; 1480b7e2b536SPali Rohár uart_clock_base->div = div; 1481b7e2b536SPali Rohár 1482b7e2b536SPali Rohár dev_notice(dev, "Using parent clock %s as base UART clock\n", 1483b7e2b536SPali Rohár __clk_get_name(parent_clks[parent_clk_idx])); 1484b7e2b536SPali Rohár 1485b7e2b536SPali Rohár for (i = 0; i < ARRAY_SIZE(uart_clk_names); i++) { 1486b7e2b536SPali Rohár ret = mvebu_uart_clock_register(dev, 1487b7e2b536SPali Rohár &uart_clock_base->clocks[i], 1488b7e2b536SPali Rohár uart_clk_names[i], 1489b7e2b536SPali Rohár __clk_get_name(parent_clks[parent_clk_idx])); 1490b7e2b536SPali Rohár if (ret) { 1491b7e2b536SPali Rohár dev_err(dev, "Can't register UART clock %d: %d\n", 1492b7e2b536SPali Rohár i, ret); 1493b7e2b536SPali Rohár return ret; 1494b7e2b536SPali Rohár } 1495b7e2b536SPali Rohár } 1496b7e2b536SPali Rohár 1497b7e2b536SPali Rohár return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, 1498b7e2b536SPali Rohár hw_clk_data); 1499b7e2b536SPali Rohár } 1500b7e2b536SPali Rohár 1501b7e2b536SPali Rohár static const struct of_device_id mvebu_uart_clock_of_match[] = { 1502b7e2b536SPali Rohár { .compatible = "marvell,armada-3700-uart-clock", }, 1503b7e2b536SPali Rohár { } 1504b7e2b536SPali Rohár }; 1505b7e2b536SPali Rohár 1506b7e2b536SPali Rohár static struct platform_driver mvebu_uart_clock_platform_driver = { 1507b7e2b536SPali Rohár .probe = mvebu_uart_clock_probe, 1508b7e2b536SPali Rohár .driver = { 1509b7e2b536SPali Rohár .name = "mvebu-uart-clock", 1510b7e2b536SPali Rohár .of_match_table = mvebu_uart_clock_of_match, 1511b7e2b536SPali Rohár }, 1512b7e2b536SPali Rohár }; 1513b7e2b536SPali Rohár 151430530791SWilson Ding static int __init mvebu_uart_init(void) 151530530791SWilson Ding { 151630530791SWilson Ding int ret; 151730530791SWilson Ding 151830530791SWilson Ding ret = uart_register_driver(&mvebu_uart_driver); 151930530791SWilson Ding if (ret) 152030530791SWilson Ding return ret; 152130530791SWilson Ding 1522b7e2b536SPali Rohár ret = platform_driver_register(&mvebu_uart_clock_platform_driver); 1523b7e2b536SPali Rohár if (ret) { 152430530791SWilson Ding uart_unregister_driver(&mvebu_uart_driver); 152530530791SWilson Ding return ret; 152630530791SWilson Ding } 1527b7e2b536SPali Rohár 1528b7e2b536SPali Rohár ret = platform_driver_register(&mvebu_uart_platform_driver); 1529b7e2b536SPali Rohár if (ret) { 1530b7e2b536SPali Rohár platform_driver_unregister(&mvebu_uart_clock_platform_driver); 1531b7e2b536SPali Rohár uart_unregister_driver(&mvebu_uart_driver); 1532b7e2b536SPali Rohár return ret; 1533b7e2b536SPali Rohár } 1534b7e2b536SPali Rohár 1535b7e2b536SPali Rohár return 0; 1536b7e2b536SPali Rohár } 153730530791SWilson Ding arch_initcall(mvebu_uart_init); 1538