1 /* 2 * Driver for msm7k serial device and console 3 * 4 * Copyright (C) 2007 Google, Inc. 5 * Author: Robert Love <rlove@google.com> 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 # define SUPPORT_SYSRQ 20 #endif 21 22 #include <linux/atomic.h> 23 #include <linux/hrtimer.h> 24 #include <linux/module.h> 25 #include <linux/io.h> 26 #include <linux/ioport.h> 27 #include <linux/irq.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial_core.h> 33 #include <linux/serial.h> 34 #include <linux/clk.h> 35 #include <linux/platform_device.h> 36 #include <linux/delay.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 40 #include "msm_serial.h" 41 42 struct msm_port { 43 struct uart_port uart; 44 char name[16]; 45 struct clk *clk; 46 struct clk *pclk; 47 unsigned int imr; 48 void __iomem *gsbi_base; 49 int is_uartdm; 50 unsigned int old_snap_state; 51 }; 52 53 static inline void wait_for_xmitr(struct uart_port *port) 54 { 55 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) { 56 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY) 57 break; 58 udelay(1); 59 } 60 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); 61 } 62 63 static void msm_stop_tx(struct uart_port *port) 64 { 65 struct msm_port *msm_port = UART_TO_MSM(port); 66 67 msm_port->imr &= ~UART_IMR_TXLEV; 68 msm_write(port, msm_port->imr, UART_IMR); 69 } 70 71 static void msm_start_tx(struct uart_port *port) 72 { 73 struct msm_port *msm_port = UART_TO_MSM(port); 74 75 msm_port->imr |= UART_IMR_TXLEV; 76 msm_write(port, msm_port->imr, UART_IMR); 77 } 78 79 static void msm_stop_rx(struct uart_port *port) 80 { 81 struct msm_port *msm_port = UART_TO_MSM(port); 82 83 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 84 msm_write(port, msm_port->imr, UART_IMR); 85 } 86 87 static void msm_enable_ms(struct uart_port *port) 88 { 89 struct msm_port *msm_port = UART_TO_MSM(port); 90 91 msm_port->imr |= UART_IMR_DELTA_CTS; 92 msm_write(port, msm_port->imr, UART_IMR); 93 } 94 95 static void handle_rx_dm(struct uart_port *port, unsigned int misr) 96 { 97 struct tty_port *tport = &port->state->port; 98 unsigned int sr; 99 int count = 0; 100 struct msm_port *msm_port = UART_TO_MSM(port); 101 102 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 103 port->icount.overrun++; 104 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 105 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 106 } 107 108 if (misr & UART_IMR_RXSTALE) { 109 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 110 msm_port->old_snap_state; 111 msm_port->old_snap_state = 0; 112 } else { 113 count = 4 * (msm_read(port, UART_RFWR)); 114 msm_port->old_snap_state += count; 115 } 116 117 /* TODO: Precise error reporting */ 118 119 port->icount.rx += count; 120 121 while (count > 0) { 122 unsigned int c; 123 124 sr = msm_read(port, UART_SR); 125 if ((sr & UART_SR_RX_READY) == 0) { 126 msm_port->old_snap_state -= count; 127 break; 128 } 129 c = msm_read(port, UARTDM_RF); 130 if (sr & UART_SR_RX_BREAK) { 131 port->icount.brk++; 132 if (uart_handle_break(port)) 133 continue; 134 } else if (sr & UART_SR_PAR_FRAME_ERR) 135 port->icount.frame++; 136 137 /* TODO: handle sysrq */ 138 tty_insert_flip_string(tport, (char *)&c, 139 (count > 4) ? 4 : count); 140 count -= 4; 141 } 142 143 spin_unlock(&port->lock); 144 tty_flip_buffer_push(tport); 145 spin_lock(&port->lock); 146 147 if (misr & (UART_IMR_RXSTALE)) 148 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 149 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 150 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 151 } 152 153 static void handle_rx(struct uart_port *port) 154 { 155 struct tty_port *tport = &port->state->port; 156 unsigned int sr; 157 158 /* 159 * Handle overrun. My understanding of the hardware is that overrun 160 * is not tied to the RX buffer, so we handle the case out of band. 161 */ 162 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 163 port->icount.overrun++; 164 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 165 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 166 } 167 168 /* and now the main RX loop */ 169 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 170 unsigned int c; 171 char flag = TTY_NORMAL; 172 173 c = msm_read(port, UART_RF); 174 175 if (sr & UART_SR_RX_BREAK) { 176 port->icount.brk++; 177 if (uart_handle_break(port)) 178 continue; 179 } else if (sr & UART_SR_PAR_FRAME_ERR) { 180 port->icount.frame++; 181 } else { 182 port->icount.rx++; 183 } 184 185 /* Mask conditions we're ignorning. */ 186 sr &= port->read_status_mask; 187 188 if (sr & UART_SR_RX_BREAK) { 189 flag = TTY_BREAK; 190 } else if (sr & UART_SR_PAR_FRAME_ERR) { 191 flag = TTY_FRAME; 192 } 193 194 if (!uart_handle_sysrq_char(port, c)) 195 tty_insert_flip_char(tport, c, flag); 196 } 197 198 spin_unlock(&port->lock); 199 tty_flip_buffer_push(tport); 200 spin_lock(&port->lock); 201 } 202 203 static void reset_dm_count(struct uart_port *port, int count) 204 { 205 wait_for_xmitr(port); 206 msm_write(port, count, UARTDM_NCF_TX); 207 msm_read(port, UARTDM_NCF_TX); 208 } 209 210 static void handle_tx(struct uart_port *port) 211 { 212 struct circ_buf *xmit = &port->state->xmit; 213 struct msm_port *msm_port = UART_TO_MSM(port); 214 unsigned int tx_count, num_chars; 215 unsigned int tf_pointer = 0; 216 217 tx_count = uart_circ_chars_pending(xmit); 218 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail, 219 port->fifosize); 220 221 if (port->x_char) { 222 if (msm_port->is_uartdm) 223 reset_dm_count(port, tx_count + 1); 224 225 msm_write(port, port->x_char, 226 msm_port->is_uartdm ? UARTDM_TF : UART_TF); 227 port->icount.tx++; 228 port->x_char = 0; 229 } else if (tx_count && msm_port->is_uartdm) { 230 reset_dm_count(port, tx_count); 231 } 232 233 while (tf_pointer < tx_count) { 234 int i; 235 char buf[4] = { 0 }; 236 unsigned int *bf = (unsigned int *)&buf; 237 238 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 239 break; 240 241 if (msm_port->is_uartdm) 242 num_chars = min(tx_count - tf_pointer, 243 (unsigned int)sizeof(buf)); 244 else 245 num_chars = 1; 246 247 for (i = 0; i < num_chars; i++) { 248 buf[i] = xmit->buf[xmit->tail + i]; 249 port->icount.tx++; 250 } 251 252 msm_write(port, *bf, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 253 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); 254 tf_pointer += num_chars; 255 } 256 257 /* disable tx interrupts if nothing more to send */ 258 if (uart_circ_empty(xmit)) 259 msm_stop_tx(port); 260 261 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 262 uart_write_wakeup(port); 263 } 264 265 static void handle_delta_cts(struct uart_port *port) 266 { 267 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 268 port->icount.cts++; 269 wake_up_interruptible(&port->state->port.delta_msr_wait); 270 } 271 272 static irqreturn_t msm_irq(int irq, void *dev_id) 273 { 274 struct uart_port *port = dev_id; 275 struct msm_port *msm_port = UART_TO_MSM(port); 276 unsigned int misr; 277 278 spin_lock(&port->lock); 279 misr = msm_read(port, UART_MISR); 280 msm_write(port, 0, UART_IMR); /* disable interrupt */ 281 282 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 283 if (msm_port->is_uartdm) 284 handle_rx_dm(port, misr); 285 else 286 handle_rx(port); 287 } 288 if (misr & UART_IMR_TXLEV) 289 handle_tx(port); 290 if (misr & UART_IMR_DELTA_CTS) 291 handle_delta_cts(port); 292 293 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 294 spin_unlock(&port->lock); 295 296 return IRQ_HANDLED; 297 } 298 299 static unsigned int msm_tx_empty(struct uart_port *port) 300 { 301 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 302 } 303 304 static unsigned int msm_get_mctrl(struct uart_port *port) 305 { 306 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 307 } 308 309 310 static void msm_reset(struct uart_port *port) 311 { 312 /* reset everything */ 313 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 314 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 315 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 316 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 317 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 318 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); 319 } 320 321 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 322 { 323 unsigned int mr; 324 mr = msm_read(port, UART_MR1); 325 326 if (!(mctrl & TIOCM_RTS)) { 327 mr &= ~UART_MR1_RX_RDY_CTL; 328 msm_write(port, mr, UART_MR1); 329 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 330 } else { 331 mr |= UART_MR1_RX_RDY_CTL; 332 msm_write(port, mr, UART_MR1); 333 } 334 } 335 336 static void msm_break_ctl(struct uart_port *port, int break_ctl) 337 { 338 if (break_ctl) 339 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 340 else 341 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 342 } 343 344 struct msm_baud_map { 345 u16 divisor; 346 u8 code; 347 u8 rxstale; 348 }; 349 350 static const struct msm_baud_map * 351 msm_find_best_baud(struct uart_port *port, unsigned int baud) 352 { 353 unsigned int i, divisor; 354 const struct msm_baud_map *entry; 355 static const struct msm_baud_map table[] = { 356 { 1536, 0x00, 1 }, 357 { 768, 0x11, 1 }, 358 { 384, 0x22, 1 }, 359 { 192, 0x33, 1 }, 360 { 96, 0x44, 1 }, 361 { 48, 0x55, 1 }, 362 { 32, 0x66, 1 }, 363 { 24, 0x77, 1 }, 364 { 16, 0x88, 1 }, 365 { 12, 0x99, 6 }, 366 { 8, 0xaa, 6 }, 367 { 6, 0xbb, 6 }, 368 { 4, 0xcc, 6 }, 369 { 3, 0xdd, 8 }, 370 { 2, 0xee, 16 }, 371 { 1, 0xff, 31 }, 372 }; 373 374 divisor = uart_get_divisor(port, baud); 375 376 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++) 377 if (entry->divisor <= divisor) 378 break; 379 380 return entry; /* Default to smallest divider */ 381 } 382 383 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) 384 { 385 unsigned int rxstale, watermark; 386 struct msm_port *msm_port = UART_TO_MSM(port); 387 const struct msm_baud_map *entry; 388 389 entry = msm_find_best_baud(port, baud); 390 391 if (msm_port->is_uartdm) 392 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 393 394 msm_write(port, entry->code, UART_CSR); 395 396 /* RX stale watermark */ 397 rxstale = entry->rxstale; 398 watermark = UART_IPR_STALE_LSB & rxstale; 399 watermark |= UART_IPR_RXSTALE_LAST; 400 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2); 401 msm_write(port, watermark, UART_IPR); 402 403 /* set RX watermark */ 404 watermark = (port->fifosize * 3) / 4; 405 msm_write(port, watermark, UART_RFWR); 406 407 /* set TX watermark */ 408 msm_write(port, 10, UART_TFWR); 409 410 if (msm_port->is_uartdm) { 411 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 412 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 413 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 414 } 415 416 return baud; 417 } 418 419 420 static void msm_init_clock(struct uart_port *port) 421 { 422 struct msm_port *msm_port = UART_TO_MSM(port); 423 424 clk_prepare_enable(msm_port->clk); 425 clk_prepare_enable(msm_port->pclk); 426 msm_serial_set_mnd_regs(port); 427 } 428 429 static int msm_startup(struct uart_port *port) 430 { 431 struct msm_port *msm_port = UART_TO_MSM(port); 432 unsigned int data, rfr_level; 433 int ret; 434 435 snprintf(msm_port->name, sizeof(msm_port->name), 436 "msm_serial%d", port->line); 437 438 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH, 439 msm_port->name, port); 440 if (unlikely(ret)) 441 return ret; 442 443 msm_init_clock(port); 444 445 if (likely(port->fifosize > 12)) 446 rfr_level = port->fifosize - 12; 447 else 448 rfr_level = port->fifosize; 449 450 /* set automatic RFR level */ 451 data = msm_read(port, UART_MR1); 452 data &= ~UART_MR1_AUTO_RFR_LEVEL1; 453 data &= ~UART_MR1_AUTO_RFR_LEVEL0; 454 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2); 455 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 456 msm_write(port, data, UART_MR1); 457 458 /* make sure that RXSTALE count is non-zero */ 459 data = msm_read(port, UART_IPR); 460 if (unlikely(!data)) { 461 data |= UART_IPR_RXSTALE_LAST; 462 data |= UART_IPR_STALE_LSB; 463 msm_write(port, data, UART_IPR); 464 } 465 466 data = 0; 467 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) { 468 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 469 msm_reset(port); 470 data = UART_CR_TX_ENABLE; 471 } 472 473 data |= UART_CR_RX_ENABLE; 474 msm_write(port, data, UART_CR); /* enable TX & RX */ 475 476 /* Make sure IPR is not 0 to start with*/ 477 if (msm_port->is_uartdm) 478 msm_write(port, UART_IPR_STALE_LSB, UART_IPR); 479 480 /* turn on RX and CTS interrupts */ 481 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 482 UART_IMR_CURRENT_CTS; 483 484 if (msm_port->is_uartdm) { 485 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 486 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 487 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 488 } 489 490 msm_write(port, msm_port->imr, UART_IMR); 491 return 0; 492 } 493 494 static void msm_shutdown(struct uart_port *port) 495 { 496 struct msm_port *msm_port = UART_TO_MSM(port); 497 498 msm_port->imr = 0; 499 msm_write(port, 0, UART_IMR); /* disable interrupts */ 500 501 clk_disable_unprepare(msm_port->clk); 502 503 free_irq(port->irq, port); 504 } 505 506 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 507 struct ktermios *old) 508 { 509 unsigned long flags; 510 unsigned int baud, mr; 511 512 spin_lock_irqsave(&port->lock, flags); 513 514 /* calculate and set baud rate */ 515 baud = uart_get_baud_rate(port, termios, old, 300, 115200); 516 baud = msm_set_baud_rate(port, baud); 517 if (tty_termios_baud_rate(termios)) 518 tty_termios_encode_baud_rate(termios, baud, baud); 519 520 /* calculate parity */ 521 mr = msm_read(port, UART_MR2); 522 mr &= ~UART_MR2_PARITY_MODE; 523 if (termios->c_cflag & PARENB) { 524 if (termios->c_cflag & PARODD) 525 mr |= UART_MR2_PARITY_MODE_ODD; 526 else if (termios->c_cflag & CMSPAR) 527 mr |= UART_MR2_PARITY_MODE_SPACE; 528 else 529 mr |= UART_MR2_PARITY_MODE_EVEN; 530 } 531 532 /* calculate bits per char */ 533 mr &= ~UART_MR2_BITS_PER_CHAR; 534 switch (termios->c_cflag & CSIZE) { 535 case CS5: 536 mr |= UART_MR2_BITS_PER_CHAR_5; 537 break; 538 case CS6: 539 mr |= UART_MR2_BITS_PER_CHAR_6; 540 break; 541 case CS7: 542 mr |= UART_MR2_BITS_PER_CHAR_7; 543 break; 544 case CS8: 545 default: 546 mr |= UART_MR2_BITS_PER_CHAR_8; 547 break; 548 } 549 550 /* calculate stop bits */ 551 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 552 if (termios->c_cflag & CSTOPB) 553 mr |= UART_MR2_STOP_BIT_LEN_TWO; 554 else 555 mr |= UART_MR2_STOP_BIT_LEN_ONE; 556 557 /* set parity, bits per char, and stop bit */ 558 msm_write(port, mr, UART_MR2); 559 560 /* calculate and set hardware flow control */ 561 mr = msm_read(port, UART_MR1); 562 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 563 if (termios->c_cflag & CRTSCTS) { 564 mr |= UART_MR1_CTS_CTL; 565 mr |= UART_MR1_RX_RDY_CTL; 566 } 567 msm_write(port, mr, UART_MR1); 568 569 /* Configure status bits to ignore based on termio flags. */ 570 port->read_status_mask = 0; 571 if (termios->c_iflag & INPCK) 572 port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 573 if (termios->c_iflag & (BRKINT | PARMRK)) 574 port->read_status_mask |= UART_SR_RX_BREAK; 575 576 uart_update_timeout(port, termios->c_cflag, baud); 577 578 spin_unlock_irqrestore(&port->lock, flags); 579 } 580 581 static const char *msm_type(struct uart_port *port) 582 { 583 return "MSM"; 584 } 585 586 static void msm_release_port(struct uart_port *port) 587 { 588 struct platform_device *pdev = to_platform_device(port->dev); 589 struct msm_port *msm_port = UART_TO_MSM(port); 590 struct resource *uart_resource; 591 struct resource *gsbi_resource; 592 resource_size_t size; 593 594 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 595 if (unlikely(!uart_resource)) 596 return; 597 size = resource_size(uart_resource); 598 599 release_mem_region(port->mapbase, size); 600 iounmap(port->membase); 601 port->membase = NULL; 602 603 if (msm_port->gsbi_base) { 604 writel_relaxed(GSBI_PROTOCOL_IDLE, 605 msm_port->gsbi_base + GSBI_CONTROL); 606 607 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1); 608 if (unlikely(!gsbi_resource)) 609 return; 610 611 size = resource_size(gsbi_resource); 612 release_mem_region(gsbi_resource->start, size); 613 iounmap(msm_port->gsbi_base); 614 msm_port->gsbi_base = NULL; 615 } 616 } 617 618 static int msm_request_port(struct uart_port *port) 619 { 620 struct msm_port *msm_port = UART_TO_MSM(port); 621 struct platform_device *pdev = to_platform_device(port->dev); 622 struct resource *uart_resource; 623 struct resource *gsbi_resource; 624 resource_size_t size; 625 int ret; 626 627 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 628 if (unlikely(!uart_resource)) 629 return -ENXIO; 630 631 size = resource_size(uart_resource); 632 633 if (!request_mem_region(port->mapbase, size, "msm_serial")) 634 return -EBUSY; 635 636 port->membase = ioremap(port->mapbase, size); 637 if (!port->membase) { 638 ret = -EBUSY; 639 goto fail_release_port; 640 } 641 642 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1); 643 /* Is this a GSBI-based port? */ 644 if (gsbi_resource) { 645 size = resource_size(gsbi_resource); 646 647 if (!request_mem_region(gsbi_resource->start, size, 648 "msm_serial")) { 649 ret = -EBUSY; 650 goto fail_release_port_membase; 651 } 652 653 msm_port->gsbi_base = ioremap(gsbi_resource->start, size); 654 if (!msm_port->gsbi_base) { 655 ret = -EBUSY; 656 goto fail_release_gsbi; 657 } 658 } 659 660 return 0; 661 662 fail_release_gsbi: 663 release_mem_region(gsbi_resource->start, size); 664 fail_release_port_membase: 665 iounmap(port->membase); 666 fail_release_port: 667 release_mem_region(port->mapbase, size); 668 return ret; 669 } 670 671 static void msm_config_port(struct uart_port *port, int flags) 672 { 673 struct msm_port *msm_port = UART_TO_MSM(port); 674 int ret; 675 if (flags & UART_CONFIG_TYPE) { 676 port->type = PORT_MSM; 677 ret = msm_request_port(port); 678 if (ret) 679 return; 680 } 681 if (msm_port->gsbi_base) 682 writel_relaxed(GSBI_PROTOCOL_UART, 683 msm_port->gsbi_base + GSBI_CONTROL); 684 } 685 686 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 687 { 688 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 689 return -EINVAL; 690 if (unlikely(port->irq != ser->irq)) 691 return -EINVAL; 692 return 0; 693 } 694 695 static void msm_power(struct uart_port *port, unsigned int state, 696 unsigned int oldstate) 697 { 698 struct msm_port *msm_port = UART_TO_MSM(port); 699 700 switch (state) { 701 case 0: 702 clk_prepare_enable(msm_port->clk); 703 clk_prepare_enable(msm_port->pclk); 704 break; 705 case 3: 706 clk_disable_unprepare(msm_port->clk); 707 clk_disable_unprepare(msm_port->pclk); 708 break; 709 default: 710 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state); 711 } 712 } 713 714 static struct uart_ops msm_uart_pops = { 715 .tx_empty = msm_tx_empty, 716 .set_mctrl = msm_set_mctrl, 717 .get_mctrl = msm_get_mctrl, 718 .stop_tx = msm_stop_tx, 719 .start_tx = msm_start_tx, 720 .stop_rx = msm_stop_rx, 721 .enable_ms = msm_enable_ms, 722 .break_ctl = msm_break_ctl, 723 .startup = msm_startup, 724 .shutdown = msm_shutdown, 725 .set_termios = msm_set_termios, 726 .type = msm_type, 727 .release_port = msm_release_port, 728 .request_port = msm_request_port, 729 .config_port = msm_config_port, 730 .verify_port = msm_verify_port, 731 .pm = msm_power, 732 }; 733 734 static struct msm_port msm_uart_ports[] = { 735 { 736 .uart = { 737 .iotype = UPIO_MEM, 738 .ops = &msm_uart_pops, 739 .flags = UPF_BOOT_AUTOCONF, 740 .fifosize = 64, 741 .line = 0, 742 }, 743 }, 744 { 745 .uart = { 746 .iotype = UPIO_MEM, 747 .ops = &msm_uart_pops, 748 .flags = UPF_BOOT_AUTOCONF, 749 .fifosize = 64, 750 .line = 1, 751 }, 752 }, 753 { 754 .uart = { 755 .iotype = UPIO_MEM, 756 .ops = &msm_uart_pops, 757 .flags = UPF_BOOT_AUTOCONF, 758 .fifosize = 64, 759 .line = 2, 760 }, 761 }, 762 }; 763 764 #define UART_NR ARRAY_SIZE(msm_uart_ports) 765 766 static inline struct uart_port *get_port_from_line(unsigned int line) 767 { 768 return &msm_uart_ports[line].uart; 769 } 770 771 #ifdef CONFIG_SERIAL_MSM_CONSOLE 772 static void msm_console_write(struct console *co, const char *s, 773 unsigned int count) 774 { 775 int i; 776 struct uart_port *port; 777 struct msm_port *msm_port; 778 int num_newlines = 0; 779 bool replaced = false; 780 781 BUG_ON(co->index < 0 || co->index >= UART_NR); 782 783 port = get_port_from_line(co->index); 784 msm_port = UART_TO_MSM(port); 785 786 /* Account for newlines that will get a carriage return added */ 787 for (i = 0; i < count; i++) 788 if (s[i] == '\n') 789 num_newlines++; 790 count += num_newlines; 791 792 spin_lock(&port->lock); 793 if (msm_port->is_uartdm) 794 reset_dm_count(port, count); 795 796 i = 0; 797 while (i < count) { 798 int j; 799 unsigned int num_chars; 800 char buf[4] = { 0 }; 801 unsigned int *bf = (unsigned int *)&buf; 802 803 if (msm_port->is_uartdm) 804 num_chars = min(count - i, (unsigned int)sizeof(buf)); 805 else 806 num_chars = 1; 807 808 for (j = 0; j < num_chars; j++) { 809 char c = *s; 810 811 if (c == '\n' && !replaced) { 812 buf[j] = '\r'; 813 j++; 814 replaced = true; 815 } 816 if (j < num_chars) { 817 buf[j] = c; 818 s++; 819 replaced = false; 820 } 821 } 822 823 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 824 cpu_relax(); 825 826 msm_write(port, *bf, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 827 i += num_chars; 828 } 829 spin_unlock(&port->lock); 830 } 831 832 static int __init msm_console_setup(struct console *co, char *options) 833 { 834 struct uart_port *port; 835 struct msm_port *msm_port; 836 int baud, flow, bits, parity; 837 838 if (unlikely(co->index >= UART_NR || co->index < 0)) 839 return -ENXIO; 840 841 port = get_port_from_line(co->index); 842 msm_port = UART_TO_MSM(port); 843 844 if (unlikely(!port->membase)) 845 return -ENXIO; 846 847 msm_init_clock(port); 848 849 if (options) 850 uart_parse_options(options, &baud, &parity, &bits, &flow); 851 852 bits = 8; 853 parity = 'n'; 854 flow = 'n'; 855 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE, 856 UART_MR2); /* 8N1 */ 857 858 if (baud < 300 || baud > 115200) 859 baud = 115200; 860 msm_set_baud_rate(port, baud); 861 862 msm_reset(port); 863 864 if (msm_port->is_uartdm) { 865 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 866 msm_write(port, UART_CR_TX_ENABLE, UART_CR); 867 } 868 869 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line); 870 871 return uart_set_options(port, co, baud, parity, bits, flow); 872 } 873 874 static struct uart_driver msm_uart_driver; 875 876 static struct console msm_console = { 877 .name = "ttyMSM", 878 .write = msm_console_write, 879 .device = uart_console_device, 880 .setup = msm_console_setup, 881 .flags = CON_PRINTBUFFER, 882 .index = -1, 883 .data = &msm_uart_driver, 884 }; 885 886 #define MSM_CONSOLE (&msm_console) 887 888 #else 889 #define MSM_CONSOLE NULL 890 #endif 891 892 static struct uart_driver msm_uart_driver = { 893 .owner = THIS_MODULE, 894 .driver_name = "msm_serial", 895 .dev_name = "ttyMSM", 896 .nr = UART_NR, 897 .cons = MSM_CONSOLE, 898 }; 899 900 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 901 902 static const struct of_device_id msm_uartdm_table[] = { 903 { .compatible = "qcom,msm-uartdm" }, 904 { } 905 }; 906 907 static int __init msm_serial_probe(struct platform_device *pdev) 908 { 909 struct msm_port *msm_port; 910 struct resource *resource; 911 struct uart_port *port; 912 int irq; 913 914 if (pdev->id == -1) 915 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1; 916 917 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR)) 918 return -ENXIO; 919 920 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id); 921 922 port = get_port_from_line(pdev->id); 923 port->dev = &pdev->dev; 924 msm_port = UART_TO_MSM(port); 925 926 if (of_match_device(msm_uartdm_table, &pdev->dev)) 927 msm_port->is_uartdm = 1; 928 else 929 msm_port->is_uartdm = 0; 930 931 msm_port->clk = devm_clk_get(&pdev->dev, "core"); 932 if (IS_ERR(msm_port->clk)) 933 return PTR_ERR(msm_port->clk); 934 935 if (msm_port->is_uartdm) { 936 msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); 937 if (IS_ERR(msm_port->pclk)) 938 return PTR_ERR(msm_port->pclk); 939 940 clk_set_rate(msm_port->clk, 1843200); 941 } 942 943 port->uartclk = clk_get_rate(msm_port->clk); 944 printk(KERN_INFO "uartclk = %d\n", port->uartclk); 945 946 947 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 948 if (unlikely(!resource)) 949 return -ENXIO; 950 port->mapbase = resource->start; 951 952 irq = platform_get_irq(pdev, 0); 953 if (unlikely(irq < 0)) 954 return -ENXIO; 955 port->irq = irq; 956 957 platform_set_drvdata(pdev, port); 958 959 return uart_add_one_port(&msm_uart_driver, port); 960 } 961 962 static int msm_serial_remove(struct platform_device *pdev) 963 { 964 struct uart_port *port = platform_get_drvdata(pdev); 965 966 uart_remove_one_port(&msm_uart_driver, port); 967 968 return 0; 969 } 970 971 static struct of_device_id msm_match_table[] = { 972 { .compatible = "qcom,msm-uart" }, 973 { .compatible = "qcom,msm-uartdm" }, 974 {} 975 }; 976 977 static struct platform_driver msm_platform_driver = { 978 .remove = msm_serial_remove, 979 .driver = { 980 .name = "msm_serial", 981 .owner = THIS_MODULE, 982 .of_match_table = msm_match_table, 983 }, 984 }; 985 986 static int __init msm_serial_init(void) 987 { 988 int ret; 989 990 ret = uart_register_driver(&msm_uart_driver); 991 if (unlikely(ret)) 992 return ret; 993 994 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe); 995 if (unlikely(ret)) 996 uart_unregister_driver(&msm_uart_driver); 997 998 printk(KERN_INFO "msm_serial: driver initialized\n"); 999 1000 return ret; 1001 } 1002 1003 static void __exit msm_serial_exit(void) 1004 { 1005 #ifdef CONFIG_SERIAL_MSM_CONSOLE 1006 unregister_console(&msm_console); 1007 #endif 1008 platform_driver_unregister(&msm_platform_driver); 1009 uart_unregister_driver(&msm_uart_driver); 1010 } 1011 1012 module_init(msm_serial_init); 1013 module_exit(msm_serial_exit); 1014 1015 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 1016 MODULE_DESCRIPTION("Driver for msm7x serial device"); 1017 MODULE_LICENSE("GPL"); 1018