1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for msm7k serial device and console 4 * 5 * Copyright (C) 2007 Google, Inc. 6 * Author: Robert Love <rlove@google.com> 7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/atomic.h> 12 #include <linux/dma/qcom_adm.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/module.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/interrupt.h> 19 #include <linux/init.h> 20 #include <linux/console.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/clk.h> 26 #include <linux/platform_device.h> 27 #include <linux/delay.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/wait.h> 31 32 #define UART_MR1 0x0000 33 34 #define UART_MR1_AUTO_RFR_LEVEL0 0x3F 35 #define UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 36 #define UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 37 #define UART_MR1_RX_RDY_CTL BIT(7) 38 #define UART_MR1_CTS_CTL BIT(6) 39 40 #define UART_MR2 0x0004 41 #define UART_MR2_ERROR_MODE BIT(6) 42 #define UART_MR2_BITS_PER_CHAR 0x30 43 #define UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) 44 #define UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) 45 #define UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) 46 #define UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) 47 #define UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) 48 #define UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) 49 #define UART_MR2_PARITY_MODE_NONE 0x0 50 #define UART_MR2_PARITY_MODE_ODD 0x1 51 #define UART_MR2_PARITY_MODE_EVEN 0x2 52 #define UART_MR2_PARITY_MODE_SPACE 0x3 53 #define UART_MR2_PARITY_MODE 0x3 54 55 #define UART_CSR 0x0008 56 57 #define UART_TF 0x000C 58 #define UARTDM_TF 0x0070 59 60 #define UART_CR 0x0010 61 #define UART_CR_CMD_NULL (0 << 4) 62 #define UART_CR_CMD_RESET_RX (1 << 4) 63 #define UART_CR_CMD_RESET_TX (2 << 4) 64 #define UART_CR_CMD_RESET_ERR (3 << 4) 65 #define UART_CR_CMD_RESET_BREAK_INT (4 << 4) 66 #define UART_CR_CMD_START_BREAK (5 << 4) 67 #define UART_CR_CMD_STOP_BREAK (6 << 4) 68 #define UART_CR_CMD_RESET_CTS (7 << 4) 69 #define UART_CR_CMD_RESET_STALE_INT (8 << 4) 70 #define UART_CR_CMD_PACKET_MODE (9 << 4) 71 #define UART_CR_CMD_MODE_RESET (12 << 4) 72 #define UART_CR_CMD_SET_RFR (13 << 4) 73 #define UART_CR_CMD_RESET_RFR (14 << 4) 74 #define UART_CR_CMD_PROTECTION_EN (16 << 4) 75 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) 76 #define UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) 77 #define UART_CR_CMD_FORCE_STALE (4 << 8) 78 #define UART_CR_CMD_RESET_TX_READY (3 << 8) 79 #define UART_CR_TX_DISABLE BIT(3) 80 #define UART_CR_TX_ENABLE BIT(2) 81 #define UART_CR_RX_DISABLE BIT(1) 82 #define UART_CR_RX_ENABLE BIT(0) 83 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) 84 85 #define UART_IMR 0x0014 86 #define UART_IMR_TXLEV BIT(0) 87 #define UART_IMR_RXSTALE BIT(3) 88 #define UART_IMR_RXLEV BIT(4) 89 #define UART_IMR_DELTA_CTS BIT(5) 90 #define UART_IMR_CURRENT_CTS BIT(6) 91 #define UART_IMR_RXBREAK_START BIT(10) 92 93 #define UART_IPR_RXSTALE_LAST 0x20 94 #define UART_IPR_STALE_LSB 0x1F 95 #define UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 96 #define UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 97 98 #define UART_IPR 0x0018 99 #define UART_TFWR 0x001C 100 #define UART_RFWR 0x0020 101 #define UART_HCR 0x0024 102 103 #define UART_MREG 0x0028 104 #define UART_NREG 0x002C 105 #define UART_DREG 0x0030 106 #define UART_MNDREG 0x0034 107 #define UART_IRDA 0x0038 108 #define UART_MISR_MODE 0x0040 109 #define UART_MISR_RESET 0x0044 110 #define UART_MISR_EXPORT 0x0048 111 #define UART_MISR_VAL 0x004C 112 #define UART_TEST_CTRL 0x0050 113 114 #define UART_SR 0x0008 115 #define UART_SR_HUNT_CHAR BIT(7) 116 #define UART_SR_RX_BREAK BIT(6) 117 #define UART_SR_PAR_FRAME_ERR BIT(5) 118 #define UART_SR_OVERRUN BIT(4) 119 #define UART_SR_TX_EMPTY BIT(3) 120 #define UART_SR_TX_READY BIT(2) 121 #define UART_SR_RX_FULL BIT(1) 122 #define UART_SR_RX_READY BIT(0) 123 124 #define UART_RF 0x000C 125 #define UARTDM_RF 0x0070 126 #define UART_MISR 0x0010 127 #define UART_ISR 0x0014 128 #define UART_ISR_TX_READY BIT(7) 129 130 #define UARTDM_RXFS 0x50 131 #define UARTDM_RXFS_BUF_SHIFT 0x7 132 #define UARTDM_RXFS_BUF_MASK 0x7 133 134 #define UARTDM_DMEN 0x3C 135 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5) 136 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4) 137 138 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ 139 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ 140 141 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ 142 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ 143 144 #define UARTDM_DMRX 0x34 145 #define UARTDM_NCF_TX 0x40 146 #define UARTDM_RX_TOTAL_SNAP 0x38 147 148 #define UARTDM_BURST_SIZE 16 /* in bytes */ 149 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ 150 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */ 151 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4) 152 153 enum { 154 UARTDM_1P1 = 1, 155 UARTDM_1P2, 156 UARTDM_1P3, 157 UARTDM_1P4, 158 }; 159 160 struct msm_dma { 161 struct dma_chan *chan; 162 enum dma_data_direction dir; 163 dma_addr_t phys; 164 unsigned char *virt; 165 dma_cookie_t cookie; 166 u32 enable_bit; 167 unsigned int count; 168 struct dma_async_tx_descriptor *desc; 169 }; 170 171 struct msm_port { 172 struct uart_port uart; 173 char name[16]; 174 struct clk *clk; 175 struct clk *pclk; 176 unsigned int imr; 177 int is_uartdm; 178 unsigned int old_snap_state; 179 bool break_detected; 180 struct msm_dma tx_dma; 181 struct msm_dma rx_dma; 182 }; 183 184 #define UART_TO_MSM(uart_port) container_of(uart_port, struct msm_port, uart) 185 186 static 187 void msm_write(struct uart_port *port, unsigned int val, unsigned int off) 188 { 189 writel_relaxed(val, port->membase + off); 190 } 191 192 static 193 unsigned int msm_read(struct uart_port *port, unsigned int off) 194 { 195 return readl_relaxed(port->membase + off); 196 } 197 198 /* 199 * Setup the MND registers to use the TCXO clock. 200 */ 201 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) 202 { 203 msm_write(port, 0x06, UART_MREG); 204 msm_write(port, 0xF1, UART_NREG); 205 msm_write(port, 0x0F, UART_DREG); 206 msm_write(port, 0x1A, UART_MNDREG); 207 port->uartclk = 1843200; 208 } 209 210 /* 211 * Setup the MND registers to use the TCXO clock divided by 4. 212 */ 213 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) 214 { 215 msm_write(port, 0x18, UART_MREG); 216 msm_write(port, 0xF6, UART_NREG); 217 msm_write(port, 0x0F, UART_DREG); 218 msm_write(port, 0x0A, UART_MNDREG); 219 port->uartclk = 1843200; 220 } 221 222 static void msm_serial_set_mnd_regs(struct uart_port *port) 223 { 224 struct msm_port *msm_port = UART_TO_MSM(port); 225 226 /* 227 * These registers don't exist so we change the clk input rate 228 * on uartdm hardware instead 229 */ 230 if (msm_port->is_uartdm) 231 return; 232 233 if (port->uartclk == 19200000) 234 msm_serial_set_mnd_regs_tcxo(port); 235 else if (port->uartclk == 4800000) 236 msm_serial_set_mnd_regs_tcxoby4(port); 237 } 238 239 static void msm_handle_tx(struct uart_port *port); 240 static void msm_start_rx_dma(struct msm_port *msm_port); 241 242 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) 243 { 244 struct device *dev = port->dev; 245 unsigned int mapped; 246 u32 val; 247 248 mapped = dma->count; 249 dma->count = 0; 250 251 dmaengine_terminate_all(dma->chan); 252 253 /* 254 * DMA Stall happens if enqueue and flush command happens concurrently. 255 * For example before changing the baud rate/protocol configuration and 256 * sending flush command to ADM, disable the channel of UARTDM. 257 * Note: should not reset the receiver here immediately as it is not 258 * suggested to do disable/reset or reset/disable at the same time. 259 */ 260 val = msm_read(port, UARTDM_DMEN); 261 val &= ~dma->enable_bit; 262 msm_write(port, val, UARTDM_DMEN); 263 264 if (mapped) 265 dma_unmap_single(dev, dma->phys, mapped, dma->dir); 266 } 267 268 static void msm_release_dma(struct msm_port *msm_port) 269 { 270 struct msm_dma *dma; 271 272 dma = &msm_port->tx_dma; 273 if (dma->chan) { 274 msm_stop_dma(&msm_port->uart, dma); 275 dma_release_channel(dma->chan); 276 } 277 278 memset(dma, 0, sizeof(*dma)); 279 280 dma = &msm_port->rx_dma; 281 if (dma->chan) { 282 msm_stop_dma(&msm_port->uart, dma); 283 dma_release_channel(dma->chan); 284 kfree(dma->virt); 285 } 286 287 memset(dma, 0, sizeof(*dma)); 288 } 289 290 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base) 291 { 292 struct device *dev = msm_port->uart.dev; 293 struct dma_slave_config conf; 294 struct qcom_adm_peripheral_config periph_conf = {}; 295 struct msm_dma *dma; 296 u32 crci = 0; 297 int ret; 298 299 dma = &msm_port->tx_dma; 300 301 /* allocate DMA resources, if available */ 302 dma->chan = dma_request_chan(dev, "tx"); 303 if (IS_ERR(dma->chan)) 304 goto no_tx; 305 306 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci); 307 308 memset(&conf, 0, sizeof(conf)); 309 conf.direction = DMA_MEM_TO_DEV; 310 conf.device_fc = true; 311 conf.dst_addr = base + UARTDM_TF; 312 conf.dst_maxburst = UARTDM_BURST_SIZE; 313 if (crci) { 314 conf.peripheral_config = &periph_conf; 315 conf.peripheral_size = sizeof(periph_conf); 316 periph_conf.crci = crci; 317 } 318 319 ret = dmaengine_slave_config(dma->chan, &conf); 320 if (ret) 321 goto rel_tx; 322 323 dma->dir = DMA_TO_DEVICE; 324 325 if (msm_port->is_uartdm < UARTDM_1P4) 326 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; 327 else 328 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; 329 330 return; 331 332 rel_tx: 333 dma_release_channel(dma->chan); 334 no_tx: 335 memset(dma, 0, sizeof(*dma)); 336 } 337 338 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base) 339 { 340 struct device *dev = msm_port->uart.dev; 341 struct dma_slave_config conf; 342 struct qcom_adm_peripheral_config periph_conf = {}; 343 struct msm_dma *dma; 344 u32 crci = 0; 345 int ret; 346 347 dma = &msm_port->rx_dma; 348 349 /* allocate DMA resources, if available */ 350 dma->chan = dma_request_chan(dev, "rx"); 351 if (IS_ERR(dma->chan)) 352 goto no_rx; 353 354 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci); 355 356 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL); 357 if (!dma->virt) 358 goto rel_rx; 359 360 memset(&conf, 0, sizeof(conf)); 361 conf.direction = DMA_DEV_TO_MEM; 362 conf.device_fc = true; 363 conf.src_addr = base + UARTDM_RF; 364 conf.src_maxburst = UARTDM_BURST_SIZE; 365 if (crci) { 366 conf.peripheral_config = &periph_conf; 367 conf.peripheral_size = sizeof(periph_conf); 368 periph_conf.crci = crci; 369 } 370 371 ret = dmaengine_slave_config(dma->chan, &conf); 372 if (ret) 373 goto err; 374 375 dma->dir = DMA_FROM_DEVICE; 376 377 if (msm_port->is_uartdm < UARTDM_1P4) 378 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; 379 else 380 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; 381 382 return; 383 err: 384 kfree(dma->virt); 385 rel_rx: 386 dma_release_channel(dma->chan); 387 no_rx: 388 memset(dma, 0, sizeof(*dma)); 389 } 390 391 static inline void msm_wait_for_xmitr(struct uart_port *port) 392 { 393 unsigned int timeout = 500000; 394 395 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) { 396 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY) 397 break; 398 udelay(1); 399 if (!timeout--) 400 break; 401 } 402 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); 403 } 404 405 static void msm_stop_tx(struct uart_port *port) 406 { 407 struct msm_port *msm_port = UART_TO_MSM(port); 408 409 msm_port->imr &= ~UART_IMR_TXLEV; 410 msm_write(port, msm_port->imr, UART_IMR); 411 } 412 413 static void msm_start_tx(struct uart_port *port) 414 { 415 struct msm_port *msm_port = UART_TO_MSM(port); 416 struct msm_dma *dma = &msm_port->tx_dma; 417 418 /* Already started in DMA mode */ 419 if (dma->count) 420 return; 421 422 msm_port->imr |= UART_IMR_TXLEV; 423 msm_write(port, msm_port->imr, UART_IMR); 424 } 425 426 static void msm_reset_dm_count(struct uart_port *port, int count) 427 { 428 msm_wait_for_xmitr(port); 429 msm_write(port, count, UARTDM_NCF_TX); 430 msm_read(port, UARTDM_NCF_TX); 431 } 432 433 static void msm_complete_tx_dma(void *args) 434 { 435 struct msm_port *msm_port = args; 436 struct uart_port *port = &msm_port->uart; 437 struct circ_buf *xmit = &port->state->xmit; 438 struct msm_dma *dma = &msm_port->tx_dma; 439 struct dma_tx_state state; 440 unsigned long flags; 441 unsigned int count; 442 u32 val; 443 444 spin_lock_irqsave(&port->lock, flags); 445 446 /* Already stopped */ 447 if (!dma->count) 448 goto done; 449 450 dmaengine_tx_status(dma->chan, dma->cookie, &state); 451 452 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir); 453 454 val = msm_read(port, UARTDM_DMEN); 455 val &= ~dma->enable_bit; 456 msm_write(port, val, UARTDM_DMEN); 457 458 if (msm_port->is_uartdm > UARTDM_1P3) { 459 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 460 msm_write(port, UART_CR_TX_ENABLE, UART_CR); 461 } 462 463 count = dma->count - state.residue; 464 port->icount.tx += count; 465 dma->count = 0; 466 467 xmit->tail += count; 468 xmit->tail &= UART_XMIT_SIZE - 1; 469 470 /* Restore "Tx FIFO below watermark" interrupt */ 471 msm_port->imr |= UART_IMR_TXLEV; 472 msm_write(port, msm_port->imr, UART_IMR); 473 474 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 475 uart_write_wakeup(port); 476 477 msm_handle_tx(port); 478 done: 479 spin_unlock_irqrestore(&port->lock, flags); 480 } 481 482 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count) 483 { 484 struct circ_buf *xmit = &msm_port->uart.state->xmit; 485 struct uart_port *port = &msm_port->uart; 486 struct msm_dma *dma = &msm_port->tx_dma; 487 void *cpu_addr; 488 int ret; 489 u32 val; 490 491 cpu_addr = &xmit->buf[xmit->tail]; 492 493 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir); 494 ret = dma_mapping_error(port->dev, dma->phys); 495 if (ret) 496 return ret; 497 498 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 499 count, DMA_MEM_TO_DEV, 500 DMA_PREP_INTERRUPT | 501 DMA_PREP_FENCE); 502 if (!dma->desc) { 503 ret = -EIO; 504 goto unmap; 505 } 506 507 dma->desc->callback = msm_complete_tx_dma; 508 dma->desc->callback_param = msm_port; 509 510 dma->cookie = dmaengine_submit(dma->desc); 511 ret = dma_submit_error(dma->cookie); 512 if (ret) 513 goto unmap; 514 515 /* 516 * Using DMA complete for Tx FIFO reload, no need for 517 * "Tx FIFO below watermark" one, disable it 518 */ 519 msm_port->imr &= ~UART_IMR_TXLEV; 520 msm_write(port, msm_port->imr, UART_IMR); 521 522 dma->count = count; 523 524 val = msm_read(port, UARTDM_DMEN); 525 val |= dma->enable_bit; 526 527 if (msm_port->is_uartdm < UARTDM_1P4) 528 msm_write(port, val, UARTDM_DMEN); 529 530 msm_reset_dm_count(port, count); 531 532 if (msm_port->is_uartdm > UARTDM_1P3) 533 msm_write(port, val, UARTDM_DMEN); 534 535 dma_async_issue_pending(dma->chan); 536 return 0; 537 unmap: 538 dma_unmap_single(port->dev, dma->phys, count, dma->dir); 539 return ret; 540 } 541 542 static void msm_complete_rx_dma(void *args) 543 { 544 struct msm_port *msm_port = args; 545 struct uart_port *port = &msm_port->uart; 546 struct tty_port *tport = &port->state->port; 547 struct msm_dma *dma = &msm_port->rx_dma; 548 int count = 0, i, sysrq; 549 unsigned long flags; 550 u32 val; 551 552 spin_lock_irqsave(&port->lock, flags); 553 554 /* Already stopped */ 555 if (!dma->count) 556 goto done; 557 558 val = msm_read(port, UARTDM_DMEN); 559 val &= ~dma->enable_bit; 560 msm_write(port, val, UARTDM_DMEN); 561 562 if (msm_read(port, UART_SR) & UART_SR_OVERRUN) { 563 port->icount.overrun++; 564 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 565 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 566 } 567 568 count = msm_read(port, UARTDM_RX_TOTAL_SNAP); 569 570 port->icount.rx += count; 571 572 dma->count = 0; 573 574 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 575 576 for (i = 0; i < count; i++) { 577 char flag = TTY_NORMAL; 578 579 if (msm_port->break_detected && dma->virt[i] == 0) { 580 port->icount.brk++; 581 flag = TTY_BREAK; 582 msm_port->break_detected = false; 583 if (uart_handle_break(port)) 584 continue; 585 } 586 587 if (!(port->read_status_mask & UART_SR_RX_BREAK)) 588 flag = TTY_NORMAL; 589 590 spin_unlock_irqrestore(&port->lock, flags); 591 sysrq = uart_handle_sysrq_char(port, dma->virt[i]); 592 spin_lock_irqsave(&port->lock, flags); 593 if (!sysrq) 594 tty_insert_flip_char(tport, dma->virt[i], flag); 595 } 596 597 msm_start_rx_dma(msm_port); 598 done: 599 spin_unlock_irqrestore(&port->lock, flags); 600 601 if (count) 602 tty_flip_buffer_push(tport); 603 } 604 605 static void msm_start_rx_dma(struct msm_port *msm_port) 606 { 607 struct msm_dma *dma = &msm_port->rx_dma; 608 struct uart_port *uart = &msm_port->uart; 609 u32 val; 610 int ret; 611 612 if (!dma->chan) 613 return; 614 615 dma->phys = dma_map_single(uart->dev, dma->virt, 616 UARTDM_RX_SIZE, dma->dir); 617 ret = dma_mapping_error(uart->dev, dma->phys); 618 if (ret) 619 goto sw_mode; 620 621 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 622 UARTDM_RX_SIZE, DMA_DEV_TO_MEM, 623 DMA_PREP_INTERRUPT); 624 if (!dma->desc) 625 goto unmap; 626 627 dma->desc->callback = msm_complete_rx_dma; 628 dma->desc->callback_param = msm_port; 629 630 dma->cookie = dmaengine_submit(dma->desc); 631 ret = dma_submit_error(dma->cookie); 632 if (ret) 633 goto unmap; 634 /* 635 * Using DMA for FIFO off-load, no need for "Rx FIFO over 636 * watermark" or "stale" interrupts, disable them 637 */ 638 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 639 640 /* 641 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3), 642 * we need RXSTALE to flush input DMA fifo to memory 643 */ 644 if (msm_port->is_uartdm < UARTDM_1P4) 645 msm_port->imr |= UART_IMR_RXSTALE; 646 647 msm_write(uart, msm_port->imr, UART_IMR); 648 649 dma->count = UARTDM_RX_SIZE; 650 651 dma_async_issue_pending(dma->chan); 652 653 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); 654 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 655 656 val = msm_read(uart, UARTDM_DMEN); 657 val |= dma->enable_bit; 658 659 if (msm_port->is_uartdm < UARTDM_1P4) 660 msm_write(uart, val, UARTDM_DMEN); 661 662 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX); 663 664 if (msm_port->is_uartdm > UARTDM_1P3) 665 msm_write(uart, val, UARTDM_DMEN); 666 667 return; 668 unmap: 669 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 670 671 sw_mode: 672 /* 673 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN), 674 * receiver must be reset. 675 */ 676 msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR); 677 msm_write(uart, UART_CR_RX_ENABLE, UART_CR); 678 679 msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR); 680 msm_write(uart, 0xFFFFFF, UARTDM_DMRX); 681 msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 682 683 /* Re-enable RX interrupts */ 684 msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE); 685 msm_write(uart, msm_port->imr, UART_IMR); 686 } 687 688 static void msm_stop_rx(struct uart_port *port) 689 { 690 struct msm_port *msm_port = UART_TO_MSM(port); 691 struct msm_dma *dma = &msm_port->rx_dma; 692 693 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 694 msm_write(port, msm_port->imr, UART_IMR); 695 696 if (dma->chan) 697 msm_stop_dma(port, dma); 698 } 699 700 static void msm_enable_ms(struct uart_port *port) 701 { 702 struct msm_port *msm_port = UART_TO_MSM(port); 703 704 msm_port->imr |= UART_IMR_DELTA_CTS; 705 msm_write(port, msm_port->imr, UART_IMR); 706 } 707 708 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr) 709 __must_hold(&port->lock) 710 { 711 struct tty_port *tport = &port->state->port; 712 unsigned int sr; 713 int count = 0; 714 struct msm_port *msm_port = UART_TO_MSM(port); 715 716 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 717 port->icount.overrun++; 718 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 719 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 720 } 721 722 if (misr & UART_IMR_RXSTALE) { 723 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 724 msm_port->old_snap_state; 725 msm_port->old_snap_state = 0; 726 } else { 727 count = 4 * (msm_read(port, UART_RFWR)); 728 msm_port->old_snap_state += count; 729 } 730 731 /* TODO: Precise error reporting */ 732 733 port->icount.rx += count; 734 735 while (count > 0) { 736 unsigned char buf[4]; 737 int sysrq, r_count, i; 738 739 sr = msm_read(port, UART_SR); 740 if ((sr & UART_SR_RX_READY) == 0) { 741 msm_port->old_snap_state -= count; 742 break; 743 } 744 745 ioread32_rep(port->membase + UARTDM_RF, buf, 1); 746 r_count = min_t(int, count, sizeof(buf)); 747 748 for (i = 0; i < r_count; i++) { 749 char flag = TTY_NORMAL; 750 751 if (msm_port->break_detected && buf[i] == 0) { 752 port->icount.brk++; 753 flag = TTY_BREAK; 754 msm_port->break_detected = false; 755 if (uart_handle_break(port)) 756 continue; 757 } 758 759 if (!(port->read_status_mask & UART_SR_RX_BREAK)) 760 flag = TTY_NORMAL; 761 762 spin_unlock(&port->lock); 763 sysrq = uart_handle_sysrq_char(port, buf[i]); 764 spin_lock(&port->lock); 765 if (!sysrq) 766 tty_insert_flip_char(tport, buf[i], flag); 767 } 768 count -= r_count; 769 } 770 771 tty_flip_buffer_push(tport); 772 773 if (misr & (UART_IMR_RXSTALE)) 774 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 775 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 776 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 777 778 /* Try to use DMA */ 779 msm_start_rx_dma(msm_port); 780 } 781 782 static void msm_handle_rx(struct uart_port *port) 783 __must_hold(&port->lock) 784 { 785 struct tty_port *tport = &port->state->port; 786 unsigned int sr; 787 788 /* 789 * Handle overrun. My understanding of the hardware is that overrun 790 * is not tied to the RX buffer, so we handle the case out of band. 791 */ 792 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 793 port->icount.overrun++; 794 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 795 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 796 } 797 798 /* and now the main RX loop */ 799 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 800 unsigned int c; 801 char flag = TTY_NORMAL; 802 int sysrq; 803 804 c = msm_read(port, UART_RF); 805 806 if (sr & UART_SR_RX_BREAK) { 807 port->icount.brk++; 808 if (uart_handle_break(port)) 809 continue; 810 } else if (sr & UART_SR_PAR_FRAME_ERR) { 811 port->icount.frame++; 812 } else { 813 port->icount.rx++; 814 } 815 816 /* Mask conditions we're ignorning. */ 817 sr &= port->read_status_mask; 818 819 if (sr & UART_SR_RX_BREAK) 820 flag = TTY_BREAK; 821 else if (sr & UART_SR_PAR_FRAME_ERR) 822 flag = TTY_FRAME; 823 824 spin_unlock(&port->lock); 825 sysrq = uart_handle_sysrq_char(port, c); 826 spin_lock(&port->lock); 827 if (!sysrq) 828 tty_insert_flip_char(tport, c, flag); 829 } 830 831 tty_flip_buffer_push(tport); 832 } 833 834 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count) 835 { 836 struct circ_buf *xmit = &port->state->xmit; 837 struct msm_port *msm_port = UART_TO_MSM(port); 838 unsigned int num_chars; 839 unsigned int tf_pointer = 0; 840 void __iomem *tf; 841 842 if (msm_port->is_uartdm) 843 tf = port->membase + UARTDM_TF; 844 else 845 tf = port->membase + UART_TF; 846 847 if (tx_count && msm_port->is_uartdm) 848 msm_reset_dm_count(port, tx_count); 849 850 while (tf_pointer < tx_count) { 851 int i; 852 char buf[4] = { 0 }; 853 854 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 855 break; 856 857 if (msm_port->is_uartdm) 858 num_chars = min(tx_count - tf_pointer, 859 (unsigned int)sizeof(buf)); 860 else 861 num_chars = 1; 862 863 for (i = 0; i < num_chars; i++) { 864 buf[i] = xmit->buf[xmit->tail + i]; 865 port->icount.tx++; 866 } 867 868 iowrite32_rep(tf, buf, 1); 869 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); 870 tf_pointer += num_chars; 871 } 872 873 /* disable tx interrupts if nothing more to send */ 874 if (uart_circ_empty(xmit)) 875 msm_stop_tx(port); 876 877 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 878 uart_write_wakeup(port); 879 } 880 881 static void msm_handle_tx(struct uart_port *port) 882 { 883 struct msm_port *msm_port = UART_TO_MSM(port); 884 struct circ_buf *xmit = &msm_port->uart.state->xmit; 885 struct msm_dma *dma = &msm_port->tx_dma; 886 unsigned int pio_count, dma_count, dma_min; 887 char buf[4] = { 0 }; 888 void __iomem *tf; 889 int err = 0; 890 891 if (port->x_char) { 892 if (msm_port->is_uartdm) 893 tf = port->membase + UARTDM_TF; 894 else 895 tf = port->membase + UART_TF; 896 897 buf[0] = port->x_char; 898 899 if (msm_port->is_uartdm) 900 msm_reset_dm_count(port, 1); 901 902 iowrite32_rep(tf, buf, 1); 903 port->icount.tx++; 904 port->x_char = 0; 905 return; 906 } 907 908 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 909 msm_stop_tx(port); 910 return; 911 } 912 913 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 914 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 915 916 dma_min = 1; /* Always DMA */ 917 if (msm_port->is_uartdm > UARTDM_1P3) { 918 dma_count = UARTDM_TX_AIGN(dma_count); 919 dma_min = UARTDM_BURST_SIZE; 920 } else { 921 if (dma_count > UARTDM_TX_MAX) 922 dma_count = UARTDM_TX_MAX; 923 } 924 925 if (pio_count > port->fifosize) 926 pio_count = port->fifosize; 927 928 if (!dma->chan || dma_count < dma_min) 929 msm_handle_tx_pio(port, pio_count); 930 else 931 err = msm_handle_tx_dma(msm_port, dma_count); 932 933 if (err) /* fall back to PIO mode */ 934 msm_handle_tx_pio(port, pio_count); 935 } 936 937 static void msm_handle_delta_cts(struct uart_port *port) 938 { 939 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 940 port->icount.cts++; 941 wake_up_interruptible(&port->state->port.delta_msr_wait); 942 } 943 944 static irqreturn_t msm_uart_irq(int irq, void *dev_id) 945 { 946 struct uart_port *port = dev_id; 947 struct msm_port *msm_port = UART_TO_MSM(port); 948 struct msm_dma *dma = &msm_port->rx_dma; 949 unsigned long flags; 950 unsigned int misr; 951 u32 val; 952 953 spin_lock_irqsave(&port->lock, flags); 954 misr = msm_read(port, UART_MISR); 955 msm_write(port, 0, UART_IMR); /* disable interrupt */ 956 957 if (misr & UART_IMR_RXBREAK_START) { 958 msm_port->break_detected = true; 959 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR); 960 } 961 962 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 963 if (dma->count) { 964 val = UART_CR_CMD_STALE_EVENT_DISABLE; 965 msm_write(port, val, UART_CR); 966 val = UART_CR_CMD_RESET_STALE_INT; 967 msm_write(port, val, UART_CR); 968 /* 969 * Flush DMA input fifo to memory, this will also 970 * trigger DMA RX completion 971 */ 972 dmaengine_terminate_all(dma->chan); 973 } else if (msm_port->is_uartdm) { 974 msm_handle_rx_dm(port, misr); 975 } else { 976 msm_handle_rx(port); 977 } 978 } 979 if (misr & UART_IMR_TXLEV) 980 msm_handle_tx(port); 981 if (misr & UART_IMR_DELTA_CTS) 982 msm_handle_delta_cts(port); 983 984 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 985 spin_unlock_irqrestore(&port->lock, flags); 986 987 return IRQ_HANDLED; 988 } 989 990 static unsigned int msm_tx_empty(struct uart_port *port) 991 { 992 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 993 } 994 995 static unsigned int msm_get_mctrl(struct uart_port *port) 996 { 997 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 998 } 999 1000 static void msm_reset(struct uart_port *port) 1001 { 1002 struct msm_port *msm_port = UART_TO_MSM(port); 1003 unsigned int mr; 1004 1005 /* reset everything */ 1006 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 1007 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 1008 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 1009 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 1010 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 1011 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 1012 mr = msm_read(port, UART_MR1); 1013 mr &= ~UART_MR1_RX_RDY_CTL; 1014 msm_write(port, mr, UART_MR1); 1015 1016 /* Disable DM modes */ 1017 if (msm_port->is_uartdm) 1018 msm_write(port, 0, UARTDM_DMEN); 1019 } 1020 1021 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 1022 { 1023 unsigned int mr; 1024 1025 mr = msm_read(port, UART_MR1); 1026 1027 if (!(mctrl & TIOCM_RTS)) { 1028 mr &= ~UART_MR1_RX_RDY_CTL; 1029 msm_write(port, mr, UART_MR1); 1030 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 1031 } else { 1032 mr |= UART_MR1_RX_RDY_CTL; 1033 msm_write(port, mr, UART_MR1); 1034 } 1035 } 1036 1037 static void msm_break_ctl(struct uart_port *port, int break_ctl) 1038 { 1039 if (break_ctl) 1040 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 1041 else 1042 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 1043 } 1044 1045 struct msm_baud_map { 1046 u16 divisor; 1047 u8 code; 1048 u8 rxstale; 1049 }; 1050 1051 static const struct msm_baud_map * 1052 msm_find_best_baud(struct uart_port *port, unsigned int baud, 1053 unsigned long *rate) 1054 { 1055 struct msm_port *msm_port = UART_TO_MSM(port); 1056 unsigned int divisor, result; 1057 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX; 1058 const struct msm_baud_map *entry, *end, *best; 1059 static const struct msm_baud_map table[] = { 1060 { 1, 0xff, 31 }, 1061 { 2, 0xee, 16 }, 1062 { 3, 0xdd, 8 }, 1063 { 4, 0xcc, 6 }, 1064 { 6, 0xbb, 6 }, 1065 { 8, 0xaa, 6 }, 1066 { 12, 0x99, 6 }, 1067 { 16, 0x88, 1 }, 1068 { 24, 0x77, 1 }, 1069 { 32, 0x66, 1 }, 1070 { 48, 0x55, 1 }, 1071 { 96, 0x44, 1 }, 1072 { 192, 0x33, 1 }, 1073 { 384, 0x22, 1 }, 1074 { 768, 0x11, 1 }, 1075 { 1536, 0x00, 1 }, 1076 }; 1077 1078 best = table; /* Default to smallest divider */ 1079 target = clk_round_rate(msm_port->clk, 16 * baud); 1080 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1081 1082 end = table + ARRAY_SIZE(table); 1083 entry = table; 1084 while (entry < end) { 1085 if (entry->divisor <= divisor) { 1086 result = target / entry->divisor / 16; 1087 diff = abs(result - baud); 1088 1089 /* Keep track of best entry */ 1090 if (diff < best_diff) { 1091 best_diff = diff; 1092 best = entry; 1093 best_rate = target; 1094 } 1095 1096 if (result == baud) 1097 break; 1098 } else if (entry->divisor > divisor) { 1099 old = target; 1100 target = clk_round_rate(msm_port->clk, old + 1); 1101 /* 1102 * The rate didn't get any faster so we can't do 1103 * better at dividing it down 1104 */ 1105 if (target == old) 1106 break; 1107 1108 /* Start the divisor search over at this new rate */ 1109 entry = table; 1110 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1111 continue; 1112 } 1113 entry++; 1114 } 1115 1116 *rate = best_rate; 1117 return best; 1118 } 1119 1120 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, 1121 unsigned long *saved_flags) 1122 { 1123 unsigned int rxstale, watermark, mask; 1124 struct msm_port *msm_port = UART_TO_MSM(port); 1125 const struct msm_baud_map *entry; 1126 unsigned long flags, rate; 1127 1128 flags = *saved_flags; 1129 spin_unlock_irqrestore(&port->lock, flags); 1130 1131 entry = msm_find_best_baud(port, baud, &rate); 1132 clk_set_rate(msm_port->clk, rate); 1133 baud = rate / 16 / entry->divisor; 1134 1135 spin_lock_irqsave(&port->lock, flags); 1136 *saved_flags = flags; 1137 port->uartclk = rate; 1138 1139 msm_write(port, entry->code, UART_CSR); 1140 1141 /* RX stale watermark */ 1142 rxstale = entry->rxstale; 1143 watermark = UART_IPR_STALE_LSB & rxstale; 1144 if (msm_port->is_uartdm) { 1145 mask = UART_DM_IPR_STALE_TIMEOUT_MSB; 1146 } else { 1147 watermark |= UART_IPR_RXSTALE_LAST; 1148 mask = UART_IPR_STALE_TIMEOUT_MSB; 1149 } 1150 1151 watermark |= mask & (rxstale << 2); 1152 1153 msm_write(port, watermark, UART_IPR); 1154 1155 /* set RX watermark */ 1156 watermark = (port->fifosize * 3) / 4; 1157 msm_write(port, watermark, UART_RFWR); 1158 1159 /* set TX watermark */ 1160 msm_write(port, 10, UART_TFWR); 1161 1162 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 1163 msm_reset(port); 1164 1165 /* Enable RX and TX */ 1166 msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR); 1167 1168 /* turn on RX and CTS interrupts */ 1169 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 1170 UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START; 1171 1172 msm_write(port, msm_port->imr, UART_IMR); 1173 1174 if (msm_port->is_uartdm) { 1175 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 1176 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1177 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 1178 } 1179 1180 return baud; 1181 } 1182 1183 static void msm_init_clock(struct uart_port *port) 1184 { 1185 struct msm_port *msm_port = UART_TO_MSM(port); 1186 1187 clk_prepare_enable(msm_port->clk); 1188 clk_prepare_enable(msm_port->pclk); 1189 msm_serial_set_mnd_regs(port); 1190 } 1191 1192 static int msm_startup(struct uart_port *port) 1193 { 1194 struct msm_port *msm_port = UART_TO_MSM(port); 1195 unsigned int data, rfr_level, mask; 1196 int ret; 1197 1198 snprintf(msm_port->name, sizeof(msm_port->name), 1199 "msm_serial%d", port->line); 1200 1201 msm_init_clock(port); 1202 1203 if (likely(port->fifosize > 12)) 1204 rfr_level = port->fifosize - 12; 1205 else 1206 rfr_level = port->fifosize; 1207 1208 /* set automatic RFR level */ 1209 data = msm_read(port, UART_MR1); 1210 1211 if (msm_port->is_uartdm) 1212 mask = UART_DM_MR1_AUTO_RFR_LEVEL1; 1213 else 1214 mask = UART_MR1_AUTO_RFR_LEVEL1; 1215 1216 data &= ~mask; 1217 data &= ~UART_MR1_AUTO_RFR_LEVEL0; 1218 data |= mask & (rfr_level << 2); 1219 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 1220 msm_write(port, data, UART_MR1); 1221 1222 if (msm_port->is_uartdm) { 1223 msm_request_tx_dma(msm_port, msm_port->uart.mapbase); 1224 msm_request_rx_dma(msm_port, msm_port->uart.mapbase); 1225 } 1226 1227 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, 1228 msm_port->name, port); 1229 if (unlikely(ret)) 1230 goto err_irq; 1231 1232 return 0; 1233 1234 err_irq: 1235 if (msm_port->is_uartdm) 1236 msm_release_dma(msm_port); 1237 1238 clk_disable_unprepare(msm_port->pclk); 1239 clk_disable_unprepare(msm_port->clk); 1240 1241 return ret; 1242 } 1243 1244 static void msm_shutdown(struct uart_port *port) 1245 { 1246 struct msm_port *msm_port = UART_TO_MSM(port); 1247 1248 msm_port->imr = 0; 1249 msm_write(port, 0, UART_IMR); /* disable interrupts */ 1250 1251 if (msm_port->is_uartdm) 1252 msm_release_dma(msm_port); 1253 1254 clk_disable_unprepare(msm_port->clk); 1255 1256 free_irq(port->irq, port); 1257 } 1258 1259 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 1260 struct ktermios *old) 1261 { 1262 struct msm_port *msm_port = UART_TO_MSM(port); 1263 struct msm_dma *dma = &msm_port->rx_dma; 1264 unsigned long flags; 1265 unsigned int baud, mr; 1266 1267 spin_lock_irqsave(&port->lock, flags); 1268 1269 if (dma->chan) /* Terminate if any */ 1270 msm_stop_dma(port, dma); 1271 1272 /* calculate and set baud rate */ 1273 baud = uart_get_baud_rate(port, termios, old, 300, 4000000); 1274 baud = msm_set_baud_rate(port, baud, &flags); 1275 if (tty_termios_baud_rate(termios)) 1276 tty_termios_encode_baud_rate(termios, baud, baud); 1277 1278 /* calculate parity */ 1279 mr = msm_read(port, UART_MR2); 1280 mr &= ~UART_MR2_PARITY_MODE; 1281 if (termios->c_cflag & PARENB) { 1282 if (termios->c_cflag & PARODD) 1283 mr |= UART_MR2_PARITY_MODE_ODD; 1284 else if (termios->c_cflag & CMSPAR) 1285 mr |= UART_MR2_PARITY_MODE_SPACE; 1286 else 1287 mr |= UART_MR2_PARITY_MODE_EVEN; 1288 } 1289 1290 /* calculate bits per char */ 1291 mr &= ~UART_MR2_BITS_PER_CHAR; 1292 switch (termios->c_cflag & CSIZE) { 1293 case CS5: 1294 mr |= UART_MR2_BITS_PER_CHAR_5; 1295 break; 1296 case CS6: 1297 mr |= UART_MR2_BITS_PER_CHAR_6; 1298 break; 1299 case CS7: 1300 mr |= UART_MR2_BITS_PER_CHAR_7; 1301 break; 1302 case CS8: 1303 default: 1304 mr |= UART_MR2_BITS_PER_CHAR_8; 1305 break; 1306 } 1307 1308 /* calculate stop bits */ 1309 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 1310 if (termios->c_cflag & CSTOPB) 1311 mr |= UART_MR2_STOP_BIT_LEN_TWO; 1312 else 1313 mr |= UART_MR2_STOP_BIT_LEN_ONE; 1314 1315 /* set parity, bits per char, and stop bit */ 1316 msm_write(port, mr, UART_MR2); 1317 1318 /* calculate and set hardware flow control */ 1319 mr = msm_read(port, UART_MR1); 1320 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 1321 if (termios->c_cflag & CRTSCTS) { 1322 mr |= UART_MR1_CTS_CTL; 1323 mr |= UART_MR1_RX_RDY_CTL; 1324 } 1325 msm_write(port, mr, UART_MR1); 1326 1327 /* Configure status bits to ignore based on termio flags. */ 1328 port->read_status_mask = 0; 1329 if (termios->c_iflag & INPCK) 1330 port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 1331 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1332 port->read_status_mask |= UART_SR_RX_BREAK; 1333 1334 uart_update_timeout(port, termios->c_cflag, baud); 1335 1336 /* Try to use DMA */ 1337 msm_start_rx_dma(msm_port); 1338 1339 spin_unlock_irqrestore(&port->lock, flags); 1340 } 1341 1342 static const char *msm_type(struct uart_port *port) 1343 { 1344 return "MSM"; 1345 } 1346 1347 static void msm_release_port(struct uart_port *port) 1348 { 1349 struct platform_device *pdev = to_platform_device(port->dev); 1350 struct resource *uart_resource; 1351 resource_size_t size; 1352 1353 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1354 if (unlikely(!uart_resource)) 1355 return; 1356 size = resource_size(uart_resource); 1357 1358 release_mem_region(port->mapbase, size); 1359 iounmap(port->membase); 1360 port->membase = NULL; 1361 } 1362 1363 static int msm_request_port(struct uart_port *port) 1364 { 1365 struct platform_device *pdev = to_platform_device(port->dev); 1366 struct resource *uart_resource; 1367 resource_size_t size; 1368 int ret; 1369 1370 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1371 if (unlikely(!uart_resource)) 1372 return -ENXIO; 1373 1374 size = resource_size(uart_resource); 1375 1376 if (!request_mem_region(port->mapbase, size, "msm_serial")) 1377 return -EBUSY; 1378 1379 port->membase = ioremap(port->mapbase, size); 1380 if (!port->membase) { 1381 ret = -EBUSY; 1382 goto fail_release_port; 1383 } 1384 1385 return 0; 1386 1387 fail_release_port: 1388 release_mem_region(port->mapbase, size); 1389 return ret; 1390 } 1391 1392 static void msm_config_port(struct uart_port *port, int flags) 1393 { 1394 int ret; 1395 1396 if (flags & UART_CONFIG_TYPE) { 1397 port->type = PORT_MSM; 1398 ret = msm_request_port(port); 1399 if (ret) 1400 return; 1401 } 1402 } 1403 1404 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 1405 { 1406 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 1407 return -EINVAL; 1408 if (unlikely(port->irq != ser->irq)) 1409 return -EINVAL; 1410 return 0; 1411 } 1412 1413 static void msm_power(struct uart_port *port, unsigned int state, 1414 unsigned int oldstate) 1415 { 1416 struct msm_port *msm_port = UART_TO_MSM(port); 1417 1418 switch (state) { 1419 case 0: 1420 clk_prepare_enable(msm_port->clk); 1421 clk_prepare_enable(msm_port->pclk); 1422 break; 1423 case 3: 1424 clk_disable_unprepare(msm_port->clk); 1425 clk_disable_unprepare(msm_port->pclk); 1426 break; 1427 default: 1428 pr_err("msm_serial: Unknown PM state %d\n", state); 1429 } 1430 } 1431 1432 #ifdef CONFIG_CONSOLE_POLL 1433 static int msm_poll_get_char_single(struct uart_port *port) 1434 { 1435 struct msm_port *msm_port = UART_TO_MSM(port); 1436 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF; 1437 1438 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) 1439 return NO_POLL_CHAR; 1440 1441 return msm_read(port, rf_reg) & 0xff; 1442 } 1443 1444 static int msm_poll_get_char_dm(struct uart_port *port) 1445 { 1446 int c; 1447 static u32 slop; 1448 static int count; 1449 unsigned char *sp = (unsigned char *)&slop; 1450 1451 /* Check if a previous read had more than one char */ 1452 if (count) { 1453 c = sp[sizeof(slop) - count]; 1454 count--; 1455 /* Or if FIFO is empty */ 1456 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) { 1457 /* 1458 * If RX packing buffer has less than a word, force stale to 1459 * push contents into RX FIFO 1460 */ 1461 count = msm_read(port, UARTDM_RXFS); 1462 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; 1463 if (count) { 1464 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR); 1465 slop = msm_read(port, UARTDM_RF); 1466 c = sp[0]; 1467 count--; 1468 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 1469 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1470 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, 1471 UART_CR); 1472 } else { 1473 c = NO_POLL_CHAR; 1474 } 1475 /* FIFO has a word */ 1476 } else { 1477 slop = msm_read(port, UARTDM_RF); 1478 c = sp[0]; 1479 count = sizeof(slop) - 1; 1480 } 1481 1482 return c; 1483 } 1484 1485 static int msm_poll_get_char(struct uart_port *port) 1486 { 1487 u32 imr; 1488 int c; 1489 struct msm_port *msm_port = UART_TO_MSM(port); 1490 1491 /* Disable all interrupts */ 1492 imr = msm_read(port, UART_IMR); 1493 msm_write(port, 0, UART_IMR); 1494 1495 if (msm_port->is_uartdm) 1496 c = msm_poll_get_char_dm(port); 1497 else 1498 c = msm_poll_get_char_single(port); 1499 1500 /* Enable interrupts */ 1501 msm_write(port, imr, UART_IMR); 1502 1503 return c; 1504 } 1505 1506 static void msm_poll_put_char(struct uart_port *port, unsigned char c) 1507 { 1508 u32 imr; 1509 struct msm_port *msm_port = UART_TO_MSM(port); 1510 1511 /* Disable all interrupts */ 1512 imr = msm_read(port, UART_IMR); 1513 msm_write(port, 0, UART_IMR); 1514 1515 if (msm_port->is_uartdm) 1516 msm_reset_dm_count(port, 1); 1517 1518 /* Wait until FIFO is empty */ 1519 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1520 cpu_relax(); 1521 1522 /* Write a character */ 1523 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 1524 1525 /* Wait until FIFO is empty */ 1526 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1527 cpu_relax(); 1528 1529 /* Enable interrupts */ 1530 msm_write(port, imr, UART_IMR); 1531 } 1532 #endif 1533 1534 static const struct uart_ops msm_uart_pops = { 1535 .tx_empty = msm_tx_empty, 1536 .set_mctrl = msm_set_mctrl, 1537 .get_mctrl = msm_get_mctrl, 1538 .stop_tx = msm_stop_tx, 1539 .start_tx = msm_start_tx, 1540 .stop_rx = msm_stop_rx, 1541 .enable_ms = msm_enable_ms, 1542 .break_ctl = msm_break_ctl, 1543 .startup = msm_startup, 1544 .shutdown = msm_shutdown, 1545 .set_termios = msm_set_termios, 1546 .type = msm_type, 1547 .release_port = msm_release_port, 1548 .request_port = msm_request_port, 1549 .config_port = msm_config_port, 1550 .verify_port = msm_verify_port, 1551 .pm = msm_power, 1552 #ifdef CONFIG_CONSOLE_POLL 1553 .poll_get_char = msm_poll_get_char, 1554 .poll_put_char = msm_poll_put_char, 1555 #endif 1556 }; 1557 1558 static struct msm_port msm_uart_ports[] = { 1559 { 1560 .uart = { 1561 .iotype = UPIO_MEM, 1562 .ops = &msm_uart_pops, 1563 .flags = UPF_BOOT_AUTOCONF, 1564 .fifosize = 64, 1565 .line = 0, 1566 }, 1567 }, 1568 { 1569 .uart = { 1570 .iotype = UPIO_MEM, 1571 .ops = &msm_uart_pops, 1572 .flags = UPF_BOOT_AUTOCONF, 1573 .fifosize = 64, 1574 .line = 1, 1575 }, 1576 }, 1577 { 1578 .uart = { 1579 .iotype = UPIO_MEM, 1580 .ops = &msm_uart_pops, 1581 .flags = UPF_BOOT_AUTOCONF, 1582 .fifosize = 64, 1583 .line = 2, 1584 }, 1585 }, 1586 }; 1587 1588 #define UART_NR ARRAY_SIZE(msm_uart_ports) 1589 1590 static inline struct uart_port *msm_get_port_from_line(unsigned int line) 1591 { 1592 return &msm_uart_ports[line].uart; 1593 } 1594 1595 #ifdef CONFIG_SERIAL_MSM_CONSOLE 1596 static void __msm_console_write(struct uart_port *port, const char *s, 1597 unsigned int count, bool is_uartdm) 1598 { 1599 int i; 1600 int num_newlines = 0; 1601 bool replaced = false; 1602 void __iomem *tf; 1603 int locked = 1; 1604 1605 if (is_uartdm) 1606 tf = port->membase + UARTDM_TF; 1607 else 1608 tf = port->membase + UART_TF; 1609 1610 /* Account for newlines that will get a carriage return added */ 1611 for (i = 0; i < count; i++) 1612 if (s[i] == '\n') 1613 num_newlines++; 1614 count += num_newlines; 1615 1616 if (port->sysrq) 1617 locked = 0; 1618 else if (oops_in_progress) 1619 locked = spin_trylock(&port->lock); 1620 else 1621 spin_lock(&port->lock); 1622 1623 if (is_uartdm) 1624 msm_reset_dm_count(port, count); 1625 1626 i = 0; 1627 while (i < count) { 1628 int j; 1629 unsigned int num_chars; 1630 char buf[4] = { 0 }; 1631 1632 if (is_uartdm) 1633 num_chars = min(count - i, (unsigned int)sizeof(buf)); 1634 else 1635 num_chars = 1; 1636 1637 for (j = 0; j < num_chars; j++) { 1638 char c = *s; 1639 1640 if (c == '\n' && !replaced) { 1641 buf[j] = '\r'; 1642 j++; 1643 replaced = true; 1644 } 1645 if (j < num_chars) { 1646 buf[j] = c; 1647 s++; 1648 replaced = false; 1649 } 1650 } 1651 1652 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 1653 cpu_relax(); 1654 1655 iowrite32_rep(tf, buf, 1); 1656 i += num_chars; 1657 } 1658 1659 if (locked) 1660 spin_unlock(&port->lock); 1661 } 1662 1663 static void msm_console_write(struct console *co, const char *s, 1664 unsigned int count) 1665 { 1666 struct uart_port *port; 1667 struct msm_port *msm_port; 1668 1669 BUG_ON(co->index < 0 || co->index >= UART_NR); 1670 1671 port = msm_get_port_from_line(co->index); 1672 msm_port = UART_TO_MSM(port); 1673 1674 __msm_console_write(port, s, count, msm_port->is_uartdm); 1675 } 1676 1677 static int msm_console_setup(struct console *co, char *options) 1678 { 1679 struct uart_port *port; 1680 int baud = 115200; 1681 int bits = 8; 1682 int parity = 'n'; 1683 int flow = 'n'; 1684 1685 if (unlikely(co->index >= UART_NR || co->index < 0)) 1686 return -ENXIO; 1687 1688 port = msm_get_port_from_line(co->index); 1689 1690 if (unlikely(!port->membase)) 1691 return -ENXIO; 1692 1693 msm_init_clock(port); 1694 1695 if (options) 1696 uart_parse_options(options, &baud, &parity, &bits, &flow); 1697 1698 pr_info("msm_serial: console setup on port #%d\n", port->line); 1699 1700 return uart_set_options(port, co, baud, parity, bits, flow); 1701 } 1702 1703 static void 1704 msm_serial_early_write(struct console *con, const char *s, unsigned n) 1705 { 1706 struct earlycon_device *dev = con->data; 1707 1708 __msm_console_write(&dev->port, s, n, false); 1709 } 1710 1711 static int __init 1712 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt) 1713 { 1714 if (!device->port.membase) 1715 return -ENODEV; 1716 1717 device->con->write = msm_serial_early_write; 1718 return 0; 1719 } 1720 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", 1721 msm_serial_early_console_setup); 1722 1723 static void 1724 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n) 1725 { 1726 struct earlycon_device *dev = con->data; 1727 1728 __msm_console_write(&dev->port, s, n, true); 1729 } 1730 1731 static int __init 1732 msm_serial_early_console_setup_dm(struct earlycon_device *device, 1733 const char *opt) 1734 { 1735 if (!device->port.membase) 1736 return -ENODEV; 1737 1738 device->con->write = msm_serial_early_write_dm; 1739 return 0; 1740 } 1741 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", 1742 msm_serial_early_console_setup_dm); 1743 1744 static struct uart_driver msm_uart_driver; 1745 1746 static struct console msm_console = { 1747 .name = "ttyMSM", 1748 .write = msm_console_write, 1749 .device = uart_console_device, 1750 .setup = msm_console_setup, 1751 .flags = CON_PRINTBUFFER, 1752 .index = -1, 1753 .data = &msm_uart_driver, 1754 }; 1755 1756 #define MSM_CONSOLE (&msm_console) 1757 1758 #else 1759 #define MSM_CONSOLE NULL 1760 #endif 1761 1762 static struct uart_driver msm_uart_driver = { 1763 .owner = THIS_MODULE, 1764 .driver_name = "msm_serial", 1765 .dev_name = "ttyMSM", 1766 .nr = UART_NR, 1767 .cons = MSM_CONSOLE, 1768 }; 1769 1770 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 1771 1772 static const struct of_device_id msm_uartdm_table[] = { 1773 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 }, 1774 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 }, 1775 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 }, 1776 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 }, 1777 { } 1778 }; 1779 1780 static int msm_serial_probe(struct platform_device *pdev) 1781 { 1782 struct msm_port *msm_port; 1783 struct resource *resource; 1784 struct uart_port *port; 1785 const struct of_device_id *id; 1786 int irq, line; 1787 1788 if (pdev->dev.of_node) 1789 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1790 else 1791 line = pdev->id; 1792 1793 if (line < 0) 1794 line = atomic_inc_return(&msm_uart_next_id) - 1; 1795 1796 if (unlikely(line < 0 || line >= UART_NR)) 1797 return -ENXIO; 1798 1799 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line); 1800 1801 port = msm_get_port_from_line(line); 1802 port->dev = &pdev->dev; 1803 msm_port = UART_TO_MSM(port); 1804 1805 id = of_match_device(msm_uartdm_table, &pdev->dev); 1806 if (id) 1807 msm_port->is_uartdm = (unsigned long)id->data; 1808 else 1809 msm_port->is_uartdm = 0; 1810 1811 msm_port->clk = devm_clk_get(&pdev->dev, "core"); 1812 if (IS_ERR(msm_port->clk)) 1813 return PTR_ERR(msm_port->clk); 1814 1815 if (msm_port->is_uartdm) { 1816 msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); 1817 if (IS_ERR(msm_port->pclk)) 1818 return PTR_ERR(msm_port->pclk); 1819 } 1820 1821 port->uartclk = clk_get_rate(msm_port->clk); 1822 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk); 1823 1824 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1825 if (unlikely(!resource)) 1826 return -ENXIO; 1827 port->mapbase = resource->start; 1828 1829 irq = platform_get_irq(pdev, 0); 1830 if (unlikely(irq < 0)) 1831 return -ENXIO; 1832 port->irq = irq; 1833 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE); 1834 1835 platform_set_drvdata(pdev, port); 1836 1837 return uart_add_one_port(&msm_uart_driver, port); 1838 } 1839 1840 static int msm_serial_remove(struct platform_device *pdev) 1841 { 1842 struct uart_port *port = platform_get_drvdata(pdev); 1843 1844 uart_remove_one_port(&msm_uart_driver, port); 1845 1846 return 0; 1847 } 1848 1849 static const struct of_device_id msm_match_table[] = { 1850 { .compatible = "qcom,msm-uart" }, 1851 { .compatible = "qcom,msm-uartdm" }, 1852 {} 1853 }; 1854 MODULE_DEVICE_TABLE(of, msm_match_table); 1855 1856 static int __maybe_unused msm_serial_suspend(struct device *dev) 1857 { 1858 struct msm_port *port = dev_get_drvdata(dev); 1859 1860 uart_suspend_port(&msm_uart_driver, &port->uart); 1861 1862 return 0; 1863 } 1864 1865 static int __maybe_unused msm_serial_resume(struct device *dev) 1866 { 1867 struct msm_port *port = dev_get_drvdata(dev); 1868 1869 uart_resume_port(&msm_uart_driver, &port->uart); 1870 1871 return 0; 1872 } 1873 1874 static const struct dev_pm_ops msm_serial_dev_pm_ops = { 1875 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume) 1876 }; 1877 1878 static struct platform_driver msm_platform_driver = { 1879 .remove = msm_serial_remove, 1880 .probe = msm_serial_probe, 1881 .driver = { 1882 .name = "msm_serial", 1883 .pm = &msm_serial_dev_pm_ops, 1884 .of_match_table = msm_match_table, 1885 }, 1886 }; 1887 1888 static int __init msm_serial_init(void) 1889 { 1890 int ret; 1891 1892 ret = uart_register_driver(&msm_uart_driver); 1893 if (unlikely(ret)) 1894 return ret; 1895 1896 ret = platform_driver_register(&msm_platform_driver); 1897 if (unlikely(ret)) 1898 uart_unregister_driver(&msm_uart_driver); 1899 1900 pr_info("msm_serial: driver initialized\n"); 1901 1902 return ret; 1903 } 1904 1905 static void __exit msm_serial_exit(void) 1906 { 1907 platform_driver_unregister(&msm_platform_driver); 1908 uart_unregister_driver(&msm_uart_driver); 1909 } 1910 1911 module_init(msm_serial_init); 1912 module_exit(msm_serial_exit); 1913 1914 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 1915 MODULE_DESCRIPTION("Driver for msm7x serial device"); 1916 MODULE_LICENSE("GPL"); 1917