1 /* 2 * Driver for msm7k serial device and console 3 * 4 * Copyright (C) 2007 Google, Inc. 5 * Author: Robert Love <rlove@google.com> 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 # define SUPPORT_SYSRQ 20 #endif 21 22 #include <linux/atomic.h> 23 #include <linux/hrtimer.h> 24 #include <linux/module.h> 25 #include <linux/io.h> 26 #include <linux/ioport.h> 27 #include <linux/irq.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial_core.h> 33 #include <linux/serial.h> 34 #include <linux/clk.h> 35 #include <linux/platform_device.h> 36 #include <linux/delay.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 40 #include "msm_serial.h" 41 42 enum { 43 UARTDM_1P1 = 1, 44 UARTDM_1P2, 45 UARTDM_1P3, 46 UARTDM_1P4, 47 }; 48 49 struct msm_port { 50 struct uart_port uart; 51 char name[16]; 52 struct clk *clk; 53 struct clk *pclk; 54 unsigned int imr; 55 int is_uartdm; 56 unsigned int old_snap_state; 57 }; 58 59 static inline void wait_for_xmitr(struct uart_port *port) 60 { 61 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) { 62 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY) 63 break; 64 udelay(1); 65 } 66 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR); 67 } 68 69 static void msm_stop_tx(struct uart_port *port) 70 { 71 struct msm_port *msm_port = UART_TO_MSM(port); 72 73 msm_port->imr &= ~UART_IMR_TXLEV; 74 msm_write(port, msm_port->imr, UART_IMR); 75 } 76 77 static void msm_start_tx(struct uart_port *port) 78 { 79 struct msm_port *msm_port = UART_TO_MSM(port); 80 81 msm_port->imr |= UART_IMR_TXLEV; 82 msm_write(port, msm_port->imr, UART_IMR); 83 } 84 85 static void msm_stop_rx(struct uart_port *port) 86 { 87 struct msm_port *msm_port = UART_TO_MSM(port); 88 89 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 90 msm_write(port, msm_port->imr, UART_IMR); 91 } 92 93 static void msm_enable_ms(struct uart_port *port) 94 { 95 struct msm_port *msm_port = UART_TO_MSM(port); 96 97 msm_port->imr |= UART_IMR_DELTA_CTS; 98 msm_write(port, msm_port->imr, UART_IMR); 99 } 100 101 static void handle_rx_dm(struct uart_port *port, unsigned int misr) 102 { 103 struct tty_port *tport = &port->state->port; 104 unsigned int sr; 105 int count = 0; 106 struct msm_port *msm_port = UART_TO_MSM(port); 107 108 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 109 port->icount.overrun++; 110 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 111 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 112 } 113 114 if (misr & UART_IMR_RXSTALE) { 115 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 116 msm_port->old_snap_state; 117 msm_port->old_snap_state = 0; 118 } else { 119 count = 4 * (msm_read(port, UART_RFWR)); 120 msm_port->old_snap_state += count; 121 } 122 123 /* TODO: Precise error reporting */ 124 125 port->icount.rx += count; 126 127 while (count > 0) { 128 unsigned int c; 129 130 sr = msm_read(port, UART_SR); 131 if ((sr & UART_SR_RX_READY) == 0) { 132 msm_port->old_snap_state -= count; 133 break; 134 } 135 c = msm_read(port, UARTDM_RF); 136 if (sr & UART_SR_RX_BREAK) { 137 port->icount.brk++; 138 if (uart_handle_break(port)) 139 continue; 140 } else if (sr & UART_SR_PAR_FRAME_ERR) 141 port->icount.frame++; 142 143 /* TODO: handle sysrq */ 144 tty_insert_flip_string(tport, (char *)&c, 145 (count > 4) ? 4 : count); 146 count -= 4; 147 } 148 149 spin_unlock(&port->lock); 150 tty_flip_buffer_push(tport); 151 spin_lock(&port->lock); 152 153 if (misr & (UART_IMR_RXSTALE)) 154 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 155 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 156 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 157 } 158 159 static void handle_rx(struct uart_port *port) 160 { 161 struct tty_port *tport = &port->state->port; 162 unsigned int sr; 163 164 /* 165 * Handle overrun. My understanding of the hardware is that overrun 166 * is not tied to the RX buffer, so we handle the case out of band. 167 */ 168 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 169 port->icount.overrun++; 170 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 171 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 172 } 173 174 /* and now the main RX loop */ 175 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 176 unsigned int c; 177 char flag = TTY_NORMAL; 178 179 c = msm_read(port, UART_RF); 180 181 if (sr & UART_SR_RX_BREAK) { 182 port->icount.brk++; 183 if (uart_handle_break(port)) 184 continue; 185 } else if (sr & UART_SR_PAR_FRAME_ERR) { 186 port->icount.frame++; 187 } else { 188 port->icount.rx++; 189 } 190 191 /* Mask conditions we're ignorning. */ 192 sr &= port->read_status_mask; 193 194 if (sr & UART_SR_RX_BREAK) { 195 flag = TTY_BREAK; 196 } else if (sr & UART_SR_PAR_FRAME_ERR) { 197 flag = TTY_FRAME; 198 } 199 200 if (!uart_handle_sysrq_char(port, c)) 201 tty_insert_flip_char(tport, c, flag); 202 } 203 204 spin_unlock(&port->lock); 205 tty_flip_buffer_push(tport); 206 spin_lock(&port->lock); 207 } 208 209 static void reset_dm_count(struct uart_port *port, int count) 210 { 211 wait_for_xmitr(port); 212 msm_write(port, count, UARTDM_NCF_TX); 213 msm_read(port, UARTDM_NCF_TX); 214 } 215 216 static void handle_tx(struct uart_port *port) 217 { 218 struct circ_buf *xmit = &port->state->xmit; 219 struct msm_port *msm_port = UART_TO_MSM(port); 220 unsigned int tx_count, num_chars; 221 unsigned int tf_pointer = 0; 222 223 tx_count = uart_circ_chars_pending(xmit); 224 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail, 225 port->fifosize); 226 227 if (port->x_char) { 228 if (msm_port->is_uartdm) 229 reset_dm_count(port, tx_count + 1); 230 231 msm_write(port, port->x_char, 232 msm_port->is_uartdm ? UARTDM_TF : UART_TF); 233 port->icount.tx++; 234 port->x_char = 0; 235 } else if (tx_count && msm_port->is_uartdm) { 236 reset_dm_count(port, tx_count); 237 } 238 239 while (tf_pointer < tx_count) { 240 int i; 241 char buf[4] = { 0 }; 242 unsigned int *bf = (unsigned int *)&buf; 243 244 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 245 break; 246 247 if (msm_port->is_uartdm) 248 num_chars = min(tx_count - tf_pointer, 249 (unsigned int)sizeof(buf)); 250 else 251 num_chars = 1; 252 253 for (i = 0; i < num_chars; i++) { 254 buf[i] = xmit->buf[xmit->tail + i]; 255 port->icount.tx++; 256 } 257 258 msm_write(port, *bf, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 259 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); 260 tf_pointer += num_chars; 261 } 262 263 /* disable tx interrupts if nothing more to send */ 264 if (uart_circ_empty(xmit)) 265 msm_stop_tx(port); 266 267 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 268 uart_write_wakeup(port); 269 } 270 271 static void handle_delta_cts(struct uart_port *port) 272 { 273 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 274 port->icount.cts++; 275 wake_up_interruptible(&port->state->port.delta_msr_wait); 276 } 277 278 static irqreturn_t msm_irq(int irq, void *dev_id) 279 { 280 struct uart_port *port = dev_id; 281 struct msm_port *msm_port = UART_TO_MSM(port); 282 unsigned int misr; 283 284 spin_lock(&port->lock); 285 misr = msm_read(port, UART_MISR); 286 msm_write(port, 0, UART_IMR); /* disable interrupt */ 287 288 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 289 if (msm_port->is_uartdm) 290 handle_rx_dm(port, misr); 291 else 292 handle_rx(port); 293 } 294 if (misr & UART_IMR_TXLEV) 295 handle_tx(port); 296 if (misr & UART_IMR_DELTA_CTS) 297 handle_delta_cts(port); 298 299 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 300 spin_unlock(&port->lock); 301 302 return IRQ_HANDLED; 303 } 304 305 static unsigned int msm_tx_empty(struct uart_port *port) 306 { 307 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 308 } 309 310 static unsigned int msm_get_mctrl(struct uart_port *port) 311 { 312 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 313 } 314 315 316 static void msm_reset(struct uart_port *port) 317 { 318 struct msm_port *msm_port = UART_TO_MSM(port); 319 320 /* reset everything */ 321 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 322 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 323 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 324 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 325 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 326 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); 327 328 /* Disable DM modes */ 329 if (msm_port->is_uartdm) 330 msm_write(port, 0, UARTDM_DMEN); 331 } 332 333 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 334 { 335 unsigned int mr; 336 mr = msm_read(port, UART_MR1); 337 338 if (!(mctrl & TIOCM_RTS)) { 339 mr &= ~UART_MR1_RX_RDY_CTL; 340 msm_write(port, mr, UART_MR1); 341 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 342 } else { 343 mr |= UART_MR1_RX_RDY_CTL; 344 msm_write(port, mr, UART_MR1); 345 } 346 } 347 348 static void msm_break_ctl(struct uart_port *port, int break_ctl) 349 { 350 if (break_ctl) 351 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 352 else 353 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 354 } 355 356 struct msm_baud_map { 357 u16 divisor; 358 u8 code; 359 u8 rxstale; 360 }; 361 362 static const struct msm_baud_map * 363 msm_find_best_baud(struct uart_port *port, unsigned int baud) 364 { 365 unsigned int i, divisor; 366 const struct msm_baud_map *entry; 367 static const struct msm_baud_map table[] = { 368 { 1536, 0x00, 1 }, 369 { 768, 0x11, 1 }, 370 { 384, 0x22, 1 }, 371 { 192, 0x33, 1 }, 372 { 96, 0x44, 1 }, 373 { 48, 0x55, 1 }, 374 { 32, 0x66, 1 }, 375 { 24, 0x77, 1 }, 376 { 16, 0x88, 1 }, 377 { 12, 0x99, 6 }, 378 { 8, 0xaa, 6 }, 379 { 6, 0xbb, 6 }, 380 { 4, 0xcc, 6 }, 381 { 3, 0xdd, 8 }, 382 { 2, 0xee, 16 }, 383 { 1, 0xff, 31 }, 384 }; 385 386 divisor = uart_get_divisor(port, baud); 387 388 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++) 389 if (entry->divisor <= divisor) 390 break; 391 392 return entry; /* Default to smallest divider */ 393 } 394 395 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) 396 { 397 unsigned int rxstale, watermark; 398 struct msm_port *msm_port = UART_TO_MSM(port); 399 const struct msm_baud_map *entry; 400 401 entry = msm_find_best_baud(port, baud); 402 403 if (msm_port->is_uartdm) 404 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 405 406 msm_write(port, entry->code, UART_CSR); 407 408 /* RX stale watermark */ 409 rxstale = entry->rxstale; 410 watermark = UART_IPR_STALE_LSB & rxstale; 411 watermark |= UART_IPR_RXSTALE_LAST; 412 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2); 413 msm_write(port, watermark, UART_IPR); 414 415 /* set RX watermark */ 416 watermark = (port->fifosize * 3) / 4; 417 msm_write(port, watermark, UART_RFWR); 418 419 /* set TX watermark */ 420 msm_write(port, 10, UART_TFWR); 421 422 if (msm_port->is_uartdm) { 423 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 424 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 425 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 426 } 427 428 return baud; 429 } 430 431 432 static void msm_init_clock(struct uart_port *port) 433 { 434 struct msm_port *msm_port = UART_TO_MSM(port); 435 436 clk_prepare_enable(msm_port->clk); 437 clk_prepare_enable(msm_port->pclk); 438 msm_serial_set_mnd_regs(port); 439 } 440 441 static int msm_startup(struct uart_port *port) 442 { 443 struct msm_port *msm_port = UART_TO_MSM(port); 444 unsigned int data, rfr_level; 445 int ret; 446 447 snprintf(msm_port->name, sizeof(msm_port->name), 448 "msm_serial%d", port->line); 449 450 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH, 451 msm_port->name, port); 452 if (unlikely(ret)) 453 return ret; 454 455 msm_init_clock(port); 456 457 if (likely(port->fifosize > 12)) 458 rfr_level = port->fifosize - 12; 459 else 460 rfr_level = port->fifosize; 461 462 /* set automatic RFR level */ 463 data = msm_read(port, UART_MR1); 464 data &= ~UART_MR1_AUTO_RFR_LEVEL1; 465 data &= ~UART_MR1_AUTO_RFR_LEVEL0; 466 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2); 467 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 468 msm_write(port, data, UART_MR1); 469 470 /* make sure that RXSTALE count is non-zero */ 471 data = msm_read(port, UART_IPR); 472 if (unlikely(!data)) { 473 data |= UART_IPR_RXSTALE_LAST; 474 data |= UART_IPR_STALE_LSB; 475 msm_write(port, data, UART_IPR); 476 } 477 478 data = 0; 479 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) { 480 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 481 msm_reset(port); 482 data = UART_CR_TX_ENABLE; 483 } 484 485 data |= UART_CR_RX_ENABLE; 486 msm_write(port, data, UART_CR); /* enable TX & RX */ 487 488 /* Make sure IPR is not 0 to start with*/ 489 if (msm_port->is_uartdm) 490 msm_write(port, UART_IPR_STALE_LSB, UART_IPR); 491 492 /* turn on RX and CTS interrupts */ 493 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 494 UART_IMR_CURRENT_CTS; 495 496 if (msm_port->is_uartdm) { 497 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 498 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 499 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 500 } 501 502 msm_write(port, msm_port->imr, UART_IMR); 503 return 0; 504 } 505 506 static void msm_shutdown(struct uart_port *port) 507 { 508 struct msm_port *msm_port = UART_TO_MSM(port); 509 510 msm_port->imr = 0; 511 msm_write(port, 0, UART_IMR); /* disable interrupts */ 512 513 clk_disable_unprepare(msm_port->clk); 514 515 free_irq(port->irq, port); 516 } 517 518 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 519 struct ktermios *old) 520 { 521 unsigned long flags; 522 unsigned int baud, mr; 523 524 spin_lock_irqsave(&port->lock, flags); 525 526 /* calculate and set baud rate */ 527 baud = uart_get_baud_rate(port, termios, old, 300, 115200); 528 baud = msm_set_baud_rate(port, baud); 529 if (tty_termios_baud_rate(termios)) 530 tty_termios_encode_baud_rate(termios, baud, baud); 531 532 /* calculate parity */ 533 mr = msm_read(port, UART_MR2); 534 mr &= ~UART_MR2_PARITY_MODE; 535 if (termios->c_cflag & PARENB) { 536 if (termios->c_cflag & PARODD) 537 mr |= UART_MR2_PARITY_MODE_ODD; 538 else if (termios->c_cflag & CMSPAR) 539 mr |= UART_MR2_PARITY_MODE_SPACE; 540 else 541 mr |= UART_MR2_PARITY_MODE_EVEN; 542 } 543 544 /* calculate bits per char */ 545 mr &= ~UART_MR2_BITS_PER_CHAR; 546 switch (termios->c_cflag & CSIZE) { 547 case CS5: 548 mr |= UART_MR2_BITS_PER_CHAR_5; 549 break; 550 case CS6: 551 mr |= UART_MR2_BITS_PER_CHAR_6; 552 break; 553 case CS7: 554 mr |= UART_MR2_BITS_PER_CHAR_7; 555 break; 556 case CS8: 557 default: 558 mr |= UART_MR2_BITS_PER_CHAR_8; 559 break; 560 } 561 562 /* calculate stop bits */ 563 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 564 if (termios->c_cflag & CSTOPB) 565 mr |= UART_MR2_STOP_BIT_LEN_TWO; 566 else 567 mr |= UART_MR2_STOP_BIT_LEN_ONE; 568 569 /* set parity, bits per char, and stop bit */ 570 msm_write(port, mr, UART_MR2); 571 572 /* calculate and set hardware flow control */ 573 mr = msm_read(port, UART_MR1); 574 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 575 if (termios->c_cflag & CRTSCTS) { 576 mr |= UART_MR1_CTS_CTL; 577 mr |= UART_MR1_RX_RDY_CTL; 578 } 579 msm_write(port, mr, UART_MR1); 580 581 /* Configure status bits to ignore based on termio flags. */ 582 port->read_status_mask = 0; 583 if (termios->c_iflag & INPCK) 584 port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 585 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 586 port->read_status_mask |= UART_SR_RX_BREAK; 587 588 uart_update_timeout(port, termios->c_cflag, baud); 589 590 spin_unlock_irqrestore(&port->lock, flags); 591 } 592 593 static const char *msm_type(struct uart_port *port) 594 { 595 return "MSM"; 596 } 597 598 static void msm_release_port(struct uart_port *port) 599 { 600 struct platform_device *pdev = to_platform_device(port->dev); 601 struct resource *uart_resource; 602 resource_size_t size; 603 604 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 605 if (unlikely(!uart_resource)) 606 return; 607 size = resource_size(uart_resource); 608 609 release_mem_region(port->mapbase, size); 610 iounmap(port->membase); 611 port->membase = NULL; 612 } 613 614 static int msm_request_port(struct uart_port *port) 615 { 616 struct platform_device *pdev = to_platform_device(port->dev); 617 struct resource *uart_resource; 618 resource_size_t size; 619 int ret; 620 621 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 622 if (unlikely(!uart_resource)) 623 return -ENXIO; 624 625 size = resource_size(uart_resource); 626 627 if (!request_mem_region(port->mapbase, size, "msm_serial")) 628 return -EBUSY; 629 630 port->membase = ioremap(port->mapbase, size); 631 if (!port->membase) { 632 ret = -EBUSY; 633 goto fail_release_port; 634 } 635 636 return 0; 637 638 fail_release_port: 639 release_mem_region(port->mapbase, size); 640 return ret; 641 } 642 643 static void msm_config_port(struct uart_port *port, int flags) 644 { 645 int ret; 646 if (flags & UART_CONFIG_TYPE) { 647 port->type = PORT_MSM; 648 ret = msm_request_port(port); 649 if (ret) 650 return; 651 } 652 } 653 654 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 655 { 656 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 657 return -EINVAL; 658 if (unlikely(port->irq != ser->irq)) 659 return -EINVAL; 660 return 0; 661 } 662 663 static void msm_power(struct uart_port *port, unsigned int state, 664 unsigned int oldstate) 665 { 666 struct msm_port *msm_port = UART_TO_MSM(port); 667 668 switch (state) { 669 case 0: 670 clk_prepare_enable(msm_port->clk); 671 clk_prepare_enable(msm_port->pclk); 672 break; 673 case 3: 674 clk_disable_unprepare(msm_port->clk); 675 clk_disable_unprepare(msm_port->pclk); 676 break; 677 default: 678 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state); 679 } 680 } 681 682 #ifdef CONFIG_CONSOLE_POLL 683 static int msm_poll_init(struct uart_port *port) 684 { 685 struct msm_port *msm_port = UART_TO_MSM(port); 686 687 /* Enable single character mode on RX FIFO */ 688 if (msm_port->is_uartdm >= UARTDM_1P4) 689 msm_write(port, UARTDM_DMEN_RX_SC_ENABLE, UARTDM_DMEN); 690 691 return 0; 692 } 693 694 static int msm_poll_get_char_single(struct uart_port *port) 695 { 696 struct msm_port *msm_port = UART_TO_MSM(port); 697 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF; 698 699 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) 700 return NO_POLL_CHAR; 701 else 702 return msm_read(port, rf_reg) & 0xff; 703 } 704 705 static int msm_poll_get_char_dm_1p3(struct uart_port *port) 706 { 707 int c; 708 static u32 slop; 709 static int count; 710 unsigned char *sp = (unsigned char *)&slop; 711 712 /* Check if a previous read had more than one char */ 713 if (count) { 714 c = sp[sizeof(slop) - count]; 715 count--; 716 /* Or if FIFO is empty */ 717 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) { 718 /* 719 * If RX packing buffer has less than a word, force stale to 720 * push contents into RX FIFO 721 */ 722 count = msm_read(port, UARTDM_RXFS); 723 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; 724 if (count) { 725 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR); 726 slop = msm_read(port, UARTDM_RF); 727 c = sp[0]; 728 count--; 729 } else { 730 c = NO_POLL_CHAR; 731 } 732 /* FIFO has a word */ 733 } else { 734 slop = msm_read(port, UARTDM_RF); 735 c = sp[0]; 736 count = sizeof(slop) - 1; 737 } 738 739 return c; 740 } 741 742 static int msm_poll_get_char(struct uart_port *port) 743 { 744 u32 imr; 745 int c; 746 struct msm_port *msm_port = UART_TO_MSM(port); 747 748 /* Disable all interrupts */ 749 imr = msm_read(port, UART_IMR); 750 msm_write(port, 0, UART_IMR); 751 752 if (msm_port->is_uartdm == UARTDM_1P3) 753 c = msm_poll_get_char_dm_1p3(port); 754 else 755 c = msm_poll_get_char_single(port); 756 757 /* Enable interrupts */ 758 msm_write(port, imr, UART_IMR); 759 760 return c; 761 } 762 763 static void msm_poll_put_char(struct uart_port *port, unsigned char c) 764 { 765 u32 imr; 766 struct msm_port *msm_port = UART_TO_MSM(port); 767 768 /* Disable all interrupts */ 769 imr = msm_read(port, UART_IMR); 770 msm_write(port, 0, UART_IMR); 771 772 if (msm_port->is_uartdm) 773 reset_dm_count(port, 1); 774 775 /* Wait until FIFO is empty */ 776 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 777 cpu_relax(); 778 779 /* Write a character */ 780 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 781 782 /* Wait until FIFO is empty */ 783 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 784 cpu_relax(); 785 786 /* Enable interrupts */ 787 msm_write(port, imr, UART_IMR); 788 789 return; 790 } 791 #endif 792 793 static struct uart_ops msm_uart_pops = { 794 .tx_empty = msm_tx_empty, 795 .set_mctrl = msm_set_mctrl, 796 .get_mctrl = msm_get_mctrl, 797 .stop_tx = msm_stop_tx, 798 .start_tx = msm_start_tx, 799 .stop_rx = msm_stop_rx, 800 .enable_ms = msm_enable_ms, 801 .break_ctl = msm_break_ctl, 802 .startup = msm_startup, 803 .shutdown = msm_shutdown, 804 .set_termios = msm_set_termios, 805 .type = msm_type, 806 .release_port = msm_release_port, 807 .request_port = msm_request_port, 808 .config_port = msm_config_port, 809 .verify_port = msm_verify_port, 810 .pm = msm_power, 811 #ifdef CONFIG_CONSOLE_POLL 812 .poll_init = msm_poll_init, 813 .poll_get_char = msm_poll_get_char, 814 .poll_put_char = msm_poll_put_char, 815 #endif 816 }; 817 818 static struct msm_port msm_uart_ports[] = { 819 { 820 .uart = { 821 .iotype = UPIO_MEM, 822 .ops = &msm_uart_pops, 823 .flags = UPF_BOOT_AUTOCONF, 824 .fifosize = 64, 825 .line = 0, 826 }, 827 }, 828 { 829 .uart = { 830 .iotype = UPIO_MEM, 831 .ops = &msm_uart_pops, 832 .flags = UPF_BOOT_AUTOCONF, 833 .fifosize = 64, 834 .line = 1, 835 }, 836 }, 837 { 838 .uart = { 839 .iotype = UPIO_MEM, 840 .ops = &msm_uart_pops, 841 .flags = UPF_BOOT_AUTOCONF, 842 .fifosize = 64, 843 .line = 2, 844 }, 845 }, 846 }; 847 848 #define UART_NR ARRAY_SIZE(msm_uart_ports) 849 850 static inline struct uart_port *get_port_from_line(unsigned int line) 851 { 852 return &msm_uart_ports[line].uart; 853 } 854 855 #ifdef CONFIG_SERIAL_MSM_CONSOLE 856 static void msm_console_write(struct console *co, const char *s, 857 unsigned int count) 858 { 859 int i; 860 struct uart_port *port; 861 struct msm_port *msm_port; 862 int num_newlines = 0; 863 bool replaced = false; 864 865 BUG_ON(co->index < 0 || co->index >= UART_NR); 866 867 port = get_port_from_line(co->index); 868 msm_port = UART_TO_MSM(port); 869 870 /* Account for newlines that will get a carriage return added */ 871 for (i = 0; i < count; i++) 872 if (s[i] == '\n') 873 num_newlines++; 874 count += num_newlines; 875 876 spin_lock(&port->lock); 877 if (msm_port->is_uartdm) 878 reset_dm_count(port, count); 879 880 i = 0; 881 while (i < count) { 882 int j; 883 unsigned int num_chars; 884 char buf[4] = { 0 }; 885 unsigned int *bf = (unsigned int *)&buf; 886 887 if (msm_port->is_uartdm) 888 num_chars = min(count - i, (unsigned int)sizeof(buf)); 889 else 890 num_chars = 1; 891 892 for (j = 0; j < num_chars; j++) { 893 char c = *s; 894 895 if (c == '\n' && !replaced) { 896 buf[j] = '\r'; 897 j++; 898 replaced = true; 899 } 900 if (j < num_chars) { 901 buf[j] = c; 902 s++; 903 replaced = false; 904 } 905 } 906 907 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 908 cpu_relax(); 909 910 msm_write(port, *bf, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 911 i += num_chars; 912 } 913 spin_unlock(&port->lock); 914 } 915 916 static int __init msm_console_setup(struct console *co, char *options) 917 { 918 struct uart_port *port; 919 struct msm_port *msm_port; 920 int baud, flow, bits, parity; 921 922 if (unlikely(co->index >= UART_NR || co->index < 0)) 923 return -ENXIO; 924 925 port = get_port_from_line(co->index); 926 msm_port = UART_TO_MSM(port); 927 928 if (unlikely(!port->membase)) 929 return -ENXIO; 930 931 msm_init_clock(port); 932 933 if (options) 934 uart_parse_options(options, &baud, &parity, &bits, &flow); 935 936 bits = 8; 937 parity = 'n'; 938 flow = 'n'; 939 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE, 940 UART_MR2); /* 8N1 */ 941 942 if (baud < 300 || baud > 115200) 943 baud = 115200; 944 msm_set_baud_rate(port, baud); 945 946 msm_reset(port); 947 948 if (msm_port->is_uartdm) { 949 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 950 msm_write(port, UART_CR_TX_ENABLE, UART_CR); 951 } 952 953 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line); 954 955 return uart_set_options(port, co, baud, parity, bits, flow); 956 } 957 958 static struct uart_driver msm_uart_driver; 959 960 static struct console msm_console = { 961 .name = "ttyMSM", 962 .write = msm_console_write, 963 .device = uart_console_device, 964 .setup = msm_console_setup, 965 .flags = CON_PRINTBUFFER, 966 .index = -1, 967 .data = &msm_uart_driver, 968 }; 969 970 #define MSM_CONSOLE (&msm_console) 971 972 #else 973 #define MSM_CONSOLE NULL 974 #endif 975 976 static struct uart_driver msm_uart_driver = { 977 .owner = THIS_MODULE, 978 .driver_name = "msm_serial", 979 .dev_name = "ttyMSM", 980 .nr = UART_NR, 981 .cons = MSM_CONSOLE, 982 }; 983 984 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 985 986 static const struct of_device_id msm_uartdm_table[] = { 987 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 }, 988 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 }, 989 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 }, 990 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 }, 991 { } 992 }; 993 994 static int msm_serial_probe(struct platform_device *pdev) 995 { 996 struct msm_port *msm_port; 997 struct resource *resource; 998 struct uart_port *port; 999 const struct of_device_id *id; 1000 int irq; 1001 1002 if (pdev->id == -1) 1003 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1; 1004 1005 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR)) 1006 return -ENXIO; 1007 1008 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id); 1009 1010 port = get_port_from_line(pdev->id); 1011 port->dev = &pdev->dev; 1012 msm_port = UART_TO_MSM(port); 1013 1014 id = of_match_device(msm_uartdm_table, &pdev->dev); 1015 if (id) 1016 msm_port->is_uartdm = (unsigned long)id->data; 1017 else 1018 msm_port->is_uartdm = 0; 1019 1020 msm_port->clk = devm_clk_get(&pdev->dev, "core"); 1021 if (IS_ERR(msm_port->clk)) 1022 return PTR_ERR(msm_port->clk); 1023 1024 if (msm_port->is_uartdm) { 1025 msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); 1026 if (IS_ERR(msm_port->pclk)) 1027 return PTR_ERR(msm_port->pclk); 1028 1029 clk_set_rate(msm_port->clk, 1843200); 1030 } 1031 1032 port->uartclk = clk_get_rate(msm_port->clk); 1033 printk(KERN_INFO "uartclk = %d\n", port->uartclk); 1034 1035 1036 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1037 if (unlikely(!resource)) 1038 return -ENXIO; 1039 port->mapbase = resource->start; 1040 1041 irq = platform_get_irq(pdev, 0); 1042 if (unlikely(irq < 0)) 1043 return -ENXIO; 1044 port->irq = irq; 1045 1046 platform_set_drvdata(pdev, port); 1047 1048 return uart_add_one_port(&msm_uart_driver, port); 1049 } 1050 1051 static int msm_serial_remove(struct platform_device *pdev) 1052 { 1053 struct uart_port *port = platform_get_drvdata(pdev); 1054 1055 uart_remove_one_port(&msm_uart_driver, port); 1056 1057 return 0; 1058 } 1059 1060 static struct of_device_id msm_match_table[] = { 1061 { .compatible = "qcom,msm-uart" }, 1062 { .compatible = "qcom,msm-uartdm" }, 1063 {} 1064 }; 1065 1066 static struct platform_driver msm_platform_driver = { 1067 .remove = msm_serial_remove, 1068 .probe = msm_serial_probe, 1069 .driver = { 1070 .name = "msm_serial", 1071 .owner = THIS_MODULE, 1072 .of_match_table = msm_match_table, 1073 }, 1074 }; 1075 1076 static int __init msm_serial_init(void) 1077 { 1078 int ret; 1079 1080 ret = uart_register_driver(&msm_uart_driver); 1081 if (unlikely(ret)) 1082 return ret; 1083 1084 ret = platform_driver_register(&msm_platform_driver); 1085 if (unlikely(ret)) 1086 uart_unregister_driver(&msm_uart_driver); 1087 1088 printk(KERN_INFO "msm_serial: driver initialized\n"); 1089 1090 return ret; 1091 } 1092 1093 static void __exit msm_serial_exit(void) 1094 { 1095 #ifdef CONFIG_SERIAL_MSM_CONSOLE 1096 unregister_console(&msm_console); 1097 #endif 1098 platform_driver_unregister(&msm_platform_driver); 1099 uart_unregister_driver(&msm_uart_driver); 1100 } 1101 1102 module_init(msm_serial_init); 1103 module_exit(msm_serial_exit); 1104 1105 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 1106 MODULE_DESCRIPTION("Driver for msm7x serial device"); 1107 MODULE_LICENSE("GPL"); 1108