1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for msm7k serial device and console 4 * 5 * Copyright (C) 2007 Google, Inc. 6 * Author: Robert Love <rlove@google.com> 7 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/atomic.h> 12 #include <linux/dma/qcom_adm.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/dmaengine.h> 15 #include <linux/module.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/interrupt.h> 19 #include <linux/init.h> 20 #include <linux/console.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial_core.h> 24 #include <linux/slab.h> 25 #include <linux/clk.h> 26 #include <linux/platform_device.h> 27 #include <linux/delay.h> 28 #include <linux/of.h> 29 #include <linux/of_device.h> 30 #include <linux/wait.h> 31 32 #define MSM_UART_MR1 0x0000 33 34 #define MSM_UART_MR1_AUTO_RFR_LEVEL0 0x3F 35 #define MSM_UART_MR1_AUTO_RFR_LEVEL1 0x3FF00 36 #define MSM_UART_DM_MR1_AUTO_RFR_LEVEL1 0xFFFFFF00 37 #define MSM_UART_MR1_RX_RDY_CTL BIT(7) 38 #define MSM_UART_MR1_CTS_CTL BIT(6) 39 40 #define MSM_UART_MR2 0x0004 41 #define MSM_UART_MR2_ERROR_MODE BIT(6) 42 #define MSM_UART_MR2_BITS_PER_CHAR 0x30 43 #define MSM_UART_MR2_BITS_PER_CHAR_5 (0x0 << 4) 44 #define MSM_UART_MR2_BITS_PER_CHAR_6 (0x1 << 4) 45 #define MSM_UART_MR2_BITS_PER_CHAR_7 (0x2 << 4) 46 #define MSM_UART_MR2_BITS_PER_CHAR_8 (0x3 << 4) 47 #define MSM_UART_MR2_STOP_BIT_LEN_ONE (0x1 << 2) 48 #define MSM_UART_MR2_STOP_BIT_LEN_TWO (0x3 << 2) 49 #define MSM_UART_MR2_PARITY_MODE_NONE 0x0 50 #define MSM_UART_MR2_PARITY_MODE_ODD 0x1 51 #define MSM_UART_MR2_PARITY_MODE_EVEN 0x2 52 #define MSM_UART_MR2_PARITY_MODE_SPACE 0x3 53 #define MSM_UART_MR2_PARITY_MODE 0x3 54 55 #define MSM_UART_CSR 0x0008 56 57 #define MSM_UART_TF 0x000C 58 #define UARTDM_TF 0x0070 59 60 #define MSM_UART_CR 0x0010 61 #define MSM_UART_CR_CMD_NULL (0 << 4) 62 #define MSM_UART_CR_CMD_RESET_RX (1 << 4) 63 #define MSM_UART_CR_CMD_RESET_TX (2 << 4) 64 #define MSM_UART_CR_CMD_RESET_ERR (3 << 4) 65 #define MSM_UART_CR_CMD_RESET_BREAK_INT (4 << 4) 66 #define MSM_UART_CR_CMD_START_BREAK (5 << 4) 67 #define MSM_UART_CR_CMD_STOP_BREAK (6 << 4) 68 #define MSM_UART_CR_CMD_RESET_CTS (7 << 4) 69 #define MSM_UART_CR_CMD_RESET_STALE_INT (8 << 4) 70 #define MSM_UART_CR_CMD_PACKET_MODE (9 << 4) 71 #define MSM_UART_CR_CMD_MODE_RESET (12 << 4) 72 #define MSM_UART_CR_CMD_SET_RFR (13 << 4) 73 #define MSM_UART_CR_CMD_RESET_RFR (14 << 4) 74 #define MSM_UART_CR_CMD_PROTECTION_EN (16 << 4) 75 #define MSM_UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8) 76 #define MSM_UART_CR_CMD_STALE_EVENT_ENABLE (80 << 4) 77 #define MSM_UART_CR_CMD_FORCE_STALE (4 << 8) 78 #define MSM_UART_CR_CMD_RESET_TX_READY (3 << 8) 79 #define MSM_UART_CR_TX_DISABLE BIT(3) 80 #define MSM_UART_CR_TX_ENABLE BIT(2) 81 #define MSM_UART_CR_RX_DISABLE BIT(1) 82 #define MSM_UART_CR_RX_ENABLE BIT(0) 83 #define MSM_UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4)) 84 85 #define MSM_UART_IMR 0x0014 86 #define MSM_UART_IMR_TXLEV BIT(0) 87 #define MSM_UART_IMR_RXSTALE BIT(3) 88 #define MSM_UART_IMR_RXLEV BIT(4) 89 #define MSM_UART_IMR_DELTA_CTS BIT(5) 90 #define MSM_UART_IMR_CURRENT_CTS BIT(6) 91 #define MSM_UART_IMR_RXBREAK_START BIT(10) 92 93 #define MSM_UART_IPR_RXSTALE_LAST 0x20 94 #define MSM_UART_IPR_STALE_LSB 0x1F 95 #define MSM_UART_IPR_STALE_TIMEOUT_MSB 0x3FF80 96 #define MSM_UART_DM_IPR_STALE_TIMEOUT_MSB 0xFFFFFF80 97 98 #define MSM_UART_IPR 0x0018 99 #define MSM_UART_TFWR 0x001C 100 #define MSM_UART_RFWR 0x0020 101 #define MSM_UART_HCR 0x0024 102 103 #define MSM_UART_MREG 0x0028 104 #define MSM_UART_NREG 0x002C 105 #define MSM_UART_DREG 0x0030 106 #define MSM_UART_MNDREG 0x0034 107 #define MSM_UART_IRDA 0x0038 108 #define MSM_UART_MISR_MODE 0x0040 109 #define MSM_UART_MISR_RESET 0x0044 110 #define MSM_UART_MISR_EXPORT 0x0048 111 #define MSM_UART_MISR_VAL 0x004C 112 #define MSM_UART_TEST_CTRL 0x0050 113 114 #define MSM_UART_SR 0x0008 115 #define MSM_UART_SR_HUNT_CHAR BIT(7) 116 #define MSM_UART_SR_RX_BREAK BIT(6) 117 #define MSM_UART_SR_PAR_FRAME_ERR BIT(5) 118 #define MSM_UART_SR_OVERRUN BIT(4) 119 #define MSM_UART_SR_TX_EMPTY BIT(3) 120 #define MSM_UART_SR_TX_READY BIT(2) 121 #define MSM_UART_SR_RX_FULL BIT(1) 122 #define MSM_UART_SR_RX_READY BIT(0) 123 124 #define MSM_UART_RF 0x000C 125 #define UARTDM_RF 0x0070 126 #define MSM_UART_MISR 0x0010 127 #define MSM_UART_ISR 0x0014 128 #define MSM_UART_ISR_TX_READY BIT(7) 129 130 #define UARTDM_RXFS 0x50 131 #define UARTDM_RXFS_BUF_SHIFT 0x7 132 #define UARTDM_RXFS_BUF_MASK 0x7 133 134 #define UARTDM_DMEN 0x3C 135 #define UARTDM_DMEN_RX_SC_ENABLE BIT(5) 136 #define UARTDM_DMEN_TX_SC_ENABLE BIT(4) 137 138 #define UARTDM_DMEN_TX_BAM_ENABLE BIT(2) /* UARTDM_1P4 */ 139 #define UARTDM_DMEN_TX_DM_ENABLE BIT(0) /* < UARTDM_1P4 */ 140 141 #define UARTDM_DMEN_RX_BAM_ENABLE BIT(3) /* UARTDM_1P4 */ 142 #define UARTDM_DMEN_RX_DM_ENABLE BIT(1) /* < UARTDM_1P4 */ 143 144 #define UARTDM_DMRX 0x34 145 #define UARTDM_NCF_TX 0x40 146 #define UARTDM_RX_TOTAL_SNAP 0x38 147 148 #define UARTDM_BURST_SIZE 16 /* in bytes */ 149 #define UARTDM_TX_AIGN(x) ((x) & ~0x3) /* valid for > 1p3 */ 150 #define UARTDM_TX_MAX 256 /* in bytes, valid for <= 1p3 */ 151 #define UARTDM_RX_SIZE (UART_XMIT_SIZE / 4) 152 153 enum { 154 UARTDM_1P1 = 1, 155 UARTDM_1P2, 156 UARTDM_1P3, 157 UARTDM_1P4, 158 }; 159 160 struct msm_dma { 161 struct dma_chan *chan; 162 enum dma_data_direction dir; 163 dma_addr_t phys; 164 unsigned char *virt; 165 dma_cookie_t cookie; 166 u32 enable_bit; 167 unsigned int count; 168 struct dma_async_tx_descriptor *desc; 169 }; 170 171 struct msm_port { 172 struct uart_port uart; 173 char name[16]; 174 struct clk *clk; 175 struct clk *pclk; 176 unsigned int imr; 177 int is_uartdm; 178 unsigned int old_snap_state; 179 bool break_detected; 180 struct msm_dma tx_dma; 181 struct msm_dma rx_dma; 182 }; 183 184 static inline struct msm_port *to_msm_port(struct uart_port *up) 185 { 186 return container_of(up, struct msm_port, uart); 187 } 188 189 static 190 void msm_write(struct uart_port *port, unsigned int val, unsigned int off) 191 { 192 writel_relaxed(val, port->membase + off); 193 } 194 195 static 196 unsigned int msm_read(struct uart_port *port, unsigned int off) 197 { 198 return readl_relaxed(port->membase + off); 199 } 200 201 /* 202 * Setup the MND registers to use the TCXO clock. 203 */ 204 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port) 205 { 206 msm_write(port, 0x06, MSM_UART_MREG); 207 msm_write(port, 0xF1, MSM_UART_NREG); 208 msm_write(port, 0x0F, MSM_UART_DREG); 209 msm_write(port, 0x1A, MSM_UART_MNDREG); 210 port->uartclk = 1843200; 211 } 212 213 /* 214 * Setup the MND registers to use the TCXO clock divided by 4. 215 */ 216 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port) 217 { 218 msm_write(port, 0x18, MSM_UART_MREG); 219 msm_write(port, 0xF6, MSM_UART_NREG); 220 msm_write(port, 0x0F, MSM_UART_DREG); 221 msm_write(port, 0x0A, MSM_UART_MNDREG); 222 port->uartclk = 1843200; 223 } 224 225 static void msm_serial_set_mnd_regs(struct uart_port *port) 226 { 227 struct msm_port *msm_port = to_msm_port(port); 228 229 /* 230 * These registers don't exist so we change the clk input rate 231 * on uartdm hardware instead 232 */ 233 if (msm_port->is_uartdm) 234 return; 235 236 if (port->uartclk == 19200000) 237 msm_serial_set_mnd_regs_tcxo(port); 238 else if (port->uartclk == 4800000) 239 msm_serial_set_mnd_regs_tcxoby4(port); 240 } 241 242 static void msm_handle_tx(struct uart_port *port); 243 static void msm_start_rx_dma(struct msm_port *msm_port); 244 245 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma) 246 { 247 struct device *dev = port->dev; 248 unsigned int mapped; 249 u32 val; 250 251 mapped = dma->count; 252 dma->count = 0; 253 254 dmaengine_terminate_all(dma->chan); 255 256 /* 257 * DMA Stall happens if enqueue and flush command happens concurrently. 258 * For example before changing the baud rate/protocol configuration and 259 * sending flush command to ADM, disable the channel of UARTDM. 260 * Note: should not reset the receiver here immediately as it is not 261 * suggested to do disable/reset or reset/disable at the same time. 262 */ 263 val = msm_read(port, UARTDM_DMEN); 264 val &= ~dma->enable_bit; 265 msm_write(port, val, UARTDM_DMEN); 266 267 if (mapped) 268 dma_unmap_single(dev, dma->phys, mapped, dma->dir); 269 } 270 271 static void msm_release_dma(struct msm_port *msm_port) 272 { 273 struct msm_dma *dma; 274 275 dma = &msm_port->tx_dma; 276 if (dma->chan) { 277 msm_stop_dma(&msm_port->uart, dma); 278 dma_release_channel(dma->chan); 279 } 280 281 memset(dma, 0, sizeof(*dma)); 282 283 dma = &msm_port->rx_dma; 284 if (dma->chan) { 285 msm_stop_dma(&msm_port->uart, dma); 286 dma_release_channel(dma->chan); 287 kfree(dma->virt); 288 } 289 290 memset(dma, 0, sizeof(*dma)); 291 } 292 293 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base) 294 { 295 struct device *dev = msm_port->uart.dev; 296 struct dma_slave_config conf; 297 struct qcom_adm_peripheral_config periph_conf = {}; 298 struct msm_dma *dma; 299 u32 crci = 0; 300 int ret; 301 302 dma = &msm_port->tx_dma; 303 304 /* allocate DMA resources, if available */ 305 dma->chan = dma_request_chan(dev, "tx"); 306 if (IS_ERR(dma->chan)) 307 goto no_tx; 308 309 of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci); 310 311 memset(&conf, 0, sizeof(conf)); 312 conf.direction = DMA_MEM_TO_DEV; 313 conf.device_fc = true; 314 conf.dst_addr = base + UARTDM_TF; 315 conf.dst_maxburst = UARTDM_BURST_SIZE; 316 if (crci) { 317 conf.peripheral_config = &periph_conf; 318 conf.peripheral_size = sizeof(periph_conf); 319 periph_conf.crci = crci; 320 } 321 322 ret = dmaengine_slave_config(dma->chan, &conf); 323 if (ret) 324 goto rel_tx; 325 326 dma->dir = DMA_TO_DEVICE; 327 328 if (msm_port->is_uartdm < UARTDM_1P4) 329 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE; 330 else 331 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE; 332 333 return; 334 335 rel_tx: 336 dma_release_channel(dma->chan); 337 no_tx: 338 memset(dma, 0, sizeof(*dma)); 339 } 340 341 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base) 342 { 343 struct device *dev = msm_port->uart.dev; 344 struct dma_slave_config conf; 345 struct qcom_adm_peripheral_config periph_conf = {}; 346 struct msm_dma *dma; 347 u32 crci = 0; 348 int ret; 349 350 dma = &msm_port->rx_dma; 351 352 /* allocate DMA resources, if available */ 353 dma->chan = dma_request_chan(dev, "rx"); 354 if (IS_ERR(dma->chan)) 355 goto no_rx; 356 357 of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci); 358 359 dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL); 360 if (!dma->virt) 361 goto rel_rx; 362 363 memset(&conf, 0, sizeof(conf)); 364 conf.direction = DMA_DEV_TO_MEM; 365 conf.device_fc = true; 366 conf.src_addr = base + UARTDM_RF; 367 conf.src_maxburst = UARTDM_BURST_SIZE; 368 if (crci) { 369 conf.peripheral_config = &periph_conf; 370 conf.peripheral_size = sizeof(periph_conf); 371 periph_conf.crci = crci; 372 } 373 374 ret = dmaengine_slave_config(dma->chan, &conf); 375 if (ret) 376 goto err; 377 378 dma->dir = DMA_FROM_DEVICE; 379 380 if (msm_port->is_uartdm < UARTDM_1P4) 381 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE; 382 else 383 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE; 384 385 return; 386 err: 387 kfree(dma->virt); 388 rel_rx: 389 dma_release_channel(dma->chan); 390 no_rx: 391 memset(dma, 0, sizeof(*dma)); 392 } 393 394 static inline void msm_wait_for_xmitr(struct uart_port *port) 395 { 396 unsigned int timeout = 500000; 397 398 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY)) { 399 if (msm_read(port, MSM_UART_ISR) & MSM_UART_ISR_TX_READY) 400 break; 401 udelay(1); 402 if (!timeout--) 403 break; 404 } 405 msm_write(port, MSM_UART_CR_CMD_RESET_TX_READY, MSM_UART_CR); 406 } 407 408 static void msm_stop_tx(struct uart_port *port) 409 { 410 struct msm_port *msm_port = to_msm_port(port); 411 412 msm_port->imr &= ~MSM_UART_IMR_TXLEV; 413 msm_write(port, msm_port->imr, MSM_UART_IMR); 414 } 415 416 static void msm_start_tx(struct uart_port *port) 417 { 418 struct msm_port *msm_port = to_msm_port(port); 419 struct msm_dma *dma = &msm_port->tx_dma; 420 421 /* Already started in DMA mode */ 422 if (dma->count) 423 return; 424 425 msm_port->imr |= MSM_UART_IMR_TXLEV; 426 msm_write(port, msm_port->imr, MSM_UART_IMR); 427 } 428 429 static void msm_reset_dm_count(struct uart_port *port, int count) 430 { 431 msm_wait_for_xmitr(port); 432 msm_write(port, count, UARTDM_NCF_TX); 433 msm_read(port, UARTDM_NCF_TX); 434 } 435 436 static void msm_complete_tx_dma(void *args) 437 { 438 struct msm_port *msm_port = args; 439 struct uart_port *port = &msm_port->uart; 440 struct circ_buf *xmit = &port->state->xmit; 441 struct msm_dma *dma = &msm_port->tx_dma; 442 struct dma_tx_state state; 443 unsigned long flags; 444 unsigned int count; 445 u32 val; 446 447 spin_lock_irqsave(&port->lock, flags); 448 449 /* Already stopped */ 450 if (!dma->count) 451 goto done; 452 453 dmaengine_tx_status(dma->chan, dma->cookie, &state); 454 455 dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir); 456 457 val = msm_read(port, UARTDM_DMEN); 458 val &= ~dma->enable_bit; 459 msm_write(port, val, UARTDM_DMEN); 460 461 if (msm_port->is_uartdm > UARTDM_1P3) { 462 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); 463 msm_write(port, MSM_UART_CR_TX_ENABLE, MSM_UART_CR); 464 } 465 466 count = dma->count - state.residue; 467 port->icount.tx += count; 468 dma->count = 0; 469 470 xmit->tail += count; 471 xmit->tail &= UART_XMIT_SIZE - 1; 472 473 /* Restore "Tx FIFO below watermark" interrupt */ 474 msm_port->imr |= MSM_UART_IMR_TXLEV; 475 msm_write(port, msm_port->imr, MSM_UART_IMR); 476 477 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 478 uart_write_wakeup(port); 479 480 msm_handle_tx(port); 481 done: 482 spin_unlock_irqrestore(&port->lock, flags); 483 } 484 485 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count) 486 { 487 struct circ_buf *xmit = &msm_port->uart.state->xmit; 488 struct uart_port *port = &msm_port->uart; 489 struct msm_dma *dma = &msm_port->tx_dma; 490 void *cpu_addr; 491 int ret; 492 u32 val; 493 494 cpu_addr = &xmit->buf[xmit->tail]; 495 496 dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir); 497 ret = dma_mapping_error(port->dev, dma->phys); 498 if (ret) 499 return ret; 500 501 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 502 count, DMA_MEM_TO_DEV, 503 DMA_PREP_INTERRUPT | 504 DMA_PREP_FENCE); 505 if (!dma->desc) { 506 ret = -EIO; 507 goto unmap; 508 } 509 510 dma->desc->callback = msm_complete_tx_dma; 511 dma->desc->callback_param = msm_port; 512 513 dma->cookie = dmaengine_submit(dma->desc); 514 ret = dma_submit_error(dma->cookie); 515 if (ret) 516 goto unmap; 517 518 /* 519 * Using DMA complete for Tx FIFO reload, no need for 520 * "Tx FIFO below watermark" one, disable it 521 */ 522 msm_port->imr &= ~MSM_UART_IMR_TXLEV; 523 msm_write(port, msm_port->imr, MSM_UART_IMR); 524 525 dma->count = count; 526 527 val = msm_read(port, UARTDM_DMEN); 528 val |= dma->enable_bit; 529 530 if (msm_port->is_uartdm < UARTDM_1P4) 531 msm_write(port, val, UARTDM_DMEN); 532 533 msm_reset_dm_count(port, count); 534 535 if (msm_port->is_uartdm > UARTDM_1P3) 536 msm_write(port, val, UARTDM_DMEN); 537 538 dma_async_issue_pending(dma->chan); 539 return 0; 540 unmap: 541 dma_unmap_single(port->dev, dma->phys, count, dma->dir); 542 return ret; 543 } 544 545 static void msm_complete_rx_dma(void *args) 546 { 547 struct msm_port *msm_port = args; 548 struct uart_port *port = &msm_port->uart; 549 struct tty_port *tport = &port->state->port; 550 struct msm_dma *dma = &msm_port->rx_dma; 551 int count = 0, i, sysrq; 552 unsigned long flags; 553 u32 val; 554 555 spin_lock_irqsave(&port->lock, flags); 556 557 /* Already stopped */ 558 if (!dma->count) 559 goto done; 560 561 val = msm_read(port, UARTDM_DMEN); 562 val &= ~dma->enable_bit; 563 msm_write(port, val, UARTDM_DMEN); 564 565 if (msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN) { 566 port->icount.overrun++; 567 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 568 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 569 } 570 571 count = msm_read(port, UARTDM_RX_TOTAL_SNAP); 572 573 port->icount.rx += count; 574 575 dma->count = 0; 576 577 dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 578 579 for (i = 0; i < count; i++) { 580 char flag = TTY_NORMAL; 581 582 if (msm_port->break_detected && dma->virt[i] == 0) { 583 port->icount.brk++; 584 flag = TTY_BREAK; 585 msm_port->break_detected = false; 586 if (uart_handle_break(port)) 587 continue; 588 } 589 590 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 591 flag = TTY_NORMAL; 592 593 spin_unlock_irqrestore(&port->lock, flags); 594 sysrq = uart_handle_sysrq_char(port, dma->virt[i]); 595 spin_lock_irqsave(&port->lock, flags); 596 if (!sysrq) 597 tty_insert_flip_char(tport, dma->virt[i], flag); 598 } 599 600 msm_start_rx_dma(msm_port); 601 done: 602 spin_unlock_irqrestore(&port->lock, flags); 603 604 if (count) 605 tty_flip_buffer_push(tport); 606 } 607 608 static void msm_start_rx_dma(struct msm_port *msm_port) 609 { 610 struct msm_dma *dma = &msm_port->rx_dma; 611 struct uart_port *uart = &msm_port->uart; 612 u32 val; 613 int ret; 614 615 if (IS_ENABLED(CONFIG_CONSOLE_POLL)) 616 return; 617 618 if (!dma->chan) 619 return; 620 621 dma->phys = dma_map_single(uart->dev, dma->virt, 622 UARTDM_RX_SIZE, dma->dir); 623 ret = dma_mapping_error(uart->dev, dma->phys); 624 if (ret) 625 goto sw_mode; 626 627 dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys, 628 UARTDM_RX_SIZE, DMA_DEV_TO_MEM, 629 DMA_PREP_INTERRUPT); 630 if (!dma->desc) 631 goto unmap; 632 633 dma->desc->callback = msm_complete_rx_dma; 634 dma->desc->callback_param = msm_port; 635 636 dma->cookie = dmaengine_submit(dma->desc); 637 ret = dma_submit_error(dma->cookie); 638 if (ret) 639 goto unmap; 640 /* 641 * Using DMA for FIFO off-load, no need for "Rx FIFO over 642 * watermark" or "stale" interrupts, disable them 643 */ 644 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE); 645 646 /* 647 * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3), 648 * we need RXSTALE to flush input DMA fifo to memory 649 */ 650 if (msm_port->is_uartdm < UARTDM_1P4) 651 msm_port->imr |= MSM_UART_IMR_RXSTALE; 652 653 msm_write(uart, msm_port->imr, MSM_UART_IMR); 654 655 dma->count = UARTDM_RX_SIZE; 656 657 dma_async_issue_pending(dma->chan); 658 659 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 660 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 661 662 val = msm_read(uart, UARTDM_DMEN); 663 val |= dma->enable_bit; 664 665 if (msm_port->is_uartdm < UARTDM_1P4) 666 msm_write(uart, val, UARTDM_DMEN); 667 668 msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX); 669 670 if (msm_port->is_uartdm > UARTDM_1P3) 671 msm_write(uart, val, UARTDM_DMEN); 672 673 return; 674 unmap: 675 dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir); 676 677 sw_mode: 678 /* 679 * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN), 680 * receiver must be reset. 681 */ 682 msm_write(uart, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); 683 msm_write(uart, MSM_UART_CR_RX_ENABLE, MSM_UART_CR); 684 685 msm_write(uart, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 686 msm_write(uart, 0xFFFFFF, UARTDM_DMRX); 687 msm_write(uart, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 688 689 /* Re-enable RX interrupts */ 690 msm_port->imr |= MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE; 691 msm_write(uart, msm_port->imr, MSM_UART_IMR); 692 } 693 694 static void msm_stop_rx(struct uart_port *port) 695 { 696 struct msm_port *msm_port = to_msm_port(port); 697 struct msm_dma *dma = &msm_port->rx_dma; 698 699 msm_port->imr &= ~(MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE); 700 msm_write(port, msm_port->imr, MSM_UART_IMR); 701 702 if (dma->chan) 703 msm_stop_dma(port, dma); 704 } 705 706 static void msm_enable_ms(struct uart_port *port) 707 { 708 struct msm_port *msm_port = to_msm_port(port); 709 710 msm_port->imr |= MSM_UART_IMR_DELTA_CTS; 711 msm_write(port, msm_port->imr, MSM_UART_IMR); 712 } 713 714 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr) 715 __must_hold(&port->lock) 716 { 717 struct tty_port *tport = &port->state->port; 718 unsigned int sr; 719 int count = 0; 720 struct msm_port *msm_port = to_msm_port(port); 721 722 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) { 723 port->icount.overrun++; 724 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 725 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 726 } 727 728 if (misr & MSM_UART_IMR_RXSTALE) { 729 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 730 msm_port->old_snap_state; 731 msm_port->old_snap_state = 0; 732 } else { 733 count = 4 * (msm_read(port, MSM_UART_RFWR)); 734 msm_port->old_snap_state += count; 735 } 736 737 /* TODO: Precise error reporting */ 738 739 port->icount.rx += count; 740 741 while (count > 0) { 742 unsigned char buf[4]; 743 int sysrq, r_count, i; 744 745 sr = msm_read(port, MSM_UART_SR); 746 if ((sr & MSM_UART_SR_RX_READY) == 0) { 747 msm_port->old_snap_state -= count; 748 break; 749 } 750 751 ioread32_rep(port->membase + UARTDM_RF, buf, 1); 752 r_count = min_t(int, count, sizeof(buf)); 753 754 for (i = 0; i < r_count; i++) { 755 char flag = TTY_NORMAL; 756 757 if (msm_port->break_detected && buf[i] == 0) { 758 port->icount.brk++; 759 flag = TTY_BREAK; 760 msm_port->break_detected = false; 761 if (uart_handle_break(port)) 762 continue; 763 } 764 765 if (!(port->read_status_mask & MSM_UART_SR_RX_BREAK)) 766 flag = TTY_NORMAL; 767 768 spin_unlock(&port->lock); 769 sysrq = uart_handle_sysrq_char(port, buf[i]); 770 spin_lock(&port->lock); 771 if (!sysrq) 772 tty_insert_flip_char(tport, buf[i], flag); 773 } 774 count -= r_count; 775 } 776 777 tty_flip_buffer_push(tport); 778 779 if (misr & (MSM_UART_IMR_RXSTALE)) 780 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 781 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 782 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 783 784 /* Try to use DMA */ 785 msm_start_rx_dma(msm_port); 786 } 787 788 static void msm_handle_rx(struct uart_port *port) 789 __must_hold(&port->lock) 790 { 791 struct tty_port *tport = &port->state->port; 792 unsigned int sr; 793 794 /* 795 * Handle overrun. My understanding of the hardware is that overrun 796 * is not tied to the RX buffer, so we handle the case out of band. 797 */ 798 if ((msm_read(port, MSM_UART_SR) & MSM_UART_SR_OVERRUN)) { 799 port->icount.overrun++; 800 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 801 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 802 } 803 804 /* and now the main RX loop */ 805 while ((sr = msm_read(port, MSM_UART_SR)) & MSM_UART_SR_RX_READY) { 806 unsigned int c; 807 char flag = TTY_NORMAL; 808 int sysrq; 809 810 c = msm_read(port, MSM_UART_RF); 811 812 if (sr & MSM_UART_SR_RX_BREAK) { 813 port->icount.brk++; 814 if (uart_handle_break(port)) 815 continue; 816 } else if (sr & MSM_UART_SR_PAR_FRAME_ERR) { 817 port->icount.frame++; 818 } else { 819 port->icount.rx++; 820 } 821 822 /* Mask conditions we're ignorning. */ 823 sr &= port->read_status_mask; 824 825 if (sr & MSM_UART_SR_RX_BREAK) 826 flag = TTY_BREAK; 827 else if (sr & MSM_UART_SR_PAR_FRAME_ERR) 828 flag = TTY_FRAME; 829 830 spin_unlock(&port->lock); 831 sysrq = uart_handle_sysrq_char(port, c); 832 spin_lock(&port->lock); 833 if (!sysrq) 834 tty_insert_flip_char(tport, c, flag); 835 } 836 837 tty_flip_buffer_push(tport); 838 } 839 840 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count) 841 { 842 struct circ_buf *xmit = &port->state->xmit; 843 struct msm_port *msm_port = to_msm_port(port); 844 unsigned int num_chars; 845 unsigned int tf_pointer = 0; 846 void __iomem *tf; 847 848 if (msm_port->is_uartdm) 849 tf = port->membase + UARTDM_TF; 850 else 851 tf = port->membase + MSM_UART_TF; 852 853 if (tx_count && msm_port->is_uartdm) 854 msm_reset_dm_count(port, tx_count); 855 856 while (tf_pointer < tx_count) { 857 int i; 858 char buf[4] = { 0 }; 859 860 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 861 break; 862 863 if (msm_port->is_uartdm) 864 num_chars = min(tx_count - tf_pointer, 865 (unsigned int)sizeof(buf)); 866 else 867 num_chars = 1; 868 869 for (i = 0; i < num_chars; i++) { 870 buf[i] = xmit->buf[xmit->tail + i]; 871 port->icount.tx++; 872 } 873 874 iowrite32_rep(tf, buf, 1); 875 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1); 876 tf_pointer += num_chars; 877 } 878 879 /* disable tx interrupts if nothing more to send */ 880 if (uart_circ_empty(xmit)) 881 msm_stop_tx(port); 882 883 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 884 uart_write_wakeup(port); 885 } 886 887 static void msm_handle_tx(struct uart_port *port) 888 { 889 struct msm_port *msm_port = to_msm_port(port); 890 struct circ_buf *xmit = &msm_port->uart.state->xmit; 891 struct msm_dma *dma = &msm_port->tx_dma; 892 unsigned int pio_count, dma_count, dma_min; 893 char buf[4] = { 0 }; 894 void __iomem *tf; 895 int err = 0; 896 897 if (port->x_char) { 898 if (msm_port->is_uartdm) 899 tf = port->membase + UARTDM_TF; 900 else 901 tf = port->membase + MSM_UART_TF; 902 903 buf[0] = port->x_char; 904 905 if (msm_port->is_uartdm) 906 msm_reset_dm_count(port, 1); 907 908 iowrite32_rep(tf, buf, 1); 909 port->icount.tx++; 910 port->x_char = 0; 911 return; 912 } 913 914 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) { 915 msm_stop_tx(port); 916 return; 917 } 918 919 pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 920 dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 921 922 dma_min = 1; /* Always DMA */ 923 if (msm_port->is_uartdm > UARTDM_1P3) { 924 dma_count = UARTDM_TX_AIGN(dma_count); 925 dma_min = UARTDM_BURST_SIZE; 926 } else { 927 if (dma_count > UARTDM_TX_MAX) 928 dma_count = UARTDM_TX_MAX; 929 } 930 931 if (pio_count > port->fifosize) 932 pio_count = port->fifosize; 933 934 if (!dma->chan || dma_count < dma_min) 935 msm_handle_tx_pio(port, pio_count); 936 else 937 err = msm_handle_tx_dma(msm_port, dma_count); 938 939 if (err) /* fall back to PIO mode */ 940 msm_handle_tx_pio(port, pio_count); 941 } 942 943 static void msm_handle_delta_cts(struct uart_port *port) 944 { 945 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); 946 port->icount.cts++; 947 wake_up_interruptible(&port->state->port.delta_msr_wait); 948 } 949 950 static irqreturn_t msm_uart_irq(int irq, void *dev_id) 951 { 952 struct uart_port *port = dev_id; 953 struct msm_port *msm_port = to_msm_port(port); 954 struct msm_dma *dma = &msm_port->rx_dma; 955 unsigned long flags; 956 unsigned int misr; 957 u32 val; 958 959 spin_lock_irqsave(&port->lock, flags); 960 misr = msm_read(port, MSM_UART_MISR); 961 msm_write(port, 0, MSM_UART_IMR); /* disable interrupt */ 962 963 if (misr & MSM_UART_IMR_RXBREAK_START) { 964 msm_port->break_detected = true; 965 msm_write(port, MSM_UART_CR_CMD_RESET_RXBREAK_START, MSM_UART_CR); 966 } 967 968 if (misr & (MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE)) { 969 if (dma->count) { 970 val = MSM_UART_CR_CMD_STALE_EVENT_DISABLE; 971 msm_write(port, val, MSM_UART_CR); 972 val = MSM_UART_CR_CMD_RESET_STALE_INT; 973 msm_write(port, val, MSM_UART_CR); 974 /* 975 * Flush DMA input fifo to memory, this will also 976 * trigger DMA RX completion 977 */ 978 dmaengine_terminate_all(dma->chan); 979 } else if (msm_port->is_uartdm) { 980 msm_handle_rx_dm(port, misr); 981 } else { 982 msm_handle_rx(port); 983 } 984 } 985 if (misr & MSM_UART_IMR_TXLEV) 986 msm_handle_tx(port); 987 if (misr & MSM_UART_IMR_DELTA_CTS) 988 msm_handle_delta_cts(port); 989 990 msm_write(port, msm_port->imr, MSM_UART_IMR); /* restore interrupt */ 991 spin_unlock_irqrestore(&port->lock, flags); 992 993 return IRQ_HANDLED; 994 } 995 996 static unsigned int msm_tx_empty(struct uart_port *port) 997 { 998 return (msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 999 } 1000 1001 static unsigned int msm_get_mctrl(struct uart_port *port) 1002 { 1003 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 1004 } 1005 1006 static void msm_reset(struct uart_port *port) 1007 { 1008 struct msm_port *msm_port = to_msm_port(port); 1009 unsigned int mr; 1010 1011 /* reset everything */ 1012 msm_write(port, MSM_UART_CR_CMD_RESET_RX, MSM_UART_CR); 1013 msm_write(port, MSM_UART_CR_CMD_RESET_TX, MSM_UART_CR); 1014 msm_write(port, MSM_UART_CR_CMD_RESET_ERR, MSM_UART_CR); 1015 msm_write(port, MSM_UART_CR_CMD_RESET_BREAK_INT, MSM_UART_CR); 1016 msm_write(port, MSM_UART_CR_CMD_RESET_CTS, MSM_UART_CR); 1017 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); 1018 mr = msm_read(port, MSM_UART_MR1); 1019 mr &= ~MSM_UART_MR1_RX_RDY_CTL; 1020 msm_write(port, mr, MSM_UART_MR1); 1021 1022 /* Disable DM modes */ 1023 if (msm_port->is_uartdm) 1024 msm_write(port, 0, UARTDM_DMEN); 1025 } 1026 1027 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 1028 { 1029 unsigned int mr; 1030 1031 mr = msm_read(port, MSM_UART_MR1); 1032 1033 if (!(mctrl & TIOCM_RTS)) { 1034 mr &= ~MSM_UART_MR1_RX_RDY_CTL; 1035 msm_write(port, mr, MSM_UART_MR1); 1036 msm_write(port, MSM_UART_CR_CMD_RESET_RFR, MSM_UART_CR); 1037 } else { 1038 mr |= MSM_UART_MR1_RX_RDY_CTL; 1039 msm_write(port, mr, MSM_UART_MR1); 1040 } 1041 } 1042 1043 static void msm_break_ctl(struct uart_port *port, int break_ctl) 1044 { 1045 if (break_ctl) 1046 msm_write(port, MSM_UART_CR_CMD_START_BREAK, MSM_UART_CR); 1047 else 1048 msm_write(port, MSM_UART_CR_CMD_STOP_BREAK, MSM_UART_CR); 1049 } 1050 1051 struct msm_baud_map { 1052 u16 divisor; 1053 u8 code; 1054 u8 rxstale; 1055 }; 1056 1057 static const struct msm_baud_map * 1058 msm_find_best_baud(struct uart_port *port, unsigned int baud, 1059 unsigned long *rate) 1060 { 1061 struct msm_port *msm_port = to_msm_port(port); 1062 unsigned int divisor, result; 1063 unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX; 1064 const struct msm_baud_map *entry, *end, *best; 1065 static const struct msm_baud_map table[] = { 1066 { 1, 0xff, 31 }, 1067 { 2, 0xee, 16 }, 1068 { 3, 0xdd, 8 }, 1069 { 4, 0xcc, 6 }, 1070 { 6, 0xbb, 6 }, 1071 { 8, 0xaa, 6 }, 1072 { 12, 0x99, 6 }, 1073 { 16, 0x88, 1 }, 1074 { 24, 0x77, 1 }, 1075 { 32, 0x66, 1 }, 1076 { 48, 0x55, 1 }, 1077 { 96, 0x44, 1 }, 1078 { 192, 0x33, 1 }, 1079 { 384, 0x22, 1 }, 1080 { 768, 0x11, 1 }, 1081 { 1536, 0x00, 1 }, 1082 }; 1083 1084 best = table; /* Default to smallest divider */ 1085 target = clk_round_rate(msm_port->clk, 16 * baud); 1086 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1087 1088 end = table + ARRAY_SIZE(table); 1089 entry = table; 1090 while (entry < end) { 1091 if (entry->divisor <= divisor) { 1092 result = target / entry->divisor / 16; 1093 diff = abs(result - baud); 1094 1095 /* Keep track of best entry */ 1096 if (diff < best_diff) { 1097 best_diff = diff; 1098 best = entry; 1099 best_rate = target; 1100 } 1101 1102 if (result == baud) 1103 break; 1104 } else if (entry->divisor > divisor) { 1105 old = target; 1106 target = clk_round_rate(msm_port->clk, old + 1); 1107 /* 1108 * The rate didn't get any faster so we can't do 1109 * better at dividing it down 1110 */ 1111 if (target == old) 1112 break; 1113 1114 /* Start the divisor search over at this new rate */ 1115 entry = table; 1116 divisor = DIV_ROUND_CLOSEST(target, 16 * baud); 1117 continue; 1118 } 1119 entry++; 1120 } 1121 1122 *rate = best_rate; 1123 return best; 1124 } 1125 1126 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud, 1127 unsigned long *saved_flags) 1128 { 1129 unsigned int rxstale, watermark, mask; 1130 struct msm_port *msm_port = to_msm_port(port); 1131 const struct msm_baud_map *entry; 1132 unsigned long flags, rate; 1133 1134 flags = *saved_flags; 1135 spin_unlock_irqrestore(&port->lock, flags); 1136 1137 entry = msm_find_best_baud(port, baud, &rate); 1138 clk_set_rate(msm_port->clk, rate); 1139 baud = rate / 16 / entry->divisor; 1140 1141 spin_lock_irqsave(&port->lock, flags); 1142 *saved_flags = flags; 1143 port->uartclk = rate; 1144 1145 msm_write(port, entry->code, MSM_UART_CSR); 1146 1147 /* RX stale watermark */ 1148 rxstale = entry->rxstale; 1149 watermark = MSM_UART_IPR_STALE_LSB & rxstale; 1150 if (msm_port->is_uartdm) { 1151 mask = MSM_UART_DM_IPR_STALE_TIMEOUT_MSB; 1152 } else { 1153 watermark |= MSM_UART_IPR_RXSTALE_LAST; 1154 mask = MSM_UART_IPR_STALE_TIMEOUT_MSB; 1155 } 1156 1157 watermark |= mask & (rxstale << 2); 1158 1159 msm_write(port, watermark, MSM_UART_IPR); 1160 1161 /* set RX watermark */ 1162 watermark = (port->fifosize * 3) / 4; 1163 msm_write(port, watermark, MSM_UART_RFWR); 1164 1165 /* set TX watermark */ 1166 msm_write(port, 10, MSM_UART_TFWR); 1167 1168 msm_write(port, MSM_UART_CR_CMD_PROTECTION_EN, MSM_UART_CR); 1169 msm_reset(port); 1170 1171 /* Enable RX and TX */ 1172 msm_write(port, MSM_UART_CR_TX_ENABLE | MSM_UART_CR_RX_ENABLE, MSM_UART_CR); 1173 1174 /* turn on RX and CTS interrupts */ 1175 msm_port->imr = MSM_UART_IMR_RXLEV | MSM_UART_IMR_RXSTALE | 1176 MSM_UART_IMR_CURRENT_CTS | MSM_UART_IMR_RXBREAK_START; 1177 1178 msm_write(port, msm_port->imr, MSM_UART_IMR); 1179 1180 if (msm_port->is_uartdm) { 1181 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 1182 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1183 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 1184 } 1185 1186 return baud; 1187 } 1188 1189 static void msm_init_clock(struct uart_port *port) 1190 { 1191 struct msm_port *msm_port = to_msm_port(port); 1192 1193 clk_prepare_enable(msm_port->clk); 1194 clk_prepare_enable(msm_port->pclk); 1195 msm_serial_set_mnd_regs(port); 1196 } 1197 1198 static int msm_startup(struct uart_port *port) 1199 { 1200 struct msm_port *msm_port = to_msm_port(port); 1201 unsigned int data, rfr_level, mask; 1202 int ret; 1203 1204 snprintf(msm_port->name, sizeof(msm_port->name), 1205 "msm_serial%d", port->line); 1206 1207 msm_init_clock(port); 1208 1209 if (likely(port->fifosize > 12)) 1210 rfr_level = port->fifosize - 12; 1211 else 1212 rfr_level = port->fifosize; 1213 1214 /* set automatic RFR level */ 1215 data = msm_read(port, MSM_UART_MR1); 1216 1217 if (msm_port->is_uartdm) 1218 mask = MSM_UART_DM_MR1_AUTO_RFR_LEVEL1; 1219 else 1220 mask = MSM_UART_MR1_AUTO_RFR_LEVEL1; 1221 1222 data &= ~mask; 1223 data &= ~MSM_UART_MR1_AUTO_RFR_LEVEL0; 1224 data |= mask & (rfr_level << 2); 1225 data |= MSM_UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 1226 msm_write(port, data, MSM_UART_MR1); 1227 1228 if (msm_port->is_uartdm) { 1229 msm_request_tx_dma(msm_port, msm_port->uart.mapbase); 1230 msm_request_rx_dma(msm_port, msm_port->uart.mapbase); 1231 } 1232 1233 ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH, 1234 msm_port->name, port); 1235 if (unlikely(ret)) 1236 goto err_irq; 1237 1238 return 0; 1239 1240 err_irq: 1241 if (msm_port->is_uartdm) 1242 msm_release_dma(msm_port); 1243 1244 clk_disable_unprepare(msm_port->pclk); 1245 clk_disable_unprepare(msm_port->clk); 1246 1247 return ret; 1248 } 1249 1250 static void msm_shutdown(struct uart_port *port) 1251 { 1252 struct msm_port *msm_port = to_msm_port(port); 1253 1254 msm_port->imr = 0; 1255 msm_write(port, 0, MSM_UART_IMR); /* disable interrupts */ 1256 1257 if (msm_port->is_uartdm) 1258 msm_release_dma(msm_port); 1259 1260 clk_disable_unprepare(msm_port->clk); 1261 1262 free_irq(port->irq, port); 1263 } 1264 1265 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 1266 const struct ktermios *old) 1267 { 1268 struct msm_port *msm_port = to_msm_port(port); 1269 struct msm_dma *dma = &msm_port->rx_dma; 1270 unsigned long flags; 1271 unsigned int baud, mr; 1272 1273 spin_lock_irqsave(&port->lock, flags); 1274 1275 if (dma->chan) /* Terminate if any */ 1276 msm_stop_dma(port, dma); 1277 1278 /* calculate and set baud rate */ 1279 baud = uart_get_baud_rate(port, termios, old, 300, 4000000); 1280 baud = msm_set_baud_rate(port, baud, &flags); 1281 if (tty_termios_baud_rate(termios)) 1282 tty_termios_encode_baud_rate(termios, baud, baud); 1283 1284 /* calculate parity */ 1285 mr = msm_read(port, MSM_UART_MR2); 1286 mr &= ~MSM_UART_MR2_PARITY_MODE; 1287 if (termios->c_cflag & PARENB) { 1288 if (termios->c_cflag & PARODD) 1289 mr |= MSM_UART_MR2_PARITY_MODE_ODD; 1290 else if (termios->c_cflag & CMSPAR) 1291 mr |= MSM_UART_MR2_PARITY_MODE_SPACE; 1292 else 1293 mr |= MSM_UART_MR2_PARITY_MODE_EVEN; 1294 } 1295 1296 /* calculate bits per char */ 1297 mr &= ~MSM_UART_MR2_BITS_PER_CHAR; 1298 switch (termios->c_cflag & CSIZE) { 1299 case CS5: 1300 mr |= MSM_UART_MR2_BITS_PER_CHAR_5; 1301 break; 1302 case CS6: 1303 mr |= MSM_UART_MR2_BITS_PER_CHAR_6; 1304 break; 1305 case CS7: 1306 mr |= MSM_UART_MR2_BITS_PER_CHAR_7; 1307 break; 1308 case CS8: 1309 default: 1310 mr |= MSM_UART_MR2_BITS_PER_CHAR_8; 1311 break; 1312 } 1313 1314 /* calculate stop bits */ 1315 mr &= ~(MSM_UART_MR2_STOP_BIT_LEN_ONE | MSM_UART_MR2_STOP_BIT_LEN_TWO); 1316 if (termios->c_cflag & CSTOPB) 1317 mr |= MSM_UART_MR2_STOP_BIT_LEN_TWO; 1318 else 1319 mr |= MSM_UART_MR2_STOP_BIT_LEN_ONE; 1320 1321 /* set parity, bits per char, and stop bit */ 1322 msm_write(port, mr, MSM_UART_MR2); 1323 1324 /* calculate and set hardware flow control */ 1325 mr = msm_read(port, MSM_UART_MR1); 1326 mr &= ~(MSM_UART_MR1_CTS_CTL | MSM_UART_MR1_RX_RDY_CTL); 1327 if (termios->c_cflag & CRTSCTS) { 1328 mr |= MSM_UART_MR1_CTS_CTL; 1329 mr |= MSM_UART_MR1_RX_RDY_CTL; 1330 } 1331 msm_write(port, mr, MSM_UART_MR1); 1332 1333 /* Configure status bits to ignore based on termio flags. */ 1334 port->read_status_mask = 0; 1335 if (termios->c_iflag & INPCK) 1336 port->read_status_mask |= MSM_UART_SR_PAR_FRAME_ERR; 1337 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1338 port->read_status_mask |= MSM_UART_SR_RX_BREAK; 1339 1340 uart_update_timeout(port, termios->c_cflag, baud); 1341 1342 /* Try to use DMA */ 1343 msm_start_rx_dma(msm_port); 1344 1345 spin_unlock_irqrestore(&port->lock, flags); 1346 } 1347 1348 static const char *msm_type(struct uart_port *port) 1349 { 1350 return "MSM"; 1351 } 1352 1353 static void msm_release_port(struct uart_port *port) 1354 { 1355 struct platform_device *pdev = to_platform_device(port->dev); 1356 struct resource *uart_resource; 1357 resource_size_t size; 1358 1359 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1360 if (unlikely(!uart_resource)) 1361 return; 1362 size = resource_size(uart_resource); 1363 1364 release_mem_region(port->mapbase, size); 1365 iounmap(port->membase); 1366 port->membase = NULL; 1367 } 1368 1369 static int msm_request_port(struct uart_port *port) 1370 { 1371 struct platform_device *pdev = to_platform_device(port->dev); 1372 struct resource *uart_resource; 1373 resource_size_t size; 1374 int ret; 1375 1376 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1377 if (unlikely(!uart_resource)) 1378 return -ENXIO; 1379 1380 size = resource_size(uart_resource); 1381 1382 if (!request_mem_region(port->mapbase, size, "msm_serial")) 1383 return -EBUSY; 1384 1385 port->membase = ioremap(port->mapbase, size); 1386 if (!port->membase) { 1387 ret = -EBUSY; 1388 goto fail_release_port; 1389 } 1390 1391 return 0; 1392 1393 fail_release_port: 1394 release_mem_region(port->mapbase, size); 1395 return ret; 1396 } 1397 1398 static void msm_config_port(struct uart_port *port, int flags) 1399 { 1400 int ret; 1401 1402 if (flags & UART_CONFIG_TYPE) { 1403 port->type = PORT_MSM; 1404 ret = msm_request_port(port); 1405 if (ret) 1406 return; 1407 } 1408 } 1409 1410 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 1411 { 1412 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 1413 return -EINVAL; 1414 if (unlikely(port->irq != ser->irq)) 1415 return -EINVAL; 1416 return 0; 1417 } 1418 1419 static void msm_power(struct uart_port *port, unsigned int state, 1420 unsigned int oldstate) 1421 { 1422 struct msm_port *msm_port = to_msm_port(port); 1423 1424 switch (state) { 1425 case 0: 1426 clk_prepare_enable(msm_port->clk); 1427 clk_prepare_enable(msm_port->pclk); 1428 break; 1429 case 3: 1430 clk_disable_unprepare(msm_port->clk); 1431 clk_disable_unprepare(msm_port->pclk); 1432 break; 1433 default: 1434 pr_err("msm_serial: Unknown PM state %d\n", state); 1435 } 1436 } 1437 1438 #ifdef CONFIG_CONSOLE_POLL 1439 static int msm_poll_get_char_single(struct uart_port *port) 1440 { 1441 struct msm_port *msm_port = to_msm_port(port); 1442 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : MSM_UART_RF; 1443 1444 if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) 1445 return NO_POLL_CHAR; 1446 1447 return msm_read(port, rf_reg) & 0xff; 1448 } 1449 1450 static int msm_poll_get_char_dm(struct uart_port *port) 1451 { 1452 int c; 1453 static u32 slop; 1454 static int count; 1455 unsigned char *sp = (unsigned char *)&slop; 1456 1457 /* Check if a previous read had more than one char */ 1458 if (count) { 1459 c = sp[sizeof(slop) - count]; 1460 count--; 1461 /* Or if FIFO is empty */ 1462 } else if (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_RX_READY)) { 1463 /* 1464 * If RX packing buffer has less than a word, force stale to 1465 * push contents into RX FIFO 1466 */ 1467 count = msm_read(port, UARTDM_RXFS); 1468 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK; 1469 if (count) { 1470 msm_write(port, MSM_UART_CR_CMD_FORCE_STALE, MSM_UART_CR); 1471 slop = msm_read(port, UARTDM_RF); 1472 c = sp[0]; 1473 count--; 1474 msm_write(port, MSM_UART_CR_CMD_RESET_STALE_INT, MSM_UART_CR); 1475 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 1476 msm_write(port, MSM_UART_CR_CMD_STALE_EVENT_ENABLE, MSM_UART_CR); 1477 } else { 1478 c = NO_POLL_CHAR; 1479 } 1480 /* FIFO has a word */ 1481 } else { 1482 slop = msm_read(port, UARTDM_RF); 1483 c = sp[0]; 1484 count = sizeof(slop) - 1; 1485 } 1486 1487 return c; 1488 } 1489 1490 static int msm_poll_get_char(struct uart_port *port) 1491 { 1492 u32 imr; 1493 int c; 1494 struct msm_port *msm_port = to_msm_port(port); 1495 1496 /* Disable all interrupts */ 1497 imr = msm_read(port, MSM_UART_IMR); 1498 msm_write(port, 0, MSM_UART_IMR); 1499 1500 if (msm_port->is_uartdm) 1501 c = msm_poll_get_char_dm(port); 1502 else 1503 c = msm_poll_get_char_single(port); 1504 1505 /* Enable interrupts */ 1506 msm_write(port, imr, MSM_UART_IMR); 1507 1508 return c; 1509 } 1510 1511 static void msm_poll_put_char(struct uart_port *port, unsigned char c) 1512 { 1513 u32 imr; 1514 struct msm_port *msm_port = to_msm_port(port); 1515 1516 /* Disable all interrupts */ 1517 imr = msm_read(port, MSM_UART_IMR); 1518 msm_write(port, 0, MSM_UART_IMR); 1519 1520 if (msm_port->is_uartdm) 1521 msm_reset_dm_count(port, 1); 1522 1523 /* Wait until FIFO is empty */ 1524 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1525 cpu_relax(); 1526 1527 /* Write a character */ 1528 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : MSM_UART_TF); 1529 1530 /* Wait until FIFO is empty */ 1531 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1532 cpu_relax(); 1533 1534 /* Enable interrupts */ 1535 msm_write(port, imr, MSM_UART_IMR); 1536 } 1537 #endif 1538 1539 static const struct uart_ops msm_uart_pops = { 1540 .tx_empty = msm_tx_empty, 1541 .set_mctrl = msm_set_mctrl, 1542 .get_mctrl = msm_get_mctrl, 1543 .stop_tx = msm_stop_tx, 1544 .start_tx = msm_start_tx, 1545 .stop_rx = msm_stop_rx, 1546 .enable_ms = msm_enable_ms, 1547 .break_ctl = msm_break_ctl, 1548 .startup = msm_startup, 1549 .shutdown = msm_shutdown, 1550 .set_termios = msm_set_termios, 1551 .type = msm_type, 1552 .release_port = msm_release_port, 1553 .request_port = msm_request_port, 1554 .config_port = msm_config_port, 1555 .verify_port = msm_verify_port, 1556 .pm = msm_power, 1557 #ifdef CONFIG_CONSOLE_POLL 1558 .poll_get_char = msm_poll_get_char, 1559 .poll_put_char = msm_poll_put_char, 1560 #endif 1561 }; 1562 1563 static struct msm_port msm_uart_ports[] = { 1564 { 1565 .uart = { 1566 .iotype = UPIO_MEM, 1567 .ops = &msm_uart_pops, 1568 .flags = UPF_BOOT_AUTOCONF, 1569 .fifosize = 64, 1570 .line = 0, 1571 }, 1572 }, 1573 { 1574 .uart = { 1575 .iotype = UPIO_MEM, 1576 .ops = &msm_uart_pops, 1577 .flags = UPF_BOOT_AUTOCONF, 1578 .fifosize = 64, 1579 .line = 1, 1580 }, 1581 }, 1582 { 1583 .uart = { 1584 .iotype = UPIO_MEM, 1585 .ops = &msm_uart_pops, 1586 .flags = UPF_BOOT_AUTOCONF, 1587 .fifosize = 64, 1588 .line = 2, 1589 }, 1590 }, 1591 }; 1592 1593 #define MSM_UART_NR ARRAY_SIZE(msm_uart_ports) 1594 1595 static inline struct uart_port *msm_get_port_from_line(unsigned int line) 1596 { 1597 return &msm_uart_ports[line].uart; 1598 } 1599 1600 #ifdef CONFIG_SERIAL_MSM_CONSOLE 1601 static void __msm_console_write(struct uart_port *port, const char *s, 1602 unsigned int count, bool is_uartdm) 1603 { 1604 unsigned long flags; 1605 int i; 1606 int num_newlines = 0; 1607 bool replaced = false; 1608 void __iomem *tf; 1609 int locked = 1; 1610 1611 if (is_uartdm) 1612 tf = port->membase + UARTDM_TF; 1613 else 1614 tf = port->membase + MSM_UART_TF; 1615 1616 /* Account for newlines that will get a carriage return added */ 1617 for (i = 0; i < count; i++) 1618 if (s[i] == '\n') 1619 num_newlines++; 1620 count += num_newlines; 1621 1622 local_irq_save(flags); 1623 1624 if (port->sysrq) 1625 locked = 0; 1626 else if (oops_in_progress) 1627 locked = spin_trylock(&port->lock); 1628 else 1629 spin_lock(&port->lock); 1630 1631 if (is_uartdm) 1632 msm_reset_dm_count(port, count); 1633 1634 i = 0; 1635 while (i < count) { 1636 int j; 1637 unsigned int num_chars; 1638 char buf[4] = { 0 }; 1639 1640 if (is_uartdm) 1641 num_chars = min(count - i, (unsigned int)sizeof(buf)); 1642 else 1643 num_chars = 1; 1644 1645 for (j = 0; j < num_chars; j++) { 1646 char c = *s; 1647 1648 if (c == '\n' && !replaced) { 1649 buf[j] = '\r'; 1650 j++; 1651 replaced = true; 1652 } 1653 if (j < num_chars) { 1654 buf[j] = c; 1655 s++; 1656 replaced = false; 1657 } 1658 } 1659 1660 while (!(msm_read(port, MSM_UART_SR) & MSM_UART_SR_TX_READY)) 1661 cpu_relax(); 1662 1663 iowrite32_rep(tf, buf, 1); 1664 i += num_chars; 1665 } 1666 1667 if (locked) 1668 spin_unlock(&port->lock); 1669 1670 local_irq_restore(flags); 1671 } 1672 1673 static void msm_console_write(struct console *co, const char *s, 1674 unsigned int count) 1675 { 1676 struct uart_port *port; 1677 struct msm_port *msm_port; 1678 1679 BUG_ON(co->index < 0 || co->index >= MSM_UART_NR); 1680 1681 port = msm_get_port_from_line(co->index); 1682 msm_port = to_msm_port(port); 1683 1684 __msm_console_write(port, s, count, msm_port->is_uartdm); 1685 } 1686 1687 static int msm_console_setup(struct console *co, char *options) 1688 { 1689 struct uart_port *port; 1690 int baud = 115200; 1691 int bits = 8; 1692 int parity = 'n'; 1693 int flow = 'n'; 1694 1695 if (unlikely(co->index >= MSM_UART_NR || co->index < 0)) 1696 return -ENXIO; 1697 1698 port = msm_get_port_from_line(co->index); 1699 1700 if (unlikely(!port->membase)) 1701 return -ENXIO; 1702 1703 msm_init_clock(port); 1704 1705 if (options) 1706 uart_parse_options(options, &baud, &parity, &bits, &flow); 1707 1708 pr_info("msm_serial: console setup on port #%d\n", port->line); 1709 1710 return uart_set_options(port, co, baud, parity, bits, flow); 1711 } 1712 1713 static void 1714 msm_serial_early_write(struct console *con, const char *s, unsigned n) 1715 { 1716 struct earlycon_device *dev = con->data; 1717 1718 __msm_console_write(&dev->port, s, n, false); 1719 } 1720 1721 static int __init 1722 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt) 1723 { 1724 if (!device->port.membase) 1725 return -ENODEV; 1726 1727 device->con->write = msm_serial_early_write; 1728 return 0; 1729 } 1730 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart", 1731 msm_serial_early_console_setup); 1732 1733 static void 1734 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n) 1735 { 1736 struct earlycon_device *dev = con->data; 1737 1738 __msm_console_write(&dev->port, s, n, true); 1739 } 1740 1741 static int __init 1742 msm_serial_early_console_setup_dm(struct earlycon_device *device, 1743 const char *opt) 1744 { 1745 if (!device->port.membase) 1746 return -ENODEV; 1747 1748 device->con->write = msm_serial_early_write_dm; 1749 return 0; 1750 } 1751 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm", 1752 msm_serial_early_console_setup_dm); 1753 1754 static struct uart_driver msm_uart_driver; 1755 1756 static struct console msm_console = { 1757 .name = "ttyMSM", 1758 .write = msm_console_write, 1759 .device = uart_console_device, 1760 .setup = msm_console_setup, 1761 .flags = CON_PRINTBUFFER, 1762 .index = -1, 1763 .data = &msm_uart_driver, 1764 }; 1765 1766 #define MSM_CONSOLE (&msm_console) 1767 1768 #else 1769 #define MSM_CONSOLE NULL 1770 #endif 1771 1772 static struct uart_driver msm_uart_driver = { 1773 .owner = THIS_MODULE, 1774 .driver_name = "msm_serial", 1775 .dev_name = "ttyMSM", 1776 .nr = MSM_UART_NR, 1777 .cons = MSM_CONSOLE, 1778 }; 1779 1780 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 1781 1782 static const struct of_device_id msm_uartdm_table[] = { 1783 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 }, 1784 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 }, 1785 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 }, 1786 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 }, 1787 { } 1788 }; 1789 1790 static int msm_serial_probe(struct platform_device *pdev) 1791 { 1792 struct msm_port *msm_port; 1793 struct resource *resource; 1794 struct uart_port *port; 1795 const struct of_device_id *id; 1796 int irq, line; 1797 1798 if (pdev->dev.of_node) 1799 line = of_alias_get_id(pdev->dev.of_node, "serial"); 1800 else 1801 line = pdev->id; 1802 1803 if (line < 0) 1804 line = atomic_inc_return(&msm_uart_next_id) - 1; 1805 1806 if (unlikely(line < 0 || line >= MSM_UART_NR)) 1807 return -ENXIO; 1808 1809 dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line); 1810 1811 port = msm_get_port_from_line(line); 1812 port->dev = &pdev->dev; 1813 msm_port = to_msm_port(port); 1814 1815 id = of_match_device(msm_uartdm_table, &pdev->dev); 1816 if (id) 1817 msm_port->is_uartdm = (unsigned long)id->data; 1818 else 1819 msm_port->is_uartdm = 0; 1820 1821 msm_port->clk = devm_clk_get(&pdev->dev, "core"); 1822 if (IS_ERR(msm_port->clk)) 1823 return PTR_ERR(msm_port->clk); 1824 1825 if (msm_port->is_uartdm) { 1826 msm_port->pclk = devm_clk_get(&pdev->dev, "iface"); 1827 if (IS_ERR(msm_port->pclk)) 1828 return PTR_ERR(msm_port->pclk); 1829 } 1830 1831 port->uartclk = clk_get_rate(msm_port->clk); 1832 dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk); 1833 1834 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1835 if (unlikely(!resource)) 1836 return -ENXIO; 1837 port->mapbase = resource->start; 1838 1839 irq = platform_get_irq(pdev, 0); 1840 if (unlikely(irq < 0)) 1841 return -ENXIO; 1842 port->irq = irq; 1843 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE); 1844 1845 platform_set_drvdata(pdev, port); 1846 1847 return uart_add_one_port(&msm_uart_driver, port); 1848 } 1849 1850 static int msm_serial_remove(struct platform_device *pdev) 1851 { 1852 struct uart_port *port = platform_get_drvdata(pdev); 1853 1854 uart_remove_one_port(&msm_uart_driver, port); 1855 1856 return 0; 1857 } 1858 1859 static const struct of_device_id msm_match_table[] = { 1860 { .compatible = "qcom,msm-uart" }, 1861 { .compatible = "qcom,msm-uartdm" }, 1862 {} 1863 }; 1864 MODULE_DEVICE_TABLE(of, msm_match_table); 1865 1866 static int __maybe_unused msm_serial_suspend(struct device *dev) 1867 { 1868 struct msm_port *port = dev_get_drvdata(dev); 1869 1870 uart_suspend_port(&msm_uart_driver, &port->uart); 1871 1872 return 0; 1873 } 1874 1875 static int __maybe_unused msm_serial_resume(struct device *dev) 1876 { 1877 struct msm_port *port = dev_get_drvdata(dev); 1878 1879 uart_resume_port(&msm_uart_driver, &port->uart); 1880 1881 return 0; 1882 } 1883 1884 static const struct dev_pm_ops msm_serial_dev_pm_ops = { 1885 SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume) 1886 }; 1887 1888 static struct platform_driver msm_platform_driver = { 1889 .remove = msm_serial_remove, 1890 .probe = msm_serial_probe, 1891 .driver = { 1892 .name = "msm_serial", 1893 .pm = &msm_serial_dev_pm_ops, 1894 .of_match_table = msm_match_table, 1895 }, 1896 }; 1897 1898 static int __init msm_serial_init(void) 1899 { 1900 int ret; 1901 1902 ret = uart_register_driver(&msm_uart_driver); 1903 if (unlikely(ret)) 1904 return ret; 1905 1906 ret = platform_driver_register(&msm_platform_driver); 1907 if (unlikely(ret)) 1908 uart_unregister_driver(&msm_uart_driver); 1909 1910 pr_info("msm_serial: driver initialized\n"); 1911 1912 return ret; 1913 } 1914 1915 static void __exit msm_serial_exit(void) 1916 { 1917 platform_driver_unregister(&msm_platform_driver); 1918 uart_unregister_driver(&msm_uart_driver); 1919 } 1920 1921 module_init(msm_serial_init); 1922 module_exit(msm_serial_exit); 1923 1924 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 1925 MODULE_DESCRIPTION("Driver for msm7x serial device"); 1926 MODULE_LICENSE("GPL"); 1927