1 /* 2 * Driver for msm7k serial device and console 3 * 4 * Copyright (C) 2007 Google, Inc. 5 * Author: Robert Love <rlove@google.com> 6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved. 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 19 # define SUPPORT_SYSRQ 20 #endif 21 22 #include <linux/atomic.h> 23 #include <linux/hrtimer.h> 24 #include <linux/module.h> 25 #include <linux/io.h> 26 #include <linux/ioport.h> 27 #include <linux/irq.h> 28 #include <linux/init.h> 29 #include <linux/console.h> 30 #include <linux/tty.h> 31 #include <linux/tty_flip.h> 32 #include <linux/serial_core.h> 33 #include <linux/serial.h> 34 #include <linux/clk.h> 35 #include <linux/platform_device.h> 36 #include <linux/delay.h> 37 #include <linux/of.h> 38 #include <linux/of_device.h> 39 40 #include "msm_serial.h" 41 42 struct msm_port { 43 struct uart_port uart; 44 char name[16]; 45 struct clk *clk; 46 struct clk *pclk; 47 unsigned int imr; 48 unsigned int *gsbi_base; 49 int is_uartdm; 50 unsigned int old_snap_state; 51 }; 52 53 static inline void wait_for_xmitr(struct uart_port *port, int bits) 54 { 55 if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) 56 while ((msm_read(port, UART_ISR) & bits) != bits) 57 cpu_relax(); 58 } 59 60 static void msm_stop_tx(struct uart_port *port) 61 { 62 struct msm_port *msm_port = UART_TO_MSM(port); 63 64 msm_port->imr &= ~UART_IMR_TXLEV; 65 msm_write(port, msm_port->imr, UART_IMR); 66 } 67 68 static void msm_start_tx(struct uart_port *port) 69 { 70 struct msm_port *msm_port = UART_TO_MSM(port); 71 72 msm_port->imr |= UART_IMR_TXLEV; 73 msm_write(port, msm_port->imr, UART_IMR); 74 } 75 76 static void msm_stop_rx(struct uart_port *port) 77 { 78 struct msm_port *msm_port = UART_TO_MSM(port); 79 80 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE); 81 msm_write(port, msm_port->imr, UART_IMR); 82 } 83 84 static void msm_enable_ms(struct uart_port *port) 85 { 86 struct msm_port *msm_port = UART_TO_MSM(port); 87 88 msm_port->imr |= UART_IMR_DELTA_CTS; 89 msm_write(port, msm_port->imr, UART_IMR); 90 } 91 92 static void handle_rx_dm(struct uart_port *port, unsigned int misr) 93 { 94 struct tty_struct *tty = port->state->port.tty; 95 unsigned int sr; 96 int count = 0; 97 struct msm_port *msm_port = UART_TO_MSM(port); 98 99 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 100 port->icount.overrun++; 101 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 102 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 103 } 104 105 if (misr & UART_IMR_RXSTALE) { 106 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) - 107 msm_port->old_snap_state; 108 msm_port->old_snap_state = 0; 109 } else { 110 count = 4 * (msm_read(port, UART_RFWR)); 111 msm_port->old_snap_state += count; 112 } 113 114 /* TODO: Precise error reporting */ 115 116 port->icount.rx += count; 117 118 while (count > 0) { 119 unsigned int c; 120 121 sr = msm_read(port, UART_SR); 122 if ((sr & UART_SR_RX_READY) == 0) { 123 msm_port->old_snap_state -= count; 124 break; 125 } 126 c = msm_read(port, UARTDM_RF); 127 if (sr & UART_SR_RX_BREAK) { 128 port->icount.brk++; 129 if (uart_handle_break(port)) 130 continue; 131 } else if (sr & UART_SR_PAR_FRAME_ERR) 132 port->icount.frame++; 133 134 /* TODO: handle sysrq */ 135 tty_insert_flip_string(tty, (char *) &c, 136 (count > 4) ? 4 : count); 137 count -= 4; 138 } 139 140 tty_flip_buffer_push(tty); 141 if (misr & (UART_IMR_RXSTALE)) 142 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 143 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 144 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 145 } 146 147 static void handle_rx(struct uart_port *port) 148 { 149 struct tty_struct *tty = port->state->port.tty; 150 unsigned int sr; 151 152 /* 153 * Handle overrun. My understanding of the hardware is that overrun 154 * is not tied to the RX buffer, so we handle the case out of band. 155 */ 156 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) { 157 port->icount.overrun++; 158 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 159 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 160 } 161 162 /* and now the main RX loop */ 163 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) { 164 unsigned int c; 165 char flag = TTY_NORMAL; 166 167 c = msm_read(port, UART_RF); 168 169 if (sr & UART_SR_RX_BREAK) { 170 port->icount.brk++; 171 if (uart_handle_break(port)) 172 continue; 173 } else if (sr & UART_SR_PAR_FRAME_ERR) { 174 port->icount.frame++; 175 } else { 176 port->icount.rx++; 177 } 178 179 /* Mask conditions we're ignorning. */ 180 sr &= port->read_status_mask; 181 182 if (sr & UART_SR_RX_BREAK) { 183 flag = TTY_BREAK; 184 } else if (sr & UART_SR_PAR_FRAME_ERR) { 185 flag = TTY_FRAME; 186 } 187 188 if (!uart_handle_sysrq_char(port, c)) 189 tty_insert_flip_char(tty, c, flag); 190 } 191 192 tty_flip_buffer_push(tty); 193 } 194 195 static void reset_dm_count(struct uart_port *port) 196 { 197 wait_for_xmitr(port, UART_ISR_TX_READY); 198 msm_write(port, 1, UARTDM_NCF_TX); 199 } 200 201 static void handle_tx(struct uart_port *port) 202 { 203 struct circ_buf *xmit = &port->state->xmit; 204 struct msm_port *msm_port = UART_TO_MSM(port); 205 int sent_tx; 206 207 if (port->x_char) { 208 if (msm_port->is_uartdm) 209 reset_dm_count(port); 210 211 msm_write(port, port->x_char, 212 msm_port->is_uartdm ? UARTDM_TF : UART_TF); 213 port->icount.tx++; 214 port->x_char = 0; 215 } 216 217 if (msm_port->is_uartdm) 218 reset_dm_count(port); 219 220 while (msm_read(port, UART_SR) & UART_SR_TX_READY) { 221 if (uart_circ_empty(xmit)) { 222 /* disable tx interrupts */ 223 msm_port->imr &= ~UART_IMR_TXLEV; 224 msm_write(port, msm_port->imr, UART_IMR); 225 break; 226 } 227 msm_write(port, xmit->buf[xmit->tail], 228 msm_port->is_uartdm ? UARTDM_TF : UART_TF); 229 230 if (msm_port->is_uartdm) 231 reset_dm_count(port); 232 233 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 234 port->icount.tx++; 235 sent_tx = 1; 236 } 237 238 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 239 uart_write_wakeup(port); 240 } 241 242 static void handle_delta_cts(struct uart_port *port) 243 { 244 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 245 port->icount.cts++; 246 wake_up_interruptible(&port->state->port.delta_msr_wait); 247 } 248 249 static irqreturn_t msm_irq(int irq, void *dev_id) 250 { 251 struct uart_port *port = dev_id; 252 struct msm_port *msm_port = UART_TO_MSM(port); 253 unsigned int misr; 254 255 spin_lock(&port->lock); 256 misr = msm_read(port, UART_MISR); 257 msm_write(port, 0, UART_IMR); /* disable interrupt */ 258 259 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) { 260 if (msm_port->is_uartdm) 261 handle_rx_dm(port, misr); 262 else 263 handle_rx(port); 264 } 265 if (misr & UART_IMR_TXLEV) 266 handle_tx(port); 267 if (misr & UART_IMR_DELTA_CTS) 268 handle_delta_cts(port); 269 270 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */ 271 spin_unlock(&port->lock); 272 273 return IRQ_HANDLED; 274 } 275 276 static unsigned int msm_tx_empty(struct uart_port *port) 277 { 278 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0; 279 } 280 281 static unsigned int msm_get_mctrl(struct uart_port *port) 282 { 283 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS; 284 } 285 286 287 static void msm_reset(struct uart_port *port) 288 { 289 /* reset everything */ 290 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 291 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR); 292 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR); 293 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR); 294 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR); 295 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR); 296 } 297 298 void msm_set_mctrl(struct uart_port *port, unsigned int mctrl) 299 { 300 unsigned int mr; 301 mr = msm_read(port, UART_MR1); 302 303 if (!(mctrl & TIOCM_RTS)) { 304 mr &= ~UART_MR1_RX_RDY_CTL; 305 msm_write(port, mr, UART_MR1); 306 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR); 307 } else { 308 mr |= UART_MR1_RX_RDY_CTL; 309 msm_write(port, mr, UART_MR1); 310 } 311 } 312 313 static void msm_break_ctl(struct uart_port *port, int break_ctl) 314 { 315 if (break_ctl) 316 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR); 317 else 318 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR); 319 } 320 321 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud) 322 { 323 unsigned int baud_code, rxstale, watermark; 324 struct msm_port *msm_port = UART_TO_MSM(port); 325 326 switch (baud) { 327 case 300: 328 baud_code = UART_CSR_300; 329 rxstale = 1; 330 break; 331 case 600: 332 baud_code = UART_CSR_600; 333 rxstale = 1; 334 break; 335 case 1200: 336 baud_code = UART_CSR_1200; 337 rxstale = 1; 338 break; 339 case 2400: 340 baud_code = UART_CSR_2400; 341 rxstale = 1; 342 break; 343 case 4800: 344 baud_code = UART_CSR_4800; 345 rxstale = 1; 346 break; 347 case 9600: 348 baud_code = UART_CSR_9600; 349 rxstale = 2; 350 break; 351 case 14400: 352 baud_code = UART_CSR_14400; 353 rxstale = 3; 354 break; 355 case 19200: 356 baud_code = UART_CSR_19200; 357 rxstale = 4; 358 break; 359 case 28800: 360 baud_code = UART_CSR_28800; 361 rxstale = 6; 362 break; 363 case 38400: 364 baud_code = UART_CSR_38400; 365 rxstale = 8; 366 break; 367 case 57600: 368 baud_code = UART_CSR_57600; 369 rxstale = 16; 370 break; 371 case 115200: 372 default: 373 baud_code = UART_CSR_115200; 374 baud = 115200; 375 rxstale = 31; 376 break; 377 } 378 379 if (msm_port->is_uartdm) 380 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR); 381 382 msm_write(port, baud_code, UART_CSR); 383 384 /* RX stale watermark */ 385 watermark = UART_IPR_STALE_LSB & rxstale; 386 watermark |= UART_IPR_RXSTALE_LAST; 387 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2); 388 msm_write(port, watermark, UART_IPR); 389 390 /* set RX watermark */ 391 watermark = (port->fifosize * 3) / 4; 392 msm_write(port, watermark, UART_RFWR); 393 394 /* set TX watermark */ 395 msm_write(port, 10, UART_TFWR); 396 397 if (msm_port->is_uartdm) { 398 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 399 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 400 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 401 } 402 403 return baud; 404 } 405 406 407 static void msm_init_clock(struct uart_port *port) 408 { 409 struct msm_port *msm_port = UART_TO_MSM(port); 410 411 clk_enable(msm_port->clk); 412 if (!IS_ERR(msm_port->pclk)) 413 clk_enable(msm_port->pclk); 414 msm_serial_set_mnd_regs(port); 415 } 416 417 static int msm_startup(struct uart_port *port) 418 { 419 struct msm_port *msm_port = UART_TO_MSM(port); 420 unsigned int data, rfr_level; 421 int ret; 422 423 snprintf(msm_port->name, sizeof(msm_port->name), 424 "msm_serial%d", port->line); 425 426 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH, 427 msm_port->name, port); 428 if (unlikely(ret)) 429 return ret; 430 431 msm_init_clock(port); 432 433 if (likely(port->fifosize > 12)) 434 rfr_level = port->fifosize - 12; 435 else 436 rfr_level = port->fifosize; 437 438 /* set automatic RFR level */ 439 data = msm_read(port, UART_MR1); 440 data &= ~UART_MR1_AUTO_RFR_LEVEL1; 441 data &= ~UART_MR1_AUTO_RFR_LEVEL0; 442 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2); 443 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level; 444 msm_write(port, data, UART_MR1); 445 446 /* make sure that RXSTALE count is non-zero */ 447 data = msm_read(port, UART_IPR); 448 if (unlikely(!data)) { 449 data |= UART_IPR_RXSTALE_LAST; 450 data |= UART_IPR_STALE_LSB; 451 msm_write(port, data, UART_IPR); 452 } 453 454 data = 0; 455 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) { 456 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 457 msm_reset(port); 458 data = UART_CR_TX_ENABLE; 459 } 460 461 data |= UART_CR_RX_ENABLE; 462 msm_write(port, data, UART_CR); /* enable TX & RX */ 463 464 /* Make sure IPR is not 0 to start with*/ 465 if (msm_port->is_uartdm) 466 msm_write(port, UART_IPR_STALE_LSB, UART_IPR); 467 468 /* turn on RX and CTS interrupts */ 469 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE | 470 UART_IMR_CURRENT_CTS; 471 472 if (msm_port->is_uartdm) { 473 msm_write(port, 0xFFFFFF, UARTDM_DMRX); 474 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR); 475 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR); 476 } 477 478 msm_write(port, msm_port->imr, UART_IMR); 479 return 0; 480 } 481 482 static void msm_shutdown(struct uart_port *port) 483 { 484 struct msm_port *msm_port = UART_TO_MSM(port); 485 486 msm_port->imr = 0; 487 msm_write(port, 0, UART_IMR); /* disable interrupts */ 488 489 clk_disable(msm_port->clk); 490 491 free_irq(port->irq, port); 492 } 493 494 static void msm_set_termios(struct uart_port *port, struct ktermios *termios, 495 struct ktermios *old) 496 { 497 unsigned long flags; 498 unsigned int baud, mr; 499 500 spin_lock_irqsave(&port->lock, flags); 501 502 /* calculate and set baud rate */ 503 baud = uart_get_baud_rate(port, termios, old, 300, 115200); 504 baud = msm_set_baud_rate(port, baud); 505 if (tty_termios_baud_rate(termios)) 506 tty_termios_encode_baud_rate(termios, baud, baud); 507 508 /* calculate parity */ 509 mr = msm_read(port, UART_MR2); 510 mr &= ~UART_MR2_PARITY_MODE; 511 if (termios->c_cflag & PARENB) { 512 if (termios->c_cflag & PARODD) 513 mr |= UART_MR2_PARITY_MODE_ODD; 514 else if (termios->c_cflag & CMSPAR) 515 mr |= UART_MR2_PARITY_MODE_SPACE; 516 else 517 mr |= UART_MR2_PARITY_MODE_EVEN; 518 } 519 520 /* calculate bits per char */ 521 mr &= ~UART_MR2_BITS_PER_CHAR; 522 switch (termios->c_cflag & CSIZE) { 523 case CS5: 524 mr |= UART_MR2_BITS_PER_CHAR_5; 525 break; 526 case CS6: 527 mr |= UART_MR2_BITS_PER_CHAR_6; 528 break; 529 case CS7: 530 mr |= UART_MR2_BITS_PER_CHAR_7; 531 break; 532 case CS8: 533 default: 534 mr |= UART_MR2_BITS_PER_CHAR_8; 535 break; 536 } 537 538 /* calculate stop bits */ 539 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO); 540 if (termios->c_cflag & CSTOPB) 541 mr |= UART_MR2_STOP_BIT_LEN_TWO; 542 else 543 mr |= UART_MR2_STOP_BIT_LEN_ONE; 544 545 /* set parity, bits per char, and stop bit */ 546 msm_write(port, mr, UART_MR2); 547 548 /* calculate and set hardware flow control */ 549 mr = msm_read(port, UART_MR1); 550 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL); 551 if (termios->c_cflag & CRTSCTS) { 552 mr |= UART_MR1_CTS_CTL; 553 mr |= UART_MR1_RX_RDY_CTL; 554 } 555 msm_write(port, mr, UART_MR1); 556 557 /* Configure status bits to ignore based on termio flags. */ 558 port->read_status_mask = 0; 559 if (termios->c_iflag & INPCK) 560 port->read_status_mask |= UART_SR_PAR_FRAME_ERR; 561 if (termios->c_iflag & (BRKINT | PARMRK)) 562 port->read_status_mask |= UART_SR_RX_BREAK; 563 564 uart_update_timeout(port, termios->c_cflag, baud); 565 566 spin_unlock_irqrestore(&port->lock, flags); 567 } 568 569 static const char *msm_type(struct uart_port *port) 570 { 571 return "MSM"; 572 } 573 574 static void msm_release_port(struct uart_port *port) 575 { 576 struct platform_device *pdev = to_platform_device(port->dev); 577 struct msm_port *msm_port = UART_TO_MSM(port); 578 struct resource *uart_resource; 579 struct resource *gsbi_resource; 580 resource_size_t size; 581 582 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 583 if (unlikely(!uart_resource)) 584 return; 585 size = resource_size(uart_resource); 586 587 release_mem_region(port->mapbase, size); 588 iounmap(port->membase); 589 port->membase = NULL; 590 591 if (msm_port->gsbi_base) { 592 iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base + 593 GSBI_CONTROL); 594 595 gsbi_resource = platform_get_resource(pdev, 596 IORESOURCE_MEM, 1); 597 598 if (unlikely(!gsbi_resource)) 599 return; 600 601 size = resource_size(gsbi_resource); 602 release_mem_region(gsbi_resource->start, size); 603 iounmap(msm_port->gsbi_base); 604 msm_port->gsbi_base = NULL; 605 } 606 } 607 608 static int msm_request_port(struct uart_port *port) 609 { 610 struct msm_port *msm_port = UART_TO_MSM(port); 611 struct platform_device *pdev = to_platform_device(port->dev); 612 struct resource *uart_resource; 613 struct resource *gsbi_resource; 614 resource_size_t size; 615 int ret; 616 617 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 618 if (unlikely(!uart_resource)) 619 return -ENXIO; 620 621 size = resource_size(uart_resource); 622 623 if (!request_mem_region(port->mapbase, size, "msm_serial")) 624 return -EBUSY; 625 626 port->membase = ioremap(port->mapbase, size); 627 if (!port->membase) { 628 ret = -EBUSY; 629 goto fail_release_port; 630 } 631 632 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1); 633 /* Is this a GSBI-based port? */ 634 if (gsbi_resource) { 635 size = resource_size(gsbi_resource); 636 637 if (!request_mem_region(gsbi_resource->start, size, 638 "msm_serial")) { 639 ret = -EBUSY; 640 goto fail_release_port; 641 } 642 643 msm_port->gsbi_base = ioremap(gsbi_resource->start, size); 644 if (!msm_port->gsbi_base) { 645 ret = -EBUSY; 646 goto fail_release_gsbi; 647 } 648 } 649 650 return 0; 651 652 fail_release_gsbi: 653 release_mem_region(gsbi_resource->start, size); 654 fail_release_port: 655 release_mem_region(port->mapbase, size); 656 return ret; 657 } 658 659 static void msm_config_port(struct uart_port *port, int flags) 660 { 661 struct msm_port *msm_port = UART_TO_MSM(port); 662 int ret; 663 if (flags & UART_CONFIG_TYPE) { 664 port->type = PORT_MSM; 665 ret = msm_request_port(port); 666 if (ret) 667 return; 668 } 669 670 if (msm_port->is_uartdm) 671 iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base + 672 GSBI_CONTROL); 673 } 674 675 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser) 676 { 677 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM)) 678 return -EINVAL; 679 if (unlikely(port->irq != ser->irq)) 680 return -EINVAL; 681 return 0; 682 } 683 684 static void msm_power(struct uart_port *port, unsigned int state, 685 unsigned int oldstate) 686 { 687 struct msm_port *msm_port = UART_TO_MSM(port); 688 689 switch (state) { 690 case 0: 691 clk_enable(msm_port->clk); 692 if (!IS_ERR(msm_port->pclk)) 693 clk_enable(msm_port->pclk); 694 break; 695 case 3: 696 clk_disable(msm_port->clk); 697 if (!IS_ERR(msm_port->pclk)) 698 clk_disable(msm_port->pclk); 699 break; 700 default: 701 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state); 702 } 703 } 704 705 static struct uart_ops msm_uart_pops = { 706 .tx_empty = msm_tx_empty, 707 .set_mctrl = msm_set_mctrl, 708 .get_mctrl = msm_get_mctrl, 709 .stop_tx = msm_stop_tx, 710 .start_tx = msm_start_tx, 711 .stop_rx = msm_stop_rx, 712 .enable_ms = msm_enable_ms, 713 .break_ctl = msm_break_ctl, 714 .startup = msm_startup, 715 .shutdown = msm_shutdown, 716 .set_termios = msm_set_termios, 717 .type = msm_type, 718 .release_port = msm_release_port, 719 .request_port = msm_request_port, 720 .config_port = msm_config_port, 721 .verify_port = msm_verify_port, 722 .pm = msm_power, 723 }; 724 725 static struct msm_port msm_uart_ports[] = { 726 { 727 .uart = { 728 .iotype = UPIO_MEM, 729 .ops = &msm_uart_pops, 730 .flags = UPF_BOOT_AUTOCONF, 731 .fifosize = 64, 732 .line = 0, 733 }, 734 }, 735 { 736 .uart = { 737 .iotype = UPIO_MEM, 738 .ops = &msm_uart_pops, 739 .flags = UPF_BOOT_AUTOCONF, 740 .fifosize = 64, 741 .line = 1, 742 }, 743 }, 744 { 745 .uart = { 746 .iotype = UPIO_MEM, 747 .ops = &msm_uart_pops, 748 .flags = UPF_BOOT_AUTOCONF, 749 .fifosize = 64, 750 .line = 2, 751 }, 752 }, 753 }; 754 755 #define UART_NR ARRAY_SIZE(msm_uart_ports) 756 757 static inline struct uart_port *get_port_from_line(unsigned int line) 758 { 759 return &msm_uart_ports[line].uart; 760 } 761 762 #ifdef CONFIG_SERIAL_MSM_CONSOLE 763 764 static void msm_console_putchar(struct uart_port *port, int c) 765 { 766 struct msm_port *msm_port = UART_TO_MSM(port); 767 768 if (msm_port->is_uartdm) 769 reset_dm_count(port); 770 771 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY)) 772 ; 773 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF); 774 } 775 776 static void msm_console_write(struct console *co, const char *s, 777 unsigned int count) 778 { 779 struct uart_port *port; 780 struct msm_port *msm_port; 781 782 BUG_ON(co->index < 0 || co->index >= UART_NR); 783 784 port = get_port_from_line(co->index); 785 msm_port = UART_TO_MSM(port); 786 787 spin_lock(&port->lock); 788 uart_console_write(port, s, count, msm_console_putchar); 789 spin_unlock(&port->lock); 790 } 791 792 static int __init msm_console_setup(struct console *co, char *options) 793 { 794 struct uart_port *port; 795 struct msm_port *msm_port; 796 int baud, flow, bits, parity; 797 798 if (unlikely(co->index >= UART_NR || co->index < 0)) 799 return -ENXIO; 800 801 port = get_port_from_line(co->index); 802 msm_port = UART_TO_MSM(port); 803 804 if (unlikely(!port->membase)) 805 return -ENXIO; 806 807 msm_init_clock(port); 808 809 if (options) 810 uart_parse_options(options, &baud, &parity, &bits, &flow); 811 812 bits = 8; 813 parity = 'n'; 814 flow = 'n'; 815 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE, 816 UART_MR2); /* 8N1 */ 817 818 if (baud < 300 || baud > 115200) 819 baud = 115200; 820 msm_set_baud_rate(port, baud); 821 822 msm_reset(port); 823 824 if (msm_port->is_uartdm) { 825 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR); 826 msm_write(port, UART_CR_TX_ENABLE, UART_CR); 827 } 828 829 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line); 830 831 return uart_set_options(port, co, baud, parity, bits, flow); 832 } 833 834 static struct uart_driver msm_uart_driver; 835 836 static struct console msm_console = { 837 .name = "ttyMSM", 838 .write = msm_console_write, 839 .device = uart_console_device, 840 .setup = msm_console_setup, 841 .flags = CON_PRINTBUFFER, 842 .index = -1, 843 .data = &msm_uart_driver, 844 }; 845 846 #define MSM_CONSOLE (&msm_console) 847 848 #else 849 #define MSM_CONSOLE NULL 850 #endif 851 852 static struct uart_driver msm_uart_driver = { 853 .owner = THIS_MODULE, 854 .driver_name = "msm_serial", 855 .dev_name = "ttyMSM", 856 .nr = UART_NR, 857 .cons = MSM_CONSOLE, 858 }; 859 860 static atomic_t msm_uart_next_id = ATOMIC_INIT(0); 861 862 static int __init msm_serial_probe(struct platform_device *pdev) 863 { 864 struct msm_port *msm_port; 865 struct resource *resource; 866 struct uart_port *port; 867 int irq; 868 869 if (pdev->id == -1) 870 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1; 871 872 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR)) 873 return -ENXIO; 874 875 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id); 876 877 port = get_port_from_line(pdev->id); 878 port->dev = &pdev->dev; 879 msm_port = UART_TO_MSM(port); 880 881 if (platform_get_resource(pdev, IORESOURCE_MEM, 1)) 882 msm_port->is_uartdm = 1; 883 else 884 msm_port->is_uartdm = 0; 885 886 if (msm_port->is_uartdm) { 887 msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk"); 888 msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk"); 889 } else { 890 msm_port->clk = clk_get(&pdev->dev, "uart_clk"); 891 msm_port->pclk = ERR_PTR(-ENOENT); 892 } 893 894 if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) && 895 msm_port->is_uartdm))) 896 return PTR_ERR(msm_port->clk); 897 898 if (msm_port->is_uartdm) 899 clk_set_rate(msm_port->clk, 7372800); 900 901 port->uartclk = clk_get_rate(msm_port->clk); 902 printk(KERN_INFO "uartclk = %d\n", port->uartclk); 903 904 905 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0); 906 if (unlikely(!resource)) 907 return -ENXIO; 908 port->mapbase = resource->start; 909 910 irq = platform_get_irq(pdev, 0); 911 if (unlikely(irq < 0)) 912 return -ENXIO; 913 port->irq = irq; 914 915 platform_set_drvdata(pdev, port); 916 917 return uart_add_one_port(&msm_uart_driver, port); 918 } 919 920 static int __devexit msm_serial_remove(struct platform_device *pdev) 921 { 922 struct msm_port *msm_port = platform_get_drvdata(pdev); 923 924 clk_put(msm_port->clk); 925 926 return 0; 927 } 928 929 static struct of_device_id msm_match_table[] = { 930 { .compatible = "qcom,msm-uart" }, 931 {} 932 }; 933 934 static struct platform_driver msm_platform_driver = { 935 .remove = msm_serial_remove, 936 .driver = { 937 .name = "msm_serial", 938 .owner = THIS_MODULE, 939 .of_match_table = msm_match_table, 940 }, 941 }; 942 943 static int __init msm_serial_init(void) 944 { 945 int ret; 946 947 ret = uart_register_driver(&msm_uart_driver); 948 if (unlikely(ret)) 949 return ret; 950 951 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe); 952 if (unlikely(ret)) 953 uart_unregister_driver(&msm_uart_driver); 954 955 printk(KERN_INFO "msm_serial: driver initialized\n"); 956 957 return ret; 958 } 959 960 static void __exit msm_serial_exit(void) 961 { 962 #ifdef CONFIG_SERIAL_MSM_CONSOLE 963 unregister_console(&msm_console); 964 #endif 965 platform_driver_unregister(&msm_platform_driver); 966 uart_unregister_driver(&msm_uart_driver); 967 } 968 969 module_init(msm_serial_init); 970 module_exit(msm_serial_exit); 971 972 MODULE_AUTHOR("Robert Love <rlove@google.com>"); 973 MODULE_DESCRIPTION("Driver for msm7x serial device"); 974 MODULE_LICENSE("GPL"); 975