1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MPS2 UART driver 4 * 5 * Copyright (C) 2015 ARM Limited 6 * 7 * Author: Vladimir Murzin <vladimir.murzin@arm.com> 8 * 9 * TODO: support for SysRq 10 */ 11 12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/console.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/of_device.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty_flip.h> 24 #include <linux/types.h> 25 26 #define SERIAL_NAME "ttyMPS" 27 #define DRIVER_NAME "mps2-uart" 28 #define MAKE_NAME(x) (DRIVER_NAME # x) 29 30 #define UARTn_DATA 0x00 31 32 #define UARTn_STATE 0x04 33 #define UARTn_STATE_TX_FULL BIT(0) 34 #define UARTn_STATE_RX_FULL BIT(1) 35 #define UARTn_STATE_TX_OVERRUN BIT(2) 36 #define UARTn_STATE_RX_OVERRUN BIT(3) 37 38 #define UARTn_CTRL 0x08 39 #define UARTn_CTRL_TX_ENABLE BIT(0) 40 #define UARTn_CTRL_RX_ENABLE BIT(1) 41 #define UARTn_CTRL_TX_INT_ENABLE BIT(2) 42 #define UARTn_CTRL_RX_INT_ENABLE BIT(3) 43 #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4) 44 #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5) 45 46 #define UARTn_INT 0x0c 47 #define UARTn_INT_TX BIT(0) 48 #define UARTn_INT_RX BIT(1) 49 #define UARTn_INT_TX_OVERRUN BIT(2) 50 #define UARTn_INT_RX_OVERRUN BIT(3) 51 52 #define UARTn_BAUDDIV 0x10 53 #define UARTn_BAUDDIV_MASK GENMASK(20, 0) 54 55 /* 56 * Helpers to make typical enable/disable operations more readable. 57 */ 58 #define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\ 59 UARTn_CTRL_TX_INT_ENABLE |\ 60 UARTn_CTRL_TX_OVERRUN_INT_ENABLE) 61 62 #define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\ 63 UARTn_CTRL_RX_INT_ENABLE |\ 64 UARTn_CTRL_RX_OVERRUN_INT_ENABLE) 65 66 #define MPS2_MAX_PORTS 3 67 68 struct mps2_uart_port { 69 struct uart_port port; 70 struct clk *clk; 71 unsigned int tx_irq; 72 unsigned int rx_irq; 73 }; 74 75 static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port) 76 { 77 return container_of(port, struct mps2_uart_port, port); 78 } 79 80 static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off) 81 { 82 struct mps2_uart_port *mps_port = to_mps2_port(port); 83 84 writeb(val, mps_port->port.membase + off); 85 } 86 87 static u8 mps2_uart_read8(struct uart_port *port, unsigned int off) 88 { 89 struct mps2_uart_port *mps_port = to_mps2_port(port); 90 91 return readb(mps_port->port.membase + off); 92 } 93 94 static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off) 95 { 96 struct mps2_uart_port *mps_port = to_mps2_port(port); 97 98 writel_relaxed(val, mps_port->port.membase + off); 99 } 100 101 static unsigned int mps2_uart_tx_empty(struct uart_port *port) 102 { 103 u8 status = mps2_uart_read8(port, UARTn_STATE); 104 105 return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT; 106 } 107 108 static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 109 { 110 } 111 112 static unsigned int mps2_uart_get_mctrl(struct uart_port *port) 113 { 114 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; 115 } 116 117 static void mps2_uart_stop_tx(struct uart_port *port) 118 { 119 u8 control = mps2_uart_read8(port, UARTn_CTRL); 120 121 control &= ~UARTn_CTRL_TX_INT_ENABLE; 122 123 mps2_uart_write8(port, control, UARTn_CTRL); 124 } 125 126 static void mps2_uart_tx_chars(struct uart_port *port) 127 { 128 struct circ_buf *xmit = &port->state->xmit; 129 130 while (!(mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL)) { 131 if (port->x_char) { 132 mps2_uart_write8(port, port->x_char, UARTn_DATA); 133 port->x_char = 0; 134 port->icount.tx++; 135 continue; 136 } 137 138 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 139 break; 140 141 mps2_uart_write8(port, xmit->buf[xmit->tail], UARTn_DATA); 142 xmit->tail = (xmit->tail + 1) % UART_XMIT_SIZE; 143 port->icount.tx++; 144 } 145 146 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 147 uart_write_wakeup(port); 148 149 if (uart_circ_empty(xmit)) 150 mps2_uart_stop_tx(port); 151 } 152 153 static void mps2_uart_start_tx(struct uart_port *port) 154 { 155 u8 control = mps2_uart_read8(port, UARTn_CTRL); 156 157 control |= UARTn_CTRL_TX_INT_ENABLE; 158 159 mps2_uart_write8(port, control, UARTn_CTRL); 160 161 /* 162 * We've just unmasked the TX IRQ and now slow-starting via 163 * polling; if there is enough data to fill up the internal 164 * write buffer in one go, the TX IRQ should assert, at which 165 * point we switch to fully interrupt-driven TX. 166 */ 167 168 mps2_uart_tx_chars(port); 169 } 170 171 static void mps2_uart_stop_rx(struct uart_port *port) 172 { 173 u8 control = mps2_uart_read8(port, UARTn_CTRL); 174 175 control &= ~UARTn_CTRL_RX_GRP; 176 177 mps2_uart_write8(port, control, UARTn_CTRL); 178 } 179 180 static void mps2_uart_break_ctl(struct uart_port *port, int ctl) 181 { 182 } 183 184 static void mps2_uart_rx_chars(struct uart_port *port) 185 { 186 struct tty_port *tport = &port->state->port; 187 188 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) { 189 u8 rxdata = mps2_uart_read8(port, UARTn_DATA); 190 191 port->icount.rx++; 192 tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL); 193 } 194 195 tty_flip_buffer_push(tport); 196 } 197 198 static irqreturn_t mps2_uart_rxirq(int irq, void *data) 199 { 200 struct uart_port *port = data; 201 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 202 203 if (unlikely(!(irqflag & UARTn_INT_RX))) 204 return IRQ_NONE; 205 206 spin_lock(&port->lock); 207 208 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT); 209 mps2_uart_rx_chars(port); 210 211 spin_unlock(&port->lock); 212 213 return IRQ_HANDLED; 214 } 215 216 static irqreturn_t mps2_uart_txirq(int irq, void *data) 217 { 218 struct uart_port *port = data; 219 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 220 221 if (unlikely(!(irqflag & UARTn_INT_TX))) 222 return IRQ_NONE; 223 224 spin_lock(&port->lock); 225 226 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT); 227 mps2_uart_tx_chars(port); 228 229 spin_unlock(&port->lock); 230 231 return IRQ_HANDLED; 232 } 233 234 static irqreturn_t mps2_uart_oerrirq(int irq, void *data) 235 { 236 irqreturn_t handled = IRQ_NONE; 237 struct uart_port *port = data; 238 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 239 240 spin_lock(&port->lock); 241 242 if (irqflag & UARTn_INT_RX_OVERRUN) { 243 struct tty_port *tport = &port->state->port; 244 245 mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT); 246 port->icount.overrun++; 247 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 248 tty_flip_buffer_push(tport); 249 handled = IRQ_HANDLED; 250 } 251 252 /* 253 * It's never been seen in practice and it never *should* happen since 254 * we check if there is enough room in TX buffer before sending data. 255 * So we keep this check in case something suspicious has happened. 256 */ 257 if (irqflag & UARTn_INT_TX_OVERRUN) { 258 mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT); 259 handled = IRQ_HANDLED; 260 } 261 262 spin_unlock(&port->lock); 263 264 return handled; 265 } 266 267 static int mps2_uart_startup(struct uart_port *port) 268 { 269 struct mps2_uart_port *mps_port = to_mps2_port(port); 270 u8 control = mps2_uart_read8(port, UARTn_CTRL); 271 int ret; 272 273 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 274 275 mps2_uart_write8(port, control, UARTn_CTRL); 276 277 ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0, 278 MAKE_NAME(-rx), mps_port); 279 if (ret) { 280 dev_err(port->dev, "failed to register rxirq (%d)\n", ret); 281 return ret; 282 } 283 284 ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0, 285 MAKE_NAME(-tx), mps_port); 286 if (ret) { 287 dev_err(port->dev, "failed to register txirq (%d)\n", ret); 288 goto err_free_rxirq; 289 } 290 291 ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED, 292 MAKE_NAME(-overrun), mps_port); 293 294 if (ret) { 295 dev_err(port->dev, "failed to register oerrirq (%d)\n", ret); 296 goto err_free_txirq; 297 } 298 299 control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP; 300 301 mps2_uart_write8(port, control, UARTn_CTRL); 302 303 return 0; 304 305 err_free_txirq: 306 free_irq(mps_port->tx_irq, mps_port); 307 err_free_rxirq: 308 free_irq(mps_port->rx_irq, mps_port); 309 310 return ret; 311 } 312 313 static void mps2_uart_shutdown(struct uart_port *port) 314 { 315 struct mps2_uart_port *mps_port = to_mps2_port(port); 316 u8 control = mps2_uart_read8(port, UARTn_CTRL); 317 318 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 319 320 mps2_uart_write8(port, control, UARTn_CTRL); 321 322 free_irq(mps_port->rx_irq, mps_port); 323 free_irq(mps_port->tx_irq, mps_port); 324 free_irq(port->irq, mps_port); 325 } 326 327 static void 328 mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios, 329 struct ktermios *old) 330 { 331 unsigned long flags; 332 unsigned int baud, bauddiv; 333 334 termios->c_cflag &= ~(CRTSCTS | CMSPAR); 335 termios->c_cflag &= ~CSIZE; 336 termios->c_cflag |= CS8; 337 termios->c_cflag &= ~PARENB; 338 termios->c_cflag &= ~CSTOPB; 339 340 baud = uart_get_baud_rate(port, termios, old, 341 DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK), 342 DIV_ROUND_CLOSEST(port->uartclk, 16)); 343 344 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 345 346 spin_lock_irqsave(&port->lock, flags); 347 348 uart_update_timeout(port, termios->c_cflag, baud); 349 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV); 350 351 spin_unlock_irqrestore(&port->lock, flags); 352 353 if (tty_termios_baud_rate(termios)) 354 tty_termios_encode_baud_rate(termios, baud, baud); 355 } 356 357 static const char *mps2_uart_type(struct uart_port *port) 358 { 359 return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL; 360 } 361 362 static void mps2_uart_release_port(struct uart_port *port) 363 { 364 } 365 366 static int mps2_uart_request_port(struct uart_port *port) 367 { 368 return 0; 369 } 370 371 static void mps2_uart_config_port(struct uart_port *port, int type) 372 { 373 if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port)) 374 port->type = PORT_MPS2UART; 375 } 376 377 static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo) 378 { 379 return -EINVAL; 380 } 381 382 static const struct uart_ops mps2_uart_pops = { 383 .tx_empty = mps2_uart_tx_empty, 384 .set_mctrl = mps2_uart_set_mctrl, 385 .get_mctrl = mps2_uart_get_mctrl, 386 .stop_tx = mps2_uart_stop_tx, 387 .start_tx = mps2_uart_start_tx, 388 .stop_rx = mps2_uart_stop_rx, 389 .break_ctl = mps2_uart_break_ctl, 390 .startup = mps2_uart_startup, 391 .shutdown = mps2_uart_shutdown, 392 .set_termios = mps2_uart_set_termios, 393 .type = mps2_uart_type, 394 .release_port = mps2_uart_release_port, 395 .request_port = mps2_uart_request_port, 396 .config_port = mps2_uart_config_port, 397 .verify_port = mps2_uart_verify_port, 398 }; 399 400 static struct mps2_uart_port mps2_uart_ports[MPS2_MAX_PORTS]; 401 402 #ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE 403 static void mps2_uart_console_putchar(struct uart_port *port, int ch) 404 { 405 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL) 406 cpu_relax(); 407 408 mps2_uart_write8(port, ch, UARTn_DATA); 409 } 410 411 static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt) 412 { 413 struct uart_port *port = &mps2_uart_ports[co->index].port; 414 415 uart_console_write(port, s, cnt, mps2_uart_console_putchar); 416 } 417 418 static int mps2_uart_console_setup(struct console *co, char *options) 419 { 420 struct mps2_uart_port *mps_port; 421 int baud = 9600; 422 int bits = 8; 423 int parity = 'n'; 424 int flow = 'n'; 425 426 if (co->index < 0 || co->index >= MPS2_MAX_PORTS) 427 return -ENODEV; 428 429 mps_port = &mps2_uart_ports[co->index]; 430 431 if (options) 432 uart_parse_options(options, &baud, &parity, &bits, &flow); 433 434 return uart_set_options(&mps_port->port, co, baud, parity, bits, flow); 435 } 436 437 static struct uart_driver mps2_uart_driver; 438 439 static struct console mps2_uart_console = { 440 .name = SERIAL_NAME, 441 .device = uart_console_device, 442 .write = mps2_uart_console_write, 443 .setup = mps2_uart_console_setup, 444 .flags = CON_PRINTBUFFER, 445 .index = -1, 446 .data = &mps2_uart_driver, 447 }; 448 449 #define MPS2_SERIAL_CONSOLE (&mps2_uart_console) 450 451 static void mps2_early_putchar(struct uart_port *port, int ch) 452 { 453 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL) 454 cpu_relax(); 455 456 writeb((unsigned char)ch, port->membase + UARTn_DATA); 457 } 458 459 static void mps2_early_write(struct console *con, const char *s, unsigned int n) 460 { 461 struct earlycon_device *dev = con->data; 462 463 uart_console_write(&dev->port, s, n, mps2_early_putchar); 464 } 465 466 static int __init mps2_early_console_setup(struct earlycon_device *device, 467 const char *opt) 468 { 469 if (!device->port.membase) 470 return -ENODEV; 471 472 device->con->write = mps2_early_write; 473 474 return 0; 475 } 476 477 OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup); 478 479 #else 480 #define MPS2_SERIAL_CONSOLE NULL 481 #endif 482 483 static struct uart_driver mps2_uart_driver = { 484 .driver_name = DRIVER_NAME, 485 .dev_name = SERIAL_NAME, 486 .nr = MPS2_MAX_PORTS, 487 .cons = MPS2_SERIAL_CONSOLE, 488 }; 489 490 static struct mps2_uart_port *mps2_of_get_port(struct platform_device *pdev) 491 { 492 struct device_node *np = pdev->dev.of_node; 493 int id; 494 495 if (!np) 496 return NULL; 497 498 id = of_alias_get_id(np, "serial"); 499 if (id < 0) 500 id = 0; 501 502 if (WARN_ON(id >= MPS2_MAX_PORTS)) 503 return NULL; 504 505 mps2_uart_ports[id].port.line = id; 506 return &mps2_uart_ports[id]; 507 } 508 509 static int mps2_init_port(struct mps2_uart_port *mps_port, 510 struct platform_device *pdev) 511 { 512 struct resource *res; 513 int ret; 514 515 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 516 mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res); 517 if (IS_ERR(mps_port->port.membase)) 518 return PTR_ERR(mps_port->port.membase); 519 520 mps_port->port.mapbase = res->start; 521 mps_port->port.mapsize = resource_size(res); 522 523 mps_port->rx_irq = platform_get_irq(pdev, 0); 524 mps_port->tx_irq = platform_get_irq(pdev, 1); 525 mps_port->port.irq = platform_get_irq(pdev, 2); 526 527 mps_port->port.iotype = UPIO_MEM; 528 mps_port->port.flags = UPF_BOOT_AUTOCONF; 529 mps_port->port.fifosize = 1; 530 mps_port->port.ops = &mps2_uart_pops; 531 mps_port->port.dev = &pdev->dev; 532 533 mps_port->clk = devm_clk_get(&pdev->dev, NULL); 534 if (IS_ERR(mps_port->clk)) 535 return PTR_ERR(mps_port->clk); 536 537 ret = clk_prepare_enable(mps_port->clk); 538 if (ret) 539 return ret; 540 541 mps_port->port.uartclk = clk_get_rate(mps_port->clk); 542 543 clk_disable_unprepare(mps_port->clk); 544 545 return ret; 546 } 547 548 static int mps2_serial_probe(struct platform_device *pdev) 549 { 550 struct mps2_uart_port *mps_port; 551 int ret; 552 553 mps_port = mps2_of_get_port(pdev); 554 if (!mps_port) 555 return -ENODEV; 556 557 ret = mps2_init_port(mps_port, pdev); 558 if (ret) 559 return ret; 560 561 ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port); 562 if (ret) 563 return ret; 564 565 platform_set_drvdata(pdev, mps_port); 566 567 return 0; 568 } 569 570 #ifdef CONFIG_OF 571 static const struct of_device_id mps2_match[] = { 572 { .compatible = "arm,mps2-uart", }, 573 {}, 574 }; 575 #endif 576 577 static struct platform_driver mps2_serial_driver = { 578 .probe = mps2_serial_probe, 579 580 .driver = { 581 .name = DRIVER_NAME, 582 .of_match_table = of_match_ptr(mps2_match), 583 .suppress_bind_attrs = true, 584 }, 585 }; 586 587 static int __init mps2_uart_init(void) 588 { 589 int ret; 590 591 ret = uart_register_driver(&mps2_uart_driver); 592 if (ret) 593 return ret; 594 595 ret = platform_driver_register(&mps2_serial_driver); 596 if (ret) 597 uart_unregister_driver(&mps2_uart_driver); 598 599 return ret; 600 } 601 arch_initcall(mps2_uart_init); 602