1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MPS2 UART driver 4 * 5 * Copyright (C) 2015 ARM Limited 6 * 7 * Author: Vladimir Murzin <vladimir.murzin@arm.com> 8 * 9 * TODO: support for SysRq 10 */ 11 12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/console.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/of_device.h> 20 #include <linux/of.h> 21 #include <linux/platform_device.h> 22 #include <linux/serial_core.h> 23 #include <linux/tty_flip.h> 24 #include <linux/types.h> 25 #include <linux/idr.h> 26 27 #define SERIAL_NAME "ttyMPS" 28 #define DRIVER_NAME "mps2-uart" 29 #define MAKE_NAME(x) (DRIVER_NAME # x) 30 31 #define UARTn_DATA 0x00 32 33 #define UARTn_STATE 0x04 34 #define UARTn_STATE_TX_FULL BIT(0) 35 #define UARTn_STATE_RX_FULL BIT(1) 36 #define UARTn_STATE_TX_OVERRUN BIT(2) 37 #define UARTn_STATE_RX_OVERRUN BIT(3) 38 39 #define UARTn_CTRL 0x08 40 #define UARTn_CTRL_TX_ENABLE BIT(0) 41 #define UARTn_CTRL_RX_ENABLE BIT(1) 42 #define UARTn_CTRL_TX_INT_ENABLE BIT(2) 43 #define UARTn_CTRL_RX_INT_ENABLE BIT(3) 44 #define UARTn_CTRL_TX_OVERRUN_INT_ENABLE BIT(4) 45 #define UARTn_CTRL_RX_OVERRUN_INT_ENABLE BIT(5) 46 47 #define UARTn_INT 0x0c 48 #define UARTn_INT_TX BIT(0) 49 #define UARTn_INT_RX BIT(1) 50 #define UARTn_INT_TX_OVERRUN BIT(2) 51 #define UARTn_INT_RX_OVERRUN BIT(3) 52 53 #define UARTn_BAUDDIV 0x10 54 #define UARTn_BAUDDIV_MASK GENMASK(20, 0) 55 56 /* 57 * Helpers to make typical enable/disable operations more readable. 58 */ 59 #define UARTn_CTRL_TX_GRP (UARTn_CTRL_TX_ENABLE |\ 60 UARTn_CTRL_TX_INT_ENABLE |\ 61 UARTn_CTRL_TX_OVERRUN_INT_ENABLE) 62 63 #define UARTn_CTRL_RX_GRP (UARTn_CTRL_RX_ENABLE |\ 64 UARTn_CTRL_RX_INT_ENABLE |\ 65 UARTn_CTRL_RX_OVERRUN_INT_ENABLE) 66 67 #define MPS2_MAX_PORTS 3 68 69 #define UART_PORT_COMBINED_IRQ BIT(0) 70 71 struct mps2_uart_port { 72 struct uart_port port; 73 struct clk *clk; 74 unsigned int tx_irq; 75 unsigned int rx_irq; 76 unsigned int flags; 77 }; 78 79 static inline struct mps2_uart_port *to_mps2_port(struct uart_port *port) 80 { 81 return container_of(port, struct mps2_uart_port, port); 82 } 83 84 static void mps2_uart_write8(struct uart_port *port, u8 val, unsigned int off) 85 { 86 struct mps2_uart_port *mps_port = to_mps2_port(port); 87 88 writeb(val, mps_port->port.membase + off); 89 } 90 91 static u8 mps2_uart_read8(struct uart_port *port, unsigned int off) 92 { 93 struct mps2_uart_port *mps_port = to_mps2_port(port); 94 95 return readb(mps_port->port.membase + off); 96 } 97 98 static void mps2_uart_write32(struct uart_port *port, u32 val, unsigned int off) 99 { 100 struct mps2_uart_port *mps_port = to_mps2_port(port); 101 102 writel_relaxed(val, mps_port->port.membase + off); 103 } 104 105 static unsigned int mps2_uart_tx_empty(struct uart_port *port) 106 { 107 u8 status = mps2_uart_read8(port, UARTn_STATE); 108 109 return (status & UARTn_STATE_TX_FULL) ? 0 : TIOCSER_TEMT; 110 } 111 112 static void mps2_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 113 { 114 } 115 116 static unsigned int mps2_uart_get_mctrl(struct uart_port *port) 117 { 118 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR; 119 } 120 121 static void mps2_uart_stop_tx(struct uart_port *port) 122 { 123 u8 control = mps2_uart_read8(port, UARTn_CTRL); 124 125 control &= ~UARTn_CTRL_TX_INT_ENABLE; 126 127 mps2_uart_write8(port, control, UARTn_CTRL); 128 } 129 130 static void mps2_uart_tx_chars(struct uart_port *port) 131 { 132 u8 ch; 133 134 uart_port_tx(port, ch, 135 mps2_uart_tx_empty(port), 136 mps2_uart_write8(port, ch, UARTn_DATA)); 137 } 138 139 static void mps2_uart_start_tx(struct uart_port *port) 140 { 141 u8 control = mps2_uart_read8(port, UARTn_CTRL); 142 143 control |= UARTn_CTRL_TX_INT_ENABLE; 144 145 mps2_uart_write8(port, control, UARTn_CTRL); 146 147 /* 148 * We've just unmasked the TX IRQ and now slow-starting via 149 * polling; if there is enough data to fill up the internal 150 * write buffer in one go, the TX IRQ should assert, at which 151 * point we switch to fully interrupt-driven TX. 152 */ 153 154 mps2_uart_tx_chars(port); 155 } 156 157 static void mps2_uart_stop_rx(struct uart_port *port) 158 { 159 u8 control = mps2_uart_read8(port, UARTn_CTRL); 160 161 control &= ~UARTn_CTRL_RX_GRP; 162 163 mps2_uart_write8(port, control, UARTn_CTRL); 164 } 165 166 static void mps2_uart_break_ctl(struct uart_port *port, int ctl) 167 { 168 } 169 170 static void mps2_uart_rx_chars(struct uart_port *port) 171 { 172 struct tty_port *tport = &port->state->port; 173 174 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_RX_FULL) { 175 u8 rxdata = mps2_uart_read8(port, UARTn_DATA); 176 177 port->icount.rx++; 178 tty_insert_flip_char(&port->state->port, rxdata, TTY_NORMAL); 179 } 180 181 tty_flip_buffer_push(tport); 182 } 183 184 static irqreturn_t mps2_uart_rxirq(int irq, void *data) 185 { 186 struct uart_port *port = data; 187 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 188 189 if (unlikely(!(irqflag & UARTn_INT_RX))) 190 return IRQ_NONE; 191 192 spin_lock(&port->lock); 193 194 mps2_uart_write8(port, UARTn_INT_RX, UARTn_INT); 195 mps2_uart_rx_chars(port); 196 197 spin_unlock(&port->lock); 198 199 return IRQ_HANDLED; 200 } 201 202 static irqreturn_t mps2_uart_txirq(int irq, void *data) 203 { 204 struct uart_port *port = data; 205 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 206 207 if (unlikely(!(irqflag & UARTn_INT_TX))) 208 return IRQ_NONE; 209 210 spin_lock(&port->lock); 211 212 mps2_uart_write8(port, UARTn_INT_TX, UARTn_INT); 213 mps2_uart_tx_chars(port); 214 215 spin_unlock(&port->lock); 216 217 return IRQ_HANDLED; 218 } 219 220 static irqreturn_t mps2_uart_oerrirq(int irq, void *data) 221 { 222 irqreturn_t handled = IRQ_NONE; 223 struct uart_port *port = data; 224 u8 irqflag = mps2_uart_read8(port, UARTn_INT); 225 226 spin_lock(&port->lock); 227 228 if (irqflag & UARTn_INT_RX_OVERRUN) { 229 struct tty_port *tport = &port->state->port; 230 231 mps2_uart_write8(port, UARTn_INT_RX_OVERRUN, UARTn_INT); 232 port->icount.overrun++; 233 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 234 tty_flip_buffer_push(tport); 235 handled = IRQ_HANDLED; 236 } 237 238 /* 239 * It's never been seen in practice and it never *should* happen since 240 * we check if there is enough room in TX buffer before sending data. 241 * So we keep this check in case something suspicious has happened. 242 */ 243 if (irqflag & UARTn_INT_TX_OVERRUN) { 244 mps2_uart_write8(port, UARTn_INT_TX_OVERRUN, UARTn_INT); 245 handled = IRQ_HANDLED; 246 } 247 248 spin_unlock(&port->lock); 249 250 return handled; 251 } 252 253 static irqreturn_t mps2_uart_combinedirq(int irq, void *data) 254 { 255 if (mps2_uart_rxirq(irq, data) == IRQ_HANDLED) 256 return IRQ_HANDLED; 257 258 if (mps2_uart_txirq(irq, data) == IRQ_HANDLED) 259 return IRQ_HANDLED; 260 261 if (mps2_uart_oerrirq(irq, data) == IRQ_HANDLED) 262 return IRQ_HANDLED; 263 264 return IRQ_NONE; 265 } 266 267 static int mps2_uart_startup(struct uart_port *port) 268 { 269 struct mps2_uart_port *mps_port = to_mps2_port(port); 270 u8 control = mps2_uart_read8(port, UARTn_CTRL); 271 int ret; 272 273 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 274 275 mps2_uart_write8(port, control, UARTn_CTRL); 276 277 if (mps_port->flags & UART_PORT_COMBINED_IRQ) { 278 ret = request_irq(port->irq, mps2_uart_combinedirq, 0, 279 MAKE_NAME(-combined), mps_port); 280 281 if (ret) { 282 dev_err(port->dev, "failed to register combinedirq (%d)\n", ret); 283 return ret; 284 } 285 } else { 286 ret = request_irq(port->irq, mps2_uart_oerrirq, IRQF_SHARED, 287 MAKE_NAME(-overrun), mps_port); 288 289 if (ret) { 290 dev_err(port->dev, "failed to register oerrirq (%d)\n", ret); 291 return ret; 292 } 293 294 ret = request_irq(mps_port->rx_irq, mps2_uart_rxirq, 0, 295 MAKE_NAME(-rx), mps_port); 296 if (ret) { 297 dev_err(port->dev, "failed to register rxirq (%d)\n", ret); 298 goto err_free_oerrirq; 299 } 300 301 ret = request_irq(mps_port->tx_irq, mps2_uart_txirq, 0, 302 MAKE_NAME(-tx), mps_port); 303 if (ret) { 304 dev_err(port->dev, "failed to register txirq (%d)\n", ret); 305 goto err_free_rxirq; 306 } 307 308 } 309 310 control |= UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP; 311 312 mps2_uart_write8(port, control, UARTn_CTRL); 313 314 return 0; 315 316 err_free_rxirq: 317 free_irq(mps_port->rx_irq, mps_port); 318 err_free_oerrirq: 319 free_irq(port->irq, mps_port); 320 321 return ret; 322 } 323 324 static void mps2_uart_shutdown(struct uart_port *port) 325 { 326 struct mps2_uart_port *mps_port = to_mps2_port(port); 327 u8 control = mps2_uart_read8(port, UARTn_CTRL); 328 329 control &= ~(UARTn_CTRL_RX_GRP | UARTn_CTRL_TX_GRP); 330 331 mps2_uart_write8(port, control, UARTn_CTRL); 332 333 if (!(mps_port->flags & UART_PORT_COMBINED_IRQ)) { 334 free_irq(mps_port->rx_irq, mps_port); 335 free_irq(mps_port->tx_irq, mps_port); 336 } 337 338 free_irq(port->irq, mps_port); 339 } 340 341 static void 342 mps2_uart_set_termios(struct uart_port *port, struct ktermios *termios, 343 const struct ktermios *old) 344 { 345 unsigned long flags; 346 unsigned int baud, bauddiv; 347 348 termios->c_cflag &= ~(CRTSCTS | CMSPAR); 349 termios->c_cflag &= ~CSIZE; 350 termios->c_cflag |= CS8; 351 termios->c_cflag &= ~PARENB; 352 termios->c_cflag &= ~CSTOPB; 353 354 baud = uart_get_baud_rate(port, termios, old, 355 DIV_ROUND_CLOSEST(port->uartclk, UARTn_BAUDDIV_MASK), 356 DIV_ROUND_CLOSEST(port->uartclk, 16)); 357 358 bauddiv = DIV_ROUND_CLOSEST(port->uartclk, baud); 359 360 spin_lock_irqsave(&port->lock, flags); 361 362 uart_update_timeout(port, termios->c_cflag, baud); 363 mps2_uart_write32(port, bauddiv, UARTn_BAUDDIV); 364 365 spin_unlock_irqrestore(&port->lock, flags); 366 367 if (tty_termios_baud_rate(termios)) 368 tty_termios_encode_baud_rate(termios, baud, baud); 369 } 370 371 static const char *mps2_uart_type(struct uart_port *port) 372 { 373 return (port->type == PORT_MPS2UART) ? DRIVER_NAME : NULL; 374 } 375 376 static void mps2_uart_release_port(struct uart_port *port) 377 { 378 } 379 380 static int mps2_uart_request_port(struct uart_port *port) 381 { 382 return 0; 383 } 384 385 static void mps2_uart_config_port(struct uart_port *port, int type) 386 { 387 if (type & UART_CONFIG_TYPE && !mps2_uart_request_port(port)) 388 port->type = PORT_MPS2UART; 389 } 390 391 static int mps2_uart_verify_port(struct uart_port *port, struct serial_struct *serinfo) 392 { 393 return -EINVAL; 394 } 395 396 static const struct uart_ops mps2_uart_pops = { 397 .tx_empty = mps2_uart_tx_empty, 398 .set_mctrl = mps2_uart_set_mctrl, 399 .get_mctrl = mps2_uart_get_mctrl, 400 .stop_tx = mps2_uart_stop_tx, 401 .start_tx = mps2_uart_start_tx, 402 .stop_rx = mps2_uart_stop_rx, 403 .break_ctl = mps2_uart_break_ctl, 404 .startup = mps2_uart_startup, 405 .shutdown = mps2_uart_shutdown, 406 .set_termios = mps2_uart_set_termios, 407 .type = mps2_uart_type, 408 .release_port = mps2_uart_release_port, 409 .request_port = mps2_uart_request_port, 410 .config_port = mps2_uart_config_port, 411 .verify_port = mps2_uart_verify_port, 412 }; 413 414 static DEFINE_IDR(ports_idr); 415 416 #ifdef CONFIG_SERIAL_MPS2_UART_CONSOLE 417 static void mps2_uart_console_putchar(struct uart_port *port, unsigned char ch) 418 { 419 while (mps2_uart_read8(port, UARTn_STATE) & UARTn_STATE_TX_FULL) 420 cpu_relax(); 421 422 mps2_uart_write8(port, ch, UARTn_DATA); 423 } 424 425 static void mps2_uart_console_write(struct console *co, const char *s, unsigned int cnt) 426 { 427 struct mps2_uart_port *mps_port = idr_find(&ports_idr, co->index); 428 struct uart_port *port = &mps_port->port; 429 430 uart_console_write(port, s, cnt, mps2_uart_console_putchar); 431 } 432 433 static int mps2_uart_console_setup(struct console *co, char *options) 434 { 435 struct mps2_uart_port *mps_port; 436 int baud = 9600; 437 int bits = 8; 438 int parity = 'n'; 439 int flow = 'n'; 440 441 if (co->index < 0 || co->index >= MPS2_MAX_PORTS) 442 return -ENODEV; 443 444 mps_port = idr_find(&ports_idr, co->index); 445 446 if (!mps_port) 447 return -ENODEV; 448 449 if (options) 450 uart_parse_options(options, &baud, &parity, &bits, &flow); 451 452 return uart_set_options(&mps_port->port, co, baud, parity, bits, flow); 453 } 454 455 static struct uart_driver mps2_uart_driver; 456 457 static struct console mps2_uart_console = { 458 .name = SERIAL_NAME, 459 .device = uart_console_device, 460 .write = mps2_uart_console_write, 461 .setup = mps2_uart_console_setup, 462 .flags = CON_PRINTBUFFER, 463 .index = -1, 464 .data = &mps2_uart_driver, 465 }; 466 467 #define MPS2_SERIAL_CONSOLE (&mps2_uart_console) 468 469 static void mps2_early_putchar(struct uart_port *port, unsigned char ch) 470 { 471 while (readb(port->membase + UARTn_STATE) & UARTn_STATE_TX_FULL) 472 cpu_relax(); 473 474 writeb((unsigned char)ch, port->membase + UARTn_DATA); 475 } 476 477 static void mps2_early_write(struct console *con, const char *s, unsigned int n) 478 { 479 struct earlycon_device *dev = con->data; 480 481 uart_console_write(&dev->port, s, n, mps2_early_putchar); 482 } 483 484 static int __init mps2_early_console_setup(struct earlycon_device *device, 485 const char *opt) 486 { 487 if (!device->port.membase) 488 return -ENODEV; 489 490 device->con->write = mps2_early_write; 491 492 return 0; 493 } 494 495 OF_EARLYCON_DECLARE(mps2, "arm,mps2-uart", mps2_early_console_setup); 496 497 #else 498 #define MPS2_SERIAL_CONSOLE NULL 499 #endif 500 501 static struct uart_driver mps2_uart_driver = { 502 .driver_name = DRIVER_NAME, 503 .dev_name = SERIAL_NAME, 504 .nr = MPS2_MAX_PORTS, 505 .cons = MPS2_SERIAL_CONSOLE, 506 }; 507 508 static int mps2_of_get_port(struct platform_device *pdev, 509 struct mps2_uart_port *mps_port) 510 { 511 struct device_node *np = pdev->dev.of_node; 512 int id; 513 514 if (!np) 515 return -ENODEV; 516 517 id = of_alias_get_id(np, "serial"); 518 519 if (id < 0) 520 id = idr_alloc_cyclic(&ports_idr, (void *)mps_port, 0, MPS2_MAX_PORTS, GFP_KERNEL); 521 else 522 id = idr_alloc(&ports_idr, (void *)mps_port, id, MPS2_MAX_PORTS, GFP_KERNEL); 523 524 if (id < 0) 525 return id; 526 527 /* Only combined irq is presesnt */ 528 if (platform_irq_count(pdev) == 1) 529 mps_port->flags |= UART_PORT_COMBINED_IRQ; 530 531 mps_port->port.line = id; 532 533 return 0; 534 } 535 536 static int mps2_init_port(struct platform_device *pdev, 537 struct mps2_uart_port *mps_port) 538 { 539 struct resource *res; 540 int ret; 541 542 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 543 mps_port->port.membase = devm_ioremap_resource(&pdev->dev, res); 544 if (IS_ERR(mps_port->port.membase)) 545 return PTR_ERR(mps_port->port.membase); 546 547 mps_port->port.mapbase = res->start; 548 mps_port->port.mapsize = resource_size(res); 549 mps_port->port.iotype = UPIO_MEM; 550 mps_port->port.flags = UPF_BOOT_AUTOCONF; 551 mps_port->port.fifosize = 1; 552 mps_port->port.ops = &mps2_uart_pops; 553 mps_port->port.dev = &pdev->dev; 554 555 mps_port->clk = devm_clk_get(&pdev->dev, NULL); 556 if (IS_ERR(mps_port->clk)) 557 return PTR_ERR(mps_port->clk); 558 559 ret = clk_prepare_enable(mps_port->clk); 560 if (ret) 561 return ret; 562 563 mps_port->port.uartclk = clk_get_rate(mps_port->clk); 564 565 clk_disable_unprepare(mps_port->clk); 566 567 568 if (mps_port->flags & UART_PORT_COMBINED_IRQ) { 569 mps_port->port.irq = platform_get_irq(pdev, 0); 570 } else { 571 mps_port->rx_irq = platform_get_irq(pdev, 0); 572 mps_port->tx_irq = platform_get_irq(pdev, 1); 573 mps_port->port.irq = platform_get_irq(pdev, 2); 574 } 575 576 return ret; 577 } 578 579 static int mps2_serial_probe(struct platform_device *pdev) 580 { 581 struct mps2_uart_port *mps_port; 582 int ret; 583 584 mps_port = devm_kzalloc(&pdev->dev, sizeof(struct mps2_uart_port), GFP_KERNEL); 585 586 if (!mps_port) 587 return -ENOMEM; 588 589 ret = mps2_of_get_port(pdev, mps_port); 590 if (ret) 591 return ret; 592 593 ret = mps2_init_port(pdev, mps_port); 594 if (ret) 595 return ret; 596 597 ret = uart_add_one_port(&mps2_uart_driver, &mps_port->port); 598 if (ret) 599 return ret; 600 601 platform_set_drvdata(pdev, mps_port); 602 603 return 0; 604 } 605 606 #ifdef CONFIG_OF 607 static const struct of_device_id mps2_match[] = { 608 { .compatible = "arm,mps2-uart", }, 609 {}, 610 }; 611 #endif 612 613 static struct platform_driver mps2_serial_driver = { 614 .probe = mps2_serial_probe, 615 616 .driver = { 617 .name = DRIVER_NAME, 618 .of_match_table = of_match_ptr(mps2_match), 619 .suppress_bind_attrs = true, 620 }, 621 }; 622 623 static int __init mps2_uart_init(void) 624 { 625 int ret; 626 627 ret = uart_register_driver(&mps2_uart_driver); 628 if (ret) 629 return ret; 630 631 ret = platform_driver_register(&mps2_serial_driver); 632 if (ret) 633 uart_unregister_driver(&mps2_uart_driver); 634 635 return ret; 636 } 637 arch_initcall(mps2_uart_init); 638