1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on meson_uart.c, by AMLOGIC, INC. 4 * 5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/delay.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/serial.h> 19 #include <linux/serial_core.h> 20 #include <linux/tty.h> 21 #include <linux/tty_flip.h> 22 23 /* Register offsets */ 24 #define AML_UART_WFIFO 0x00 25 #define AML_UART_RFIFO 0x04 26 #define AML_UART_CONTROL 0x08 27 #define AML_UART_STATUS 0x0c 28 #define AML_UART_MISC 0x10 29 #define AML_UART_REG5 0x14 30 31 /* AML_UART_CONTROL bits */ 32 #define AML_UART_TX_EN BIT(12) 33 #define AML_UART_RX_EN BIT(13) 34 #define AML_UART_TWO_WIRE_EN BIT(15) 35 #define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16) 36 #define AML_UART_STOP_BIT_1SB (0x00 << 16) 37 #define AML_UART_STOP_BIT_2SB (0x01 << 16) 38 #define AML_UART_PARITY_TYPE BIT(18) 39 #define AML_UART_PARITY_EN BIT(19) 40 #define AML_UART_TX_RST BIT(22) 41 #define AML_UART_RX_RST BIT(23) 42 #define AML_UART_CLEAR_ERR BIT(24) 43 #define AML_UART_RX_INT_EN BIT(27) 44 #define AML_UART_TX_INT_EN BIT(28) 45 #define AML_UART_DATA_LEN_MASK (0x03 << 20) 46 #define AML_UART_DATA_LEN_8BIT (0x00 << 20) 47 #define AML_UART_DATA_LEN_7BIT (0x01 << 20) 48 #define AML_UART_DATA_LEN_6BIT (0x02 << 20) 49 #define AML_UART_DATA_LEN_5BIT (0x03 << 20) 50 51 /* AML_UART_STATUS bits */ 52 #define AML_UART_PARITY_ERR BIT(16) 53 #define AML_UART_FRAME_ERR BIT(17) 54 #define AML_UART_TX_FIFO_WERR BIT(18) 55 #define AML_UART_RX_EMPTY BIT(20) 56 #define AML_UART_TX_FULL BIT(21) 57 #define AML_UART_TX_EMPTY BIT(22) 58 #define AML_UART_XMIT_BUSY BIT(25) 59 #define AML_UART_ERR (AML_UART_PARITY_ERR | \ 60 AML_UART_FRAME_ERR | \ 61 AML_UART_TX_FIFO_WERR) 62 63 /* AML_UART_MISC bits */ 64 #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) 65 #define AML_UART_RECV_IRQ(c) ((c) & 0xff) 66 67 /* AML_UART_REG5 bits */ 68 #define AML_UART_BAUD_MASK 0x7fffff 69 #define AML_UART_BAUD_USE BIT(23) 70 #define AML_UART_BAUD_XTAL BIT(24) 71 #define AML_UART_BAUD_XTAL_DIV2 BIT(27) 72 73 #define AML_UART_PORT_NUM 12 74 #define AML_UART_PORT_OFFSET 6 75 #define AML_UART_DEV_NAME "ttyAML" 76 77 #define AML_UART_POLL_USEC 5 78 #define AML_UART_TIMEOUT_USEC 10000 79 80 static struct uart_driver meson_uart_driver; 81 82 static struct uart_port *meson_ports[AML_UART_PORT_NUM]; 83 84 struct meson_uart_data { 85 bool has_xtal_div2; 86 }; 87 88 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 89 { 90 } 91 92 static unsigned int meson_uart_get_mctrl(struct uart_port *port) 93 { 94 return TIOCM_CTS; 95 } 96 97 static unsigned int meson_uart_tx_empty(struct uart_port *port) 98 { 99 u32 val; 100 101 val = readl(port->membase + AML_UART_STATUS); 102 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); 103 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; 104 } 105 106 static void meson_uart_stop_tx(struct uart_port *port) 107 { 108 u32 val; 109 110 val = readl(port->membase + AML_UART_CONTROL); 111 val &= ~AML_UART_TX_INT_EN; 112 writel(val, port->membase + AML_UART_CONTROL); 113 } 114 115 static void meson_uart_stop_rx(struct uart_port *port) 116 { 117 u32 val; 118 119 val = readl(port->membase + AML_UART_CONTROL); 120 val &= ~AML_UART_RX_EN; 121 writel(val, port->membase + AML_UART_CONTROL); 122 } 123 124 static void meson_uart_shutdown(struct uart_port *port) 125 { 126 unsigned long flags; 127 u32 val; 128 129 free_irq(port->irq, port); 130 131 spin_lock_irqsave(&port->lock, flags); 132 133 val = readl(port->membase + AML_UART_CONTROL); 134 val &= ~AML_UART_RX_EN; 135 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 136 writel(val, port->membase + AML_UART_CONTROL); 137 138 spin_unlock_irqrestore(&port->lock, flags); 139 } 140 141 static void meson_uart_start_tx(struct uart_port *port) 142 { 143 struct circ_buf *xmit = &port->state->xmit; 144 unsigned int ch; 145 u32 val; 146 147 if (uart_tx_stopped(port)) { 148 meson_uart_stop_tx(port); 149 return; 150 } 151 152 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 153 if (port->x_char) { 154 writel(port->x_char, port->membase + AML_UART_WFIFO); 155 port->icount.tx++; 156 port->x_char = 0; 157 continue; 158 } 159 160 if (uart_circ_empty(xmit)) 161 break; 162 163 ch = xmit->buf[xmit->tail]; 164 writel(ch, port->membase + AML_UART_WFIFO); 165 uart_xmit_advance(port, 1); 166 } 167 168 if (!uart_circ_empty(xmit)) { 169 val = readl(port->membase + AML_UART_CONTROL); 170 val |= AML_UART_TX_INT_EN; 171 writel(val, port->membase + AML_UART_CONTROL); 172 } 173 174 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 175 uart_write_wakeup(port); 176 } 177 178 static void meson_receive_chars(struct uart_port *port) 179 { 180 struct tty_port *tport = &port->state->port; 181 char flag; 182 u32 ostatus, status, ch, mode; 183 184 do { 185 flag = TTY_NORMAL; 186 port->icount.rx++; 187 ostatus = status = readl(port->membase + AML_UART_STATUS); 188 189 if (status & AML_UART_ERR) { 190 if (status & AML_UART_TX_FIFO_WERR) 191 port->icount.overrun++; 192 else if (status & AML_UART_FRAME_ERR) 193 port->icount.frame++; 194 else if (status & AML_UART_PARITY_ERR) 195 port->icount.frame++; 196 197 mode = readl(port->membase + AML_UART_CONTROL); 198 mode |= AML_UART_CLEAR_ERR; 199 writel(mode, port->membase + AML_UART_CONTROL); 200 201 /* It doesn't clear to 0 automatically */ 202 mode &= ~AML_UART_CLEAR_ERR; 203 writel(mode, port->membase + AML_UART_CONTROL); 204 205 status &= port->read_status_mask; 206 if (status & AML_UART_FRAME_ERR) 207 flag = TTY_FRAME; 208 else if (status & AML_UART_PARITY_ERR) 209 flag = TTY_PARITY; 210 } 211 212 ch = readl(port->membase + AML_UART_RFIFO); 213 ch &= 0xff; 214 215 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) { 216 port->icount.brk++; 217 flag = TTY_BREAK; 218 if (uart_handle_break(port)) 219 continue; 220 } 221 222 if (uart_handle_sysrq_char(port, ch)) 223 continue; 224 225 if ((status & port->ignore_status_mask) == 0) 226 tty_insert_flip_char(tport, ch, flag); 227 228 if (status & AML_UART_TX_FIFO_WERR) 229 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 230 231 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); 232 233 tty_flip_buffer_push(tport); 234 } 235 236 static irqreturn_t meson_uart_interrupt(int irq, void *dev_id) 237 { 238 struct uart_port *port = (struct uart_port *)dev_id; 239 240 spin_lock(&port->lock); 241 242 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) 243 meson_receive_chars(port); 244 245 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 246 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN) 247 meson_uart_start_tx(port); 248 } 249 250 spin_unlock(&port->lock); 251 252 return IRQ_HANDLED; 253 } 254 255 static const char *meson_uart_type(struct uart_port *port) 256 { 257 return (port->type == PORT_MESON) ? "meson_uart" : NULL; 258 } 259 260 /* 261 * This function is called only from probe() using a temporary io mapping 262 * in order to perform a reset before setting up the device. Since the 263 * temporarily mapped region was successfully requested, there can be no 264 * console on this port at this time. Hence it is not necessary for this 265 * function to acquire the port->lock. (Since there is no console on this 266 * port at this time, the port->lock is not initialized yet.) 267 */ 268 static void meson_uart_reset(struct uart_port *port) 269 { 270 u32 val; 271 272 val = readl(port->membase + AML_UART_CONTROL); 273 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 274 writel(val, port->membase + AML_UART_CONTROL); 275 276 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 277 writel(val, port->membase + AML_UART_CONTROL); 278 } 279 280 static int meson_uart_startup(struct uart_port *port) 281 { 282 unsigned long flags; 283 u32 val; 284 int ret = 0; 285 286 spin_lock_irqsave(&port->lock, flags); 287 288 val = readl(port->membase + AML_UART_CONTROL); 289 val |= AML_UART_CLEAR_ERR; 290 writel(val, port->membase + AML_UART_CONTROL); 291 val &= ~AML_UART_CLEAR_ERR; 292 writel(val, port->membase + AML_UART_CONTROL); 293 294 val |= (AML_UART_RX_EN | AML_UART_TX_EN); 295 writel(val, port->membase + AML_UART_CONTROL); 296 297 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 298 writel(val, port->membase + AML_UART_CONTROL); 299 300 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); 301 writel(val, port->membase + AML_UART_MISC); 302 303 spin_unlock_irqrestore(&port->lock, flags); 304 305 ret = request_irq(port->irq, meson_uart_interrupt, 0, 306 port->name, port); 307 308 return ret; 309 } 310 311 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) 312 { 313 const struct meson_uart_data *private_data = port->private_data; 314 u32 val = 0; 315 316 while (!meson_uart_tx_empty(port)) 317 cpu_relax(); 318 319 if (port->uartclk == 24000000) { 320 unsigned int xtal_div = 3; 321 322 if (private_data && private_data->has_xtal_div2) { 323 xtal_div = 2; 324 val |= AML_UART_BAUD_XTAL_DIV2; 325 } 326 val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1; 327 val |= AML_UART_BAUD_XTAL; 328 } else { 329 val = DIV_ROUND_CLOSEST(port->uartclk / 4, baud) - 1; 330 } 331 val |= AML_UART_BAUD_USE; 332 writel(val, port->membase + AML_UART_REG5); 333 } 334 335 static void meson_uart_set_termios(struct uart_port *port, 336 struct ktermios *termios, 337 const struct ktermios *old) 338 { 339 unsigned int cflags, iflags, baud; 340 unsigned long flags; 341 u32 val; 342 343 spin_lock_irqsave(&port->lock, flags); 344 345 cflags = termios->c_cflag; 346 iflags = termios->c_iflag; 347 348 val = readl(port->membase + AML_UART_CONTROL); 349 350 val &= ~AML_UART_DATA_LEN_MASK; 351 switch (cflags & CSIZE) { 352 case CS8: 353 val |= AML_UART_DATA_LEN_8BIT; 354 break; 355 case CS7: 356 val |= AML_UART_DATA_LEN_7BIT; 357 break; 358 case CS6: 359 val |= AML_UART_DATA_LEN_6BIT; 360 break; 361 case CS5: 362 val |= AML_UART_DATA_LEN_5BIT; 363 break; 364 } 365 366 if (cflags & PARENB) 367 val |= AML_UART_PARITY_EN; 368 else 369 val &= ~AML_UART_PARITY_EN; 370 371 if (cflags & PARODD) 372 val |= AML_UART_PARITY_TYPE; 373 else 374 val &= ~AML_UART_PARITY_TYPE; 375 376 val &= ~AML_UART_STOP_BIT_LEN_MASK; 377 if (cflags & CSTOPB) 378 val |= AML_UART_STOP_BIT_2SB; 379 else 380 val |= AML_UART_STOP_BIT_1SB; 381 382 if (cflags & CRTSCTS) 383 val &= ~AML_UART_TWO_WIRE_EN; 384 else 385 val |= AML_UART_TWO_WIRE_EN; 386 387 writel(val, port->membase + AML_UART_CONTROL); 388 389 baud = uart_get_baud_rate(port, termios, old, 50, 4000000); 390 meson_uart_change_speed(port, baud); 391 392 port->read_status_mask = AML_UART_TX_FIFO_WERR; 393 if (iflags & INPCK) 394 port->read_status_mask |= AML_UART_PARITY_ERR | 395 AML_UART_FRAME_ERR; 396 397 port->ignore_status_mask = 0; 398 if (iflags & IGNPAR) 399 port->ignore_status_mask |= AML_UART_PARITY_ERR | 400 AML_UART_FRAME_ERR; 401 402 uart_update_timeout(port, termios->c_cflag, baud); 403 spin_unlock_irqrestore(&port->lock, flags); 404 } 405 406 static int meson_uart_verify_port(struct uart_port *port, 407 struct serial_struct *ser) 408 { 409 int ret = 0; 410 411 if (port->type != PORT_MESON) 412 ret = -EINVAL; 413 if (port->irq != ser->irq) 414 ret = -EINVAL; 415 if (ser->baud_base < 9600) 416 ret = -EINVAL; 417 return ret; 418 } 419 420 static void meson_uart_release_port(struct uart_port *port) 421 { 422 devm_iounmap(port->dev, port->membase); 423 port->membase = NULL; 424 devm_release_mem_region(port->dev, port->mapbase, port->mapsize); 425 } 426 427 static int meson_uart_request_port(struct uart_port *port) 428 { 429 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize, 430 dev_name(port->dev))) { 431 dev_err(port->dev, "Memory region busy\n"); 432 return -EBUSY; 433 } 434 435 port->membase = devm_ioremap(port->dev, port->mapbase, 436 port->mapsize); 437 if (!port->membase) 438 return -ENOMEM; 439 440 return 0; 441 } 442 443 static void meson_uart_config_port(struct uart_port *port, int flags) 444 { 445 if (flags & UART_CONFIG_TYPE) { 446 port->type = PORT_MESON; 447 meson_uart_request_port(port); 448 } 449 } 450 451 #ifdef CONFIG_CONSOLE_POLL 452 /* 453 * Console polling routines for writing and reading from the uart while 454 * in an interrupt or debug context (i.e. kgdb). 455 */ 456 457 static int meson_uart_poll_get_char(struct uart_port *port) 458 { 459 u32 c; 460 unsigned long flags; 461 462 spin_lock_irqsave(&port->lock, flags); 463 464 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY) 465 c = NO_POLL_CHAR; 466 else 467 c = readl(port->membase + AML_UART_RFIFO); 468 469 spin_unlock_irqrestore(&port->lock, flags); 470 471 return c; 472 } 473 474 static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c) 475 { 476 unsigned long flags; 477 u32 reg; 478 int ret; 479 480 spin_lock_irqsave(&port->lock, flags); 481 482 /* Wait until FIFO is empty or timeout */ 483 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 484 reg & AML_UART_TX_EMPTY, 485 AML_UART_POLL_USEC, 486 AML_UART_TIMEOUT_USEC); 487 if (ret == -ETIMEDOUT) { 488 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 489 goto out; 490 } 491 492 /* Write the character */ 493 writel(c, port->membase + AML_UART_WFIFO); 494 495 /* Wait until FIFO is empty or timeout */ 496 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 497 reg & AML_UART_TX_EMPTY, 498 AML_UART_POLL_USEC, 499 AML_UART_TIMEOUT_USEC); 500 if (ret == -ETIMEDOUT) 501 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 502 503 out: 504 spin_unlock_irqrestore(&port->lock, flags); 505 } 506 507 #endif /* CONFIG_CONSOLE_POLL */ 508 509 static const struct uart_ops meson_uart_ops = { 510 .set_mctrl = meson_uart_set_mctrl, 511 .get_mctrl = meson_uart_get_mctrl, 512 .tx_empty = meson_uart_tx_empty, 513 .start_tx = meson_uart_start_tx, 514 .stop_tx = meson_uart_stop_tx, 515 .stop_rx = meson_uart_stop_rx, 516 .startup = meson_uart_startup, 517 .shutdown = meson_uart_shutdown, 518 .set_termios = meson_uart_set_termios, 519 .type = meson_uart_type, 520 .config_port = meson_uart_config_port, 521 .request_port = meson_uart_request_port, 522 .release_port = meson_uart_release_port, 523 .verify_port = meson_uart_verify_port, 524 #ifdef CONFIG_CONSOLE_POLL 525 .poll_get_char = meson_uart_poll_get_char, 526 .poll_put_char = meson_uart_poll_put_char, 527 #endif 528 }; 529 530 #ifdef CONFIG_SERIAL_MESON_CONSOLE 531 static void meson_uart_enable_tx_engine(struct uart_port *port) 532 { 533 u32 val; 534 535 val = readl(port->membase + AML_UART_CONTROL); 536 val |= AML_UART_TX_EN; 537 writel(val, port->membase + AML_UART_CONTROL); 538 } 539 540 static void meson_console_putchar(struct uart_port *port, unsigned char ch) 541 { 542 if (!port->membase) 543 return; 544 545 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) 546 cpu_relax(); 547 writel(ch, port->membase + AML_UART_WFIFO); 548 } 549 550 static void meson_serial_port_write(struct uart_port *port, const char *s, 551 u_int count) 552 { 553 unsigned long flags; 554 int locked; 555 u32 val, tmp; 556 557 local_irq_save(flags); 558 if (port->sysrq) { 559 locked = 0; 560 } else if (oops_in_progress) { 561 locked = spin_trylock(&port->lock); 562 } else { 563 spin_lock(&port->lock); 564 locked = 1; 565 } 566 567 val = readl(port->membase + AML_UART_CONTROL); 568 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); 569 writel(tmp, port->membase + AML_UART_CONTROL); 570 571 uart_console_write(port, s, count, meson_console_putchar); 572 writel(val, port->membase + AML_UART_CONTROL); 573 574 if (locked) 575 spin_unlock(&port->lock); 576 local_irq_restore(flags); 577 } 578 579 static void meson_serial_console_write(struct console *co, const char *s, 580 u_int count) 581 { 582 struct uart_port *port; 583 584 port = meson_ports[co->index]; 585 if (!port) 586 return; 587 588 meson_serial_port_write(port, s, count); 589 } 590 591 static int meson_serial_console_setup(struct console *co, char *options) 592 { 593 struct uart_port *port; 594 int baud = 115200; 595 int bits = 8; 596 int parity = 'n'; 597 int flow = 'n'; 598 599 if (co->index < 0 || co->index >= AML_UART_PORT_NUM) 600 return -EINVAL; 601 602 port = meson_ports[co->index]; 603 if (!port || !port->membase) 604 return -ENODEV; 605 606 meson_uart_enable_tx_engine(port); 607 608 if (options) 609 uart_parse_options(options, &baud, &parity, &bits, &flow); 610 611 return uart_set_options(port, co, baud, parity, bits, flow); 612 } 613 614 static struct console meson_serial_console = { 615 .name = AML_UART_DEV_NAME, 616 .write = meson_serial_console_write, 617 .device = uart_console_device, 618 .setup = meson_serial_console_setup, 619 .flags = CON_PRINTBUFFER, 620 .index = -1, 621 .data = &meson_uart_driver, 622 }; 623 624 static int __init meson_serial_console_init(void) 625 { 626 register_console(&meson_serial_console); 627 return 0; 628 } 629 630 static void meson_serial_early_console_write(struct console *co, 631 const char *s, 632 u_int count) 633 { 634 struct earlycon_device *dev = co->data; 635 636 meson_serial_port_write(&dev->port, s, count); 637 } 638 639 static int __init 640 meson_serial_early_console_setup(struct earlycon_device *device, const char *opt) 641 { 642 if (!device->port.membase) 643 return -ENODEV; 644 645 meson_uart_enable_tx_engine(&device->port); 646 device->con->write = meson_serial_early_console_write; 647 return 0; 648 } 649 650 OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", 651 meson_serial_early_console_setup); 652 653 #define MESON_SERIAL_CONSOLE (&meson_serial_console) 654 #else 655 static int __init meson_serial_console_init(void) { 656 return 0; 657 } 658 #define MESON_SERIAL_CONSOLE NULL 659 #endif 660 661 static struct uart_driver meson_uart_driver = { 662 .owner = THIS_MODULE, 663 .driver_name = "meson_uart", 664 .dev_name = AML_UART_DEV_NAME, 665 .nr = AML_UART_PORT_NUM, 666 .cons = MESON_SERIAL_CONSOLE, 667 }; 668 669 static int meson_uart_probe_clocks(struct platform_device *pdev, 670 struct uart_port *port) 671 { 672 struct clk *clk_xtal = NULL; 673 struct clk *clk_pclk = NULL; 674 struct clk *clk_baud = NULL; 675 676 clk_pclk = devm_clk_get_enabled(&pdev->dev, "pclk"); 677 if (IS_ERR(clk_pclk)) 678 return PTR_ERR(clk_pclk); 679 680 clk_xtal = devm_clk_get_enabled(&pdev->dev, "xtal"); 681 if (IS_ERR(clk_xtal)) 682 return PTR_ERR(clk_xtal); 683 684 clk_baud = devm_clk_get_enabled(&pdev->dev, "baud"); 685 if (IS_ERR(clk_baud)) 686 return PTR_ERR(clk_baud); 687 688 port->uartclk = clk_get_rate(clk_baud); 689 690 return 0; 691 } 692 693 static int meson_uart_probe(struct platform_device *pdev) 694 { 695 struct resource *res_mem; 696 struct uart_port *port; 697 u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ 698 int ret = 0; 699 int irq; 700 701 if (pdev->dev.of_node) 702 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); 703 704 if (pdev->id < 0) { 705 int id; 706 707 for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { 708 if (!meson_ports[id]) { 709 pdev->id = id; 710 break; 711 } 712 } 713 } 714 715 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) 716 return -EINVAL; 717 718 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 719 if (!res_mem) 720 return -ENODEV; 721 722 irq = platform_get_irq(pdev, 0); 723 if (irq < 0) 724 return irq; 725 726 of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); 727 728 if (meson_ports[pdev->id]) { 729 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); 730 return -EBUSY; 731 } 732 733 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL); 734 if (!port) 735 return -ENOMEM; 736 737 ret = meson_uart_probe_clocks(pdev, port); 738 if (ret) 739 return ret; 740 741 port->iotype = UPIO_MEM; 742 port->mapbase = res_mem->start; 743 port->mapsize = resource_size(res_mem); 744 port->irq = irq; 745 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; 746 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE); 747 port->dev = &pdev->dev; 748 port->line = pdev->id; 749 port->type = PORT_MESON; 750 port->x_char = 0; 751 port->ops = &meson_uart_ops; 752 port->fifosize = fifosize; 753 port->private_data = (void *)device_get_match_data(&pdev->dev); 754 755 meson_ports[pdev->id] = port; 756 platform_set_drvdata(pdev, port); 757 758 /* reset port before registering (and possibly registering console) */ 759 if (meson_uart_request_port(port) >= 0) { 760 meson_uart_reset(port); 761 meson_uart_release_port(port); 762 } 763 764 ret = uart_add_one_port(&meson_uart_driver, port); 765 if (ret) 766 meson_ports[pdev->id] = NULL; 767 768 return ret; 769 } 770 771 static int meson_uart_remove(struct platform_device *pdev) 772 { 773 struct uart_port *port; 774 775 port = platform_get_drvdata(pdev); 776 uart_remove_one_port(&meson_uart_driver, port); 777 meson_ports[pdev->id] = NULL; 778 779 return 0; 780 } 781 782 static struct meson_uart_data meson_g12a_uart_data = { 783 .has_xtal_div2 = true, 784 }; 785 786 static const struct of_device_id meson_uart_dt_match[] = { 787 { .compatible = "amlogic,meson6-uart" }, 788 { .compatible = "amlogic,meson8-uart" }, 789 { .compatible = "amlogic,meson8b-uart" }, 790 { .compatible = "amlogic,meson-gx-uart" }, 791 { 792 .compatible = "amlogic,meson-g12a-uart", 793 .data = (void *)&meson_g12a_uart_data, 794 }, 795 { 796 .compatible = "amlogic,meson-s4-uart", 797 .data = (void *)&meson_g12a_uart_data, 798 }, 799 { /* sentinel */ }, 800 }; 801 MODULE_DEVICE_TABLE(of, meson_uart_dt_match); 802 803 static struct platform_driver meson_uart_platform_driver = { 804 .probe = meson_uart_probe, 805 .remove = meson_uart_remove, 806 .driver = { 807 .name = "meson_uart", 808 .of_match_table = meson_uart_dt_match, 809 }, 810 }; 811 812 static int __init meson_uart_init(void) 813 { 814 int ret; 815 816 ret = meson_serial_console_init(); 817 if (ret) 818 return ret; 819 820 ret = uart_register_driver(&meson_uart_driver); 821 if (ret) 822 return ret; 823 824 ret = platform_driver_register(&meson_uart_platform_driver); 825 if (ret) 826 uart_unregister_driver(&meson_uart_driver); 827 828 return ret; 829 } 830 831 static void __exit meson_uart_exit(void) 832 { 833 platform_driver_unregister(&meson_uart_platform_driver); 834 uart_unregister_driver(&meson_uart_driver); 835 } 836 837 module_init(meson_uart_init); 838 module_exit(meson_uart_exit); 839 840 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 841 MODULE_DESCRIPTION("Amlogic Meson serial port driver"); 842 MODULE_LICENSE("GPL v2"); 843