1 /* 2 * Based on meson_uart.c, by AMLOGIC, INC. 3 * 4 * Copyright (C) 2014 Carlo Caione <carlo@caione.org> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published 8 * by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/console.h> 19 #include <linux/delay.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/module.h> 23 #include <linux/kernel.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/serial.h> 27 #include <linux/serial_core.h> 28 #include <linux/tty.h> 29 #include <linux/tty_flip.h> 30 31 /* Register offsets */ 32 #define AML_UART_WFIFO 0x00 33 #define AML_UART_RFIFO 0x04 34 #define AML_UART_CONTROL 0x08 35 #define AML_UART_STATUS 0x0c 36 #define AML_UART_MISC 0x10 37 #define AML_UART_REG5 0x14 38 39 /* AML_UART_CONTROL bits */ 40 #define AML_UART_TX_EN BIT(12) 41 #define AML_UART_RX_EN BIT(13) 42 #define AML_UART_TX_RST BIT(22) 43 #define AML_UART_RX_RST BIT(23) 44 #define AML_UART_CLR_ERR BIT(24) 45 #define AML_UART_RX_INT_EN BIT(27) 46 #define AML_UART_TX_INT_EN BIT(28) 47 #define AML_UART_DATA_LEN_MASK (0x03 << 20) 48 #define AML_UART_DATA_LEN_8BIT (0x00 << 20) 49 #define AML_UART_DATA_LEN_7BIT (0x01 << 20) 50 #define AML_UART_DATA_LEN_6BIT (0x02 << 20) 51 #define AML_UART_DATA_LEN_5BIT (0x03 << 20) 52 53 /* AML_UART_STATUS bits */ 54 #define AML_UART_PARITY_ERR BIT(16) 55 #define AML_UART_FRAME_ERR BIT(17) 56 #define AML_UART_TX_FIFO_WERR BIT(18) 57 #define AML_UART_RX_EMPTY BIT(20) 58 #define AML_UART_TX_FULL BIT(21) 59 #define AML_UART_TX_EMPTY BIT(22) 60 #define AML_UART_XMIT_BUSY BIT(25) 61 #define AML_UART_ERR (AML_UART_PARITY_ERR | \ 62 AML_UART_FRAME_ERR | \ 63 AML_UART_TX_FIFO_WERR) 64 65 /* AML_UART_CONTROL bits */ 66 #define AML_UART_TWO_WIRE_EN BIT(15) 67 #define AML_UART_PARITY_TYPE BIT(18) 68 #define AML_UART_PARITY_EN BIT(19) 69 #define AML_UART_CLEAR_ERR BIT(24) 70 #define AML_UART_STOP_BIN_LEN_MASK (0x03 << 16) 71 #define AML_UART_STOP_BIN_1SB (0x00 << 16) 72 #define AML_UART_STOP_BIN_2SB (0x01 << 16) 73 74 /* AML_UART_MISC bits */ 75 #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) 76 #define AML_UART_RECV_IRQ(c) ((c) & 0xff) 77 78 /* AML_UART_REG5 bits */ 79 #define AML_UART_BAUD_MASK 0x7fffff 80 #define AML_UART_BAUD_USE BIT(23) 81 #define AML_UART_BAUD_XTAL BIT(24) 82 83 #define AML_UART_PORT_NUM 6 84 #define AML_UART_DEV_NAME "ttyAML" 85 86 87 static struct uart_driver meson_uart_driver; 88 89 static struct uart_port *meson_ports[AML_UART_PORT_NUM]; 90 91 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 92 { 93 } 94 95 static unsigned int meson_uart_get_mctrl(struct uart_port *port) 96 { 97 return TIOCM_CTS; 98 } 99 100 static unsigned int meson_uart_tx_empty(struct uart_port *port) 101 { 102 u32 val; 103 104 val = readl(port->membase + AML_UART_STATUS); 105 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); 106 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; 107 } 108 109 static void meson_uart_stop_tx(struct uart_port *port) 110 { 111 u32 val; 112 113 val = readl(port->membase + AML_UART_CONTROL); 114 val &= ~AML_UART_TX_INT_EN; 115 writel(val, port->membase + AML_UART_CONTROL); 116 } 117 118 static void meson_uart_stop_rx(struct uart_port *port) 119 { 120 u32 val; 121 122 val = readl(port->membase + AML_UART_CONTROL); 123 val &= ~AML_UART_RX_EN; 124 writel(val, port->membase + AML_UART_CONTROL); 125 } 126 127 static void meson_uart_shutdown(struct uart_port *port) 128 { 129 unsigned long flags; 130 u32 val; 131 132 free_irq(port->irq, port); 133 134 spin_lock_irqsave(&port->lock, flags); 135 136 val = readl(port->membase + AML_UART_CONTROL); 137 val &= ~AML_UART_RX_EN; 138 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 139 writel(val, port->membase + AML_UART_CONTROL); 140 141 spin_unlock_irqrestore(&port->lock, flags); 142 } 143 144 static void meson_uart_start_tx(struct uart_port *port) 145 { 146 struct circ_buf *xmit = &port->state->xmit; 147 unsigned int ch; 148 u32 val; 149 150 if (uart_tx_stopped(port)) { 151 meson_uart_stop_tx(port); 152 return; 153 } 154 155 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 156 if (port->x_char) { 157 writel(port->x_char, port->membase + AML_UART_WFIFO); 158 port->icount.tx++; 159 port->x_char = 0; 160 continue; 161 } 162 163 if (uart_circ_empty(xmit)) 164 break; 165 166 ch = xmit->buf[xmit->tail]; 167 writel(ch, port->membase + AML_UART_WFIFO); 168 xmit->tail = (xmit->tail+1) & (SERIAL_XMIT_SIZE - 1); 169 port->icount.tx++; 170 } 171 172 if (!uart_circ_empty(xmit)) { 173 val = readl(port->membase + AML_UART_CONTROL); 174 val |= AML_UART_TX_INT_EN; 175 writel(val, port->membase + AML_UART_CONTROL); 176 } 177 178 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 179 uart_write_wakeup(port); 180 } 181 182 static void meson_receive_chars(struct uart_port *port) 183 { 184 struct tty_port *tport = &port->state->port; 185 char flag; 186 u32 status, ch, mode; 187 188 do { 189 flag = TTY_NORMAL; 190 port->icount.rx++; 191 status = readl(port->membase + AML_UART_STATUS); 192 193 if (status & AML_UART_ERR) { 194 if (status & AML_UART_TX_FIFO_WERR) 195 port->icount.overrun++; 196 else if (status & AML_UART_FRAME_ERR) 197 port->icount.frame++; 198 else if (status & AML_UART_PARITY_ERR) 199 port->icount.frame++; 200 201 mode = readl(port->membase + AML_UART_CONTROL); 202 mode |= AML_UART_CLEAR_ERR; 203 writel(mode, port->membase + AML_UART_CONTROL); 204 205 /* It doesn't clear to 0 automatically */ 206 mode &= ~AML_UART_CLEAR_ERR; 207 writel(mode, port->membase + AML_UART_CONTROL); 208 209 status &= port->read_status_mask; 210 if (status & AML_UART_FRAME_ERR) 211 flag = TTY_FRAME; 212 else if (status & AML_UART_PARITY_ERR) 213 flag = TTY_PARITY; 214 } 215 216 ch = readl(port->membase + AML_UART_RFIFO); 217 ch &= 0xff; 218 219 if ((status & port->ignore_status_mask) == 0) 220 tty_insert_flip_char(tport, ch, flag); 221 222 if (status & AML_UART_TX_FIFO_WERR) 223 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 224 225 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); 226 227 spin_unlock(&port->lock); 228 tty_flip_buffer_push(tport); 229 spin_lock(&port->lock); 230 } 231 232 static irqreturn_t meson_uart_interrupt(int irq, void *dev_id) 233 { 234 struct uart_port *port = (struct uart_port *)dev_id; 235 236 spin_lock(&port->lock); 237 238 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) 239 meson_receive_chars(port); 240 241 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 242 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN) 243 meson_uart_start_tx(port); 244 } 245 246 spin_unlock(&port->lock); 247 248 return IRQ_HANDLED; 249 } 250 251 static const char *meson_uart_type(struct uart_port *port) 252 { 253 return (port->type == PORT_MESON) ? "meson_uart" : NULL; 254 } 255 256 static void meson_uart_reset(struct uart_port *port) 257 { 258 u32 val; 259 260 val = readl(port->membase + AML_UART_CONTROL); 261 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR); 262 writel(val, port->membase + AML_UART_CONTROL); 263 264 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLR_ERR); 265 writel(val, port->membase + AML_UART_CONTROL); 266 } 267 268 static int meson_uart_startup(struct uart_port *port) 269 { 270 u32 val; 271 int ret = 0; 272 273 val = readl(port->membase + AML_UART_CONTROL); 274 val |= AML_UART_CLR_ERR; 275 writel(val, port->membase + AML_UART_CONTROL); 276 val &= ~AML_UART_CLR_ERR; 277 writel(val, port->membase + AML_UART_CONTROL); 278 279 val |= (AML_UART_RX_EN | AML_UART_TX_EN); 280 writel(val, port->membase + AML_UART_CONTROL); 281 282 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 283 writel(val, port->membase + AML_UART_CONTROL); 284 285 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); 286 writel(val, port->membase + AML_UART_MISC); 287 288 ret = request_irq(port->irq, meson_uart_interrupt, 0, 289 port->name, port); 290 291 return ret; 292 } 293 294 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) 295 { 296 u32 val; 297 298 while (!meson_uart_tx_empty(port)) 299 cpu_relax(); 300 301 if (port->uartclk == 24000000) { 302 val = ((port->uartclk / 3) / baud) - 1; 303 val |= AML_UART_BAUD_XTAL; 304 } else { 305 val = ((port->uartclk * 10 / (baud * 4) + 5) / 10) - 1; 306 } 307 val |= AML_UART_BAUD_USE; 308 writel(val, port->membase + AML_UART_REG5); 309 } 310 311 static void meson_uart_set_termios(struct uart_port *port, 312 struct ktermios *termios, 313 struct ktermios *old) 314 { 315 unsigned int cflags, iflags, baud; 316 unsigned long flags; 317 u32 val; 318 319 spin_lock_irqsave(&port->lock, flags); 320 321 cflags = termios->c_cflag; 322 iflags = termios->c_iflag; 323 324 val = readl(port->membase + AML_UART_CONTROL); 325 326 val &= ~AML_UART_DATA_LEN_MASK; 327 switch (cflags & CSIZE) { 328 case CS8: 329 val |= AML_UART_DATA_LEN_8BIT; 330 break; 331 case CS7: 332 val |= AML_UART_DATA_LEN_7BIT; 333 break; 334 case CS6: 335 val |= AML_UART_DATA_LEN_6BIT; 336 break; 337 case CS5: 338 val |= AML_UART_DATA_LEN_5BIT; 339 break; 340 } 341 342 if (cflags & PARENB) 343 val |= AML_UART_PARITY_EN; 344 else 345 val &= ~AML_UART_PARITY_EN; 346 347 if (cflags & PARODD) 348 val |= AML_UART_PARITY_TYPE; 349 else 350 val &= ~AML_UART_PARITY_TYPE; 351 352 val &= ~AML_UART_STOP_BIN_LEN_MASK; 353 if (cflags & CSTOPB) 354 val |= AML_UART_STOP_BIN_2SB; 355 else 356 val |= AML_UART_STOP_BIN_1SB; 357 358 if (cflags & CRTSCTS) 359 val &= ~AML_UART_TWO_WIRE_EN; 360 else 361 val |= AML_UART_TWO_WIRE_EN; 362 363 writel(val, port->membase + AML_UART_CONTROL); 364 365 baud = uart_get_baud_rate(port, termios, old, 9600, 4000000); 366 meson_uart_change_speed(port, baud); 367 368 port->read_status_mask = AML_UART_TX_FIFO_WERR; 369 if (iflags & INPCK) 370 port->read_status_mask |= AML_UART_PARITY_ERR | 371 AML_UART_FRAME_ERR; 372 373 port->ignore_status_mask = 0; 374 if (iflags & IGNPAR) 375 port->ignore_status_mask |= AML_UART_PARITY_ERR | 376 AML_UART_FRAME_ERR; 377 378 uart_update_timeout(port, termios->c_cflag, baud); 379 spin_unlock_irqrestore(&port->lock, flags); 380 } 381 382 static int meson_uart_verify_port(struct uart_port *port, 383 struct serial_struct *ser) 384 { 385 int ret = 0; 386 387 if (port->type != PORT_MESON) 388 ret = -EINVAL; 389 if (port->irq != ser->irq) 390 ret = -EINVAL; 391 if (ser->baud_base < 9600) 392 ret = -EINVAL; 393 return ret; 394 } 395 396 static void meson_uart_release_port(struct uart_port *port) 397 { 398 devm_iounmap(port->dev, port->membase); 399 port->membase = NULL; 400 devm_release_mem_region(port->dev, port->mapbase, port->mapsize); 401 } 402 403 static int meson_uart_request_port(struct uart_port *port) 404 { 405 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize, 406 dev_name(port->dev))) { 407 dev_err(port->dev, "Memory region busy\n"); 408 return -EBUSY; 409 } 410 411 port->membase = devm_ioremap_nocache(port->dev, port->mapbase, 412 port->mapsize); 413 if (!port->membase) 414 return -ENOMEM; 415 416 return 0; 417 } 418 419 static void meson_uart_config_port(struct uart_port *port, int flags) 420 { 421 if (flags & UART_CONFIG_TYPE) { 422 port->type = PORT_MESON; 423 meson_uart_request_port(port); 424 } 425 } 426 427 static struct uart_ops meson_uart_ops = { 428 .set_mctrl = meson_uart_set_mctrl, 429 .get_mctrl = meson_uart_get_mctrl, 430 .tx_empty = meson_uart_tx_empty, 431 .start_tx = meson_uart_start_tx, 432 .stop_tx = meson_uart_stop_tx, 433 .stop_rx = meson_uart_stop_rx, 434 .startup = meson_uart_startup, 435 .shutdown = meson_uart_shutdown, 436 .set_termios = meson_uart_set_termios, 437 .type = meson_uart_type, 438 .config_port = meson_uart_config_port, 439 .request_port = meson_uart_request_port, 440 .release_port = meson_uart_release_port, 441 .verify_port = meson_uart_verify_port, 442 }; 443 444 #ifdef CONFIG_SERIAL_MESON_CONSOLE 445 static void meson_uart_enable_tx_engine(struct uart_port *port) 446 { 447 u32 val; 448 449 val = readl(port->membase + AML_UART_CONTROL); 450 val |= AML_UART_TX_EN; 451 writel(val, port->membase + AML_UART_CONTROL); 452 } 453 454 static void meson_console_putchar(struct uart_port *port, int ch) 455 { 456 if (!port->membase) 457 return; 458 459 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) 460 cpu_relax(); 461 writel(ch, port->membase + AML_UART_WFIFO); 462 } 463 464 static void meson_serial_port_write(struct uart_port *port, const char *s, 465 u_int count) 466 { 467 unsigned long flags; 468 int locked; 469 u32 val, tmp; 470 471 local_irq_save(flags); 472 if (port->sysrq) { 473 locked = 0; 474 } else if (oops_in_progress) { 475 locked = spin_trylock(&port->lock); 476 } else { 477 spin_lock(&port->lock); 478 locked = 1; 479 } 480 481 val = readl(port->membase + AML_UART_CONTROL); 482 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); 483 writel(tmp, port->membase + AML_UART_CONTROL); 484 485 uart_console_write(port, s, count, meson_console_putchar); 486 writel(val, port->membase + AML_UART_CONTROL); 487 488 if (locked) 489 spin_unlock(&port->lock); 490 local_irq_restore(flags); 491 } 492 493 static void meson_serial_console_write(struct console *co, const char *s, 494 u_int count) 495 { 496 struct uart_port *port; 497 498 port = meson_ports[co->index]; 499 if (!port) 500 return; 501 502 meson_serial_port_write(port, s, count); 503 } 504 505 static int meson_serial_console_setup(struct console *co, char *options) 506 { 507 struct uart_port *port; 508 int baud = 115200; 509 int bits = 8; 510 int parity = 'n'; 511 int flow = 'n'; 512 513 if (co->index < 0 || co->index >= AML_UART_PORT_NUM) 514 return -EINVAL; 515 516 port = meson_ports[co->index]; 517 if (!port || !port->membase) 518 return -ENODEV; 519 520 meson_uart_enable_tx_engine(port); 521 522 if (options) 523 uart_parse_options(options, &baud, &parity, &bits, &flow); 524 525 return uart_set_options(port, co, baud, parity, bits, flow); 526 } 527 528 static struct console meson_serial_console = { 529 .name = AML_UART_DEV_NAME, 530 .write = meson_serial_console_write, 531 .device = uart_console_device, 532 .setup = meson_serial_console_setup, 533 .flags = CON_PRINTBUFFER, 534 .index = -1, 535 .data = &meson_uart_driver, 536 }; 537 538 static int __init meson_serial_console_init(void) 539 { 540 register_console(&meson_serial_console); 541 return 0; 542 } 543 console_initcall(meson_serial_console_init); 544 545 static void meson_serial_early_console_write(struct console *co, 546 const char *s, 547 u_int count) 548 { 549 struct earlycon_device *dev = co->data; 550 551 meson_serial_port_write(&dev->port, s, count); 552 } 553 554 static int __init 555 meson_serial_early_console_setup(struct earlycon_device *device, const char *opt) 556 { 557 if (!device->port.membase) 558 return -ENODEV; 559 560 meson_uart_enable_tx_engine(&device->port); 561 device->con->write = meson_serial_early_console_write; 562 return 0; 563 } 564 /* Legacy bindings, should be removed when no more used */ 565 OF_EARLYCON_DECLARE(meson, "amlogic,meson-uart", 566 meson_serial_early_console_setup); 567 /* Stable bindings */ 568 OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", 569 meson_serial_early_console_setup); 570 571 #define MESON_SERIAL_CONSOLE (&meson_serial_console) 572 #else 573 #define MESON_SERIAL_CONSOLE NULL 574 #endif 575 576 static struct uart_driver meson_uart_driver = { 577 .owner = THIS_MODULE, 578 .driver_name = "meson_uart", 579 .dev_name = AML_UART_DEV_NAME, 580 .nr = AML_UART_PORT_NUM, 581 .cons = MESON_SERIAL_CONSOLE, 582 }; 583 584 static inline struct clk *meson_uart_probe_clock(struct device *dev, 585 const char *id) 586 { 587 struct clk *clk = NULL; 588 int ret; 589 590 clk = devm_clk_get(dev, id); 591 if (IS_ERR(clk)) 592 return clk; 593 594 ret = clk_prepare_enable(clk); 595 if (ret) { 596 dev_err(dev, "couldn't enable clk\n"); 597 return ERR_PTR(ret); 598 } 599 600 devm_add_action_or_reset(dev, 601 (void(*)(void *))clk_disable_unprepare, 602 clk); 603 604 return clk; 605 } 606 607 /* 608 * This function gets clocks in the legacy non-stable DT bindings. 609 * This code will be remove once all the platforms switch to the 610 * new DT bindings. 611 */ 612 static int meson_uart_probe_clocks_legacy(struct platform_device *pdev, 613 struct uart_port *port) 614 { 615 struct clk *clk = NULL; 616 617 clk = meson_uart_probe_clock(&pdev->dev, NULL); 618 if (IS_ERR(clk)) 619 return PTR_ERR(clk); 620 621 port->uartclk = clk_get_rate(clk); 622 623 return 0; 624 } 625 626 static int meson_uart_probe_clocks(struct platform_device *pdev, 627 struct uart_port *port) 628 { 629 struct clk *clk_xtal = NULL; 630 struct clk *clk_pclk = NULL; 631 struct clk *clk_baud = NULL; 632 633 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk"); 634 if (IS_ERR(clk_pclk)) 635 return PTR_ERR(clk_pclk); 636 637 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal"); 638 if (IS_ERR(clk_xtal)) 639 return PTR_ERR(clk_xtal); 640 641 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud"); 642 if (IS_ERR(clk_baud)) 643 return PTR_ERR(clk_baud); 644 645 port->uartclk = clk_get_rate(clk_baud); 646 647 return 0; 648 } 649 650 static int meson_uart_probe(struct platform_device *pdev) 651 { 652 struct resource *res_mem, *res_irq; 653 struct uart_port *port; 654 int ret = 0; 655 656 if (pdev->dev.of_node) 657 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); 658 659 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) 660 return -EINVAL; 661 662 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 663 if (!res_mem) 664 return -ENODEV; 665 666 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 667 if (!res_irq) 668 return -ENODEV; 669 670 if (meson_ports[pdev->id]) { 671 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); 672 return -EBUSY; 673 } 674 675 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL); 676 if (!port) 677 return -ENOMEM; 678 679 /* Use legacy way until all platforms switch to new bindings */ 680 if (of_device_is_compatible(pdev->dev.of_node, "amlogic,meson-uart")) 681 ret = meson_uart_probe_clocks_legacy(pdev, port); 682 else 683 ret = meson_uart_probe_clocks(pdev, port); 684 685 if (ret) 686 return ret; 687 688 port->iotype = UPIO_MEM; 689 port->mapbase = res_mem->start; 690 port->mapsize = resource_size(res_mem); 691 port->irq = res_irq->start; 692 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; 693 port->dev = &pdev->dev; 694 port->line = pdev->id; 695 port->type = PORT_MESON; 696 port->x_char = 0; 697 port->ops = &meson_uart_ops; 698 port->fifosize = 64; 699 700 meson_ports[pdev->id] = port; 701 platform_set_drvdata(pdev, port); 702 703 /* reset port before registering (and possibly registering console) */ 704 if (meson_uart_request_port(port) >= 0) { 705 meson_uart_reset(port); 706 meson_uart_release_port(port); 707 } 708 709 ret = uart_add_one_port(&meson_uart_driver, port); 710 if (ret) 711 meson_ports[pdev->id] = NULL; 712 713 return ret; 714 } 715 716 static int meson_uart_remove(struct platform_device *pdev) 717 { 718 struct uart_port *port; 719 720 port = platform_get_drvdata(pdev); 721 uart_remove_one_port(&meson_uart_driver, port); 722 meson_ports[pdev->id] = NULL; 723 724 return 0; 725 } 726 727 static const struct of_device_id meson_uart_dt_match[] = { 728 /* Legacy bindings, should be removed when no more used */ 729 { .compatible = "amlogic,meson-uart" }, 730 /* Stable bindings */ 731 { .compatible = "amlogic,meson6-uart" }, 732 { .compatible = "amlogic,meson8-uart" }, 733 { .compatible = "amlogic,meson8b-uart" }, 734 { .compatible = "amlogic,meson-gx-uart" }, 735 { /* sentinel */ }, 736 }; 737 MODULE_DEVICE_TABLE(of, meson_uart_dt_match); 738 739 static struct platform_driver meson_uart_platform_driver = { 740 .probe = meson_uart_probe, 741 .remove = meson_uart_remove, 742 .driver = { 743 .name = "meson_uart", 744 .of_match_table = meson_uart_dt_match, 745 }, 746 }; 747 748 static int __init meson_uart_init(void) 749 { 750 int ret; 751 752 ret = uart_register_driver(&meson_uart_driver); 753 if (ret) 754 return ret; 755 756 ret = platform_driver_register(&meson_uart_platform_driver); 757 if (ret) 758 uart_unregister_driver(&meson_uart_driver); 759 760 return ret; 761 } 762 763 static void __exit meson_uart_exit(void) 764 { 765 platform_driver_unregister(&meson_uart_platform_driver); 766 uart_unregister_driver(&meson_uart_driver); 767 } 768 769 module_init(meson_uart_init); 770 module_exit(meson_uart_exit); 771 772 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 773 MODULE_DESCRIPTION("Amlogic Meson serial port driver"); 774 MODULE_LICENSE("GPL v2"); 775