1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Based on meson_uart.c, by AMLOGIC, INC. 4 * 5 * Copyright (C) 2014 Carlo Caione <carlo@caione.org> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/delay.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/serial.h> 19 #include <linux/serial_core.h> 20 #include <linux/tty.h> 21 #include <linux/tty_flip.h> 22 23 /* Register offsets */ 24 #define AML_UART_WFIFO 0x00 25 #define AML_UART_RFIFO 0x04 26 #define AML_UART_CONTROL 0x08 27 #define AML_UART_STATUS 0x0c 28 #define AML_UART_MISC 0x10 29 #define AML_UART_REG5 0x14 30 31 /* AML_UART_CONTROL bits */ 32 #define AML_UART_TX_EN BIT(12) 33 #define AML_UART_RX_EN BIT(13) 34 #define AML_UART_TWO_WIRE_EN BIT(15) 35 #define AML_UART_STOP_BIT_LEN_MASK (0x03 << 16) 36 #define AML_UART_STOP_BIT_1SB (0x00 << 16) 37 #define AML_UART_STOP_BIT_2SB (0x01 << 16) 38 #define AML_UART_PARITY_TYPE BIT(18) 39 #define AML_UART_PARITY_EN BIT(19) 40 #define AML_UART_TX_RST BIT(22) 41 #define AML_UART_RX_RST BIT(23) 42 #define AML_UART_CLEAR_ERR BIT(24) 43 #define AML_UART_RX_INT_EN BIT(27) 44 #define AML_UART_TX_INT_EN BIT(28) 45 #define AML_UART_DATA_LEN_MASK (0x03 << 20) 46 #define AML_UART_DATA_LEN_8BIT (0x00 << 20) 47 #define AML_UART_DATA_LEN_7BIT (0x01 << 20) 48 #define AML_UART_DATA_LEN_6BIT (0x02 << 20) 49 #define AML_UART_DATA_LEN_5BIT (0x03 << 20) 50 51 /* AML_UART_STATUS bits */ 52 #define AML_UART_PARITY_ERR BIT(16) 53 #define AML_UART_FRAME_ERR BIT(17) 54 #define AML_UART_TX_FIFO_WERR BIT(18) 55 #define AML_UART_RX_EMPTY BIT(20) 56 #define AML_UART_TX_FULL BIT(21) 57 #define AML_UART_TX_EMPTY BIT(22) 58 #define AML_UART_XMIT_BUSY BIT(25) 59 #define AML_UART_ERR (AML_UART_PARITY_ERR | \ 60 AML_UART_FRAME_ERR | \ 61 AML_UART_TX_FIFO_WERR) 62 63 /* AML_UART_MISC bits */ 64 #define AML_UART_XMIT_IRQ(c) (((c) & 0xff) << 8) 65 #define AML_UART_RECV_IRQ(c) ((c) & 0xff) 66 67 /* AML_UART_REG5 bits */ 68 #define AML_UART_BAUD_MASK 0x7fffff 69 #define AML_UART_BAUD_USE BIT(23) 70 #define AML_UART_BAUD_XTAL BIT(24) 71 #define AML_UART_BAUD_XTAL_DIV2 BIT(27) 72 73 #define AML_UART_PORT_NUM 12 74 #define AML_UART_PORT_OFFSET 6 75 #define AML_UART_DEV_NAME "ttyAML" 76 77 #define AML_UART_POLL_USEC 5 78 #define AML_UART_TIMEOUT_USEC 10000 79 80 static struct uart_driver meson_uart_driver; 81 82 static struct uart_port *meson_ports[AML_UART_PORT_NUM]; 83 84 struct meson_uart_data { 85 bool has_xtal_div2; 86 }; 87 88 static void meson_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) 89 { 90 } 91 92 static unsigned int meson_uart_get_mctrl(struct uart_port *port) 93 { 94 return TIOCM_CTS; 95 } 96 97 static unsigned int meson_uart_tx_empty(struct uart_port *port) 98 { 99 u32 val; 100 101 val = readl(port->membase + AML_UART_STATUS); 102 val &= (AML_UART_TX_EMPTY | AML_UART_XMIT_BUSY); 103 return (val == AML_UART_TX_EMPTY) ? TIOCSER_TEMT : 0; 104 } 105 106 static void meson_uart_stop_tx(struct uart_port *port) 107 { 108 u32 val; 109 110 val = readl(port->membase + AML_UART_CONTROL); 111 val &= ~AML_UART_TX_INT_EN; 112 writel(val, port->membase + AML_UART_CONTROL); 113 } 114 115 static void meson_uart_stop_rx(struct uart_port *port) 116 { 117 u32 val; 118 119 val = readl(port->membase + AML_UART_CONTROL); 120 val &= ~AML_UART_RX_EN; 121 writel(val, port->membase + AML_UART_CONTROL); 122 } 123 124 static void meson_uart_shutdown(struct uart_port *port) 125 { 126 unsigned long flags; 127 u32 val; 128 129 free_irq(port->irq, port); 130 131 spin_lock_irqsave(&port->lock, flags); 132 133 val = readl(port->membase + AML_UART_CONTROL); 134 val &= ~AML_UART_RX_EN; 135 val &= ~(AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 136 writel(val, port->membase + AML_UART_CONTROL); 137 138 spin_unlock_irqrestore(&port->lock, flags); 139 } 140 141 static void meson_uart_start_tx(struct uart_port *port) 142 { 143 struct circ_buf *xmit = &port->state->xmit; 144 unsigned int ch; 145 u32 val; 146 147 if (uart_tx_stopped(port)) { 148 meson_uart_stop_tx(port); 149 return; 150 } 151 152 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 153 if (port->x_char) { 154 writel(port->x_char, port->membase + AML_UART_WFIFO); 155 port->icount.tx++; 156 port->x_char = 0; 157 continue; 158 } 159 160 if (uart_circ_empty(xmit)) 161 break; 162 163 ch = xmit->buf[xmit->tail]; 164 writel(ch, port->membase + AML_UART_WFIFO); 165 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 166 port->icount.tx++; 167 } 168 169 if (!uart_circ_empty(xmit)) { 170 val = readl(port->membase + AML_UART_CONTROL); 171 val |= AML_UART_TX_INT_EN; 172 writel(val, port->membase + AML_UART_CONTROL); 173 } 174 175 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 176 uart_write_wakeup(port); 177 } 178 179 static void meson_receive_chars(struct uart_port *port) 180 { 181 struct tty_port *tport = &port->state->port; 182 char flag; 183 u32 ostatus, status, ch, mode; 184 185 do { 186 flag = TTY_NORMAL; 187 port->icount.rx++; 188 ostatus = status = readl(port->membase + AML_UART_STATUS); 189 190 if (status & AML_UART_ERR) { 191 if (status & AML_UART_TX_FIFO_WERR) 192 port->icount.overrun++; 193 else if (status & AML_UART_FRAME_ERR) 194 port->icount.frame++; 195 else if (status & AML_UART_PARITY_ERR) 196 port->icount.frame++; 197 198 mode = readl(port->membase + AML_UART_CONTROL); 199 mode |= AML_UART_CLEAR_ERR; 200 writel(mode, port->membase + AML_UART_CONTROL); 201 202 /* It doesn't clear to 0 automatically */ 203 mode &= ~AML_UART_CLEAR_ERR; 204 writel(mode, port->membase + AML_UART_CONTROL); 205 206 status &= port->read_status_mask; 207 if (status & AML_UART_FRAME_ERR) 208 flag = TTY_FRAME; 209 else if (status & AML_UART_PARITY_ERR) 210 flag = TTY_PARITY; 211 } 212 213 ch = readl(port->membase + AML_UART_RFIFO); 214 ch &= 0xff; 215 216 if ((ostatus & AML_UART_FRAME_ERR) && (ch == 0)) { 217 port->icount.brk++; 218 flag = TTY_BREAK; 219 if (uart_handle_break(port)) 220 continue; 221 } 222 223 if (uart_handle_sysrq_char(port, ch)) 224 continue; 225 226 if ((status & port->ignore_status_mask) == 0) 227 tty_insert_flip_char(tport, ch, flag); 228 229 if (status & AML_UART_TX_FIFO_WERR) 230 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 231 232 } while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)); 233 234 tty_flip_buffer_push(tport); 235 } 236 237 static irqreturn_t meson_uart_interrupt(int irq, void *dev_id) 238 { 239 struct uart_port *port = (struct uart_port *)dev_id; 240 241 spin_lock(&port->lock); 242 243 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY)) 244 meson_receive_chars(port); 245 246 if (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { 247 if (readl(port->membase + AML_UART_CONTROL) & AML_UART_TX_INT_EN) 248 meson_uart_start_tx(port); 249 } 250 251 spin_unlock(&port->lock); 252 253 return IRQ_HANDLED; 254 } 255 256 static const char *meson_uart_type(struct uart_port *port) 257 { 258 return (port->type == PORT_MESON) ? "meson_uart" : NULL; 259 } 260 261 /* 262 * This function is called only from probe() using a temporary io mapping 263 * in order to perform a reset before setting up the device. Since the 264 * temporarily mapped region was successfully requested, there can be no 265 * console on this port at this time. Hence it is not necessary for this 266 * function to acquire the port->lock. (Since there is no console on this 267 * port at this time, the port->lock is not initialized yet.) 268 */ 269 static void meson_uart_reset(struct uart_port *port) 270 { 271 u32 val; 272 273 val = readl(port->membase + AML_UART_CONTROL); 274 val |= (AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 275 writel(val, port->membase + AML_UART_CONTROL); 276 277 val &= ~(AML_UART_RX_RST | AML_UART_TX_RST | AML_UART_CLEAR_ERR); 278 writel(val, port->membase + AML_UART_CONTROL); 279 } 280 281 static int meson_uart_startup(struct uart_port *port) 282 { 283 unsigned long flags; 284 u32 val; 285 int ret = 0; 286 287 spin_lock_irqsave(&port->lock, flags); 288 289 val = readl(port->membase + AML_UART_CONTROL); 290 val |= AML_UART_CLEAR_ERR; 291 writel(val, port->membase + AML_UART_CONTROL); 292 val &= ~AML_UART_CLEAR_ERR; 293 writel(val, port->membase + AML_UART_CONTROL); 294 295 val |= (AML_UART_RX_EN | AML_UART_TX_EN); 296 writel(val, port->membase + AML_UART_CONTROL); 297 298 val |= (AML_UART_RX_INT_EN | AML_UART_TX_INT_EN); 299 writel(val, port->membase + AML_UART_CONTROL); 300 301 val = (AML_UART_RECV_IRQ(1) | AML_UART_XMIT_IRQ(port->fifosize / 2)); 302 writel(val, port->membase + AML_UART_MISC); 303 304 spin_unlock_irqrestore(&port->lock, flags); 305 306 ret = request_irq(port->irq, meson_uart_interrupt, 0, 307 port->name, port); 308 309 return ret; 310 } 311 312 static void meson_uart_change_speed(struct uart_port *port, unsigned long baud) 313 { 314 const struct meson_uart_data *private_data = port->private_data; 315 u32 val = 0; 316 317 while (!meson_uart_tx_empty(port)) 318 cpu_relax(); 319 320 if (port->uartclk == 24000000) { 321 unsigned int xtal_div = 3; 322 323 if (private_data && private_data->has_xtal_div2) { 324 xtal_div = 2; 325 val |= AML_UART_BAUD_XTAL_DIV2; 326 } 327 val |= DIV_ROUND_CLOSEST(port->uartclk / xtal_div, baud) - 1; 328 val |= AML_UART_BAUD_XTAL; 329 } else { 330 val = DIV_ROUND_CLOSEST(port->uartclk / 4, baud) - 1; 331 } 332 val |= AML_UART_BAUD_USE; 333 writel(val, port->membase + AML_UART_REG5); 334 } 335 336 static void meson_uart_set_termios(struct uart_port *port, 337 struct ktermios *termios, 338 struct ktermios *old) 339 { 340 unsigned int cflags, iflags, baud; 341 unsigned long flags; 342 u32 val; 343 344 spin_lock_irqsave(&port->lock, flags); 345 346 cflags = termios->c_cflag; 347 iflags = termios->c_iflag; 348 349 val = readl(port->membase + AML_UART_CONTROL); 350 351 val &= ~AML_UART_DATA_LEN_MASK; 352 switch (cflags & CSIZE) { 353 case CS8: 354 val |= AML_UART_DATA_LEN_8BIT; 355 break; 356 case CS7: 357 val |= AML_UART_DATA_LEN_7BIT; 358 break; 359 case CS6: 360 val |= AML_UART_DATA_LEN_6BIT; 361 break; 362 case CS5: 363 val |= AML_UART_DATA_LEN_5BIT; 364 break; 365 } 366 367 if (cflags & PARENB) 368 val |= AML_UART_PARITY_EN; 369 else 370 val &= ~AML_UART_PARITY_EN; 371 372 if (cflags & PARODD) 373 val |= AML_UART_PARITY_TYPE; 374 else 375 val &= ~AML_UART_PARITY_TYPE; 376 377 val &= ~AML_UART_STOP_BIT_LEN_MASK; 378 if (cflags & CSTOPB) 379 val |= AML_UART_STOP_BIT_2SB; 380 else 381 val |= AML_UART_STOP_BIT_1SB; 382 383 if (cflags & CRTSCTS) 384 val &= ~AML_UART_TWO_WIRE_EN; 385 else 386 val |= AML_UART_TWO_WIRE_EN; 387 388 writel(val, port->membase + AML_UART_CONTROL); 389 390 baud = uart_get_baud_rate(port, termios, old, 50, 4000000); 391 meson_uart_change_speed(port, baud); 392 393 port->read_status_mask = AML_UART_TX_FIFO_WERR; 394 if (iflags & INPCK) 395 port->read_status_mask |= AML_UART_PARITY_ERR | 396 AML_UART_FRAME_ERR; 397 398 port->ignore_status_mask = 0; 399 if (iflags & IGNPAR) 400 port->ignore_status_mask |= AML_UART_PARITY_ERR | 401 AML_UART_FRAME_ERR; 402 403 uart_update_timeout(port, termios->c_cflag, baud); 404 spin_unlock_irqrestore(&port->lock, flags); 405 } 406 407 static int meson_uart_verify_port(struct uart_port *port, 408 struct serial_struct *ser) 409 { 410 int ret = 0; 411 412 if (port->type != PORT_MESON) 413 ret = -EINVAL; 414 if (port->irq != ser->irq) 415 ret = -EINVAL; 416 if (ser->baud_base < 9600) 417 ret = -EINVAL; 418 return ret; 419 } 420 421 static void meson_uart_release_port(struct uart_port *port) 422 { 423 devm_iounmap(port->dev, port->membase); 424 port->membase = NULL; 425 devm_release_mem_region(port->dev, port->mapbase, port->mapsize); 426 } 427 428 static int meson_uart_request_port(struct uart_port *port) 429 { 430 if (!devm_request_mem_region(port->dev, port->mapbase, port->mapsize, 431 dev_name(port->dev))) { 432 dev_err(port->dev, "Memory region busy\n"); 433 return -EBUSY; 434 } 435 436 port->membase = devm_ioremap(port->dev, port->mapbase, 437 port->mapsize); 438 if (!port->membase) 439 return -ENOMEM; 440 441 return 0; 442 } 443 444 static void meson_uart_config_port(struct uart_port *port, int flags) 445 { 446 if (flags & UART_CONFIG_TYPE) { 447 port->type = PORT_MESON; 448 meson_uart_request_port(port); 449 } 450 } 451 452 #ifdef CONFIG_CONSOLE_POLL 453 /* 454 * Console polling routines for writing and reading from the uart while 455 * in an interrupt or debug context (i.e. kgdb). 456 */ 457 458 static int meson_uart_poll_get_char(struct uart_port *port) 459 { 460 u32 c; 461 unsigned long flags; 462 463 spin_lock_irqsave(&port->lock, flags); 464 465 if (readl(port->membase + AML_UART_STATUS) & AML_UART_RX_EMPTY) 466 c = NO_POLL_CHAR; 467 else 468 c = readl(port->membase + AML_UART_RFIFO); 469 470 spin_unlock_irqrestore(&port->lock, flags); 471 472 return c; 473 } 474 475 static void meson_uart_poll_put_char(struct uart_port *port, unsigned char c) 476 { 477 unsigned long flags; 478 u32 reg; 479 int ret; 480 481 spin_lock_irqsave(&port->lock, flags); 482 483 /* Wait until FIFO is empty or timeout */ 484 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 485 reg & AML_UART_TX_EMPTY, 486 AML_UART_POLL_USEC, 487 AML_UART_TIMEOUT_USEC); 488 if (ret == -ETIMEDOUT) { 489 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 490 goto out; 491 } 492 493 /* Write the character */ 494 writel(c, port->membase + AML_UART_WFIFO); 495 496 /* Wait until FIFO is empty or timeout */ 497 ret = readl_poll_timeout_atomic(port->membase + AML_UART_STATUS, reg, 498 reg & AML_UART_TX_EMPTY, 499 AML_UART_POLL_USEC, 500 AML_UART_TIMEOUT_USEC); 501 if (ret == -ETIMEDOUT) 502 dev_err(port->dev, "Timeout waiting for UART TX EMPTY\n"); 503 504 out: 505 spin_unlock_irqrestore(&port->lock, flags); 506 } 507 508 #endif /* CONFIG_CONSOLE_POLL */ 509 510 static const struct uart_ops meson_uart_ops = { 511 .set_mctrl = meson_uart_set_mctrl, 512 .get_mctrl = meson_uart_get_mctrl, 513 .tx_empty = meson_uart_tx_empty, 514 .start_tx = meson_uart_start_tx, 515 .stop_tx = meson_uart_stop_tx, 516 .stop_rx = meson_uart_stop_rx, 517 .startup = meson_uart_startup, 518 .shutdown = meson_uart_shutdown, 519 .set_termios = meson_uart_set_termios, 520 .type = meson_uart_type, 521 .config_port = meson_uart_config_port, 522 .request_port = meson_uart_request_port, 523 .release_port = meson_uart_release_port, 524 .verify_port = meson_uart_verify_port, 525 #ifdef CONFIG_CONSOLE_POLL 526 .poll_get_char = meson_uart_poll_get_char, 527 .poll_put_char = meson_uart_poll_put_char, 528 #endif 529 }; 530 531 #ifdef CONFIG_SERIAL_MESON_CONSOLE 532 static void meson_uart_enable_tx_engine(struct uart_port *port) 533 { 534 u32 val; 535 536 val = readl(port->membase + AML_UART_CONTROL); 537 val |= AML_UART_TX_EN; 538 writel(val, port->membase + AML_UART_CONTROL); 539 } 540 541 static void meson_console_putchar(struct uart_port *port, unsigned char ch) 542 { 543 if (!port->membase) 544 return; 545 546 while (readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL) 547 cpu_relax(); 548 writel(ch, port->membase + AML_UART_WFIFO); 549 } 550 551 static void meson_serial_port_write(struct uart_port *port, const char *s, 552 u_int count) 553 { 554 unsigned long flags; 555 int locked; 556 u32 val, tmp; 557 558 local_irq_save(flags); 559 if (port->sysrq) { 560 locked = 0; 561 } else if (oops_in_progress) { 562 locked = spin_trylock(&port->lock); 563 } else { 564 spin_lock(&port->lock); 565 locked = 1; 566 } 567 568 val = readl(port->membase + AML_UART_CONTROL); 569 tmp = val & ~(AML_UART_TX_INT_EN | AML_UART_RX_INT_EN); 570 writel(tmp, port->membase + AML_UART_CONTROL); 571 572 uart_console_write(port, s, count, meson_console_putchar); 573 writel(val, port->membase + AML_UART_CONTROL); 574 575 if (locked) 576 spin_unlock(&port->lock); 577 local_irq_restore(flags); 578 } 579 580 static void meson_serial_console_write(struct console *co, const char *s, 581 u_int count) 582 { 583 struct uart_port *port; 584 585 port = meson_ports[co->index]; 586 if (!port) 587 return; 588 589 meson_serial_port_write(port, s, count); 590 } 591 592 static int meson_serial_console_setup(struct console *co, char *options) 593 { 594 struct uart_port *port; 595 int baud = 115200; 596 int bits = 8; 597 int parity = 'n'; 598 int flow = 'n'; 599 600 if (co->index < 0 || co->index >= AML_UART_PORT_NUM) 601 return -EINVAL; 602 603 port = meson_ports[co->index]; 604 if (!port || !port->membase) 605 return -ENODEV; 606 607 meson_uart_enable_tx_engine(port); 608 609 if (options) 610 uart_parse_options(options, &baud, &parity, &bits, &flow); 611 612 return uart_set_options(port, co, baud, parity, bits, flow); 613 } 614 615 static struct console meson_serial_console = { 616 .name = AML_UART_DEV_NAME, 617 .write = meson_serial_console_write, 618 .device = uart_console_device, 619 .setup = meson_serial_console_setup, 620 .flags = CON_PRINTBUFFER, 621 .index = -1, 622 .data = &meson_uart_driver, 623 }; 624 625 static int __init meson_serial_console_init(void) 626 { 627 register_console(&meson_serial_console); 628 return 0; 629 } 630 631 static void meson_serial_early_console_write(struct console *co, 632 const char *s, 633 u_int count) 634 { 635 struct earlycon_device *dev = co->data; 636 637 meson_serial_port_write(&dev->port, s, count); 638 } 639 640 static int __init 641 meson_serial_early_console_setup(struct earlycon_device *device, const char *opt) 642 { 643 if (!device->port.membase) 644 return -ENODEV; 645 646 meson_uart_enable_tx_engine(&device->port); 647 device->con->write = meson_serial_early_console_write; 648 return 0; 649 } 650 651 OF_EARLYCON_DECLARE(meson, "amlogic,meson-ao-uart", 652 meson_serial_early_console_setup); 653 654 #define MESON_SERIAL_CONSOLE (&meson_serial_console) 655 #else 656 static int __init meson_serial_console_init(void) { 657 return 0; 658 } 659 #define MESON_SERIAL_CONSOLE NULL 660 #endif 661 662 static struct uart_driver meson_uart_driver = { 663 .owner = THIS_MODULE, 664 .driver_name = "meson_uart", 665 .dev_name = AML_UART_DEV_NAME, 666 .nr = AML_UART_PORT_NUM, 667 .cons = MESON_SERIAL_CONSOLE, 668 }; 669 670 static inline struct clk *meson_uart_probe_clock(struct device *dev, 671 const char *id) 672 { 673 struct clk *clk = NULL; 674 int ret; 675 676 clk = devm_clk_get(dev, id); 677 if (IS_ERR(clk)) 678 return clk; 679 680 ret = clk_prepare_enable(clk); 681 if (ret) { 682 dev_err(dev, "couldn't enable clk\n"); 683 return ERR_PTR(ret); 684 } 685 686 devm_add_action_or_reset(dev, 687 (void(*)(void *))clk_disable_unprepare, 688 clk); 689 690 return clk; 691 } 692 693 static int meson_uart_probe_clocks(struct platform_device *pdev, 694 struct uart_port *port) 695 { 696 struct clk *clk_xtal = NULL; 697 struct clk *clk_pclk = NULL; 698 struct clk *clk_baud = NULL; 699 700 clk_pclk = meson_uart_probe_clock(&pdev->dev, "pclk"); 701 if (IS_ERR(clk_pclk)) 702 return PTR_ERR(clk_pclk); 703 704 clk_xtal = meson_uart_probe_clock(&pdev->dev, "xtal"); 705 if (IS_ERR(clk_xtal)) 706 return PTR_ERR(clk_xtal); 707 708 clk_baud = meson_uart_probe_clock(&pdev->dev, "baud"); 709 if (IS_ERR(clk_baud)) 710 return PTR_ERR(clk_baud); 711 712 port->uartclk = clk_get_rate(clk_baud); 713 714 return 0; 715 } 716 717 static int meson_uart_probe(struct platform_device *pdev) 718 { 719 struct resource *res_mem; 720 struct uart_port *port; 721 u32 fifosize = 64; /* Default is 64, 128 for EE UART_0 */ 722 int ret = 0; 723 int irq; 724 725 if (pdev->dev.of_node) 726 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial"); 727 728 if (pdev->id < 0) { 729 int id; 730 731 for (id = AML_UART_PORT_OFFSET; id < AML_UART_PORT_NUM; id++) { 732 if (!meson_ports[id]) { 733 pdev->id = id; 734 break; 735 } 736 } 737 } 738 739 if (pdev->id < 0 || pdev->id >= AML_UART_PORT_NUM) 740 return -EINVAL; 741 742 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 743 if (!res_mem) 744 return -ENODEV; 745 746 irq = platform_get_irq(pdev, 0); 747 if (irq < 0) 748 return irq; 749 750 of_property_read_u32(pdev->dev.of_node, "fifo-size", &fifosize); 751 752 if (meson_ports[pdev->id]) { 753 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id); 754 return -EBUSY; 755 } 756 757 port = devm_kzalloc(&pdev->dev, sizeof(struct uart_port), GFP_KERNEL); 758 if (!port) 759 return -ENOMEM; 760 761 ret = meson_uart_probe_clocks(pdev, port); 762 if (ret) 763 return ret; 764 765 port->iotype = UPIO_MEM; 766 port->mapbase = res_mem->start; 767 port->mapsize = resource_size(res_mem); 768 port->irq = irq; 769 port->flags = UPF_BOOT_AUTOCONF | UPF_LOW_LATENCY; 770 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MESON_CONSOLE); 771 port->dev = &pdev->dev; 772 port->line = pdev->id; 773 port->type = PORT_MESON; 774 port->x_char = 0; 775 port->ops = &meson_uart_ops; 776 port->fifosize = fifosize; 777 port->private_data = (void *)device_get_match_data(&pdev->dev); 778 779 meson_ports[pdev->id] = port; 780 platform_set_drvdata(pdev, port); 781 782 /* reset port before registering (and possibly registering console) */ 783 if (meson_uart_request_port(port) >= 0) { 784 meson_uart_reset(port); 785 meson_uart_release_port(port); 786 } 787 788 ret = uart_add_one_port(&meson_uart_driver, port); 789 if (ret) 790 meson_ports[pdev->id] = NULL; 791 792 return ret; 793 } 794 795 static int meson_uart_remove(struct platform_device *pdev) 796 { 797 struct uart_port *port; 798 799 port = platform_get_drvdata(pdev); 800 uart_remove_one_port(&meson_uart_driver, port); 801 meson_ports[pdev->id] = NULL; 802 803 return 0; 804 } 805 806 static struct meson_uart_data s4_uart_data = { 807 .has_xtal_div2 = true, 808 }; 809 810 static const struct of_device_id meson_uart_dt_match[] = { 811 { .compatible = "amlogic,meson6-uart" }, 812 { .compatible = "amlogic,meson8-uart" }, 813 { .compatible = "amlogic,meson8b-uart" }, 814 { .compatible = "amlogic,meson-gx-uart" }, 815 { 816 .compatible = "amlogic,meson-s4-uart", 817 .data = (void *)&s4_uart_data, 818 }, 819 { /* sentinel */ }, 820 }; 821 MODULE_DEVICE_TABLE(of, meson_uart_dt_match); 822 823 static struct platform_driver meson_uart_platform_driver = { 824 .probe = meson_uart_probe, 825 .remove = meson_uart_remove, 826 .driver = { 827 .name = "meson_uart", 828 .of_match_table = meson_uart_dt_match, 829 }, 830 }; 831 832 static int __init meson_uart_init(void) 833 { 834 int ret; 835 836 ret = meson_serial_console_init(); 837 if (ret) 838 return ret; 839 840 ret = uart_register_driver(&meson_uart_driver); 841 if (ret) 842 return ret; 843 844 ret = platform_driver_register(&meson_uart_platform_driver); 845 if (ret) 846 uart_unregister_driver(&meson_uart_driver); 847 848 return ret; 849 } 850 851 static void __exit meson_uart_exit(void) 852 { 853 platform_driver_unregister(&meson_uart_platform_driver); 854 uart_unregister_driver(&meson_uart_driver); 855 } 856 857 module_init(meson_uart_init); 858 module_exit(meson_uart_exit); 859 860 MODULE_AUTHOR("Carlo Caione <carlo@caione.org>"); 861 MODULE_DESCRIPTION("Amlogic Meson serial port driver"); 862 MODULE_LICENSE("GPL v2"); 863