1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MEN 16z135 High Speed UART 4 * 5 * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de) 6 * Author: Johannes Thumshirn <johannes.thumshirn@men.de> 7 */ 8 #define pr_fmt(fmt) KBUILD_MODNAME ":" fmt 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/interrupt.h> 13 #include <linux/serial_core.h> 14 #include <linux/ioport.h> 15 #include <linux/io.h> 16 #include <linux/tty_flip.h> 17 #include <linux/bitops.h> 18 #include <linux/mcb.h> 19 20 #define MEN_Z135_MAX_PORTS 12 21 #define MEN_Z135_BASECLK 29491200 22 #define MEN_Z135_FIFO_SIZE 1024 23 #define MEN_Z135_FIFO_WATERMARK 1020 24 25 #define MEN_Z135_STAT_REG 0x0 26 #define MEN_Z135_RX_RAM 0x4 27 #define MEN_Z135_TX_RAM 0x400 28 #define MEN_Z135_RX_CTRL 0x800 29 #define MEN_Z135_TX_CTRL 0x804 30 #define MEN_Z135_CONF_REG 0x808 31 #define MEN_Z135_UART_FREQ 0x80c 32 #define MEN_Z135_BAUD_REG 0x810 33 #define MEN_Z135_TIMEOUT 0x814 34 35 #define IRQ_ID(x) ((x) & 0x1f) 36 37 #define MEN_Z135_IER_RXCIEN BIT(0) /* RX Space IRQ */ 38 #define MEN_Z135_IER_TXCIEN BIT(1) /* TX Space IRQ */ 39 #define MEN_Z135_IER_RLSIEN BIT(2) /* Receiver Line Status IRQ */ 40 #define MEN_Z135_IER_MSIEN BIT(3) /* Modem Status IRQ */ 41 #define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN \ 42 | MEN_Z135_IER_RLSIEN \ 43 | MEN_Z135_IER_MSIEN \ 44 | MEN_Z135_IER_TXCIEN) 45 46 #define MEN_Z135_MCR_DTR BIT(24) 47 #define MEN_Z135_MCR_RTS BIT(25) 48 #define MEN_Z135_MCR_OUT1 BIT(26) 49 #define MEN_Z135_MCR_OUT2 BIT(27) 50 #define MEN_Z135_MCR_LOOP BIT(28) 51 #define MEN_Z135_MCR_RCFC BIT(29) 52 53 #define MEN_Z135_MSR_DCTS BIT(0) 54 #define MEN_Z135_MSR_DDSR BIT(1) 55 #define MEN_Z135_MSR_DRI BIT(2) 56 #define MEN_Z135_MSR_DDCD BIT(3) 57 #define MEN_Z135_MSR_CTS BIT(4) 58 #define MEN_Z135_MSR_DSR BIT(5) 59 #define MEN_Z135_MSR_RI BIT(6) 60 #define MEN_Z135_MSR_DCD BIT(7) 61 62 #define MEN_Z135_LCR_SHIFT 8 /* LCR shift mask */ 63 64 #define MEN_Z135_WL5 0 /* CS5 */ 65 #define MEN_Z135_WL6 1 /* CS6 */ 66 #define MEN_Z135_WL7 2 /* CS7 */ 67 #define MEN_Z135_WL8 3 /* CS8 */ 68 69 #define MEN_Z135_STB_SHIFT 2 /* Stopbits */ 70 #define MEN_Z135_NSTB1 0 71 #define MEN_Z135_NSTB2 1 72 73 #define MEN_Z135_PEN_SHIFT 3 /* Parity enable */ 74 #define MEN_Z135_PAR_DIS 0 75 #define MEN_Z135_PAR_ENA 1 76 77 #define MEN_Z135_PTY_SHIFT 4 /* Parity type */ 78 #define MEN_Z135_PTY_ODD 0 79 #define MEN_Z135_PTY_EVN 1 80 81 #define MEN_Z135_LSR_DR BIT(0) 82 #define MEN_Z135_LSR_OE BIT(1) 83 #define MEN_Z135_LSR_PE BIT(2) 84 #define MEN_Z135_LSR_FE BIT(3) 85 #define MEN_Z135_LSR_BI BIT(4) 86 #define MEN_Z135_LSR_THEP BIT(5) 87 #define MEN_Z135_LSR_TEXP BIT(6) 88 #define MEN_Z135_LSR_RXFIFOERR BIT(7) 89 90 #define MEN_Z135_IRQ_ID_RLS BIT(0) 91 #define MEN_Z135_IRQ_ID_RDA BIT(1) 92 #define MEN_Z135_IRQ_ID_CTI BIT(2) 93 #define MEN_Z135_IRQ_ID_TSA BIT(3) 94 #define MEN_Z135_IRQ_ID_MST BIT(4) 95 96 #define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff) 97 98 #define BYTES_TO_ALIGN(x) ((x) & 0x3) 99 100 static int line; 101 102 static int txlvl = 5; 103 module_param(txlvl, int, S_IRUGO); 104 MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)"); 105 106 static int rxlvl = 6; 107 module_param(rxlvl, int, S_IRUGO); 108 MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)"); 109 110 static int align; 111 module_param(align, int, S_IRUGO); 112 MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0"); 113 114 static uint rx_timeout; 115 module_param(rx_timeout, uint, S_IRUGO); 116 MODULE_PARM_DESC(rx_timeout, "RX timeout. " 117 "Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg"); 118 119 struct men_z135_port { 120 struct uart_port port; 121 struct mcb_device *mdev; 122 struct resource *mem; 123 unsigned char *rxbuf; 124 u32 stat_reg; 125 spinlock_t lock; 126 bool automode; 127 }; 128 #define to_men_z135(port) container_of((port), struct men_z135_port, port) 129 130 /** 131 * men_z135_reg_set() - Set value in register 132 * @uart: The UART port 133 * @addr: Register address 134 * @val: value to set 135 */ 136 static inline void men_z135_reg_set(struct men_z135_port *uart, 137 u32 addr, u32 val) 138 { 139 struct uart_port *port = &uart->port; 140 unsigned long flags; 141 u32 reg; 142 143 spin_lock_irqsave(&uart->lock, flags); 144 145 reg = ioread32(port->membase + addr); 146 reg |= val; 147 iowrite32(reg, port->membase + addr); 148 149 spin_unlock_irqrestore(&uart->lock, flags); 150 } 151 152 /** 153 * men_z135_reg_clr() - Unset value in register 154 * @uart: The UART port 155 * @addr: Register address 156 * @val: value to clear 157 */ 158 static void men_z135_reg_clr(struct men_z135_port *uart, 159 u32 addr, u32 val) 160 { 161 struct uart_port *port = &uart->port; 162 unsigned long flags; 163 u32 reg; 164 165 spin_lock_irqsave(&uart->lock, flags); 166 167 reg = ioread32(port->membase + addr); 168 reg &= ~val; 169 iowrite32(reg, port->membase + addr); 170 171 spin_unlock_irqrestore(&uart->lock, flags); 172 } 173 174 /** 175 * men_z135_handle_modem_status() - Handle change of modem status 176 * @port: The UART port 177 * 178 * Handle change of modem status register. This is done by reading the "delta" 179 * versions of DCD (Data Carrier Detect) and CTS (Clear To Send). 180 */ 181 static void men_z135_handle_modem_status(struct men_z135_port *uart) 182 { 183 u8 msr; 184 185 msr = (uart->stat_reg >> 8) & 0xff; 186 187 if (msr & MEN_Z135_MSR_DDCD) 188 uart_handle_dcd_change(&uart->port, 189 msr & MEN_Z135_MSR_DCD); 190 if (msr & MEN_Z135_MSR_DCTS) 191 uart_handle_cts_change(&uart->port, 192 msr & MEN_Z135_MSR_CTS); 193 } 194 195 static void men_z135_handle_lsr(struct men_z135_port *uart) 196 { 197 struct uart_port *port = &uart->port; 198 u8 lsr; 199 200 lsr = (uart->stat_reg >> 16) & 0xff; 201 202 if (lsr & MEN_Z135_LSR_OE) 203 port->icount.overrun++; 204 if (lsr & MEN_Z135_LSR_PE) 205 port->icount.parity++; 206 if (lsr & MEN_Z135_LSR_FE) 207 port->icount.frame++; 208 if (lsr & MEN_Z135_LSR_BI) { 209 port->icount.brk++; 210 uart_handle_break(port); 211 } 212 } 213 214 /** 215 * get_rx_fifo_content() - Get the number of bytes in RX FIFO 216 * @uart: The UART port 217 * 218 * Read RXC register from hardware and return current FIFO fill size. 219 */ 220 static u16 get_rx_fifo_content(struct men_z135_port *uart) 221 { 222 struct uart_port *port = &uart->port; 223 u32 stat_reg; 224 u16 rxc; 225 u8 rxc_lo; 226 u8 rxc_hi; 227 228 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); 229 rxc_lo = stat_reg >> 24; 230 rxc_hi = (stat_reg & 0xC0) >> 6; 231 232 rxc = rxc_lo | (rxc_hi << 8); 233 234 return rxc; 235 } 236 237 /** 238 * men_z135_handle_rx() - RX tasklet routine 239 * @arg: Pointer to struct men_z135_port 240 * 241 * Copy from RX FIFO and acknowledge number of bytes copied. 242 */ 243 static void men_z135_handle_rx(struct men_z135_port *uart) 244 { 245 struct uart_port *port = &uart->port; 246 struct tty_port *tport = &port->state->port; 247 int copied; 248 u16 size; 249 int room; 250 251 size = get_rx_fifo_content(uart); 252 253 if (size == 0) 254 return; 255 256 /* Avoid accidently accessing TX FIFO instead of RX FIFO. Last 257 * longword in RX FIFO cannot be read.(0x004-0x3FF) 258 */ 259 if (size > MEN_Z135_FIFO_WATERMARK) 260 size = MEN_Z135_FIFO_WATERMARK; 261 262 room = tty_buffer_request_room(tport, size); 263 if (room != size) 264 dev_warn(&uart->mdev->dev, 265 "Not enough room in flip buffer, truncating to %d\n", 266 room); 267 268 if (room == 0) 269 return; 270 271 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room); 272 /* Be sure to first copy all data and then acknowledge it */ 273 mb(); 274 iowrite32(room, port->membase + MEN_Z135_RX_CTRL); 275 276 copied = tty_insert_flip_string(tport, uart->rxbuf, room); 277 if (copied != room) 278 dev_warn(&uart->mdev->dev, 279 "Only copied %d instead of %d bytes\n", 280 copied, room); 281 282 port->icount.rx += copied; 283 284 tty_flip_buffer_push(tport); 285 286 } 287 288 /** 289 * men_z135_handle_tx() - TX tasklet routine 290 * @arg: Pointer to struct men_z135_port 291 * 292 */ 293 static void men_z135_handle_tx(struct men_z135_port *uart) 294 { 295 struct uart_port *port = &uart->port; 296 struct circ_buf *xmit = &port->state->xmit; 297 u32 txc; 298 u32 wptr; 299 int qlen; 300 int n; 301 int txfree; 302 int head; 303 int tail; 304 int s; 305 306 if (uart_circ_empty(xmit)) 307 goto out; 308 309 if (uart_tx_stopped(port)) 310 goto out; 311 312 if (port->x_char) 313 goto out; 314 315 /* calculate bytes to copy */ 316 qlen = uart_circ_chars_pending(xmit); 317 if (qlen <= 0) 318 goto out; 319 320 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); 321 txc = (wptr >> 16) & 0x3ff; 322 wptr &= 0x3ff; 323 324 if (txc > MEN_Z135_FIFO_WATERMARK) 325 txc = MEN_Z135_FIFO_WATERMARK; 326 327 txfree = MEN_Z135_FIFO_WATERMARK - txc; 328 if (txfree <= 0) { 329 dev_err(&uart->mdev->dev, 330 "Not enough room in TX FIFO have %d, need %d\n", 331 txfree, qlen); 332 goto irq_en; 333 } 334 335 /* if we're not aligned, it's better to copy only 1 or 2 bytes and 336 * then the rest. 337 */ 338 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) 339 n = 4 - BYTES_TO_ALIGN(wptr); 340 else if (qlen > txfree) 341 n = txfree; 342 else 343 n = qlen; 344 345 if (n <= 0) 346 goto irq_en; 347 348 head = xmit->head & (UART_XMIT_SIZE - 1); 349 tail = xmit->tail & (UART_XMIT_SIZE - 1); 350 351 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail; 352 n = min(n, s); 353 354 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n); 355 xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1); 356 mmiowb(); 357 358 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL); 359 360 port->icount.tx += n; 361 362 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 363 uart_write_wakeup(port); 364 365 irq_en: 366 if (!uart_circ_empty(xmit)) 367 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); 368 else 369 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); 370 371 out: 372 return; 373 374 } 375 376 /** 377 * men_z135_intr() - Handle legacy IRQs 378 * @irq: The IRQ number 379 * @data: Pointer to UART port 380 * 381 * Check IIR register to find the cause of the interrupt and handle it. 382 * It is possible that multiple interrupts reason bits are set and reading 383 * the IIR is a destructive read, so we always need to check for all possible 384 * interrupts and handle them. 385 */ 386 static irqreturn_t men_z135_intr(int irq, void *data) 387 { 388 struct men_z135_port *uart = (struct men_z135_port *)data; 389 struct uart_port *port = &uart->port; 390 bool handled = false; 391 int irq_id; 392 393 uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG); 394 irq_id = IRQ_ID(uart->stat_reg); 395 396 if (!irq_id) 397 goto out; 398 399 spin_lock(&port->lock); 400 /* It's save to write to IIR[7:6] RXC[9:8] */ 401 iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG); 402 403 if (irq_id & MEN_Z135_IRQ_ID_RLS) { 404 men_z135_handle_lsr(uart); 405 handled = true; 406 } 407 408 if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) { 409 if (irq_id & MEN_Z135_IRQ_ID_CTI) 410 dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n"); 411 men_z135_handle_rx(uart); 412 handled = true; 413 } 414 415 if (irq_id & MEN_Z135_IRQ_ID_TSA) { 416 men_z135_handle_tx(uart); 417 handled = true; 418 } 419 420 if (irq_id & MEN_Z135_IRQ_ID_MST) { 421 men_z135_handle_modem_status(uart); 422 handled = true; 423 } 424 425 spin_unlock(&port->lock); 426 out: 427 return IRQ_RETVAL(handled); 428 } 429 430 /** 431 * men_z135_request_irq() - Request IRQ for 16z135 core 432 * @uart: z135 private uart port structure 433 * 434 * Request an IRQ for 16z135 to use. First try using MSI, if it fails 435 * fall back to using legacy interrupts. 436 */ 437 static int men_z135_request_irq(struct men_z135_port *uart) 438 { 439 struct device *dev = &uart->mdev->dev; 440 struct uart_port *port = &uart->port; 441 int err = 0; 442 443 err = request_irq(port->irq, men_z135_intr, IRQF_SHARED, 444 "men_z135_intr", uart); 445 if (err) 446 dev_err(dev, "Error %d getting interrupt\n", err); 447 448 return err; 449 } 450 451 /** 452 * men_z135_tx_empty() - Handle tx_empty call 453 * @port: The UART port 454 * 455 * This function tests whether the TX FIFO and shifter for the port 456 * described by @port is empty. 457 */ 458 static unsigned int men_z135_tx_empty(struct uart_port *port) 459 { 460 u32 wptr; 461 u16 txc; 462 463 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); 464 txc = (wptr >> 16) & 0x3ff; 465 466 if (txc == 0) 467 return TIOCSER_TEMT; 468 else 469 return 0; 470 } 471 472 /** 473 * men_z135_set_mctrl() - Set modem control lines 474 * @port: The UART port 475 * @mctrl: The modem control lines 476 * 477 * This function sets the modem control lines for a port described by @port 478 * to the state described by @mctrl 479 */ 480 static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl) 481 { 482 u32 old; 483 u32 conf_reg; 484 485 conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG); 486 if (mctrl & TIOCM_RTS) 487 conf_reg |= MEN_Z135_MCR_RTS; 488 else 489 conf_reg &= ~MEN_Z135_MCR_RTS; 490 491 if (mctrl & TIOCM_DTR) 492 conf_reg |= MEN_Z135_MCR_DTR; 493 else 494 conf_reg &= ~MEN_Z135_MCR_DTR; 495 496 if (mctrl & TIOCM_OUT1) 497 conf_reg |= MEN_Z135_MCR_OUT1; 498 else 499 conf_reg &= ~MEN_Z135_MCR_OUT1; 500 501 if (mctrl & TIOCM_OUT2) 502 conf_reg |= MEN_Z135_MCR_OUT2; 503 else 504 conf_reg &= ~MEN_Z135_MCR_OUT2; 505 506 if (mctrl & TIOCM_LOOP) 507 conf_reg |= MEN_Z135_MCR_LOOP; 508 else 509 conf_reg &= ~MEN_Z135_MCR_LOOP; 510 511 if (conf_reg != old) 512 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); 513 } 514 515 /** 516 * men_z135_get_mctrl() - Get modem control lines 517 * @port: The UART port 518 * 519 * Retruns the current state of modem control inputs. 520 */ 521 static unsigned int men_z135_get_mctrl(struct uart_port *port) 522 { 523 unsigned int mctrl = 0; 524 u8 msr; 525 526 msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1); 527 528 if (msr & MEN_Z135_MSR_CTS) 529 mctrl |= TIOCM_CTS; 530 if (msr & MEN_Z135_MSR_DSR) 531 mctrl |= TIOCM_DSR; 532 if (msr & MEN_Z135_MSR_RI) 533 mctrl |= TIOCM_RI; 534 if (msr & MEN_Z135_MSR_DCD) 535 mctrl |= TIOCM_CAR; 536 537 return mctrl; 538 } 539 540 /** 541 * men_z135_stop_tx() - Stop transmitting characters 542 * @port: The UART port 543 * 544 * Stop transmitting characters. This might be due to CTS line becomming 545 * inactive or the tty layer indicating we want to stop transmission due to 546 * an XOFF character. 547 */ 548 static void men_z135_stop_tx(struct uart_port *port) 549 { 550 struct men_z135_port *uart = to_men_z135(port); 551 552 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN); 553 } 554 555 /* 556 * men_z135_disable_ms() - Disable Modem Status 557 * port: The UART port 558 * 559 * Enable Modem Status IRQ. 560 */ 561 static void men_z135_disable_ms(struct uart_port *port) 562 { 563 struct men_z135_port *uart = to_men_z135(port); 564 565 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN); 566 } 567 568 /** 569 * men_z135_start_tx() - Start transmitting characters 570 * @port: The UART port 571 * 572 * Start transmitting character. This actually doesn't transmit anything, but 573 * fires off the TX tasklet. 574 */ 575 static void men_z135_start_tx(struct uart_port *port) 576 { 577 struct men_z135_port *uart = to_men_z135(port); 578 579 if (uart->automode) 580 men_z135_disable_ms(port); 581 582 men_z135_handle_tx(uart); 583 } 584 585 /** 586 * men_z135_stop_rx() - Stop receiving characters 587 * @port: The UART port 588 * 589 * Stop receiving characters; the port is in the process of being closed. 590 */ 591 static void men_z135_stop_rx(struct uart_port *port) 592 { 593 struct men_z135_port *uart = to_men_z135(port); 594 595 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN); 596 } 597 598 /** 599 * men_z135_enable_ms() - Enable Modem Status 600 * port: 601 * 602 * Enable Modem Status IRQ. 603 */ 604 static void men_z135_enable_ms(struct uart_port *port) 605 { 606 struct men_z135_port *uart = to_men_z135(port); 607 608 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN); 609 } 610 611 static int men_z135_startup(struct uart_port *port) 612 { 613 struct men_z135_port *uart = to_men_z135(port); 614 int err; 615 u32 conf_reg = 0; 616 617 err = men_z135_request_irq(uart); 618 if (err) 619 return -ENODEV; 620 621 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); 622 623 /* Activate all but TX space available IRQ */ 624 conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN; 625 conf_reg &= ~(0xff << 16); 626 conf_reg |= (txlvl << 16); 627 conf_reg |= (rxlvl << 20); 628 629 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); 630 631 if (rx_timeout) 632 iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT); 633 634 return 0; 635 } 636 637 static void men_z135_shutdown(struct uart_port *port) 638 { 639 struct men_z135_port *uart = to_men_z135(port); 640 u32 conf_reg = 0; 641 642 conf_reg |= MEN_Z135_ALL_IRQS; 643 644 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg); 645 646 free_irq(uart->port.irq, uart); 647 } 648 649 static void men_z135_set_termios(struct uart_port *port, 650 struct ktermios *termios, 651 struct ktermios *old) 652 { 653 struct men_z135_port *uart = to_men_z135(port); 654 unsigned int baud; 655 u32 conf_reg; 656 u32 bd_reg; 657 u32 uart_freq; 658 u8 lcr; 659 660 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG); 661 lcr = LCR(conf_reg); 662 663 /* byte size */ 664 switch (termios->c_cflag & CSIZE) { 665 case CS5: 666 lcr |= MEN_Z135_WL5; 667 break; 668 case CS6: 669 lcr |= MEN_Z135_WL6; 670 break; 671 case CS7: 672 lcr |= MEN_Z135_WL7; 673 break; 674 case CS8: 675 lcr |= MEN_Z135_WL8; 676 break; 677 } 678 679 /* stop bits */ 680 if (termios->c_cflag & CSTOPB) 681 lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT; 682 683 /* parity */ 684 if (termios->c_cflag & PARENB) { 685 lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT; 686 687 if (termios->c_cflag & PARODD) 688 lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT; 689 else 690 lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT; 691 } else 692 lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT; 693 694 conf_reg |= MEN_Z135_IER_MSIEN; 695 if (termios->c_cflag & CRTSCTS) { 696 conf_reg |= MEN_Z135_MCR_RCFC; 697 uart->automode = true; 698 termios->c_cflag &= ~CLOCAL; 699 } else { 700 conf_reg &= ~MEN_Z135_MCR_RCFC; 701 uart->automode = false; 702 } 703 704 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */ 705 706 conf_reg |= lcr << MEN_Z135_LCR_SHIFT; 707 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG); 708 709 uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ); 710 if (uart_freq == 0) 711 uart_freq = MEN_Z135_BASECLK; 712 713 baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16); 714 715 spin_lock_irq(&port->lock); 716 if (tty_termios_baud_rate(termios)) 717 tty_termios_encode_baud_rate(termios, baud, baud); 718 719 bd_reg = uart_freq / (4 * baud); 720 iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG); 721 722 uart_update_timeout(port, termios->c_cflag, baud); 723 spin_unlock_irq(&port->lock); 724 } 725 726 static const char *men_z135_type(struct uart_port *port) 727 { 728 return KBUILD_MODNAME; 729 } 730 731 static void men_z135_release_port(struct uart_port *port) 732 { 733 struct men_z135_port *uart = to_men_z135(port); 734 735 iounmap(port->membase); 736 port->membase = NULL; 737 738 mcb_release_mem(uart->mem); 739 } 740 741 static int men_z135_request_port(struct uart_port *port) 742 { 743 struct men_z135_port *uart = to_men_z135(port); 744 struct mcb_device *mdev = uart->mdev; 745 struct resource *mem; 746 747 mem = mcb_request_mem(uart->mdev, dev_name(&mdev->dev)); 748 if (IS_ERR(mem)) 749 return PTR_ERR(mem); 750 751 port->mapbase = mem->start; 752 uart->mem = mem; 753 754 port->membase = ioremap(mem->start, resource_size(mem)); 755 if (port->membase == NULL) { 756 mcb_release_mem(mem); 757 return -ENOMEM; 758 } 759 760 return 0; 761 } 762 763 static void men_z135_config_port(struct uart_port *port, int type) 764 { 765 port->type = PORT_MEN_Z135; 766 men_z135_request_port(port); 767 } 768 769 static int men_z135_verify_port(struct uart_port *port, 770 struct serial_struct *serinfo) 771 { 772 return -EINVAL; 773 } 774 775 static const struct uart_ops men_z135_ops = { 776 .tx_empty = men_z135_tx_empty, 777 .set_mctrl = men_z135_set_mctrl, 778 .get_mctrl = men_z135_get_mctrl, 779 .stop_tx = men_z135_stop_tx, 780 .start_tx = men_z135_start_tx, 781 .stop_rx = men_z135_stop_rx, 782 .enable_ms = men_z135_enable_ms, 783 .startup = men_z135_startup, 784 .shutdown = men_z135_shutdown, 785 .set_termios = men_z135_set_termios, 786 .type = men_z135_type, 787 .release_port = men_z135_release_port, 788 .request_port = men_z135_request_port, 789 .config_port = men_z135_config_port, 790 .verify_port = men_z135_verify_port, 791 }; 792 793 static struct uart_driver men_z135_driver = { 794 .owner = THIS_MODULE, 795 .driver_name = KBUILD_MODNAME, 796 .dev_name = "ttyHSU", 797 .major = 0, 798 .minor = 0, 799 .nr = MEN_Z135_MAX_PORTS, 800 }; 801 802 /** 803 * men_z135_probe() - Probe a z135 instance 804 * @mdev: The MCB device 805 * @id: The MCB device ID 806 * 807 * men_z135_probe does the basic setup of hardware resources and registers the 808 * new uart port to the tty layer. 809 */ 810 static int men_z135_probe(struct mcb_device *mdev, 811 const struct mcb_device_id *id) 812 { 813 struct men_z135_port *uart; 814 struct resource *mem; 815 struct device *dev; 816 int err; 817 818 dev = &mdev->dev; 819 820 uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL); 821 if (!uart) 822 return -ENOMEM; 823 824 uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL); 825 if (!uart->rxbuf) 826 return -ENOMEM; 827 828 mem = &mdev->mem; 829 830 mcb_set_drvdata(mdev, uart); 831 832 uart->port.uartclk = MEN_Z135_BASECLK * 16; 833 uart->port.fifosize = MEN_Z135_FIFO_SIZE; 834 uart->port.iotype = UPIO_MEM; 835 uart->port.ops = &men_z135_ops; 836 uart->port.irq = mcb_get_irq(mdev); 837 uart->port.iotype = UPIO_MEM; 838 uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP; 839 uart->port.line = line++; 840 uart->port.dev = dev; 841 uart->port.type = PORT_MEN_Z135; 842 uart->port.mapbase = mem->start; 843 uart->port.membase = NULL; 844 uart->mdev = mdev; 845 846 spin_lock_init(&uart->lock); 847 848 err = uart_add_one_port(&men_z135_driver, &uart->port); 849 if (err) 850 goto err; 851 852 return 0; 853 854 err: 855 free_page((unsigned long) uart->rxbuf); 856 dev_err(dev, "Failed to add UART: %d\n", err); 857 858 return err; 859 } 860 861 /** 862 * men_z135_remove() - Remove a z135 instance from the system 863 * 864 * @mdev: The MCB device 865 */ 866 static void men_z135_remove(struct mcb_device *mdev) 867 { 868 struct men_z135_port *uart = mcb_get_drvdata(mdev); 869 870 line--; 871 uart_remove_one_port(&men_z135_driver, &uart->port); 872 free_page((unsigned long) uart->rxbuf); 873 } 874 875 static const struct mcb_device_id men_z135_ids[] = { 876 { .device = 0x87 }, 877 { } 878 }; 879 MODULE_DEVICE_TABLE(mcb, men_z135_ids); 880 881 static struct mcb_driver mcb_driver = { 882 .driver = { 883 .name = "z135-uart", 884 .owner = THIS_MODULE, 885 }, 886 .probe = men_z135_probe, 887 .remove = men_z135_remove, 888 .id_table = men_z135_ids, 889 }; 890 891 /** 892 * men_z135_init() - Driver Registration Routine 893 * 894 * men_z135_init is the first routine called when the driver is loaded. All it 895 * does is register with the legacy MEN Chameleon subsystem. 896 */ 897 static int __init men_z135_init(void) 898 { 899 int err; 900 901 err = uart_register_driver(&men_z135_driver); 902 if (err) { 903 pr_err("Failed to register UART: %d\n", err); 904 return err; 905 } 906 907 err = mcb_register_driver(&mcb_driver); 908 if (err) { 909 pr_err("Failed to register MCB driver: %d\n", err); 910 uart_unregister_driver(&men_z135_driver); 911 return err; 912 } 913 914 return 0; 915 } 916 module_init(men_z135_init); 917 918 /** 919 * men_z135_exit() - Driver Exit Routine 920 * 921 * men_z135_exit is called just before the driver is removed from memory. 922 */ 923 static void __exit men_z135_exit(void) 924 { 925 mcb_unregister_driver(&mcb_driver); 926 uart_unregister_driver(&men_z135_driver); 927 } 928 module_exit(men_z135_exit); 929 930 MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>"); 931 MODULE_LICENSE("GPL v2"); 932 MODULE_DESCRIPTION("MEN 16z135 High Speed UART"); 933 MODULE_ALIAS("mcb:16z135"); 934