xref: /openbmc/linux/drivers/tty/serial/mcf.c (revision c819e2cf) 
1 /****************************************************************************/
2 
3 /*
4  *	mcf.c -- Freescale ColdFire UART driver
5  *
6  *	(C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13 
14 /****************************************************************************/
15 
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/console.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/io.h>
26 #include <linux/uaccess.h>
27 #include <linux/platform_device.h>
28 #include <asm/coldfire.h>
29 #include <asm/mcfsim.h>
30 #include <asm/mcfuart.h>
31 #include <asm/nettel.h>
32 
33 /****************************************************************************/
34 
35 /*
36  *	Some boards implement the DTR/DCD lines using GPIO lines, most
37  *	don't. Dummy out the access macros for those that don't. Those
38  *	that do should define these macros somewhere in there board
39  *	specific inlude files.
40  */
41 #if !defined(mcf_getppdcd)
42 #define	mcf_getppdcd(p)		(1)
43 #endif
44 #if !defined(mcf_getppdtr)
45 #define	mcf_getppdtr(p)		(1)
46 #endif
47 #if !defined(mcf_setppdtr)
48 #define	mcf_setppdtr(p, v)	do { } while (0)
49 #endif
50 
51 /****************************************************************************/
52 
53 /*
54  *	Local per-uart structure.
55  */
56 struct mcf_uart {
57 	struct uart_port	port;
58 	unsigned int		sigs;		/* Local copy of line sigs */
59 	unsigned char		imr;		/* Local IMR mirror */
60 };
61 
62 /****************************************************************************/
63 
64 static unsigned int mcf_tx_empty(struct uart_port *port)
65 {
66 	return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
67 		TIOCSER_TEMT : 0;
68 }
69 
70 /****************************************************************************/
71 
72 static unsigned int mcf_get_mctrl(struct uart_port *port)
73 {
74 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
75 	unsigned int sigs;
76 
77 	sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
78 		0 : TIOCM_CTS;
79 	sigs |= (pp->sigs & TIOCM_RTS);
80 	sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
81 	sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
82 
83 	return sigs;
84 }
85 
86 /****************************************************************************/
87 
88 static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
89 {
90 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
91 
92 	pp->sigs = sigs;
93 	mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
94 	if (sigs & TIOCM_RTS)
95 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
96 	else
97 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
98 }
99 
100 /****************************************************************************/
101 
102 static void mcf_start_tx(struct uart_port *port)
103 {
104 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
105 
106 	if (port->rs485.flags & SER_RS485_ENABLED) {
107 		/* Enable Transmitter */
108 		writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
109 		/* Manually assert RTS */
110 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
111 	}
112 	pp->imr |= MCFUART_UIR_TXREADY;
113 	writeb(pp->imr, port->membase + MCFUART_UIMR);
114 }
115 
116 /****************************************************************************/
117 
118 static void mcf_stop_tx(struct uart_port *port)
119 {
120 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
121 
122 	pp->imr &= ~MCFUART_UIR_TXREADY;
123 	writeb(pp->imr, port->membase + MCFUART_UIMR);
124 }
125 
126 /****************************************************************************/
127 
128 static void mcf_stop_rx(struct uart_port *port)
129 {
130 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
131 
132 	pp->imr &= ~MCFUART_UIR_RXREADY;
133 	writeb(pp->imr, port->membase + MCFUART_UIMR);
134 }
135 
136 /****************************************************************************/
137 
138 static void mcf_break_ctl(struct uart_port *port, int break_state)
139 {
140 	unsigned long flags;
141 
142 	spin_lock_irqsave(&port->lock, flags);
143 	if (break_state == -1)
144 		writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
145 	else
146 		writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
147 	spin_unlock_irqrestore(&port->lock, flags);
148 }
149 
150 /****************************************************************************/
151 
152 static int mcf_startup(struct uart_port *port)
153 {
154 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
155 	unsigned long flags;
156 
157 	spin_lock_irqsave(&port->lock, flags);
158 
159 	/* Reset UART, get it into known state... */
160 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
161 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
162 
163 	/* Enable the UART transmitter and receiver */
164 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
165 		port->membase + MCFUART_UCR);
166 
167 	/* Enable RX interrupts now */
168 	pp->imr = MCFUART_UIR_RXREADY;
169 	writeb(pp->imr, port->membase + MCFUART_UIMR);
170 
171 	spin_unlock_irqrestore(&port->lock, flags);
172 
173 	return 0;
174 }
175 
176 /****************************************************************************/
177 
178 static void mcf_shutdown(struct uart_port *port)
179 {
180 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
181 	unsigned long flags;
182 
183 	spin_lock_irqsave(&port->lock, flags);
184 
185 	/* Disable all interrupts now */
186 	pp->imr = 0;
187 	writeb(pp->imr, port->membase + MCFUART_UIMR);
188 
189 	/* Disable UART transmitter and receiver */
190 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
191 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
192 
193 	spin_unlock_irqrestore(&port->lock, flags);
194 }
195 
196 /****************************************************************************/
197 
198 static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
199 	struct ktermios *old)
200 {
201 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
202 	unsigned long flags;
203 	unsigned int baud, baudclk;
204 #if defined(CONFIG_M5272)
205 	unsigned int baudfr;
206 #endif
207 	unsigned char mr1, mr2;
208 
209 	baud = uart_get_baud_rate(port, termios, old, 0, 230400);
210 #if defined(CONFIG_M5272)
211 	baudclk = (MCF_BUSCLK / baud) / 32;
212 	baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
213 #else
214 	baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
215 #endif
216 
217 	mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
218 	mr2 = 0;
219 
220 	switch (termios->c_cflag & CSIZE) {
221 	case CS5: mr1 |= MCFUART_MR1_CS5; break;
222 	case CS6: mr1 |= MCFUART_MR1_CS6; break;
223 	case CS7: mr1 |= MCFUART_MR1_CS7; break;
224 	case CS8:
225 	default:  mr1 |= MCFUART_MR1_CS8; break;
226 	}
227 
228 	if (termios->c_cflag & PARENB) {
229 		if (termios->c_cflag & CMSPAR) {
230 			if (termios->c_cflag & PARODD)
231 				mr1 |= MCFUART_MR1_PARITYMARK;
232 			else
233 				mr1 |= MCFUART_MR1_PARITYSPACE;
234 		} else {
235 			if (termios->c_cflag & PARODD)
236 				mr1 |= MCFUART_MR1_PARITYODD;
237 			else
238 				mr1 |= MCFUART_MR1_PARITYEVEN;
239 		}
240 	} else {
241 		mr1 |= MCFUART_MR1_PARITYNONE;
242 	}
243 
244 	/*
245 	 * FIXME: port->read_status_mask and port->ignore_status_mask
246 	 * need to be initialized based on termios settings for
247 	 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
248 	 */
249 
250 	if (termios->c_cflag & CSTOPB)
251 		mr2 |= MCFUART_MR2_STOP2;
252 	else
253 		mr2 |= MCFUART_MR2_STOP1;
254 
255 	if (termios->c_cflag & CRTSCTS) {
256 		mr1 |= MCFUART_MR1_RXRTS;
257 		mr2 |= MCFUART_MR2_TXCTS;
258 	}
259 
260 	spin_lock_irqsave(&port->lock, flags);
261 	if (port->rs485.flags & SER_RS485_ENABLED) {
262 		dev_dbg(port->dev, "Setting UART to RS485\n");
263 		mr2 |= MCFUART_MR2_TXRTS;
264 	}
265 
266 	uart_update_timeout(port, termios->c_cflag, baud);
267 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
268 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
269 	writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
270 	writeb(mr1, port->membase + MCFUART_UMR);
271 	writeb(mr2, port->membase + MCFUART_UMR);
272 	writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
273 	writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
274 #if defined(CONFIG_M5272)
275 	writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
276 #endif
277 	writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
278 		port->membase + MCFUART_UCSR);
279 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
280 		port->membase + MCFUART_UCR);
281 	spin_unlock_irqrestore(&port->lock, flags);
282 }
283 
284 /****************************************************************************/
285 
286 static void mcf_rx_chars(struct mcf_uart *pp)
287 {
288 	struct uart_port *port = &pp->port;
289 	unsigned char status, ch, flag;
290 
291 	while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
292 		ch = readb(port->membase + MCFUART_URB);
293 		flag = TTY_NORMAL;
294 		port->icount.rx++;
295 
296 		if (status & MCFUART_USR_RXERR) {
297 			writeb(MCFUART_UCR_CMDRESETERR,
298 				port->membase + MCFUART_UCR);
299 
300 			if (status & MCFUART_USR_RXBREAK) {
301 				port->icount.brk++;
302 				if (uart_handle_break(port))
303 					continue;
304 			} else if (status & MCFUART_USR_RXPARITY) {
305 				port->icount.parity++;
306 			} else if (status & MCFUART_USR_RXOVERRUN) {
307 				port->icount.overrun++;
308 			} else if (status & MCFUART_USR_RXFRAMING) {
309 				port->icount.frame++;
310 			}
311 
312 			status &= port->read_status_mask;
313 
314 			if (status & MCFUART_USR_RXBREAK)
315 				flag = TTY_BREAK;
316 			else if (status & MCFUART_USR_RXPARITY)
317 				flag = TTY_PARITY;
318 			else if (status & MCFUART_USR_RXFRAMING)
319 				flag = TTY_FRAME;
320 		}
321 
322 		if (uart_handle_sysrq_char(port, ch))
323 			continue;
324 		uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
325 	}
326 
327 	spin_unlock(&port->lock);
328 	tty_flip_buffer_push(&port->state->port);
329 	spin_lock(&port->lock);
330 }
331 
332 /****************************************************************************/
333 
334 static void mcf_tx_chars(struct mcf_uart *pp)
335 {
336 	struct uart_port *port = &pp->port;
337 	struct circ_buf *xmit = &port->state->xmit;
338 
339 	if (port->x_char) {
340 		/* Send special char - probably flow control */
341 		writeb(port->x_char, port->membase + MCFUART_UTB);
342 		port->x_char = 0;
343 		port->icount.tx++;
344 		return;
345 	}
346 
347 	while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
348 		if (xmit->head == xmit->tail)
349 			break;
350 		writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
351 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
352 		port->icount.tx++;
353 	}
354 
355 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
356 		uart_write_wakeup(port);
357 
358 	if (xmit->head == xmit->tail) {
359 		pp->imr &= ~MCFUART_UIR_TXREADY;
360 		writeb(pp->imr, port->membase + MCFUART_UIMR);
361 		/* Disable TX to negate RTS automatically */
362 		if (port->rs485.flags & SER_RS485_ENABLED)
363 			writeb(MCFUART_UCR_TXDISABLE,
364 				port->membase + MCFUART_UCR);
365 	}
366 }
367 
368 /****************************************************************************/
369 
370 static irqreturn_t mcf_interrupt(int irq, void *data)
371 {
372 	struct uart_port *port = data;
373 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
374 	unsigned int isr;
375 	irqreturn_t ret = IRQ_NONE;
376 
377 	isr = readb(port->membase + MCFUART_UISR) & pp->imr;
378 
379 	spin_lock(&port->lock);
380 	if (isr & MCFUART_UIR_RXREADY) {
381 		mcf_rx_chars(pp);
382 		ret = IRQ_HANDLED;
383 	}
384 	if (isr & MCFUART_UIR_TXREADY) {
385 		mcf_tx_chars(pp);
386 		ret = IRQ_HANDLED;
387 	}
388 	spin_unlock(&port->lock);
389 
390 	return ret;
391 }
392 
393 /****************************************************************************/
394 
395 static void mcf_config_port(struct uart_port *port, int flags)
396 {
397 	port->type = PORT_MCF;
398 	port->fifosize = MCFUART_TXFIFOSIZE;
399 
400 	/* Clear mask, so no surprise interrupts. */
401 	writeb(0, port->membase + MCFUART_UIMR);
402 
403 	if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
404 		printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
405 			"interrupt vector=%d\n", port->line, port->irq);
406 }
407 
408 /****************************************************************************/
409 
410 static const char *mcf_type(struct uart_port *port)
411 {
412 	return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
413 }
414 
415 /****************************************************************************/
416 
417 static int mcf_request_port(struct uart_port *port)
418 {
419 	/* UARTs always present */
420 	return 0;
421 }
422 
423 /****************************************************************************/
424 
425 static void mcf_release_port(struct uart_port *port)
426 {
427 	/* Nothing to release... */
428 }
429 
430 /****************************************************************************/
431 
432 static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
433 {
434 	if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
435 		return -EINVAL;
436 	return 0;
437 }
438 
439 /****************************************************************************/
440 
441 /* Enable or disable the RS485 support */
442 static int mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
443 {
444 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
445 	unsigned char mr1, mr2;
446 
447 	/* Get mode registers */
448 	mr1 = readb(port->membase + MCFUART_UMR);
449 	mr2 = readb(port->membase + MCFUART_UMR);
450 	if (rs485->flags & SER_RS485_ENABLED) {
451 		dev_dbg(port->dev, "Setting UART to RS485\n");
452 		/* Automatically negate RTS after TX completes */
453 		mr2 |= MCFUART_MR2_TXRTS;
454 	} else {
455 		dev_dbg(port->dev, "Setting UART to RS232\n");
456 		mr2 &= ~MCFUART_MR2_TXRTS;
457 	}
458 	writeb(mr1, port->membase + MCFUART_UMR);
459 	writeb(mr2, port->membase + MCFUART_UMR);
460 	port->rs485 = *rs485;
461 
462 	return 0;
463 }
464 
465 /****************************************************************************/
466 
467 /*
468  *	Define the basic serial functions we support.
469  */
470 static const struct uart_ops mcf_uart_ops = {
471 	.tx_empty	= mcf_tx_empty,
472 	.get_mctrl	= mcf_get_mctrl,
473 	.set_mctrl	= mcf_set_mctrl,
474 	.start_tx	= mcf_start_tx,
475 	.stop_tx	= mcf_stop_tx,
476 	.stop_rx	= mcf_stop_rx,
477 	.break_ctl	= mcf_break_ctl,
478 	.startup	= mcf_startup,
479 	.shutdown	= mcf_shutdown,
480 	.set_termios	= mcf_set_termios,
481 	.type		= mcf_type,
482 	.request_port	= mcf_request_port,
483 	.release_port	= mcf_release_port,
484 	.config_port	= mcf_config_port,
485 	.verify_port	= mcf_verify_port,
486 };
487 
488 static struct mcf_uart mcf_ports[4];
489 
490 #define	MCF_MAXPORTS	ARRAY_SIZE(mcf_ports)
491 
492 /****************************************************************************/
493 #if defined(CONFIG_SERIAL_MCF_CONSOLE)
494 /****************************************************************************/
495 
496 int __init early_mcf_setup(struct mcf_platform_uart *platp)
497 {
498 	struct uart_port *port;
499 	int i;
500 
501 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
502 		port = &mcf_ports[i].port;
503 
504 		port->line = i;
505 		port->type = PORT_MCF;
506 		port->mapbase = platp[i].mapbase;
507 		port->membase = (platp[i].membase) ? platp[i].membase :
508 			(unsigned char __iomem *) port->mapbase;
509 		port->iotype = SERIAL_IO_MEM;
510 		port->irq = platp[i].irq;
511 		port->uartclk = MCF_BUSCLK;
512 		port->flags = UPF_BOOT_AUTOCONF;
513 		port->rs485_config = mcf_config_rs485;
514 		port->ops = &mcf_uart_ops;
515 	}
516 
517 	return 0;
518 }
519 
520 /****************************************************************************/
521 
522 static void mcf_console_putc(struct console *co, const char c)
523 {
524 	struct uart_port *port = &(mcf_ports + co->index)->port;
525 	int i;
526 
527 	for (i = 0; (i < 0x10000); i++) {
528 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
529 			break;
530 	}
531 	writeb(c, port->membase + MCFUART_UTB);
532 	for (i = 0; (i < 0x10000); i++) {
533 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
534 			break;
535 	}
536 }
537 
538 /****************************************************************************/
539 
540 static void mcf_console_write(struct console *co, const char *s, unsigned int count)
541 {
542 	for (; (count); count--, s++) {
543 		mcf_console_putc(co, *s);
544 		if (*s == '\n')
545 			mcf_console_putc(co, '\r');
546 	}
547 }
548 
549 /****************************************************************************/
550 
551 static int __init mcf_console_setup(struct console *co, char *options)
552 {
553 	struct uart_port *port;
554 	int baud = CONFIG_SERIAL_MCF_BAUDRATE;
555 	int bits = 8;
556 	int parity = 'n';
557 	int flow = 'n';
558 
559 	if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
560 		co->index = 0;
561 	port = &mcf_ports[co->index].port;
562 	if (port->membase == 0)
563 		return -ENODEV;
564 
565 	if (options)
566 		uart_parse_options(options, &baud, &parity, &bits, &flow);
567 
568 	return uart_set_options(port, co, baud, parity, bits, flow);
569 }
570 
571 /****************************************************************************/
572 
573 static struct uart_driver mcf_driver;
574 
575 static struct console mcf_console = {
576 	.name		= "ttyS",
577 	.write		= mcf_console_write,
578 	.device		= uart_console_device,
579 	.setup		= mcf_console_setup,
580 	.flags		= CON_PRINTBUFFER,
581 	.index		= -1,
582 	.data		= &mcf_driver,
583 };
584 
585 static int __init mcf_console_init(void)
586 {
587 	register_console(&mcf_console);
588 	return 0;
589 }
590 
591 console_initcall(mcf_console_init);
592 
593 #define	MCF_CONSOLE	&mcf_console
594 
595 /****************************************************************************/
596 #else
597 /****************************************************************************/
598 
599 #define	MCF_CONSOLE	NULL
600 
601 /****************************************************************************/
602 #endif /* CONFIG_MCF_CONSOLE */
603 /****************************************************************************/
604 
605 /*
606  *	Define the mcf UART driver structure.
607  */
608 static struct uart_driver mcf_driver = {
609 	.owner		= THIS_MODULE,
610 	.driver_name	= "mcf",
611 	.dev_name	= "ttyS",
612 	.major		= TTY_MAJOR,
613 	.minor		= 64,
614 	.nr		= MCF_MAXPORTS,
615 	.cons		= MCF_CONSOLE,
616 };
617 
618 /****************************************************************************/
619 
620 static int mcf_probe(struct platform_device *pdev)
621 {
622 	struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
623 	struct uart_port *port;
624 	int i;
625 
626 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
627 		port = &mcf_ports[i].port;
628 
629 		port->line = i;
630 		port->type = PORT_MCF;
631 		port->mapbase = platp[i].mapbase;
632 		port->membase = (platp[i].membase) ? platp[i].membase :
633 			(unsigned char __iomem *) platp[i].mapbase;
634 		port->iotype = SERIAL_IO_MEM;
635 		port->irq = platp[i].irq;
636 		port->uartclk = MCF_BUSCLK;
637 		port->ops = &mcf_uart_ops;
638 		port->flags = UPF_BOOT_AUTOCONF;
639 		port->rs485_config = mcf_config_rs485;
640 
641 		uart_add_one_port(&mcf_driver, port);
642 	}
643 
644 	return 0;
645 }
646 
647 /****************************************************************************/
648 
649 static int mcf_remove(struct platform_device *pdev)
650 {
651 	struct uart_port *port;
652 	int i;
653 
654 	for (i = 0; (i < MCF_MAXPORTS); i++) {
655 		port = &mcf_ports[i].port;
656 		if (port)
657 			uart_remove_one_port(&mcf_driver, port);
658 	}
659 
660 	return 0;
661 }
662 
663 /****************************************************************************/
664 
665 static struct platform_driver mcf_platform_driver = {
666 	.probe		= mcf_probe,
667 	.remove		= mcf_remove,
668 	.driver		= {
669 		.name	= "mcfuart",
670 	},
671 };
672 
673 /****************************************************************************/
674 
675 static int __init mcf_init(void)
676 {
677 	int rc;
678 
679 	printk("ColdFire internal UART serial driver\n");
680 
681 	rc = uart_register_driver(&mcf_driver);
682 	if (rc)
683 		return rc;
684 	rc = platform_driver_register(&mcf_platform_driver);
685 	if (rc) {
686 		uart_unregister_driver(&mcf_driver);
687 		return rc;
688 	}
689 	return 0;
690 }
691 
692 /****************************************************************************/
693 
694 static void __exit mcf_exit(void)
695 {
696 	platform_driver_unregister(&mcf_platform_driver);
697 	uart_unregister_driver(&mcf_driver);
698 }
699 
700 /****************************************************************************/
701 
702 module_init(mcf_init);
703 module_exit(mcf_exit);
704 
705 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
706 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
707 MODULE_LICENSE("GPL");
708 MODULE_ALIAS("platform:mcfuart");
709 
710 /****************************************************************************/
711