xref: /openbmc/linux/drivers/tty/serial/mcf.c (revision 97da55fc) 
1 /****************************************************************************/
2 
3 /*
4  *	mcf.c -- Freescale ColdFire UART driver
5  *
6  *	(C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13 
14 /****************************************************************************/
15 
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/console.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/io.h>
26 #include <linux/uaccess.h>
27 #include <asm/coldfire.h>
28 #include <asm/mcfsim.h>
29 #include <asm/mcfuart.h>
30 #include <asm/nettel.h>
31 
32 /****************************************************************************/
33 
34 /*
35  *	Some boards implement the DTR/DCD lines using GPIO lines, most
36  *	don't. Dummy out the access macros for those that don't. Those
37  *	that do should define these macros somewhere in there board
38  *	specific inlude files.
39  */
40 #if !defined(mcf_getppdcd)
41 #define	mcf_getppdcd(p)		(1)
42 #endif
43 #if !defined(mcf_getppdtr)
44 #define	mcf_getppdtr(p)		(1)
45 #endif
46 #if !defined(mcf_setppdtr)
47 #define	mcf_setppdtr(p, v)	do { } while (0)
48 #endif
49 
50 /****************************************************************************/
51 
52 /*
53  *	Local per-uart structure.
54  */
55 struct mcf_uart {
56 	struct uart_port	port;
57 	unsigned int		sigs;		/* Local copy of line sigs */
58 	unsigned char		imr;		/* Local IMR mirror */
59 	struct serial_rs485	rs485;		/* RS485 settings */
60 };
61 
62 /****************************************************************************/
63 
64 static unsigned int mcf_tx_empty(struct uart_port *port)
65 {
66 	return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
67 		TIOCSER_TEMT : 0;
68 }
69 
70 /****************************************************************************/
71 
72 static unsigned int mcf_get_mctrl(struct uart_port *port)
73 {
74 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
75 	unsigned int sigs;
76 
77 	sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
78 		0 : TIOCM_CTS;
79 	sigs |= (pp->sigs & TIOCM_RTS);
80 	sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
81 	sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
82 
83 	return sigs;
84 }
85 
86 /****************************************************************************/
87 
88 static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
89 {
90 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
91 
92 	pp->sigs = sigs;
93 	mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
94 	if (sigs & TIOCM_RTS)
95 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
96 	else
97 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
98 }
99 
100 /****************************************************************************/
101 
102 static void mcf_start_tx(struct uart_port *port)
103 {
104 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
105 
106 	if (pp->rs485.flags & SER_RS485_ENABLED) {
107 		/* Enable Transmitter */
108 		writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
109 		/* Manually assert RTS */
110 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
111 	}
112 	pp->imr |= MCFUART_UIR_TXREADY;
113 	writeb(pp->imr, port->membase + MCFUART_UIMR);
114 }
115 
116 /****************************************************************************/
117 
118 static void mcf_stop_tx(struct uart_port *port)
119 {
120 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
121 
122 	pp->imr &= ~MCFUART_UIR_TXREADY;
123 	writeb(pp->imr, port->membase + MCFUART_UIMR);
124 }
125 
126 /****************************************************************************/
127 
128 static void mcf_stop_rx(struct uart_port *port)
129 {
130 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
131 
132 	pp->imr &= ~MCFUART_UIR_RXREADY;
133 	writeb(pp->imr, port->membase + MCFUART_UIMR);
134 }
135 
136 /****************************************************************************/
137 
138 static void mcf_break_ctl(struct uart_port *port, int break_state)
139 {
140 	unsigned long flags;
141 
142 	spin_lock_irqsave(&port->lock, flags);
143 	if (break_state == -1)
144 		writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
145 	else
146 		writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
147 	spin_unlock_irqrestore(&port->lock, flags);
148 }
149 
150 /****************************************************************************/
151 
152 static void mcf_enable_ms(struct uart_port *port)
153 {
154 }
155 
156 /****************************************************************************/
157 
158 static int mcf_startup(struct uart_port *port)
159 {
160 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
161 	unsigned long flags;
162 
163 	spin_lock_irqsave(&port->lock, flags);
164 
165 	/* Reset UART, get it into known state... */
166 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
167 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
168 
169 	/* Enable the UART transmitter and receiver */
170 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
171 		port->membase + MCFUART_UCR);
172 
173 	/* Enable RX interrupts now */
174 	pp->imr = MCFUART_UIR_RXREADY;
175 	writeb(pp->imr, port->membase + MCFUART_UIMR);
176 
177 	spin_unlock_irqrestore(&port->lock, flags);
178 
179 	return 0;
180 }
181 
182 /****************************************************************************/
183 
184 static void mcf_shutdown(struct uart_port *port)
185 {
186 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
187 	unsigned long flags;
188 
189 	spin_lock_irqsave(&port->lock, flags);
190 
191 	/* Disable all interrupts now */
192 	pp->imr = 0;
193 	writeb(pp->imr, port->membase + MCFUART_UIMR);
194 
195 	/* Disable UART transmitter and receiver */
196 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
197 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
198 
199 	spin_unlock_irqrestore(&port->lock, flags);
200 }
201 
202 /****************************************************************************/
203 
204 static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
205 	struct ktermios *old)
206 {
207 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
208 	unsigned long flags;
209 	unsigned int baud, baudclk;
210 #if defined(CONFIG_M5272)
211 	unsigned int baudfr;
212 #endif
213 	unsigned char mr1, mr2;
214 
215 	baud = uart_get_baud_rate(port, termios, old, 0, 230400);
216 #if defined(CONFIG_M5272)
217 	baudclk = (MCF_BUSCLK / baud) / 32;
218 	baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
219 #else
220 	baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
221 #endif
222 
223 	mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
224 	mr2 = 0;
225 
226 	switch (termios->c_cflag & CSIZE) {
227 	case CS5: mr1 |= MCFUART_MR1_CS5; break;
228 	case CS6: mr1 |= MCFUART_MR1_CS6; break;
229 	case CS7: mr1 |= MCFUART_MR1_CS7; break;
230 	case CS8:
231 	default:  mr1 |= MCFUART_MR1_CS8; break;
232 	}
233 
234 	if (termios->c_cflag & PARENB) {
235 		if (termios->c_cflag & CMSPAR) {
236 			if (termios->c_cflag & PARODD)
237 				mr1 |= MCFUART_MR1_PARITYMARK;
238 			else
239 				mr1 |= MCFUART_MR1_PARITYSPACE;
240 		} else {
241 			if (termios->c_cflag & PARODD)
242 				mr1 |= MCFUART_MR1_PARITYODD;
243 			else
244 				mr1 |= MCFUART_MR1_PARITYEVEN;
245 		}
246 	} else {
247 		mr1 |= MCFUART_MR1_PARITYNONE;
248 	}
249 
250 	if (termios->c_cflag & CSTOPB)
251 		mr2 |= MCFUART_MR2_STOP2;
252 	else
253 		mr2 |= MCFUART_MR2_STOP1;
254 
255 	if (termios->c_cflag & CRTSCTS) {
256 		mr1 |= MCFUART_MR1_RXRTS;
257 		mr2 |= MCFUART_MR2_TXCTS;
258 	}
259 
260 	if (pp->rs485.flags & SER_RS485_ENABLED) {
261 		dev_dbg(port->dev, "Setting UART to RS485\n");
262 		mr2 |= MCFUART_MR2_TXRTS;
263 	}
264 
265 	spin_lock_irqsave(&port->lock, flags);
266 	uart_update_timeout(port, termios->c_cflag, baud);
267 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
268 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
269 	writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
270 	writeb(mr1, port->membase + MCFUART_UMR);
271 	writeb(mr2, port->membase + MCFUART_UMR);
272 	writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
273 	writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
274 #if defined(CONFIG_M5272)
275 	writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
276 #endif
277 	writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
278 		port->membase + MCFUART_UCSR);
279 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
280 		port->membase + MCFUART_UCR);
281 	spin_unlock_irqrestore(&port->lock, flags);
282 }
283 
284 /****************************************************************************/
285 
286 static void mcf_rx_chars(struct mcf_uart *pp)
287 {
288 	struct uart_port *port = &pp->port;
289 	unsigned char status, ch, flag;
290 
291 	while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
292 		ch = readb(port->membase + MCFUART_URB);
293 		flag = TTY_NORMAL;
294 		port->icount.rx++;
295 
296 		if (status & MCFUART_USR_RXERR) {
297 			writeb(MCFUART_UCR_CMDRESETERR,
298 				port->membase + MCFUART_UCR);
299 
300 			if (status & MCFUART_USR_RXBREAK) {
301 				port->icount.brk++;
302 				if (uart_handle_break(port))
303 					continue;
304 			} else if (status & MCFUART_USR_RXPARITY) {
305 				port->icount.parity++;
306 			} else if (status & MCFUART_USR_RXOVERRUN) {
307 				port->icount.overrun++;
308 			} else if (status & MCFUART_USR_RXFRAMING) {
309 				port->icount.frame++;
310 			}
311 
312 			status &= port->read_status_mask;
313 
314 			if (status & MCFUART_USR_RXBREAK)
315 				flag = TTY_BREAK;
316 			else if (status & MCFUART_USR_RXPARITY)
317 				flag = TTY_PARITY;
318 			else if (status & MCFUART_USR_RXFRAMING)
319 				flag = TTY_FRAME;
320 		}
321 
322 		if (uart_handle_sysrq_char(port, ch))
323 			continue;
324 		uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
325 	}
326 
327 	tty_flip_buffer_push(&port->state->port);
328 }
329 
330 /****************************************************************************/
331 
332 static void mcf_tx_chars(struct mcf_uart *pp)
333 {
334 	struct uart_port *port = &pp->port;
335 	struct circ_buf *xmit = &port->state->xmit;
336 
337 	if (port->x_char) {
338 		/* Send special char - probably flow control */
339 		writeb(port->x_char, port->membase + MCFUART_UTB);
340 		port->x_char = 0;
341 		port->icount.tx++;
342 		return;
343 	}
344 
345 	while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
346 		if (xmit->head == xmit->tail)
347 			break;
348 		writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
349 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
350 		port->icount.tx++;
351 	}
352 
353 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
354 		uart_write_wakeup(port);
355 
356 	if (xmit->head == xmit->tail) {
357 		pp->imr &= ~MCFUART_UIR_TXREADY;
358 		writeb(pp->imr, port->membase + MCFUART_UIMR);
359 		/* Disable TX to negate RTS automatically */
360 		if (pp->rs485.flags & SER_RS485_ENABLED)
361 			writeb(MCFUART_UCR_TXDISABLE,
362 				port->membase + MCFUART_UCR);
363 	}
364 }
365 
366 /****************************************************************************/
367 
368 static irqreturn_t mcf_interrupt(int irq, void *data)
369 {
370 	struct uart_port *port = data;
371 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
372 	unsigned int isr;
373 	irqreturn_t ret = IRQ_NONE;
374 
375 	isr = readb(port->membase + MCFUART_UISR) & pp->imr;
376 
377 	spin_lock(&port->lock);
378 	if (isr & MCFUART_UIR_RXREADY) {
379 		mcf_rx_chars(pp);
380 		ret = IRQ_HANDLED;
381 	}
382 	if (isr & MCFUART_UIR_TXREADY) {
383 		mcf_tx_chars(pp);
384 		ret = IRQ_HANDLED;
385 	}
386 	spin_unlock(&port->lock);
387 
388 	return ret;
389 }
390 
391 /****************************************************************************/
392 
393 static void mcf_config_port(struct uart_port *port, int flags)
394 {
395 	port->type = PORT_MCF;
396 	port->fifosize = MCFUART_TXFIFOSIZE;
397 
398 	/* Clear mask, so no surprise interrupts. */
399 	writeb(0, port->membase + MCFUART_UIMR);
400 
401 	if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
402 		printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
403 			"interrupt vector=%d\n", port->line, port->irq);
404 }
405 
406 /****************************************************************************/
407 
408 static const char *mcf_type(struct uart_port *port)
409 {
410 	return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
411 }
412 
413 /****************************************************************************/
414 
415 static int mcf_request_port(struct uart_port *port)
416 {
417 	/* UARTs always present */
418 	return 0;
419 }
420 
421 /****************************************************************************/
422 
423 static void mcf_release_port(struct uart_port *port)
424 {
425 	/* Nothing to release... */
426 }
427 
428 /****************************************************************************/
429 
430 static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
431 {
432 	if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
433 		return -EINVAL;
434 	return 0;
435 }
436 
437 /****************************************************************************/
438 
439 /* Enable or disable the RS485 support */
440 static void mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
441 {
442 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
443 	unsigned long flags;
444 	unsigned char mr1, mr2;
445 
446 	spin_lock_irqsave(&port->lock, flags);
447 	/* Get mode registers */
448 	mr1 = readb(port->membase + MCFUART_UMR);
449 	mr2 = readb(port->membase + MCFUART_UMR);
450 	if (rs485->flags & SER_RS485_ENABLED) {
451 		dev_dbg(port->dev, "Setting UART to RS485\n");
452 		/* Automatically negate RTS after TX completes */
453 		mr2 |= MCFUART_MR2_TXRTS;
454 	} else {
455 		dev_dbg(port->dev, "Setting UART to RS232\n");
456 		mr2 &= ~MCFUART_MR2_TXRTS;
457 	}
458 	writeb(mr1, port->membase + MCFUART_UMR);
459 	writeb(mr2, port->membase + MCFUART_UMR);
460 	pp->rs485 = *rs485;
461 	spin_unlock_irqrestore(&port->lock, flags);
462 }
463 
464 static int mcf_ioctl(struct uart_port *port, unsigned int cmd,
465 		unsigned long arg)
466 {
467 	switch (cmd) {
468 	case TIOCSRS485: {
469 		struct serial_rs485 rs485;
470 		if (copy_from_user(&rs485, (struct serial_rs485 *)arg,
471 				sizeof(struct serial_rs485)))
472 			return -EFAULT;
473 		mcf_config_rs485(port, &rs485);
474 		break;
475 	}
476 	case TIOCGRS485: {
477 		struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
478 		if (copy_to_user((struct serial_rs485 *)arg, &pp->rs485,
479 				sizeof(struct serial_rs485)))
480 			return -EFAULT;
481 		break;
482 	}
483 	default:
484 		return -ENOIOCTLCMD;
485 	}
486 	return 0;
487 }
488 
489 /****************************************************************************/
490 
491 /*
492  *	Define the basic serial functions we support.
493  */
494 static const struct uart_ops mcf_uart_ops = {
495 	.tx_empty	= mcf_tx_empty,
496 	.get_mctrl	= mcf_get_mctrl,
497 	.set_mctrl	= mcf_set_mctrl,
498 	.start_tx	= mcf_start_tx,
499 	.stop_tx	= mcf_stop_tx,
500 	.stop_rx	= mcf_stop_rx,
501 	.enable_ms	= mcf_enable_ms,
502 	.break_ctl	= mcf_break_ctl,
503 	.startup	= mcf_startup,
504 	.shutdown	= mcf_shutdown,
505 	.set_termios	= mcf_set_termios,
506 	.type		= mcf_type,
507 	.request_port	= mcf_request_port,
508 	.release_port	= mcf_release_port,
509 	.config_port	= mcf_config_port,
510 	.verify_port	= mcf_verify_port,
511 	.ioctl		= mcf_ioctl,
512 };
513 
514 static struct mcf_uart mcf_ports[4];
515 
516 #define	MCF_MAXPORTS	ARRAY_SIZE(mcf_ports)
517 
518 /****************************************************************************/
519 #if defined(CONFIG_SERIAL_MCF_CONSOLE)
520 /****************************************************************************/
521 
522 int __init early_mcf_setup(struct mcf_platform_uart *platp)
523 {
524 	struct uart_port *port;
525 	int i;
526 
527 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
528 		port = &mcf_ports[i].port;
529 
530 		port->line = i;
531 		port->type = PORT_MCF;
532 		port->mapbase = platp[i].mapbase;
533 		port->membase = (platp[i].membase) ? platp[i].membase :
534 			(unsigned char __iomem *) port->mapbase;
535 		port->iotype = SERIAL_IO_MEM;
536 		port->irq = platp[i].irq;
537 		port->uartclk = MCF_BUSCLK;
538 		port->flags = ASYNC_BOOT_AUTOCONF;
539 		port->ops = &mcf_uart_ops;
540 	}
541 
542 	return 0;
543 }
544 
545 /****************************************************************************/
546 
547 static void mcf_console_putc(struct console *co, const char c)
548 {
549 	struct uart_port *port = &(mcf_ports + co->index)->port;
550 	int i;
551 
552 	for (i = 0; (i < 0x10000); i++) {
553 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
554 			break;
555 	}
556 	writeb(c, port->membase + MCFUART_UTB);
557 	for (i = 0; (i < 0x10000); i++) {
558 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
559 			break;
560 	}
561 }
562 
563 /****************************************************************************/
564 
565 static void mcf_console_write(struct console *co, const char *s, unsigned int count)
566 {
567 	for (; (count); count--, s++) {
568 		mcf_console_putc(co, *s);
569 		if (*s == '\n')
570 			mcf_console_putc(co, '\r');
571 	}
572 }
573 
574 /****************************************************************************/
575 
576 static int __init mcf_console_setup(struct console *co, char *options)
577 {
578 	struct uart_port *port;
579 	int baud = CONFIG_SERIAL_MCF_BAUDRATE;
580 	int bits = 8;
581 	int parity = 'n';
582 	int flow = 'n';
583 
584 	if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
585 		co->index = 0;
586 	port = &mcf_ports[co->index].port;
587 	if (port->membase == 0)
588 		return -ENODEV;
589 
590 	if (options)
591 		uart_parse_options(options, &baud, &parity, &bits, &flow);
592 
593 	return uart_set_options(port, co, baud, parity, bits, flow);
594 }
595 
596 /****************************************************************************/
597 
598 static struct uart_driver mcf_driver;
599 
600 static struct console mcf_console = {
601 	.name		= "ttyS",
602 	.write		= mcf_console_write,
603 	.device		= uart_console_device,
604 	.setup		= mcf_console_setup,
605 	.flags		= CON_PRINTBUFFER,
606 	.index		= -1,
607 	.data		= &mcf_driver,
608 };
609 
610 static int __init mcf_console_init(void)
611 {
612 	register_console(&mcf_console);
613 	return 0;
614 }
615 
616 console_initcall(mcf_console_init);
617 
618 #define	MCF_CONSOLE	&mcf_console
619 
620 /****************************************************************************/
621 #else
622 /****************************************************************************/
623 
624 #define	MCF_CONSOLE	NULL
625 
626 /****************************************************************************/
627 #endif /* CONFIG_MCF_CONSOLE */
628 /****************************************************************************/
629 
630 /*
631  *	Define the mcf UART driver structure.
632  */
633 static struct uart_driver mcf_driver = {
634 	.owner		= THIS_MODULE,
635 	.driver_name	= "mcf",
636 	.dev_name	= "ttyS",
637 	.major		= TTY_MAJOR,
638 	.minor		= 64,
639 	.nr		= MCF_MAXPORTS,
640 	.cons		= MCF_CONSOLE,
641 };
642 
643 /****************************************************************************/
644 
645 static int mcf_probe(struct platform_device *pdev)
646 {
647 	struct mcf_platform_uart *platp = pdev->dev.platform_data;
648 	struct uart_port *port;
649 	int i;
650 
651 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
652 		port = &mcf_ports[i].port;
653 
654 		port->line = i;
655 		port->type = PORT_MCF;
656 		port->mapbase = platp[i].mapbase;
657 		port->membase = (platp[i].membase) ? platp[i].membase :
658 			(unsigned char __iomem *) platp[i].mapbase;
659 		port->iotype = SERIAL_IO_MEM;
660 		port->irq = platp[i].irq;
661 		port->uartclk = MCF_BUSCLK;
662 		port->ops = &mcf_uart_ops;
663 		port->flags = ASYNC_BOOT_AUTOCONF;
664 
665 		uart_add_one_port(&mcf_driver, port);
666 	}
667 
668 	return 0;
669 }
670 
671 /****************************************************************************/
672 
673 static int mcf_remove(struct platform_device *pdev)
674 {
675 	struct uart_port *port;
676 	int i;
677 
678 	for (i = 0; (i < MCF_MAXPORTS); i++) {
679 		port = &mcf_ports[i].port;
680 		if (port)
681 			uart_remove_one_port(&mcf_driver, port);
682 	}
683 
684 	return 0;
685 }
686 
687 /****************************************************************************/
688 
689 static struct platform_driver mcf_platform_driver = {
690 	.probe		= mcf_probe,
691 	.remove		= mcf_remove,
692 	.driver		= {
693 		.name	= "mcfuart",
694 		.owner	= THIS_MODULE,
695 	},
696 };
697 
698 /****************************************************************************/
699 
700 static int __init mcf_init(void)
701 {
702 	int rc;
703 
704 	printk("ColdFire internal UART serial driver\n");
705 
706 	rc = uart_register_driver(&mcf_driver);
707 	if (rc)
708 		return rc;
709 	rc = platform_driver_register(&mcf_platform_driver);
710 	if (rc)
711 		return rc;
712 	return 0;
713 }
714 
715 /****************************************************************************/
716 
717 static void __exit mcf_exit(void)
718 {
719 	platform_driver_unregister(&mcf_platform_driver);
720 	uart_unregister_driver(&mcf_driver);
721 }
722 
723 /****************************************************************************/
724 
725 module_init(mcf_init);
726 module_exit(mcf_exit);
727 
728 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
729 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
730 MODULE_LICENSE("GPL");
731 MODULE_ALIAS("platform:mcfuart");
732 
733 /****************************************************************************/
734