xref: /openbmc/linux/drivers/tty/serial/mcf.c (revision 6774def6)
1 /****************************************************************************/
2 
3 /*
4  *	mcf.c -- Freescale ColdFire UART driver
5  *
6  *	(C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  */
13 
14 /****************************************************************************/
15 
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/console.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/serial.h>
24 #include <linux/serial_core.h>
25 #include <linux/io.h>
26 #include <linux/uaccess.h>
27 #include <linux/platform_device.h>
28 #include <asm/coldfire.h>
29 #include <asm/mcfsim.h>
30 #include <asm/mcfuart.h>
31 #include <asm/nettel.h>
32 
33 /****************************************************************************/
34 
35 /*
36  *	Some boards implement the DTR/DCD lines using GPIO lines, most
37  *	don't. Dummy out the access macros for those that don't. Those
38  *	that do should define these macros somewhere in there board
39  *	specific inlude files.
40  */
41 #if !defined(mcf_getppdcd)
42 #define	mcf_getppdcd(p)		(1)
43 #endif
44 #if !defined(mcf_getppdtr)
45 #define	mcf_getppdtr(p)		(1)
46 #endif
47 #if !defined(mcf_setppdtr)
48 #define	mcf_setppdtr(p, v)	do { } while (0)
49 #endif
50 
51 /****************************************************************************/
52 
53 /*
54  *	Local per-uart structure.
55  */
56 struct mcf_uart {
57 	struct uart_port	port;
58 	unsigned int		sigs;		/* Local copy of line sigs */
59 	unsigned char		imr;		/* Local IMR mirror */
60 	struct serial_rs485	rs485;		/* RS485 settings */
61 };
62 
63 /****************************************************************************/
64 
65 static unsigned int mcf_tx_empty(struct uart_port *port)
66 {
67 	return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ?
68 		TIOCSER_TEMT : 0;
69 }
70 
71 /****************************************************************************/
72 
73 static unsigned int mcf_get_mctrl(struct uart_port *port)
74 {
75 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
76 	unsigned int sigs;
77 
78 	sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ?
79 		0 : TIOCM_CTS;
80 	sigs |= (pp->sigs & TIOCM_RTS);
81 	sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0);
82 	sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0);
83 
84 	return sigs;
85 }
86 
87 /****************************************************************************/
88 
89 static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs)
90 {
91 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
92 
93 	pp->sigs = sigs;
94 	mcf_setppdtr(port->line, (sigs & TIOCM_DTR));
95 	if (sigs & TIOCM_RTS)
96 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
97 	else
98 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0);
99 }
100 
101 /****************************************************************************/
102 
103 static void mcf_start_tx(struct uart_port *port)
104 {
105 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
106 
107 	if (pp->rs485.flags & SER_RS485_ENABLED) {
108 		/* Enable Transmitter */
109 		writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR);
110 		/* Manually assert RTS */
111 		writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1);
112 	}
113 	pp->imr |= MCFUART_UIR_TXREADY;
114 	writeb(pp->imr, port->membase + MCFUART_UIMR);
115 }
116 
117 /****************************************************************************/
118 
119 static void mcf_stop_tx(struct uart_port *port)
120 {
121 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
122 
123 	pp->imr &= ~MCFUART_UIR_TXREADY;
124 	writeb(pp->imr, port->membase + MCFUART_UIMR);
125 }
126 
127 /****************************************************************************/
128 
129 static void mcf_stop_rx(struct uart_port *port)
130 {
131 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
132 
133 	pp->imr &= ~MCFUART_UIR_RXREADY;
134 	writeb(pp->imr, port->membase + MCFUART_UIMR);
135 }
136 
137 /****************************************************************************/
138 
139 static void mcf_break_ctl(struct uart_port *port, int break_state)
140 {
141 	unsigned long flags;
142 
143 	spin_lock_irqsave(&port->lock, flags);
144 	if (break_state == -1)
145 		writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR);
146 	else
147 		writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR);
148 	spin_unlock_irqrestore(&port->lock, flags);
149 }
150 
151 /****************************************************************************/
152 
153 static int mcf_startup(struct uart_port *port)
154 {
155 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
156 	unsigned long flags;
157 
158 	spin_lock_irqsave(&port->lock, flags);
159 
160 	/* Reset UART, get it into known state... */
161 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
162 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
163 
164 	/* Enable the UART transmitter and receiver */
165 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
166 		port->membase + MCFUART_UCR);
167 
168 	/* Enable RX interrupts now */
169 	pp->imr = MCFUART_UIR_RXREADY;
170 	writeb(pp->imr, port->membase + MCFUART_UIMR);
171 
172 	spin_unlock_irqrestore(&port->lock, flags);
173 
174 	return 0;
175 }
176 
177 /****************************************************************************/
178 
179 static void mcf_shutdown(struct uart_port *port)
180 {
181 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
182 	unsigned long flags;
183 
184 	spin_lock_irqsave(&port->lock, flags);
185 
186 	/* Disable all interrupts now */
187 	pp->imr = 0;
188 	writeb(pp->imr, port->membase + MCFUART_UIMR);
189 
190 	/* Disable UART transmitter and receiver */
191 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
192 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
193 
194 	spin_unlock_irqrestore(&port->lock, flags);
195 }
196 
197 /****************************************************************************/
198 
199 static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
200 	struct ktermios *old)
201 {
202 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
203 	unsigned long flags;
204 	unsigned int baud, baudclk;
205 #if defined(CONFIG_M5272)
206 	unsigned int baudfr;
207 #endif
208 	unsigned char mr1, mr2;
209 
210 	baud = uart_get_baud_rate(port, termios, old, 0, 230400);
211 #if defined(CONFIG_M5272)
212 	baudclk = (MCF_BUSCLK / baud) / 32;
213 	baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
214 #else
215 	baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
216 #endif
217 
218 	mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
219 	mr2 = 0;
220 
221 	switch (termios->c_cflag & CSIZE) {
222 	case CS5: mr1 |= MCFUART_MR1_CS5; break;
223 	case CS6: mr1 |= MCFUART_MR1_CS6; break;
224 	case CS7: mr1 |= MCFUART_MR1_CS7; break;
225 	case CS8:
226 	default:  mr1 |= MCFUART_MR1_CS8; break;
227 	}
228 
229 	if (termios->c_cflag & PARENB) {
230 		if (termios->c_cflag & CMSPAR) {
231 			if (termios->c_cflag & PARODD)
232 				mr1 |= MCFUART_MR1_PARITYMARK;
233 			else
234 				mr1 |= MCFUART_MR1_PARITYSPACE;
235 		} else {
236 			if (termios->c_cflag & PARODD)
237 				mr1 |= MCFUART_MR1_PARITYODD;
238 			else
239 				mr1 |= MCFUART_MR1_PARITYEVEN;
240 		}
241 	} else {
242 		mr1 |= MCFUART_MR1_PARITYNONE;
243 	}
244 
245 	/*
246 	 * FIXME: port->read_status_mask and port->ignore_status_mask
247 	 * need to be initialized based on termios settings for
248 	 * INPCK, IGNBRK, IGNPAR, PARMRK, BRKINT
249 	 */
250 
251 	if (termios->c_cflag & CSTOPB)
252 		mr2 |= MCFUART_MR2_STOP2;
253 	else
254 		mr2 |= MCFUART_MR2_STOP1;
255 
256 	if (termios->c_cflag & CRTSCTS) {
257 		mr1 |= MCFUART_MR1_RXRTS;
258 		mr2 |= MCFUART_MR2_TXCTS;
259 	}
260 
261 	if (pp->rs485.flags & SER_RS485_ENABLED) {
262 		dev_dbg(port->dev, "Setting UART to RS485\n");
263 		mr2 |= MCFUART_MR2_TXRTS;
264 	}
265 
266 	spin_lock_irqsave(&port->lock, flags);
267 	uart_update_timeout(port, termios->c_cflag, baud);
268 	writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR);
269 	writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR);
270 	writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR);
271 	writeb(mr1, port->membase + MCFUART_UMR);
272 	writeb(mr2, port->membase + MCFUART_UMR);
273 	writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
274 	writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
275 #if defined(CONFIG_M5272)
276 	writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
277 #endif
278 	writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
279 		port->membase + MCFUART_UCSR);
280 	writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,
281 		port->membase + MCFUART_UCR);
282 	spin_unlock_irqrestore(&port->lock, flags);
283 }
284 
285 /****************************************************************************/
286 
287 static void mcf_rx_chars(struct mcf_uart *pp)
288 {
289 	struct uart_port *port = &pp->port;
290 	unsigned char status, ch, flag;
291 
292 	while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) {
293 		ch = readb(port->membase + MCFUART_URB);
294 		flag = TTY_NORMAL;
295 		port->icount.rx++;
296 
297 		if (status & MCFUART_USR_RXERR) {
298 			writeb(MCFUART_UCR_CMDRESETERR,
299 				port->membase + MCFUART_UCR);
300 
301 			if (status & MCFUART_USR_RXBREAK) {
302 				port->icount.brk++;
303 				if (uart_handle_break(port))
304 					continue;
305 			} else if (status & MCFUART_USR_RXPARITY) {
306 				port->icount.parity++;
307 			} else if (status & MCFUART_USR_RXOVERRUN) {
308 				port->icount.overrun++;
309 			} else if (status & MCFUART_USR_RXFRAMING) {
310 				port->icount.frame++;
311 			}
312 
313 			status &= port->read_status_mask;
314 
315 			if (status & MCFUART_USR_RXBREAK)
316 				flag = TTY_BREAK;
317 			else if (status & MCFUART_USR_RXPARITY)
318 				flag = TTY_PARITY;
319 			else if (status & MCFUART_USR_RXFRAMING)
320 				flag = TTY_FRAME;
321 		}
322 
323 		if (uart_handle_sysrq_char(port, ch))
324 			continue;
325 		uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag);
326 	}
327 
328 	spin_unlock(&port->lock);
329 	tty_flip_buffer_push(&port->state->port);
330 	spin_lock(&port->lock);
331 }
332 
333 /****************************************************************************/
334 
335 static void mcf_tx_chars(struct mcf_uart *pp)
336 {
337 	struct uart_port *port = &pp->port;
338 	struct circ_buf *xmit = &port->state->xmit;
339 
340 	if (port->x_char) {
341 		/* Send special char - probably flow control */
342 		writeb(port->x_char, port->membase + MCFUART_UTB);
343 		port->x_char = 0;
344 		port->icount.tx++;
345 		return;
346 	}
347 
348 	while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) {
349 		if (xmit->head == xmit->tail)
350 			break;
351 		writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB);
352 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
353 		port->icount.tx++;
354 	}
355 
356 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
357 		uart_write_wakeup(port);
358 
359 	if (xmit->head == xmit->tail) {
360 		pp->imr &= ~MCFUART_UIR_TXREADY;
361 		writeb(pp->imr, port->membase + MCFUART_UIMR);
362 		/* Disable TX to negate RTS automatically */
363 		if (pp->rs485.flags & SER_RS485_ENABLED)
364 			writeb(MCFUART_UCR_TXDISABLE,
365 				port->membase + MCFUART_UCR);
366 	}
367 }
368 
369 /****************************************************************************/
370 
371 static irqreturn_t mcf_interrupt(int irq, void *data)
372 {
373 	struct uart_port *port = data;
374 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
375 	unsigned int isr;
376 	irqreturn_t ret = IRQ_NONE;
377 
378 	isr = readb(port->membase + MCFUART_UISR) & pp->imr;
379 
380 	spin_lock(&port->lock);
381 	if (isr & MCFUART_UIR_RXREADY) {
382 		mcf_rx_chars(pp);
383 		ret = IRQ_HANDLED;
384 	}
385 	if (isr & MCFUART_UIR_TXREADY) {
386 		mcf_tx_chars(pp);
387 		ret = IRQ_HANDLED;
388 	}
389 	spin_unlock(&port->lock);
390 
391 	return ret;
392 }
393 
394 /****************************************************************************/
395 
396 static void mcf_config_port(struct uart_port *port, int flags)
397 {
398 	port->type = PORT_MCF;
399 	port->fifosize = MCFUART_TXFIFOSIZE;
400 
401 	/* Clear mask, so no surprise interrupts. */
402 	writeb(0, port->membase + MCFUART_UIMR);
403 
404 	if (request_irq(port->irq, mcf_interrupt, 0, "UART", port))
405 		printk(KERN_ERR "MCF: unable to attach ColdFire UART %d "
406 			"interrupt vector=%d\n", port->line, port->irq);
407 }
408 
409 /****************************************************************************/
410 
411 static const char *mcf_type(struct uart_port *port)
412 {
413 	return (port->type == PORT_MCF) ? "ColdFire UART" : NULL;
414 }
415 
416 /****************************************************************************/
417 
418 static int mcf_request_port(struct uart_port *port)
419 {
420 	/* UARTs always present */
421 	return 0;
422 }
423 
424 /****************************************************************************/
425 
426 static void mcf_release_port(struct uart_port *port)
427 {
428 	/* Nothing to release... */
429 }
430 
431 /****************************************************************************/
432 
433 static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser)
434 {
435 	if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF))
436 		return -EINVAL;
437 	return 0;
438 }
439 
440 /****************************************************************************/
441 
442 /* Enable or disable the RS485 support */
443 static void mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485)
444 {
445 	struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
446 	unsigned long flags;
447 	unsigned char mr1, mr2;
448 
449 	spin_lock_irqsave(&port->lock, flags);
450 	/* Get mode registers */
451 	mr1 = readb(port->membase + MCFUART_UMR);
452 	mr2 = readb(port->membase + MCFUART_UMR);
453 	if (rs485->flags & SER_RS485_ENABLED) {
454 		dev_dbg(port->dev, "Setting UART to RS485\n");
455 		/* Automatically negate RTS after TX completes */
456 		mr2 |= MCFUART_MR2_TXRTS;
457 	} else {
458 		dev_dbg(port->dev, "Setting UART to RS232\n");
459 		mr2 &= ~MCFUART_MR2_TXRTS;
460 	}
461 	writeb(mr1, port->membase + MCFUART_UMR);
462 	writeb(mr2, port->membase + MCFUART_UMR);
463 	pp->rs485 = *rs485;
464 	spin_unlock_irqrestore(&port->lock, flags);
465 }
466 
467 static int mcf_ioctl(struct uart_port *port, unsigned int cmd,
468 		unsigned long arg)
469 {
470 	switch (cmd) {
471 	case TIOCSRS485: {
472 		struct serial_rs485 rs485;
473 		if (copy_from_user(&rs485, (struct serial_rs485 *)arg,
474 				sizeof(struct serial_rs485)))
475 			return -EFAULT;
476 		mcf_config_rs485(port, &rs485);
477 		break;
478 	}
479 	case TIOCGRS485: {
480 		struct mcf_uart *pp = container_of(port, struct mcf_uart, port);
481 		if (copy_to_user((struct serial_rs485 *)arg, &pp->rs485,
482 				sizeof(struct serial_rs485)))
483 			return -EFAULT;
484 		break;
485 	}
486 	default:
487 		return -ENOIOCTLCMD;
488 	}
489 	return 0;
490 }
491 
492 /****************************************************************************/
493 
494 /*
495  *	Define the basic serial functions we support.
496  */
497 static const struct uart_ops mcf_uart_ops = {
498 	.tx_empty	= mcf_tx_empty,
499 	.get_mctrl	= mcf_get_mctrl,
500 	.set_mctrl	= mcf_set_mctrl,
501 	.start_tx	= mcf_start_tx,
502 	.stop_tx	= mcf_stop_tx,
503 	.stop_rx	= mcf_stop_rx,
504 	.break_ctl	= mcf_break_ctl,
505 	.startup	= mcf_startup,
506 	.shutdown	= mcf_shutdown,
507 	.set_termios	= mcf_set_termios,
508 	.type		= mcf_type,
509 	.request_port	= mcf_request_port,
510 	.release_port	= mcf_release_port,
511 	.config_port	= mcf_config_port,
512 	.verify_port	= mcf_verify_port,
513 	.ioctl		= mcf_ioctl,
514 };
515 
516 static struct mcf_uart mcf_ports[4];
517 
518 #define	MCF_MAXPORTS	ARRAY_SIZE(mcf_ports)
519 
520 /****************************************************************************/
521 #if defined(CONFIG_SERIAL_MCF_CONSOLE)
522 /****************************************************************************/
523 
524 int __init early_mcf_setup(struct mcf_platform_uart *platp)
525 {
526 	struct uart_port *port;
527 	int i;
528 
529 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
530 		port = &mcf_ports[i].port;
531 
532 		port->line = i;
533 		port->type = PORT_MCF;
534 		port->mapbase = platp[i].mapbase;
535 		port->membase = (platp[i].membase) ? platp[i].membase :
536 			(unsigned char __iomem *) port->mapbase;
537 		port->iotype = SERIAL_IO_MEM;
538 		port->irq = platp[i].irq;
539 		port->uartclk = MCF_BUSCLK;
540 		port->flags = UPF_BOOT_AUTOCONF;
541 		port->ops = &mcf_uart_ops;
542 	}
543 
544 	return 0;
545 }
546 
547 /****************************************************************************/
548 
549 static void mcf_console_putc(struct console *co, const char c)
550 {
551 	struct uart_port *port = &(mcf_ports + co->index)->port;
552 	int i;
553 
554 	for (i = 0; (i < 0x10000); i++) {
555 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
556 			break;
557 	}
558 	writeb(c, port->membase + MCFUART_UTB);
559 	for (i = 0; (i < 0x10000); i++) {
560 		if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY)
561 			break;
562 	}
563 }
564 
565 /****************************************************************************/
566 
567 static void mcf_console_write(struct console *co, const char *s, unsigned int count)
568 {
569 	for (; (count); count--, s++) {
570 		mcf_console_putc(co, *s);
571 		if (*s == '\n')
572 			mcf_console_putc(co, '\r');
573 	}
574 }
575 
576 /****************************************************************************/
577 
578 static int __init mcf_console_setup(struct console *co, char *options)
579 {
580 	struct uart_port *port;
581 	int baud = CONFIG_SERIAL_MCF_BAUDRATE;
582 	int bits = 8;
583 	int parity = 'n';
584 	int flow = 'n';
585 
586 	if ((co->index < 0) || (co->index >= MCF_MAXPORTS))
587 		co->index = 0;
588 	port = &mcf_ports[co->index].port;
589 	if (port->membase == 0)
590 		return -ENODEV;
591 
592 	if (options)
593 		uart_parse_options(options, &baud, &parity, &bits, &flow);
594 
595 	return uart_set_options(port, co, baud, parity, bits, flow);
596 }
597 
598 /****************************************************************************/
599 
600 static struct uart_driver mcf_driver;
601 
602 static struct console mcf_console = {
603 	.name		= "ttyS",
604 	.write		= mcf_console_write,
605 	.device		= uart_console_device,
606 	.setup		= mcf_console_setup,
607 	.flags		= CON_PRINTBUFFER,
608 	.index		= -1,
609 	.data		= &mcf_driver,
610 };
611 
612 static int __init mcf_console_init(void)
613 {
614 	register_console(&mcf_console);
615 	return 0;
616 }
617 
618 console_initcall(mcf_console_init);
619 
620 #define	MCF_CONSOLE	&mcf_console
621 
622 /****************************************************************************/
623 #else
624 /****************************************************************************/
625 
626 #define	MCF_CONSOLE	NULL
627 
628 /****************************************************************************/
629 #endif /* CONFIG_MCF_CONSOLE */
630 /****************************************************************************/
631 
632 /*
633  *	Define the mcf UART driver structure.
634  */
635 static struct uart_driver mcf_driver = {
636 	.owner		= THIS_MODULE,
637 	.driver_name	= "mcf",
638 	.dev_name	= "ttyS",
639 	.major		= TTY_MAJOR,
640 	.minor		= 64,
641 	.nr		= MCF_MAXPORTS,
642 	.cons		= MCF_CONSOLE,
643 };
644 
645 /****************************************************************************/
646 
647 static int mcf_probe(struct platform_device *pdev)
648 {
649 	struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev);
650 	struct uart_port *port;
651 	int i;
652 
653 	for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) {
654 		port = &mcf_ports[i].port;
655 
656 		port->line = i;
657 		port->type = PORT_MCF;
658 		port->mapbase = platp[i].mapbase;
659 		port->membase = (platp[i].membase) ? platp[i].membase :
660 			(unsigned char __iomem *) platp[i].mapbase;
661 		port->iotype = SERIAL_IO_MEM;
662 		port->irq = platp[i].irq;
663 		port->uartclk = MCF_BUSCLK;
664 		port->ops = &mcf_uart_ops;
665 		port->flags = UPF_BOOT_AUTOCONF;
666 
667 		uart_add_one_port(&mcf_driver, port);
668 	}
669 
670 	return 0;
671 }
672 
673 /****************************************************************************/
674 
675 static int mcf_remove(struct platform_device *pdev)
676 {
677 	struct uart_port *port;
678 	int i;
679 
680 	for (i = 0; (i < MCF_MAXPORTS); i++) {
681 		port = &mcf_ports[i].port;
682 		if (port)
683 			uart_remove_one_port(&mcf_driver, port);
684 	}
685 
686 	return 0;
687 }
688 
689 /****************************************************************************/
690 
691 static struct platform_driver mcf_platform_driver = {
692 	.probe		= mcf_probe,
693 	.remove		= mcf_remove,
694 	.driver		= {
695 		.name	= "mcfuart",
696 		.owner	= THIS_MODULE,
697 	},
698 };
699 
700 /****************************************************************************/
701 
702 static int __init mcf_init(void)
703 {
704 	int rc;
705 
706 	printk("ColdFire internal UART serial driver\n");
707 
708 	rc = uart_register_driver(&mcf_driver);
709 	if (rc)
710 		return rc;
711 	rc = platform_driver_register(&mcf_platform_driver);
712 	if (rc) {
713 		uart_unregister_driver(&mcf_driver);
714 		return rc;
715 	}
716 	return 0;
717 }
718 
719 /****************************************************************************/
720 
721 static void __exit mcf_exit(void)
722 {
723 	platform_driver_unregister(&mcf_platform_driver);
724 	uart_unregister_driver(&mcf_driver);
725 }
726 
727 /****************************************************************************/
728 
729 module_init(mcf_init);
730 module_exit(mcf_exit);
731 
732 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>");
733 MODULE_DESCRIPTION("Freescale ColdFire UART driver");
734 MODULE_LICENSE("GPL");
735 MODULE_ALIAS("platform:mcfuart");
736 
737 /****************************************************************************/
738