1 /****************************************************************************/ 2 3 /* 4 * mcf.c -- Freescale ColdFire UART driver 5 * 6 * (C) Copyright 2003-2007, Greg Ungerer <gerg@snapgear.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 /****************************************************************************/ 15 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/console.h> 21 #include <linux/tty.h> 22 #include <linux/tty_flip.h> 23 #include <linux/serial.h> 24 #include <linux/serial_core.h> 25 #include <linux/io.h> 26 #include <linux/uaccess.h> 27 #include <linux/platform_device.h> 28 #include <asm/coldfire.h> 29 #include <asm/mcfsim.h> 30 #include <asm/mcfuart.h> 31 #include <asm/nettel.h> 32 33 /****************************************************************************/ 34 35 /* 36 * Some boards implement the DTR/DCD lines using GPIO lines, most 37 * don't. Dummy out the access macros for those that don't. Those 38 * that do should define these macros somewhere in there board 39 * specific inlude files. 40 */ 41 #if !defined(mcf_getppdcd) 42 #define mcf_getppdcd(p) (1) 43 #endif 44 #if !defined(mcf_getppdtr) 45 #define mcf_getppdtr(p) (1) 46 #endif 47 #if !defined(mcf_setppdtr) 48 #define mcf_setppdtr(p, v) do { } while (0) 49 #endif 50 51 /****************************************************************************/ 52 53 /* 54 * Local per-uart structure. 55 */ 56 struct mcf_uart { 57 struct uart_port port; 58 unsigned int sigs; /* Local copy of line sigs */ 59 unsigned char imr; /* Local IMR mirror */ 60 struct serial_rs485 rs485; /* RS485 settings */ 61 }; 62 63 /****************************************************************************/ 64 65 static unsigned int mcf_tx_empty(struct uart_port *port) 66 { 67 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? 68 TIOCSER_TEMT : 0; 69 } 70 71 /****************************************************************************/ 72 73 static unsigned int mcf_get_mctrl(struct uart_port *port) 74 { 75 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 76 unsigned int sigs; 77 78 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? 79 0 : TIOCM_CTS; 80 sigs |= (pp->sigs & TIOCM_RTS); 81 sigs |= (mcf_getppdcd(port->line) ? TIOCM_CD : 0); 82 sigs |= (mcf_getppdtr(port->line) ? TIOCM_DTR : 0); 83 84 return sigs; 85 } 86 87 /****************************************************************************/ 88 89 static void mcf_set_mctrl(struct uart_port *port, unsigned int sigs) 90 { 91 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 92 93 pp->sigs = sigs; 94 mcf_setppdtr(port->line, (sigs & TIOCM_DTR)); 95 if (sigs & TIOCM_RTS) 96 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); 97 else 98 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); 99 } 100 101 /****************************************************************************/ 102 103 static void mcf_start_tx(struct uart_port *port) 104 { 105 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 106 107 if (pp->rs485.flags & SER_RS485_ENABLED) { 108 /* Enable Transmitter */ 109 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); 110 /* Manually assert RTS */ 111 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); 112 } 113 pp->imr |= MCFUART_UIR_TXREADY; 114 writeb(pp->imr, port->membase + MCFUART_UIMR); 115 } 116 117 /****************************************************************************/ 118 119 static void mcf_stop_tx(struct uart_port *port) 120 { 121 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 122 123 pp->imr &= ~MCFUART_UIR_TXREADY; 124 writeb(pp->imr, port->membase + MCFUART_UIMR); 125 } 126 127 /****************************************************************************/ 128 129 static void mcf_stop_rx(struct uart_port *port) 130 { 131 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 132 133 pp->imr &= ~MCFUART_UIR_RXREADY; 134 writeb(pp->imr, port->membase + MCFUART_UIMR); 135 } 136 137 /****************************************************************************/ 138 139 static void mcf_break_ctl(struct uart_port *port, int break_state) 140 { 141 unsigned long flags; 142 143 spin_lock_irqsave(&port->lock, flags); 144 if (break_state == -1) 145 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); 146 else 147 writeb(MCFUART_UCR_CMDBREAKSTOP, port->membase + MCFUART_UCR); 148 spin_unlock_irqrestore(&port->lock, flags); 149 } 150 151 /****************************************************************************/ 152 153 static void mcf_enable_ms(struct uart_port *port) 154 { 155 } 156 157 /****************************************************************************/ 158 159 static int mcf_startup(struct uart_port *port) 160 { 161 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 162 unsigned long flags; 163 164 spin_lock_irqsave(&port->lock, flags); 165 166 /* Reset UART, get it into known state... */ 167 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); 168 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); 169 170 /* Enable the UART transmitter and receiver */ 171 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE, 172 port->membase + MCFUART_UCR); 173 174 /* Enable RX interrupts now */ 175 pp->imr = MCFUART_UIR_RXREADY; 176 writeb(pp->imr, port->membase + MCFUART_UIMR); 177 178 spin_unlock_irqrestore(&port->lock, flags); 179 180 return 0; 181 } 182 183 /****************************************************************************/ 184 185 static void mcf_shutdown(struct uart_port *port) 186 { 187 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 188 unsigned long flags; 189 190 spin_lock_irqsave(&port->lock, flags); 191 192 /* Disable all interrupts now */ 193 pp->imr = 0; 194 writeb(pp->imr, port->membase + MCFUART_UIMR); 195 196 /* Disable UART transmitter and receiver */ 197 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); 198 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); 199 200 spin_unlock_irqrestore(&port->lock, flags); 201 } 202 203 /****************************************************************************/ 204 205 static void mcf_set_termios(struct uart_port *port, struct ktermios *termios, 206 struct ktermios *old) 207 { 208 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 209 unsigned long flags; 210 unsigned int baud, baudclk; 211 #if defined(CONFIG_M5272) 212 unsigned int baudfr; 213 #endif 214 unsigned char mr1, mr2; 215 216 baud = uart_get_baud_rate(port, termios, old, 0, 230400); 217 #if defined(CONFIG_M5272) 218 baudclk = (MCF_BUSCLK / baud) / 32; 219 baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16; 220 #else 221 baudclk = ((MCF_BUSCLK / baud) + 16) / 32; 222 #endif 223 224 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR; 225 mr2 = 0; 226 227 switch (termios->c_cflag & CSIZE) { 228 case CS5: mr1 |= MCFUART_MR1_CS5; break; 229 case CS6: mr1 |= MCFUART_MR1_CS6; break; 230 case CS7: mr1 |= MCFUART_MR1_CS7; break; 231 case CS8: 232 default: mr1 |= MCFUART_MR1_CS8; break; 233 } 234 235 if (termios->c_cflag & PARENB) { 236 if (termios->c_cflag & CMSPAR) { 237 if (termios->c_cflag & PARODD) 238 mr1 |= MCFUART_MR1_PARITYMARK; 239 else 240 mr1 |= MCFUART_MR1_PARITYSPACE; 241 } else { 242 if (termios->c_cflag & PARODD) 243 mr1 |= MCFUART_MR1_PARITYODD; 244 else 245 mr1 |= MCFUART_MR1_PARITYEVEN; 246 } 247 } else { 248 mr1 |= MCFUART_MR1_PARITYNONE; 249 } 250 251 if (termios->c_cflag & CSTOPB) 252 mr2 |= MCFUART_MR2_STOP2; 253 else 254 mr2 |= MCFUART_MR2_STOP1; 255 256 if (termios->c_cflag & CRTSCTS) { 257 mr1 |= MCFUART_MR1_RXRTS; 258 mr2 |= MCFUART_MR2_TXCTS; 259 } 260 261 if (pp->rs485.flags & SER_RS485_ENABLED) { 262 dev_dbg(port->dev, "Setting UART to RS485\n"); 263 mr2 |= MCFUART_MR2_TXRTS; 264 } 265 266 spin_lock_irqsave(&port->lock, flags); 267 uart_update_timeout(port, termios->c_cflag, baud); 268 writeb(MCFUART_UCR_CMDRESETRX, port->membase + MCFUART_UCR); 269 writeb(MCFUART_UCR_CMDRESETTX, port->membase + MCFUART_UCR); 270 writeb(MCFUART_UCR_CMDRESETMRPTR, port->membase + MCFUART_UCR); 271 writeb(mr1, port->membase + MCFUART_UMR); 272 writeb(mr2, port->membase + MCFUART_UMR); 273 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1); 274 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2); 275 #if defined(CONFIG_M5272) 276 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD); 277 #endif 278 writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER, 279 port->membase + MCFUART_UCSR); 280 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE, 281 port->membase + MCFUART_UCR); 282 spin_unlock_irqrestore(&port->lock, flags); 283 } 284 285 /****************************************************************************/ 286 287 static void mcf_rx_chars(struct mcf_uart *pp) 288 { 289 struct uart_port *port = &pp->port; 290 unsigned char status, ch, flag; 291 292 while ((status = readb(port->membase + MCFUART_USR)) & MCFUART_USR_RXREADY) { 293 ch = readb(port->membase + MCFUART_URB); 294 flag = TTY_NORMAL; 295 port->icount.rx++; 296 297 if (status & MCFUART_USR_RXERR) { 298 writeb(MCFUART_UCR_CMDRESETERR, 299 port->membase + MCFUART_UCR); 300 301 if (status & MCFUART_USR_RXBREAK) { 302 port->icount.brk++; 303 if (uart_handle_break(port)) 304 continue; 305 } else if (status & MCFUART_USR_RXPARITY) { 306 port->icount.parity++; 307 } else if (status & MCFUART_USR_RXOVERRUN) { 308 port->icount.overrun++; 309 } else if (status & MCFUART_USR_RXFRAMING) { 310 port->icount.frame++; 311 } 312 313 status &= port->read_status_mask; 314 315 if (status & MCFUART_USR_RXBREAK) 316 flag = TTY_BREAK; 317 else if (status & MCFUART_USR_RXPARITY) 318 flag = TTY_PARITY; 319 else if (status & MCFUART_USR_RXFRAMING) 320 flag = TTY_FRAME; 321 } 322 323 if (uart_handle_sysrq_char(port, ch)) 324 continue; 325 uart_insert_char(port, status, MCFUART_USR_RXOVERRUN, ch, flag); 326 } 327 328 spin_unlock(&port->lock); 329 tty_flip_buffer_push(&port->state->port); 330 spin_lock(&port->lock); 331 } 332 333 /****************************************************************************/ 334 335 static void mcf_tx_chars(struct mcf_uart *pp) 336 { 337 struct uart_port *port = &pp->port; 338 struct circ_buf *xmit = &port->state->xmit; 339 340 if (port->x_char) { 341 /* Send special char - probably flow control */ 342 writeb(port->x_char, port->membase + MCFUART_UTB); 343 port->x_char = 0; 344 port->icount.tx++; 345 return; 346 } 347 348 while (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) { 349 if (xmit->head == xmit->tail) 350 break; 351 writeb(xmit->buf[xmit->tail], port->membase + MCFUART_UTB); 352 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1); 353 port->icount.tx++; 354 } 355 356 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 357 uart_write_wakeup(port); 358 359 if (xmit->head == xmit->tail) { 360 pp->imr &= ~MCFUART_UIR_TXREADY; 361 writeb(pp->imr, port->membase + MCFUART_UIMR); 362 /* Disable TX to negate RTS automatically */ 363 if (pp->rs485.flags & SER_RS485_ENABLED) 364 writeb(MCFUART_UCR_TXDISABLE, 365 port->membase + MCFUART_UCR); 366 } 367 } 368 369 /****************************************************************************/ 370 371 static irqreturn_t mcf_interrupt(int irq, void *data) 372 { 373 struct uart_port *port = data; 374 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 375 unsigned int isr; 376 irqreturn_t ret = IRQ_NONE; 377 378 isr = readb(port->membase + MCFUART_UISR) & pp->imr; 379 380 spin_lock(&port->lock); 381 if (isr & MCFUART_UIR_RXREADY) { 382 mcf_rx_chars(pp); 383 ret = IRQ_HANDLED; 384 } 385 if (isr & MCFUART_UIR_TXREADY) { 386 mcf_tx_chars(pp); 387 ret = IRQ_HANDLED; 388 } 389 spin_unlock(&port->lock); 390 391 return ret; 392 } 393 394 /****************************************************************************/ 395 396 static void mcf_config_port(struct uart_port *port, int flags) 397 { 398 port->type = PORT_MCF; 399 port->fifosize = MCFUART_TXFIFOSIZE; 400 401 /* Clear mask, so no surprise interrupts. */ 402 writeb(0, port->membase + MCFUART_UIMR); 403 404 if (request_irq(port->irq, mcf_interrupt, 0, "UART", port)) 405 printk(KERN_ERR "MCF: unable to attach ColdFire UART %d " 406 "interrupt vector=%d\n", port->line, port->irq); 407 } 408 409 /****************************************************************************/ 410 411 static const char *mcf_type(struct uart_port *port) 412 { 413 return (port->type == PORT_MCF) ? "ColdFire UART" : NULL; 414 } 415 416 /****************************************************************************/ 417 418 static int mcf_request_port(struct uart_port *port) 419 { 420 /* UARTs always present */ 421 return 0; 422 } 423 424 /****************************************************************************/ 425 426 static void mcf_release_port(struct uart_port *port) 427 { 428 /* Nothing to release... */ 429 } 430 431 /****************************************************************************/ 432 433 static int mcf_verify_port(struct uart_port *port, struct serial_struct *ser) 434 { 435 if ((ser->type != PORT_UNKNOWN) && (ser->type != PORT_MCF)) 436 return -EINVAL; 437 return 0; 438 } 439 440 /****************************************************************************/ 441 442 /* Enable or disable the RS485 support */ 443 static void mcf_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) 444 { 445 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 446 unsigned long flags; 447 unsigned char mr1, mr2; 448 449 spin_lock_irqsave(&port->lock, flags); 450 /* Get mode registers */ 451 mr1 = readb(port->membase + MCFUART_UMR); 452 mr2 = readb(port->membase + MCFUART_UMR); 453 if (rs485->flags & SER_RS485_ENABLED) { 454 dev_dbg(port->dev, "Setting UART to RS485\n"); 455 /* Automatically negate RTS after TX completes */ 456 mr2 |= MCFUART_MR2_TXRTS; 457 } else { 458 dev_dbg(port->dev, "Setting UART to RS232\n"); 459 mr2 &= ~MCFUART_MR2_TXRTS; 460 } 461 writeb(mr1, port->membase + MCFUART_UMR); 462 writeb(mr2, port->membase + MCFUART_UMR); 463 pp->rs485 = *rs485; 464 spin_unlock_irqrestore(&port->lock, flags); 465 } 466 467 static int mcf_ioctl(struct uart_port *port, unsigned int cmd, 468 unsigned long arg) 469 { 470 switch (cmd) { 471 case TIOCSRS485: { 472 struct serial_rs485 rs485; 473 if (copy_from_user(&rs485, (struct serial_rs485 *)arg, 474 sizeof(struct serial_rs485))) 475 return -EFAULT; 476 mcf_config_rs485(port, &rs485); 477 break; 478 } 479 case TIOCGRS485: { 480 struct mcf_uart *pp = container_of(port, struct mcf_uart, port); 481 if (copy_to_user((struct serial_rs485 *)arg, &pp->rs485, 482 sizeof(struct serial_rs485))) 483 return -EFAULT; 484 break; 485 } 486 default: 487 return -ENOIOCTLCMD; 488 } 489 return 0; 490 } 491 492 /****************************************************************************/ 493 494 /* 495 * Define the basic serial functions we support. 496 */ 497 static const struct uart_ops mcf_uart_ops = { 498 .tx_empty = mcf_tx_empty, 499 .get_mctrl = mcf_get_mctrl, 500 .set_mctrl = mcf_set_mctrl, 501 .start_tx = mcf_start_tx, 502 .stop_tx = mcf_stop_tx, 503 .stop_rx = mcf_stop_rx, 504 .enable_ms = mcf_enable_ms, 505 .break_ctl = mcf_break_ctl, 506 .startup = mcf_startup, 507 .shutdown = mcf_shutdown, 508 .set_termios = mcf_set_termios, 509 .type = mcf_type, 510 .request_port = mcf_request_port, 511 .release_port = mcf_release_port, 512 .config_port = mcf_config_port, 513 .verify_port = mcf_verify_port, 514 .ioctl = mcf_ioctl, 515 }; 516 517 static struct mcf_uart mcf_ports[4]; 518 519 #define MCF_MAXPORTS ARRAY_SIZE(mcf_ports) 520 521 /****************************************************************************/ 522 #if defined(CONFIG_SERIAL_MCF_CONSOLE) 523 /****************************************************************************/ 524 525 int __init early_mcf_setup(struct mcf_platform_uart *platp) 526 { 527 struct uart_port *port; 528 int i; 529 530 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) { 531 port = &mcf_ports[i].port; 532 533 port->line = i; 534 port->type = PORT_MCF; 535 port->mapbase = platp[i].mapbase; 536 port->membase = (platp[i].membase) ? platp[i].membase : 537 (unsigned char __iomem *) port->mapbase; 538 port->iotype = SERIAL_IO_MEM; 539 port->irq = platp[i].irq; 540 port->uartclk = MCF_BUSCLK; 541 port->flags = ASYNC_BOOT_AUTOCONF; 542 port->ops = &mcf_uart_ops; 543 } 544 545 return 0; 546 } 547 548 /****************************************************************************/ 549 550 static void mcf_console_putc(struct console *co, const char c) 551 { 552 struct uart_port *port = &(mcf_ports + co->index)->port; 553 int i; 554 555 for (i = 0; (i < 0x10000); i++) { 556 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) 557 break; 558 } 559 writeb(c, port->membase + MCFUART_UTB); 560 for (i = 0; (i < 0x10000); i++) { 561 if (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXREADY) 562 break; 563 } 564 } 565 566 /****************************************************************************/ 567 568 static void mcf_console_write(struct console *co, const char *s, unsigned int count) 569 { 570 for (; (count); count--, s++) { 571 mcf_console_putc(co, *s); 572 if (*s == '\n') 573 mcf_console_putc(co, '\r'); 574 } 575 } 576 577 /****************************************************************************/ 578 579 static int __init mcf_console_setup(struct console *co, char *options) 580 { 581 struct uart_port *port; 582 int baud = CONFIG_SERIAL_MCF_BAUDRATE; 583 int bits = 8; 584 int parity = 'n'; 585 int flow = 'n'; 586 587 if ((co->index < 0) || (co->index >= MCF_MAXPORTS)) 588 co->index = 0; 589 port = &mcf_ports[co->index].port; 590 if (port->membase == 0) 591 return -ENODEV; 592 593 if (options) 594 uart_parse_options(options, &baud, &parity, &bits, &flow); 595 596 return uart_set_options(port, co, baud, parity, bits, flow); 597 } 598 599 /****************************************************************************/ 600 601 static struct uart_driver mcf_driver; 602 603 static struct console mcf_console = { 604 .name = "ttyS", 605 .write = mcf_console_write, 606 .device = uart_console_device, 607 .setup = mcf_console_setup, 608 .flags = CON_PRINTBUFFER, 609 .index = -1, 610 .data = &mcf_driver, 611 }; 612 613 static int __init mcf_console_init(void) 614 { 615 register_console(&mcf_console); 616 return 0; 617 } 618 619 console_initcall(mcf_console_init); 620 621 #define MCF_CONSOLE &mcf_console 622 623 /****************************************************************************/ 624 #else 625 /****************************************************************************/ 626 627 #define MCF_CONSOLE NULL 628 629 /****************************************************************************/ 630 #endif /* CONFIG_MCF_CONSOLE */ 631 /****************************************************************************/ 632 633 /* 634 * Define the mcf UART driver structure. 635 */ 636 static struct uart_driver mcf_driver = { 637 .owner = THIS_MODULE, 638 .driver_name = "mcf", 639 .dev_name = "ttyS", 640 .major = TTY_MAJOR, 641 .minor = 64, 642 .nr = MCF_MAXPORTS, 643 .cons = MCF_CONSOLE, 644 }; 645 646 /****************************************************************************/ 647 648 static int mcf_probe(struct platform_device *pdev) 649 { 650 struct mcf_platform_uart *platp = dev_get_platdata(&pdev->dev); 651 struct uart_port *port; 652 int i; 653 654 for (i = 0; ((i < MCF_MAXPORTS) && (platp[i].mapbase)); i++) { 655 port = &mcf_ports[i].port; 656 657 port->line = i; 658 port->type = PORT_MCF; 659 port->mapbase = platp[i].mapbase; 660 port->membase = (platp[i].membase) ? platp[i].membase : 661 (unsigned char __iomem *) platp[i].mapbase; 662 port->iotype = SERIAL_IO_MEM; 663 port->irq = platp[i].irq; 664 port->uartclk = MCF_BUSCLK; 665 port->ops = &mcf_uart_ops; 666 port->flags = ASYNC_BOOT_AUTOCONF; 667 668 uart_add_one_port(&mcf_driver, port); 669 } 670 671 return 0; 672 } 673 674 /****************************************************************************/ 675 676 static int mcf_remove(struct platform_device *pdev) 677 { 678 struct uart_port *port; 679 int i; 680 681 for (i = 0; (i < MCF_MAXPORTS); i++) { 682 port = &mcf_ports[i].port; 683 if (port) 684 uart_remove_one_port(&mcf_driver, port); 685 } 686 687 return 0; 688 } 689 690 /****************************************************************************/ 691 692 static struct platform_driver mcf_platform_driver = { 693 .probe = mcf_probe, 694 .remove = mcf_remove, 695 .driver = { 696 .name = "mcfuart", 697 .owner = THIS_MODULE, 698 }, 699 }; 700 701 /****************************************************************************/ 702 703 static int __init mcf_init(void) 704 { 705 int rc; 706 707 printk("ColdFire internal UART serial driver\n"); 708 709 rc = uart_register_driver(&mcf_driver); 710 if (rc) 711 return rc; 712 rc = platform_driver_register(&mcf_platform_driver); 713 if (rc) { 714 uart_unregister_driver(&mcf_driver); 715 return rc; 716 } 717 return 0; 718 } 719 720 /****************************************************************************/ 721 722 static void __exit mcf_exit(void) 723 { 724 platform_driver_unregister(&mcf_platform_driver); 725 uart_unregister_driver(&mcf_driver); 726 } 727 728 /****************************************************************************/ 729 730 module_init(mcf_init); 731 module_exit(mcf_exit); 732 733 MODULE_AUTHOR("Greg Ungerer <gerg@snapgear.com>"); 734 MODULE_DESCRIPTION("Freescale ColdFire UART driver"); 735 MODULE_LICENSE("GPL"); 736 MODULE_ALIAS("platform:mcfuart"); 737 738 /****************************************************************************/ 739