1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 28 #define MAX310X_NAME "max310x" 29 #define MAX310X_MAJOR 204 30 #define MAX310X_MINOR 209 31 #define MAX310X_UART_NRMAX 16 32 33 /* MAX310X register definitions */ 34 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 35 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 36 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 37 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 38 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 39 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 40 #define MAX310X_REG_05 (0x05) 41 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 42 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 43 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 44 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 45 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 46 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 47 #define MAX310X_LCR_REG (0x0b) /* LCR */ 48 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 49 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 50 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 51 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 52 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 53 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 54 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 55 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 56 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 57 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 58 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 59 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 60 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 61 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 62 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 63 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 64 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 65 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 66 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 67 #define MAX310X_REG_1F (0x1f) 68 69 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 70 71 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 72 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 73 74 /* Extended registers */ 75 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 76 77 /* IRQ register bits */ 78 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 79 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 80 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 81 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 82 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 83 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 84 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 85 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 86 87 /* LSR register bits */ 88 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 89 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 90 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 91 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 92 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 93 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 94 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 95 96 /* Special character register bits */ 97 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 98 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 99 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 100 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 101 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 103 104 /* Status register bits */ 105 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 106 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 107 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 108 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 109 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 110 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 111 112 /* MODE1 register bits */ 113 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 114 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 117 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 118 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 119 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 120 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 121 122 /* MODE2 register bits */ 123 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 124 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 125 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 126 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 127 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 128 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 129 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 130 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 131 132 /* LCR register bits */ 133 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 134 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 135 * 136 * Word length bits table: 137 * 00 -> 5 bit words 138 * 01 -> 6 bit words 139 * 10 -> 7 bit words 140 * 11 -> 8 bit words 141 */ 142 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 143 * 144 * STOP length bit table: 145 * 0 -> 1 stop bit 146 * 1 -> 1-1.5 stop bits if 147 * word length is 5, 148 * 2 stop bits otherwise 149 */ 150 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 151 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 152 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 153 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 154 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 155 156 /* IRDA register bits */ 157 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 158 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 159 160 /* Flow control trigger level register masks */ 161 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 162 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 163 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 164 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 165 166 /* FIFO interrupt trigger level register masks */ 167 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 168 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 169 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 170 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 171 172 /* Flow control register bits */ 173 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 175 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 176 * are used in conjunction with 177 * XOFF2 for definition of 178 * special character */ 179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 180 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 181 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 182 * 183 * SWFLOW bits 1 & 0 table: 184 * 00 -> no transmitter flow 185 * control 186 * 01 -> receiver compares 187 * XON2 and XOFF2 188 * and controls 189 * transmitter 190 * 10 -> receiver compares 191 * XON1 and XOFF1 192 * and controls 193 * transmitter 194 * 11 -> receiver compares 195 * XON1, XON2, XOFF1 and 196 * XOFF2 and controls 197 * transmitter 198 */ 199 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 200 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 201 * 202 * SWFLOW bits 3 & 2 table: 203 * 00 -> no received flow 204 * control 205 * 01 -> transmitter generates 206 * XON2 and XOFF2 207 * 10 -> transmitter generates 208 * XON1 and XOFF1 209 * 11 -> transmitter generates 210 * XON1, XON2, XOFF1 and 211 * XOFF2 212 */ 213 214 /* PLL configuration register masks */ 215 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 216 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 217 218 /* Baud rate generator configuration register bits */ 219 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 220 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 221 222 /* Clock source register bits */ 223 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 224 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 225 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 226 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 227 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 228 229 /* Global commands */ 230 #define MAX310X_EXTREG_ENBL (0xce) 231 #define MAX310X_EXTREG_DSBL (0xcd) 232 233 /* Misc definitions */ 234 #define MAX310X_FIFO_SIZE (128) 235 #define MAX310x_REV_MASK (0xf8) 236 #define MAX310X_WRITE_BIT 0x80 237 238 /* MAX3107 specific */ 239 #define MAX3107_REV_ID (0xa0) 240 241 /* MAX3109 specific */ 242 #define MAX3109_REV_ID (0xc0) 243 244 /* MAX14830 specific */ 245 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 246 #define MAX14830_REV_ID (0xb0) 247 248 struct max310x_devtype { 249 char name[9]; 250 int nr; 251 int (*detect)(struct device *); 252 void (*power)(struct uart_port *, int); 253 }; 254 255 struct max310x_one { 256 struct uart_port port; 257 struct work_struct tx_work; 258 struct work_struct md_work; 259 struct work_struct rs_work; 260 }; 261 262 struct max310x_port { 263 struct max310x_devtype *devtype; 264 struct regmap *regmap; 265 struct mutex mutex; 266 struct clk *clk; 267 #ifdef CONFIG_GPIOLIB 268 struct gpio_chip gpio; 269 #endif 270 struct max310x_one p[0]; 271 }; 272 273 static struct uart_driver max310x_uart = { 274 .owner = THIS_MODULE, 275 .driver_name = MAX310X_NAME, 276 .dev_name = "ttyMAX", 277 .major = MAX310X_MAJOR, 278 .minor = MAX310X_MINOR, 279 .nr = MAX310X_UART_NRMAX, 280 }; 281 282 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 283 284 static u8 max310x_port_read(struct uart_port *port, u8 reg) 285 { 286 struct max310x_port *s = dev_get_drvdata(port->dev); 287 unsigned int val = 0; 288 289 regmap_read(s->regmap, port->iobase + reg, &val); 290 291 return val; 292 } 293 294 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 295 { 296 struct max310x_port *s = dev_get_drvdata(port->dev); 297 298 regmap_write(s->regmap, port->iobase + reg, val); 299 } 300 301 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 302 { 303 struct max310x_port *s = dev_get_drvdata(port->dev); 304 305 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); 306 } 307 308 static int max3107_detect(struct device *dev) 309 { 310 struct max310x_port *s = dev_get_drvdata(dev); 311 unsigned int val = 0; 312 int ret; 313 314 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 315 if (ret) 316 return ret; 317 318 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 319 dev_err(dev, 320 "%s ID 0x%02x does not match\n", s->devtype->name, val); 321 return -ENODEV; 322 } 323 324 return 0; 325 } 326 327 static int max3108_detect(struct device *dev) 328 { 329 struct max310x_port *s = dev_get_drvdata(dev); 330 unsigned int val = 0; 331 int ret; 332 333 /* MAX3108 have not REV ID register, we just check default value 334 * from clocksource register to make sure everything works. 335 */ 336 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 337 if (ret) 338 return ret; 339 340 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 341 dev_err(dev, "%s not present\n", s->devtype->name); 342 return -ENODEV; 343 } 344 345 return 0; 346 } 347 348 static int max3109_detect(struct device *dev) 349 { 350 struct max310x_port *s = dev_get_drvdata(dev); 351 unsigned int val = 0; 352 int ret; 353 354 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 355 MAX310X_EXTREG_ENBL); 356 if (ret) 357 return ret; 358 359 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 360 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 361 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 362 dev_err(dev, 363 "%s ID 0x%02x does not match\n", s->devtype->name, val); 364 return -ENODEV; 365 } 366 367 return 0; 368 } 369 370 static void max310x_power(struct uart_port *port, int on) 371 { 372 max310x_port_update(port, MAX310X_MODE1_REG, 373 MAX310X_MODE1_FORCESLEEP_BIT, 374 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 375 if (on) 376 msleep(50); 377 } 378 379 static int max14830_detect(struct device *dev) 380 { 381 struct max310x_port *s = dev_get_drvdata(dev); 382 unsigned int val = 0; 383 int ret; 384 385 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 386 MAX310X_EXTREG_ENBL); 387 if (ret) 388 return ret; 389 390 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 391 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 392 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 393 dev_err(dev, 394 "%s ID 0x%02x does not match\n", s->devtype->name, val); 395 return -ENODEV; 396 } 397 398 return 0; 399 } 400 401 static void max14830_power(struct uart_port *port, int on) 402 { 403 max310x_port_update(port, MAX310X_BRGCFG_REG, 404 MAX14830_BRGCFG_CLKDIS_BIT, 405 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 406 if (on) 407 msleep(50); 408 } 409 410 static const struct max310x_devtype max3107_devtype = { 411 .name = "MAX3107", 412 .nr = 1, 413 .detect = max3107_detect, 414 .power = max310x_power, 415 }; 416 417 static const struct max310x_devtype max3108_devtype = { 418 .name = "MAX3108", 419 .nr = 1, 420 .detect = max3108_detect, 421 .power = max310x_power, 422 }; 423 424 static const struct max310x_devtype max3109_devtype = { 425 .name = "MAX3109", 426 .nr = 2, 427 .detect = max3109_detect, 428 .power = max310x_power, 429 }; 430 431 static const struct max310x_devtype max14830_devtype = { 432 .name = "MAX14830", 433 .nr = 4, 434 .detect = max14830_detect, 435 .power = max14830_power, 436 }; 437 438 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 439 { 440 switch (reg & 0x1f) { 441 case MAX310X_IRQSTS_REG: 442 case MAX310X_LSR_IRQSTS_REG: 443 case MAX310X_SPCHR_IRQSTS_REG: 444 case MAX310X_STS_IRQSTS_REG: 445 case MAX310X_TXFIFOLVL_REG: 446 case MAX310X_RXFIFOLVL_REG: 447 return false; 448 default: 449 break; 450 } 451 452 return true; 453 } 454 455 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 456 { 457 switch (reg & 0x1f) { 458 case MAX310X_RHR_REG: 459 case MAX310X_IRQSTS_REG: 460 case MAX310X_LSR_IRQSTS_REG: 461 case MAX310X_SPCHR_IRQSTS_REG: 462 case MAX310X_STS_IRQSTS_REG: 463 case MAX310X_TXFIFOLVL_REG: 464 case MAX310X_RXFIFOLVL_REG: 465 case MAX310X_GPIODATA_REG: 466 case MAX310X_BRGDIVLSB_REG: 467 case MAX310X_REG_05: 468 case MAX310X_REG_1F: 469 return true; 470 default: 471 break; 472 } 473 474 return false; 475 } 476 477 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 478 { 479 switch (reg & 0x1f) { 480 case MAX310X_RHR_REG: 481 case MAX310X_IRQSTS_REG: 482 case MAX310X_SPCHR_IRQSTS_REG: 483 case MAX310X_STS_IRQSTS_REG: 484 return true; 485 default: 486 break; 487 } 488 489 return false; 490 } 491 492 static int max310x_set_baud(struct uart_port *port, int baud) 493 { 494 unsigned int mode = 0, clk = port->uartclk, div = clk / baud; 495 496 /* Check for minimal value for divider */ 497 if (div < 16) 498 div = 16; 499 500 if (clk % baud && (div / 16) < 0x8000) { 501 /* Mode x2 */ 502 mode = MAX310X_BRGCFG_2XMODE_BIT; 503 clk = port->uartclk * 2; 504 div = clk / baud; 505 506 if (clk % baud && (div / 16) < 0x8000) { 507 /* Mode x4 */ 508 mode = MAX310X_BRGCFG_4XMODE_BIT; 509 clk = port->uartclk * 4; 510 div = clk / baud; 511 } 512 } 513 514 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); 515 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); 516 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); 517 518 return DIV_ROUND_CLOSEST(clk, div); 519 } 520 521 static int max310x_update_best_err(unsigned long f, long *besterr) 522 { 523 /* Use baudrate 115200 for calculate error */ 524 long err = f % (115200 * 16); 525 526 if ((*besterr < 0) || (*besterr > err)) { 527 *besterr = err; 528 return 0; 529 } 530 531 return 1; 532 } 533 534 static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 535 unsigned long freq, bool xtal) 536 { 537 unsigned int div, clksrc, pllcfg = 0; 538 long besterr = -1; 539 unsigned long fdiv, fmul, bestfreq = freq; 540 541 /* First, update error without PLL */ 542 max310x_update_best_err(freq, &besterr); 543 544 /* Try all possible PLL dividers */ 545 for (div = 1; (div <= 63) && besterr; div++) { 546 fdiv = DIV_ROUND_CLOSEST(freq, div); 547 548 /* Try multiplier 6 */ 549 fmul = fdiv * 6; 550 if ((fdiv >= 500000) && (fdiv <= 800000)) 551 if (!max310x_update_best_err(fmul, &besterr)) { 552 pllcfg = (0 << 6) | div; 553 bestfreq = fmul; 554 } 555 /* Try multiplier 48 */ 556 fmul = fdiv * 48; 557 if ((fdiv >= 850000) && (fdiv <= 1200000)) 558 if (!max310x_update_best_err(fmul, &besterr)) { 559 pllcfg = (1 << 6) | div; 560 bestfreq = fmul; 561 } 562 /* Try multiplier 96 */ 563 fmul = fdiv * 96; 564 if ((fdiv >= 425000) && (fdiv <= 1000000)) 565 if (!max310x_update_best_err(fmul, &besterr)) { 566 pllcfg = (2 << 6) | div; 567 bestfreq = fmul; 568 } 569 /* Try multiplier 144 */ 570 fmul = fdiv * 144; 571 if ((fdiv >= 390000) && (fdiv <= 667000)) 572 if (!max310x_update_best_err(fmul, &besterr)) { 573 pllcfg = (3 << 6) | div; 574 bestfreq = fmul; 575 } 576 } 577 578 /* Configure clock source */ 579 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT; 580 581 /* Configure PLL */ 582 if (pllcfg) { 583 clksrc |= MAX310X_CLKSRC_PLL_BIT; 584 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 585 } else 586 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 587 588 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 589 590 /* Wait for crystal */ 591 if (xtal) { 592 unsigned int val; 593 msleep(10); 594 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 595 if (!(val & MAX310X_STS_CLKREADY_BIT)) { 596 dev_warn(dev, "clock is not stable yet\n"); 597 } 598 } 599 600 return (int)bestfreq; 601 } 602 603 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 604 { 605 u8 header[] = { (port->iobase + MAX310X_THR_REG) | MAX310X_WRITE_BIT }; 606 struct spi_transfer xfer[] = { 607 { 608 .tx_buf = &header, 609 .len = sizeof(header), 610 }, { 611 .tx_buf = txbuf, 612 .len = len, 613 } 614 }; 615 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); 616 } 617 618 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 619 { 620 u8 header[] = { port->iobase + MAX310X_RHR_REG }; 621 struct spi_transfer xfer[] = { 622 { 623 .tx_buf = &header, 624 .len = sizeof(header), 625 }, { 626 .rx_buf = rxbuf, 627 .len = len, 628 } 629 }; 630 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); 631 } 632 633 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 634 { 635 unsigned int sts, ch, flag, i; 636 u8 buf[MAX310X_FIFO_SIZE]; 637 638 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 639 /* We are just reading, happily ignoring any error conditions. 640 * Break condition, parity checking, framing errors -- they 641 * are all ignored. That means that we can do a batch-read. 642 * 643 * There is a small opportunity for race if the RX FIFO 644 * overruns while we're reading the buffer; the datasheets says 645 * that the LSR register applies to the "current" character. 646 * That's also the reason why we cannot do batched reads when 647 * asked to check the individual statuses. 648 * */ 649 650 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 651 max310x_batch_read(port, buf, rxlen); 652 653 port->icount.rx += rxlen; 654 flag = TTY_NORMAL; 655 sts &= port->read_status_mask; 656 657 if (sts & MAX310X_LSR_RXOVR_BIT) { 658 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 659 port->icount.overrun++; 660 } 661 662 for (i = 0; i < rxlen; ++i) { 663 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, buf[i], flag); 664 } 665 666 } else { 667 if (unlikely(rxlen >= port->fifosize)) { 668 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 669 port->icount.buf_overrun++; 670 /* Ensure sanity of RX level */ 671 rxlen = port->fifosize; 672 } 673 674 while (rxlen--) { 675 ch = max310x_port_read(port, MAX310X_RHR_REG); 676 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 677 678 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 679 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 680 681 port->icount.rx++; 682 flag = TTY_NORMAL; 683 684 if (unlikely(sts)) { 685 if (sts & MAX310X_LSR_RXBRK_BIT) { 686 port->icount.brk++; 687 if (uart_handle_break(port)) 688 continue; 689 } else if (sts & MAX310X_LSR_RXPAR_BIT) 690 port->icount.parity++; 691 else if (sts & MAX310X_LSR_FRERR_BIT) 692 port->icount.frame++; 693 else if (sts & MAX310X_LSR_RXOVR_BIT) 694 port->icount.overrun++; 695 696 sts &= port->read_status_mask; 697 if (sts & MAX310X_LSR_RXBRK_BIT) 698 flag = TTY_BREAK; 699 else if (sts & MAX310X_LSR_RXPAR_BIT) 700 flag = TTY_PARITY; 701 else if (sts & MAX310X_LSR_FRERR_BIT) 702 flag = TTY_FRAME; 703 else if (sts & MAX310X_LSR_RXOVR_BIT) 704 flag = TTY_OVERRUN; 705 } 706 707 if (uart_handle_sysrq_char(port, ch)) 708 continue; 709 710 if (sts & port->ignore_status_mask) 711 continue; 712 713 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 714 } 715 } 716 717 tty_flip_buffer_push(&port->state->port); 718 } 719 720 static void max310x_handle_tx(struct uart_port *port) 721 { 722 struct circ_buf *xmit = &port->state->xmit; 723 unsigned int txlen, to_send, until_end; 724 725 if (unlikely(port->x_char)) { 726 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 727 port->icount.tx++; 728 port->x_char = 0; 729 return; 730 } 731 732 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 733 return; 734 735 /* Get length of data pending in circular buffer */ 736 to_send = uart_circ_chars_pending(xmit); 737 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 738 if (likely(to_send)) { 739 /* Limit to size of TX FIFO */ 740 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 741 txlen = port->fifosize - txlen; 742 to_send = (to_send > txlen) ? txlen : to_send; 743 744 if (until_end < to_send) { 745 /* It's a circ buffer -- wrap around. 746 * We could do that in one SPI transaction, but meh. */ 747 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 748 max310x_batch_write(port, xmit->buf, to_send - until_end); 749 } else { 750 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 751 } 752 753 /* Add data to send */ 754 port->icount.tx += to_send; 755 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); 756 } 757 758 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 759 uart_write_wakeup(port); 760 } 761 762 static void max310x_start_tx(struct uart_port *port) 763 { 764 struct max310x_one *one = container_of(port, struct max310x_one, port); 765 766 if (!work_pending(&one->tx_work)) 767 schedule_work(&one->tx_work); 768 } 769 770 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 771 { 772 struct uart_port *port = &s->p[portno].port; 773 irqreturn_t res = IRQ_NONE; 774 775 do { 776 unsigned int ists, lsr, rxlen; 777 778 /* Read IRQ status & RX FIFO level */ 779 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 780 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 781 if (!ists && !rxlen) 782 break; 783 784 res = IRQ_HANDLED; 785 786 if (ists & MAX310X_IRQ_CTS_BIT) { 787 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 788 uart_handle_cts_change(port, 789 !!(lsr & MAX310X_LSR_CTS_BIT)); 790 } 791 if (rxlen) 792 max310x_handle_rx(port, rxlen); 793 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 794 max310x_start_tx(port); 795 } while (1); 796 return res; 797 } 798 799 static irqreturn_t max310x_ist(int irq, void *dev_id) 800 { 801 struct max310x_port *s = (struct max310x_port *)dev_id; 802 bool handled = false; 803 804 if (s->devtype->nr > 1) { 805 do { 806 unsigned int val = ~0; 807 808 WARN_ON_ONCE(regmap_read(s->regmap, 809 MAX310X_GLOBALIRQ_REG, &val)); 810 val = ((1 << s->devtype->nr) - 1) & ~val; 811 if (!val) 812 break; 813 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 814 handled = true; 815 } while (1); 816 } else { 817 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 818 handled = true; 819 } 820 821 return IRQ_RETVAL(handled); 822 } 823 824 static void max310x_wq_proc(struct work_struct *ws) 825 { 826 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 827 struct max310x_port *s = dev_get_drvdata(one->port.dev); 828 829 mutex_lock(&s->mutex); 830 max310x_handle_tx(&one->port); 831 mutex_unlock(&s->mutex); 832 } 833 834 static unsigned int max310x_tx_empty(struct uart_port *port) 835 { 836 unsigned int lvl, sts; 837 838 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 839 sts = max310x_port_read(port, MAX310X_IRQSTS_REG); 840 841 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0; 842 } 843 844 static unsigned int max310x_get_mctrl(struct uart_port *port) 845 { 846 /* DCD and DSR are not wired and CTS/RTS is handled automatically 847 * so just indicate DSR and CAR asserted 848 */ 849 return TIOCM_DSR | TIOCM_CAR; 850 } 851 852 static void max310x_md_proc(struct work_struct *ws) 853 { 854 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 855 856 max310x_port_update(&one->port, MAX310X_MODE2_REG, 857 MAX310X_MODE2_LOOPBACK_BIT, 858 (one->port.mctrl & TIOCM_LOOP) ? 859 MAX310X_MODE2_LOOPBACK_BIT : 0); 860 } 861 862 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 863 { 864 struct max310x_one *one = container_of(port, struct max310x_one, port); 865 866 schedule_work(&one->md_work); 867 } 868 869 static void max310x_break_ctl(struct uart_port *port, int break_state) 870 { 871 max310x_port_update(port, MAX310X_LCR_REG, 872 MAX310X_LCR_TXBREAK_BIT, 873 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 874 } 875 876 static void max310x_set_termios(struct uart_port *port, 877 struct ktermios *termios, 878 struct ktermios *old) 879 { 880 unsigned int lcr = 0, flow = 0; 881 int baud; 882 883 /* Mask termios capabilities we don't support */ 884 termios->c_cflag &= ~CMSPAR; 885 886 /* Word size */ 887 switch (termios->c_cflag & CSIZE) { 888 case CS5: 889 break; 890 case CS6: 891 lcr = MAX310X_LCR_LENGTH0_BIT; 892 break; 893 case CS7: 894 lcr = MAX310X_LCR_LENGTH1_BIT; 895 break; 896 case CS8: 897 default: 898 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 899 break; 900 } 901 902 /* Parity */ 903 if (termios->c_cflag & PARENB) { 904 lcr |= MAX310X_LCR_PARITY_BIT; 905 if (!(termios->c_cflag & PARODD)) 906 lcr |= MAX310X_LCR_EVENPARITY_BIT; 907 } 908 909 /* Stop bits */ 910 if (termios->c_cflag & CSTOPB) 911 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 912 913 /* Update LCR register */ 914 max310x_port_write(port, MAX310X_LCR_REG, lcr); 915 916 /* Set read status mask */ 917 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 918 if (termios->c_iflag & INPCK) 919 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 920 MAX310X_LSR_FRERR_BIT; 921 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 922 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 923 924 /* Set status ignore mask */ 925 port->ignore_status_mask = 0; 926 if (termios->c_iflag & IGNBRK) 927 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 928 if (!(termios->c_cflag & CREAD)) 929 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 930 MAX310X_LSR_RXOVR_BIT | 931 MAX310X_LSR_FRERR_BIT | 932 MAX310X_LSR_RXBRK_BIT; 933 934 /* Configure flow control */ 935 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 936 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 937 if (termios->c_cflag & CRTSCTS) 938 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 939 MAX310X_FLOWCTRL_AUTORTS_BIT; 940 if (termios->c_iflag & IXON) 941 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 942 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 943 if (termios->c_iflag & IXOFF) 944 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 945 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 946 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 947 948 /* Get baud rate generator configuration */ 949 baud = uart_get_baud_rate(port, termios, old, 950 port->uartclk / 16 / 0xffff, 951 port->uartclk / 4); 952 953 /* Setup baudrate generator */ 954 baud = max310x_set_baud(port, baud); 955 956 /* Update timeout according to new baud rate */ 957 uart_update_timeout(port, termios->c_cflag, baud); 958 } 959 960 static void max310x_rs_proc(struct work_struct *ws) 961 { 962 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 963 unsigned int val; 964 965 val = (one->port.rs485.delay_rts_before_send << 4) | 966 one->port.rs485.delay_rts_after_send; 967 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val); 968 969 if (one->port.rs485.flags & SER_RS485_ENABLED) { 970 max310x_port_update(&one->port, MAX310X_MODE1_REG, 971 MAX310X_MODE1_TRNSCVCTRL_BIT, 972 MAX310X_MODE1_TRNSCVCTRL_BIT); 973 max310x_port_update(&one->port, MAX310X_MODE2_REG, 974 MAX310X_MODE2_ECHOSUPR_BIT, 975 MAX310X_MODE2_ECHOSUPR_BIT); 976 } else { 977 max310x_port_update(&one->port, MAX310X_MODE1_REG, 978 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 979 max310x_port_update(&one->port, MAX310X_MODE2_REG, 980 MAX310X_MODE2_ECHOSUPR_BIT, 0); 981 } 982 } 983 984 static int max310x_rs485_config(struct uart_port *port, 985 struct serial_rs485 *rs485) 986 { 987 struct max310x_one *one = container_of(port, struct max310x_one, port); 988 989 if ((rs485->delay_rts_before_send > 0x0f) || 990 (rs485->delay_rts_after_send > 0x0f)) 991 return -ERANGE; 992 993 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED; 994 memset(rs485->padding, 0, sizeof(rs485->padding)); 995 port->rs485 = *rs485; 996 997 schedule_work(&one->rs_work); 998 999 return 0; 1000 } 1001 1002 static int max310x_startup(struct uart_port *port) 1003 { 1004 struct max310x_port *s = dev_get_drvdata(port->dev); 1005 unsigned int val; 1006 1007 s->devtype->power(port, 1); 1008 1009 /* Configure MODE1 register */ 1010 max310x_port_update(port, MAX310X_MODE1_REG, 1011 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1012 1013 /* Configure MODE2 register & Reset FIFOs*/ 1014 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1015 max310x_port_write(port, MAX310X_MODE2_REG, val); 1016 max310x_port_update(port, MAX310X_MODE2_REG, 1017 MAX310X_MODE2_FIFORST_BIT, 0); 1018 1019 /* Configure flow control levels */ 1020 /* Flow control halt level 96, resume level 48 */ 1021 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1022 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1023 1024 /* Clear IRQ status register */ 1025 max310x_port_read(port, MAX310X_IRQSTS_REG); 1026 1027 /* Enable RX, TX, CTS change interrupts */ 1028 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1029 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1030 1031 return 0; 1032 } 1033 1034 static void max310x_shutdown(struct uart_port *port) 1035 { 1036 struct max310x_port *s = dev_get_drvdata(port->dev); 1037 1038 /* Disable all interrupts */ 1039 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1040 1041 s->devtype->power(port, 0); 1042 } 1043 1044 static const char *max310x_type(struct uart_port *port) 1045 { 1046 struct max310x_port *s = dev_get_drvdata(port->dev); 1047 1048 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1049 } 1050 1051 static int max310x_request_port(struct uart_port *port) 1052 { 1053 /* Do nothing */ 1054 return 0; 1055 } 1056 1057 static void max310x_config_port(struct uart_port *port, int flags) 1058 { 1059 if (flags & UART_CONFIG_TYPE) 1060 port->type = PORT_MAX310X; 1061 } 1062 1063 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1064 { 1065 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1066 return -EINVAL; 1067 if (s->irq != port->irq) 1068 return -EINVAL; 1069 1070 return 0; 1071 } 1072 1073 static void max310x_null_void(struct uart_port *port) 1074 { 1075 /* Do nothing */ 1076 } 1077 1078 static const struct uart_ops max310x_ops = { 1079 .tx_empty = max310x_tx_empty, 1080 .set_mctrl = max310x_set_mctrl, 1081 .get_mctrl = max310x_get_mctrl, 1082 .stop_tx = max310x_null_void, 1083 .start_tx = max310x_start_tx, 1084 .stop_rx = max310x_null_void, 1085 .break_ctl = max310x_break_ctl, 1086 .startup = max310x_startup, 1087 .shutdown = max310x_shutdown, 1088 .set_termios = max310x_set_termios, 1089 .type = max310x_type, 1090 .request_port = max310x_request_port, 1091 .release_port = max310x_null_void, 1092 .config_port = max310x_config_port, 1093 .verify_port = max310x_verify_port, 1094 }; 1095 1096 static int __maybe_unused max310x_suspend(struct device *dev) 1097 { 1098 struct max310x_port *s = dev_get_drvdata(dev); 1099 int i; 1100 1101 for (i = 0; i < s->devtype->nr; i++) { 1102 uart_suspend_port(&max310x_uart, &s->p[i].port); 1103 s->devtype->power(&s->p[i].port, 0); 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int __maybe_unused max310x_resume(struct device *dev) 1110 { 1111 struct max310x_port *s = dev_get_drvdata(dev); 1112 int i; 1113 1114 for (i = 0; i < s->devtype->nr; i++) { 1115 s->devtype->power(&s->p[i].port, 1); 1116 uart_resume_port(&max310x_uart, &s->p[i].port); 1117 } 1118 1119 return 0; 1120 } 1121 1122 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1123 1124 #ifdef CONFIG_GPIOLIB 1125 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1126 { 1127 unsigned int val; 1128 struct max310x_port *s = gpiochip_get_data(chip); 1129 struct uart_port *port = &s->p[offset / 4].port; 1130 1131 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1132 1133 return !!((val >> 4) & (1 << (offset % 4))); 1134 } 1135 1136 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1137 { 1138 struct max310x_port *s = gpiochip_get_data(chip); 1139 struct uart_port *port = &s->p[offset / 4].port; 1140 1141 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1142 value ? 1 << (offset % 4) : 0); 1143 } 1144 1145 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1146 { 1147 struct max310x_port *s = gpiochip_get_data(chip); 1148 struct uart_port *port = &s->p[offset / 4].port; 1149 1150 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1151 1152 return 0; 1153 } 1154 1155 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1156 unsigned offset, int value) 1157 { 1158 struct max310x_port *s = gpiochip_get_data(chip); 1159 struct uart_port *port = &s->p[offset / 4].port; 1160 1161 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1162 value ? 1 << (offset % 4) : 0); 1163 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1164 1 << (offset % 4)); 1165 1166 return 0; 1167 } 1168 1169 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1170 unsigned long config) 1171 { 1172 struct max310x_port *s = gpiochip_get_data(chip); 1173 struct uart_port *port = &s->p[offset / 4].port; 1174 1175 switch (pinconf_to_config_param(config)) { 1176 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1177 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1178 1 << ((offset % 4) + 4), 1179 1 << ((offset % 4) + 4)); 1180 return 0; 1181 case PIN_CONFIG_DRIVE_PUSH_PULL: 1182 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1183 1 << ((offset % 4) + 4), 0); 1184 return 0; 1185 default: 1186 return -ENOTSUPP; 1187 } 1188 } 1189 #endif 1190 1191 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, 1192 struct regmap *regmap, int irq) 1193 { 1194 int i, ret, fmin, fmax, freq, uartclk; 1195 struct clk *clk_osc, *clk_xtal; 1196 struct max310x_port *s; 1197 bool xtal = false; 1198 1199 if (IS_ERR(regmap)) 1200 return PTR_ERR(regmap); 1201 1202 /* Alloc port structure */ 1203 s = devm_kzalloc(dev, sizeof(*s) + 1204 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL); 1205 if (!s) { 1206 dev_err(dev, "Error allocating port structure\n"); 1207 return -ENOMEM; 1208 } 1209 1210 clk_osc = devm_clk_get(dev, "osc"); 1211 clk_xtal = devm_clk_get(dev, "xtal"); 1212 if (!IS_ERR(clk_osc)) { 1213 s->clk = clk_osc; 1214 fmin = 500000; 1215 fmax = 35000000; 1216 } else if (!IS_ERR(clk_xtal)) { 1217 s->clk = clk_xtal; 1218 fmin = 1000000; 1219 fmax = 4000000; 1220 xtal = true; 1221 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || 1222 PTR_ERR(clk_xtal) == -EPROBE_DEFER) { 1223 return -EPROBE_DEFER; 1224 } else { 1225 dev_err(dev, "Cannot get clock\n"); 1226 return -EINVAL; 1227 } 1228 1229 ret = clk_prepare_enable(s->clk); 1230 if (ret) 1231 return ret; 1232 1233 freq = clk_get_rate(s->clk); 1234 /* Check frequency limits */ 1235 if (freq < fmin || freq > fmax) { 1236 ret = -ERANGE; 1237 goto out_clk; 1238 } 1239 1240 s->regmap = regmap; 1241 s->devtype = devtype; 1242 dev_set_drvdata(dev, s); 1243 1244 /* Check device to ensure we are talking to what we expect */ 1245 ret = devtype->detect(dev); 1246 if (ret) 1247 goto out_clk; 1248 1249 for (i = 0; i < devtype->nr; i++) { 1250 unsigned int offs = i << 5; 1251 1252 /* Reset port */ 1253 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 1254 MAX310X_MODE2_RST_BIT); 1255 /* Clear port reset */ 1256 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); 1257 1258 /* Wait for port startup */ 1259 do { 1260 regmap_read(s->regmap, 1261 MAX310X_BRGDIVLSB_REG + offs, &ret); 1262 } while (ret != 0x01); 1263 1264 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs, 1265 MAX310X_MODE1_AUTOSLEEP_BIT, 1266 MAX310X_MODE1_AUTOSLEEP_BIT); 1267 } 1268 1269 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1270 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1271 1272 mutex_init(&s->mutex); 1273 1274 for (i = 0; i < devtype->nr; i++) { 1275 unsigned int line; 1276 1277 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1278 if (line == MAX310X_UART_NRMAX) { 1279 ret = -ERANGE; 1280 goto out_uart; 1281 } 1282 1283 /* Initialize port data */ 1284 s->p[i].port.line = line; 1285 s->p[i].port.dev = dev; 1286 s->p[i].port.irq = irq; 1287 s->p[i].port.type = PORT_MAX310X; 1288 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1289 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1290 s->p[i].port.iotype = UPIO_PORT; 1291 s->p[i].port.iobase = i * 0x20; 1292 s->p[i].port.membase = (void __iomem *)~0; 1293 s->p[i].port.uartclk = uartclk; 1294 s->p[i].port.rs485_config = max310x_rs485_config; 1295 s->p[i].port.ops = &max310x_ops; 1296 /* Disable all interrupts */ 1297 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1298 /* Clear IRQ status register */ 1299 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1300 /* Enable IRQ pin */ 1301 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG, 1302 MAX310X_MODE1_IRQSEL_BIT, 1303 MAX310X_MODE1_IRQSEL_BIT); 1304 /* Initialize queue for start TX */ 1305 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc); 1306 /* Initialize queue for changing LOOPBACK mode */ 1307 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1308 /* Initialize queue for changing RS485 mode */ 1309 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1310 1311 /* Register port */ 1312 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1313 if (ret) { 1314 s->p[i].port.dev = NULL; 1315 goto out_uart; 1316 } 1317 set_bit(line, max310x_lines); 1318 1319 /* Go to suspend mode */ 1320 devtype->power(&s->p[i].port, 0); 1321 } 1322 1323 #ifdef CONFIG_GPIOLIB 1324 /* Setup GPIO cotroller */ 1325 s->gpio.owner = THIS_MODULE; 1326 s->gpio.parent = dev; 1327 s->gpio.label = devtype->name; 1328 s->gpio.direction_input = max310x_gpio_direction_input; 1329 s->gpio.get = max310x_gpio_get; 1330 s->gpio.direction_output= max310x_gpio_direction_output; 1331 s->gpio.set = max310x_gpio_set; 1332 s->gpio.set_config = max310x_gpio_set_config; 1333 s->gpio.base = -1; 1334 s->gpio.ngpio = devtype->nr * 4; 1335 s->gpio.can_sleep = 1; 1336 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1337 if (ret) 1338 goto out_uart; 1339 #endif 1340 1341 /* Setup interrupt */ 1342 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1343 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1344 if (!ret) 1345 return 0; 1346 1347 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1348 1349 out_uart: 1350 for (i = 0; i < devtype->nr; i++) { 1351 if (s->p[i].port.dev) { 1352 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1353 clear_bit(s->p[i].port.line, max310x_lines); 1354 } 1355 } 1356 1357 mutex_destroy(&s->mutex); 1358 1359 out_clk: 1360 clk_disable_unprepare(s->clk); 1361 1362 return ret; 1363 } 1364 1365 static int max310x_remove(struct device *dev) 1366 { 1367 struct max310x_port *s = dev_get_drvdata(dev); 1368 int i; 1369 1370 for (i = 0; i < s->devtype->nr; i++) { 1371 cancel_work_sync(&s->p[i].tx_work); 1372 cancel_work_sync(&s->p[i].md_work); 1373 cancel_work_sync(&s->p[i].rs_work); 1374 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1375 clear_bit(s->p[i].port.line, max310x_lines); 1376 s->devtype->power(&s->p[i].port, 0); 1377 } 1378 1379 mutex_destroy(&s->mutex); 1380 clk_disable_unprepare(s->clk); 1381 1382 return 0; 1383 } 1384 1385 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1386 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1387 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1388 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1389 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1390 { } 1391 }; 1392 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1393 1394 static struct regmap_config regcfg = { 1395 .reg_bits = 8, 1396 .val_bits = 8, 1397 .write_flag_mask = MAX310X_WRITE_BIT, 1398 .cache_type = REGCACHE_RBTREE, 1399 .writeable_reg = max310x_reg_writeable, 1400 .volatile_reg = max310x_reg_volatile, 1401 .precious_reg = max310x_reg_precious, 1402 }; 1403 1404 #ifdef CONFIG_SPI_MASTER 1405 static int max310x_spi_probe(struct spi_device *spi) 1406 { 1407 struct max310x_devtype *devtype; 1408 struct regmap *regmap; 1409 int ret; 1410 1411 /* Setup SPI bus */ 1412 spi->bits_per_word = 8; 1413 spi->mode = spi->mode ? : SPI_MODE_0; 1414 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1415 ret = spi_setup(spi); 1416 if (ret) 1417 return ret; 1418 1419 if (spi->dev.of_node) { 1420 const struct of_device_id *of_id = 1421 of_match_device(max310x_dt_ids, &spi->dev); 1422 1423 devtype = (struct max310x_devtype *)of_id->data; 1424 } else { 1425 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1426 1427 devtype = (struct max310x_devtype *)id_entry->driver_data; 1428 } 1429 1430 regcfg.max_register = devtype->nr * 0x20 - 1; 1431 regmap = devm_regmap_init_spi(spi, ®cfg); 1432 1433 return max310x_probe(&spi->dev, devtype, regmap, spi->irq); 1434 } 1435 1436 static int max310x_spi_remove(struct spi_device *spi) 1437 { 1438 return max310x_remove(&spi->dev); 1439 } 1440 1441 static const struct spi_device_id max310x_id_table[] = { 1442 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1443 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1444 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1445 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1446 { } 1447 }; 1448 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1449 1450 static struct spi_driver max310x_spi_driver = { 1451 .driver = { 1452 .name = MAX310X_NAME, 1453 .of_match_table = of_match_ptr(max310x_dt_ids), 1454 .pm = &max310x_pm_ops, 1455 }, 1456 .probe = max310x_spi_probe, 1457 .remove = max310x_spi_remove, 1458 .id_table = max310x_id_table, 1459 }; 1460 #endif 1461 1462 static int __init max310x_uart_init(void) 1463 { 1464 int ret; 1465 1466 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1467 1468 ret = uart_register_driver(&max310x_uart); 1469 if (ret) 1470 return ret; 1471 1472 #ifdef CONFIG_SPI_MASTER 1473 spi_register_driver(&max310x_spi_driver); 1474 #endif 1475 1476 return 0; 1477 } 1478 module_init(max310x_uart_init); 1479 1480 static void __exit max310x_uart_exit(void) 1481 { 1482 #ifdef CONFIG_SPI_MASTER 1483 spi_unregister_driver(&max310x_spi_driver); 1484 #endif 1485 1486 uart_unregister_driver(&max310x_uart); 1487 } 1488 module_exit(max310x_uart_exit); 1489 1490 MODULE_LICENSE("GPL"); 1491 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1492 MODULE_DESCRIPTION("MAX310X serial driver"); 1493