1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 28 #define MAX310X_NAME "max310x" 29 #define MAX310X_MAJOR 204 30 #define MAX310X_MINOR 209 31 #define MAX310X_UART_NRMAX 16 32 33 /* MAX310X register definitions */ 34 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 35 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 36 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 37 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 38 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 39 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 40 #define MAX310X_REG_05 (0x05) 41 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 42 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 43 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 44 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 45 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 46 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 47 #define MAX310X_LCR_REG (0x0b) /* LCR */ 48 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 49 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 50 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 51 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 52 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 53 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 54 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 55 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 56 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 57 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 58 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 59 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 60 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 61 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 62 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 63 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 64 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 65 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 66 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 67 #define MAX310X_REG_1F (0x1f) 68 69 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 70 71 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 72 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 73 74 /* Extended registers */ 75 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 76 77 /* IRQ register bits */ 78 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 79 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 80 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 81 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 82 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 83 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 84 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 85 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 86 87 /* LSR register bits */ 88 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 89 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 90 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 91 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 92 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 93 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 94 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 95 96 /* Special character register bits */ 97 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 98 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 99 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 100 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 101 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 103 104 /* Status register bits */ 105 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 106 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 107 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 108 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 109 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 110 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 111 112 /* MODE1 register bits */ 113 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 114 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 117 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 118 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 119 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 120 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 121 122 /* MODE2 register bits */ 123 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 124 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 125 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 126 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 127 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 128 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 129 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 130 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 131 132 /* LCR register bits */ 133 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 134 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 135 * 136 * Word length bits table: 137 * 00 -> 5 bit words 138 * 01 -> 6 bit words 139 * 10 -> 7 bit words 140 * 11 -> 8 bit words 141 */ 142 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 143 * 144 * STOP length bit table: 145 * 0 -> 1 stop bit 146 * 1 -> 1-1.5 stop bits if 147 * word length is 5, 148 * 2 stop bits otherwise 149 */ 150 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 151 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 152 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 153 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 154 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 155 156 /* IRDA register bits */ 157 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 158 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 159 160 /* Flow control trigger level register masks */ 161 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 162 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 163 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 164 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 165 166 /* FIFO interrupt trigger level register masks */ 167 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 168 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 169 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 170 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 171 172 /* Flow control register bits */ 173 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 175 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 176 * are used in conjunction with 177 * XOFF2 for definition of 178 * special character */ 179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 180 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 181 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 182 * 183 * SWFLOW bits 1 & 0 table: 184 * 00 -> no transmitter flow 185 * control 186 * 01 -> receiver compares 187 * XON2 and XOFF2 188 * and controls 189 * transmitter 190 * 10 -> receiver compares 191 * XON1 and XOFF1 192 * and controls 193 * transmitter 194 * 11 -> receiver compares 195 * XON1, XON2, XOFF1 and 196 * XOFF2 and controls 197 * transmitter 198 */ 199 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 200 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 201 * 202 * SWFLOW bits 3 & 2 table: 203 * 00 -> no received flow 204 * control 205 * 01 -> transmitter generates 206 * XON2 and XOFF2 207 * 10 -> transmitter generates 208 * XON1 and XOFF1 209 * 11 -> transmitter generates 210 * XON1, XON2, XOFF1 and 211 * XOFF2 212 */ 213 214 /* PLL configuration register masks */ 215 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 216 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 217 218 /* Baud rate generator configuration register bits */ 219 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 220 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 221 222 /* Clock source register bits */ 223 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 224 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 225 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 226 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 227 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 228 229 /* Global commands */ 230 #define MAX310X_EXTREG_ENBL (0xce) 231 #define MAX310X_EXTREG_DSBL (0xcd) 232 233 /* Misc definitions */ 234 #define MAX310X_FIFO_SIZE (128) 235 #define MAX310x_REV_MASK (0xf8) 236 #define MAX310X_WRITE_BIT 0x80 237 238 /* MAX3107 specific */ 239 #define MAX3107_REV_ID (0xa0) 240 241 /* MAX3109 specific */ 242 #define MAX3109_REV_ID (0xc0) 243 244 /* MAX14830 specific */ 245 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 246 #define MAX14830_REV_ID (0xb0) 247 248 struct max310x_devtype { 249 char name[9]; 250 int nr; 251 u8 mode1; 252 int (*detect)(struct device *); 253 void (*power)(struct uart_port *, int); 254 }; 255 256 struct max310x_one { 257 struct uart_port port; 258 struct work_struct tx_work; 259 struct work_struct md_work; 260 struct work_struct rs_work; 261 }; 262 263 struct max310x_port { 264 struct max310x_devtype *devtype; 265 struct regmap *regmap; 266 struct mutex mutex; 267 struct clk *clk; 268 #ifdef CONFIG_GPIOLIB 269 struct gpio_chip gpio; 270 #endif 271 struct max310x_one p[0]; 272 }; 273 274 static struct uart_driver max310x_uart = { 275 .owner = THIS_MODULE, 276 .driver_name = MAX310X_NAME, 277 .dev_name = "ttyMAX", 278 .major = MAX310X_MAJOR, 279 .minor = MAX310X_MINOR, 280 .nr = MAX310X_UART_NRMAX, 281 }; 282 283 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 284 285 static u8 max310x_port_read(struct uart_port *port, u8 reg) 286 { 287 struct max310x_port *s = dev_get_drvdata(port->dev); 288 unsigned int val = 0; 289 290 regmap_read(s->regmap, port->iobase + reg, &val); 291 292 return val; 293 } 294 295 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 296 { 297 struct max310x_port *s = dev_get_drvdata(port->dev); 298 299 regmap_write(s->regmap, port->iobase + reg, val); 300 } 301 302 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 303 { 304 struct max310x_port *s = dev_get_drvdata(port->dev); 305 306 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); 307 } 308 309 static int max3107_detect(struct device *dev) 310 { 311 struct max310x_port *s = dev_get_drvdata(dev); 312 unsigned int val = 0; 313 int ret; 314 315 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 316 if (ret) 317 return ret; 318 319 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 320 dev_err(dev, 321 "%s ID 0x%02x does not match\n", s->devtype->name, val); 322 return -ENODEV; 323 } 324 325 return 0; 326 } 327 328 static int max3108_detect(struct device *dev) 329 { 330 struct max310x_port *s = dev_get_drvdata(dev); 331 unsigned int val = 0; 332 int ret; 333 334 /* MAX3108 have not REV ID register, we just check default value 335 * from clocksource register to make sure everything works. 336 */ 337 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 338 if (ret) 339 return ret; 340 341 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 342 dev_err(dev, "%s not present\n", s->devtype->name); 343 return -ENODEV; 344 } 345 346 return 0; 347 } 348 349 static int max3109_detect(struct device *dev) 350 { 351 struct max310x_port *s = dev_get_drvdata(dev); 352 unsigned int val = 0; 353 int ret; 354 355 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 356 MAX310X_EXTREG_ENBL); 357 if (ret) 358 return ret; 359 360 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 361 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 362 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 363 dev_err(dev, 364 "%s ID 0x%02x does not match\n", s->devtype->name, val); 365 return -ENODEV; 366 } 367 368 return 0; 369 } 370 371 static void max310x_power(struct uart_port *port, int on) 372 { 373 max310x_port_update(port, MAX310X_MODE1_REG, 374 MAX310X_MODE1_FORCESLEEP_BIT, 375 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 376 if (on) 377 msleep(50); 378 } 379 380 static int max14830_detect(struct device *dev) 381 { 382 struct max310x_port *s = dev_get_drvdata(dev); 383 unsigned int val = 0; 384 int ret; 385 386 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 387 MAX310X_EXTREG_ENBL); 388 if (ret) 389 return ret; 390 391 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 392 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 393 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 394 dev_err(dev, 395 "%s ID 0x%02x does not match\n", s->devtype->name, val); 396 return -ENODEV; 397 } 398 399 return 0; 400 } 401 402 static void max14830_power(struct uart_port *port, int on) 403 { 404 max310x_port_update(port, MAX310X_BRGCFG_REG, 405 MAX14830_BRGCFG_CLKDIS_BIT, 406 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 407 if (on) 408 msleep(50); 409 } 410 411 static const struct max310x_devtype max3107_devtype = { 412 .name = "MAX3107", 413 .nr = 1, 414 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 415 .detect = max3107_detect, 416 .power = max310x_power, 417 }; 418 419 static const struct max310x_devtype max3108_devtype = { 420 .name = "MAX3108", 421 .nr = 1, 422 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 423 .detect = max3108_detect, 424 .power = max310x_power, 425 }; 426 427 static const struct max310x_devtype max3109_devtype = { 428 .name = "MAX3109", 429 .nr = 2, 430 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 431 .detect = max3109_detect, 432 .power = max310x_power, 433 }; 434 435 static const struct max310x_devtype max14830_devtype = { 436 .name = "MAX14830", 437 .nr = 4, 438 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 439 .detect = max14830_detect, 440 .power = max14830_power, 441 }; 442 443 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 444 { 445 switch (reg & 0x1f) { 446 case MAX310X_IRQSTS_REG: 447 case MAX310X_LSR_IRQSTS_REG: 448 case MAX310X_SPCHR_IRQSTS_REG: 449 case MAX310X_STS_IRQSTS_REG: 450 case MAX310X_TXFIFOLVL_REG: 451 case MAX310X_RXFIFOLVL_REG: 452 return false; 453 default: 454 break; 455 } 456 457 return true; 458 } 459 460 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 461 { 462 switch (reg & 0x1f) { 463 case MAX310X_RHR_REG: 464 case MAX310X_IRQSTS_REG: 465 case MAX310X_LSR_IRQSTS_REG: 466 case MAX310X_SPCHR_IRQSTS_REG: 467 case MAX310X_STS_IRQSTS_REG: 468 case MAX310X_TXFIFOLVL_REG: 469 case MAX310X_RXFIFOLVL_REG: 470 case MAX310X_GPIODATA_REG: 471 case MAX310X_BRGDIVLSB_REG: 472 case MAX310X_REG_05: 473 case MAX310X_REG_1F: 474 return true; 475 default: 476 break; 477 } 478 479 return false; 480 } 481 482 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 483 { 484 switch (reg & 0x1f) { 485 case MAX310X_RHR_REG: 486 case MAX310X_IRQSTS_REG: 487 case MAX310X_SPCHR_IRQSTS_REG: 488 case MAX310X_STS_IRQSTS_REG: 489 return true; 490 default: 491 break; 492 } 493 494 return false; 495 } 496 497 static int max310x_set_baud(struct uart_port *port, int baud) 498 { 499 unsigned int mode = 0, clk = port->uartclk, div = clk / baud; 500 501 /* Check for minimal value for divider */ 502 if (div < 16) 503 div = 16; 504 505 if (clk % baud && (div / 16) < 0x8000) { 506 /* Mode x2 */ 507 mode = MAX310X_BRGCFG_2XMODE_BIT; 508 clk = port->uartclk * 2; 509 div = clk / baud; 510 511 if (clk % baud && (div / 16) < 0x8000) { 512 /* Mode x4 */ 513 mode = MAX310X_BRGCFG_4XMODE_BIT; 514 clk = port->uartclk * 4; 515 div = clk / baud; 516 } 517 } 518 519 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); 520 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); 521 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); 522 523 return DIV_ROUND_CLOSEST(clk, div); 524 } 525 526 static int max310x_update_best_err(unsigned long f, long *besterr) 527 { 528 /* Use baudrate 115200 for calculate error */ 529 long err = f % (115200 * 16); 530 531 if ((*besterr < 0) || (*besterr > err)) { 532 *besterr = err; 533 return 0; 534 } 535 536 return 1; 537 } 538 539 static int max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 540 unsigned long freq, bool xtal) 541 { 542 unsigned int div, clksrc, pllcfg = 0; 543 long besterr = -1; 544 unsigned long fdiv, fmul, bestfreq = freq; 545 546 /* First, update error without PLL */ 547 max310x_update_best_err(freq, &besterr); 548 549 /* Try all possible PLL dividers */ 550 for (div = 1; (div <= 63) && besterr; div++) { 551 fdiv = DIV_ROUND_CLOSEST(freq, div); 552 553 /* Try multiplier 6 */ 554 fmul = fdiv * 6; 555 if ((fdiv >= 500000) && (fdiv <= 800000)) 556 if (!max310x_update_best_err(fmul, &besterr)) { 557 pllcfg = (0 << 6) | div; 558 bestfreq = fmul; 559 } 560 /* Try multiplier 48 */ 561 fmul = fdiv * 48; 562 if ((fdiv >= 850000) && (fdiv <= 1200000)) 563 if (!max310x_update_best_err(fmul, &besterr)) { 564 pllcfg = (1 << 6) | div; 565 bestfreq = fmul; 566 } 567 /* Try multiplier 96 */ 568 fmul = fdiv * 96; 569 if ((fdiv >= 425000) && (fdiv <= 1000000)) 570 if (!max310x_update_best_err(fmul, &besterr)) { 571 pllcfg = (2 << 6) | div; 572 bestfreq = fmul; 573 } 574 /* Try multiplier 144 */ 575 fmul = fdiv * 144; 576 if ((fdiv >= 390000) && (fdiv <= 667000)) 577 if (!max310x_update_best_err(fmul, &besterr)) { 578 pllcfg = (3 << 6) | div; 579 bestfreq = fmul; 580 } 581 } 582 583 /* Configure clock source */ 584 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT; 585 586 /* Configure PLL */ 587 if (pllcfg) { 588 clksrc |= MAX310X_CLKSRC_PLL_BIT; 589 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 590 } else 591 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 592 593 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 594 595 /* Wait for crystal */ 596 if (xtal) { 597 unsigned int val; 598 msleep(10); 599 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 600 if (!(val & MAX310X_STS_CLKREADY_BIT)) { 601 dev_warn(dev, "clock is not stable yet\n"); 602 } 603 } 604 605 return (int)bestfreq; 606 } 607 608 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 609 { 610 u8 header[] = { (port->iobase + MAX310X_THR_REG) | MAX310X_WRITE_BIT }; 611 struct spi_transfer xfer[] = { 612 { 613 .tx_buf = &header, 614 .len = sizeof(header), 615 }, { 616 .tx_buf = txbuf, 617 .len = len, 618 } 619 }; 620 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); 621 } 622 623 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 624 { 625 u8 header[] = { port->iobase + MAX310X_RHR_REG }; 626 struct spi_transfer xfer[] = { 627 { 628 .tx_buf = &header, 629 .len = sizeof(header), 630 }, { 631 .rx_buf = rxbuf, 632 .len = len, 633 } 634 }; 635 spi_sync_transfer(to_spi_device(port->dev), xfer, ARRAY_SIZE(xfer)); 636 } 637 638 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 639 { 640 unsigned int sts, ch, flag, i; 641 u8 buf[MAX310X_FIFO_SIZE]; 642 643 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 644 /* We are just reading, happily ignoring any error conditions. 645 * Break condition, parity checking, framing errors -- they 646 * are all ignored. That means that we can do a batch-read. 647 * 648 * There is a small opportunity for race if the RX FIFO 649 * overruns while we're reading the buffer; the datasheets says 650 * that the LSR register applies to the "current" character. 651 * That's also the reason why we cannot do batched reads when 652 * asked to check the individual statuses. 653 * */ 654 655 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 656 max310x_batch_read(port, buf, rxlen); 657 658 port->icount.rx += rxlen; 659 flag = TTY_NORMAL; 660 sts &= port->read_status_mask; 661 662 if (sts & MAX310X_LSR_RXOVR_BIT) { 663 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 664 port->icount.overrun++; 665 } 666 667 for (i = 0; i < rxlen; ++i) { 668 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, buf[i], flag); 669 } 670 671 } else { 672 if (unlikely(rxlen >= port->fifosize)) { 673 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 674 port->icount.buf_overrun++; 675 /* Ensure sanity of RX level */ 676 rxlen = port->fifosize; 677 } 678 679 while (rxlen--) { 680 ch = max310x_port_read(port, MAX310X_RHR_REG); 681 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 682 683 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 684 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 685 686 port->icount.rx++; 687 flag = TTY_NORMAL; 688 689 if (unlikely(sts)) { 690 if (sts & MAX310X_LSR_RXBRK_BIT) { 691 port->icount.brk++; 692 if (uart_handle_break(port)) 693 continue; 694 } else if (sts & MAX310X_LSR_RXPAR_BIT) 695 port->icount.parity++; 696 else if (sts & MAX310X_LSR_FRERR_BIT) 697 port->icount.frame++; 698 else if (sts & MAX310X_LSR_RXOVR_BIT) 699 port->icount.overrun++; 700 701 sts &= port->read_status_mask; 702 if (sts & MAX310X_LSR_RXBRK_BIT) 703 flag = TTY_BREAK; 704 else if (sts & MAX310X_LSR_RXPAR_BIT) 705 flag = TTY_PARITY; 706 else if (sts & MAX310X_LSR_FRERR_BIT) 707 flag = TTY_FRAME; 708 else if (sts & MAX310X_LSR_RXOVR_BIT) 709 flag = TTY_OVERRUN; 710 } 711 712 if (uart_handle_sysrq_char(port, ch)) 713 continue; 714 715 if (sts & port->ignore_status_mask) 716 continue; 717 718 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 719 } 720 } 721 722 tty_flip_buffer_push(&port->state->port); 723 } 724 725 static void max310x_handle_tx(struct uart_port *port) 726 { 727 struct circ_buf *xmit = &port->state->xmit; 728 unsigned int txlen, to_send, until_end; 729 730 if (unlikely(port->x_char)) { 731 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 732 port->icount.tx++; 733 port->x_char = 0; 734 return; 735 } 736 737 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 738 return; 739 740 /* Get length of data pending in circular buffer */ 741 to_send = uart_circ_chars_pending(xmit); 742 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 743 if (likely(to_send)) { 744 /* Limit to size of TX FIFO */ 745 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 746 txlen = port->fifosize - txlen; 747 to_send = (to_send > txlen) ? txlen : to_send; 748 749 if (until_end < to_send) { 750 /* It's a circ buffer -- wrap around. 751 * We could do that in one SPI transaction, but meh. */ 752 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 753 max310x_batch_write(port, xmit->buf, to_send - until_end); 754 } else { 755 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 756 } 757 758 /* Add data to send */ 759 port->icount.tx += to_send; 760 xmit->tail = (xmit->tail + to_send) & (UART_XMIT_SIZE - 1); 761 } 762 763 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 764 uart_write_wakeup(port); 765 } 766 767 static void max310x_start_tx(struct uart_port *port) 768 { 769 struct max310x_one *one = container_of(port, struct max310x_one, port); 770 771 if (!work_pending(&one->tx_work)) 772 schedule_work(&one->tx_work); 773 } 774 775 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 776 { 777 struct uart_port *port = &s->p[portno].port; 778 irqreturn_t res = IRQ_NONE; 779 780 do { 781 unsigned int ists, lsr, rxlen; 782 783 /* Read IRQ status & RX FIFO level */ 784 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 785 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 786 if (!ists && !rxlen) 787 break; 788 789 res = IRQ_HANDLED; 790 791 if (ists & MAX310X_IRQ_CTS_BIT) { 792 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 793 uart_handle_cts_change(port, 794 !!(lsr & MAX310X_LSR_CTS_BIT)); 795 } 796 if (rxlen) 797 max310x_handle_rx(port, rxlen); 798 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 799 max310x_start_tx(port); 800 } while (1); 801 return res; 802 } 803 804 static irqreturn_t max310x_ist(int irq, void *dev_id) 805 { 806 struct max310x_port *s = (struct max310x_port *)dev_id; 807 bool handled = false; 808 809 if (s->devtype->nr > 1) { 810 do { 811 unsigned int val = ~0; 812 813 WARN_ON_ONCE(regmap_read(s->regmap, 814 MAX310X_GLOBALIRQ_REG, &val)); 815 val = ((1 << s->devtype->nr) - 1) & ~val; 816 if (!val) 817 break; 818 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 819 handled = true; 820 } while (1); 821 } else { 822 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 823 handled = true; 824 } 825 826 return IRQ_RETVAL(handled); 827 } 828 829 static void max310x_wq_proc(struct work_struct *ws) 830 { 831 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 832 struct max310x_port *s = dev_get_drvdata(one->port.dev); 833 834 mutex_lock(&s->mutex); 835 max310x_handle_tx(&one->port); 836 mutex_unlock(&s->mutex); 837 } 838 839 static unsigned int max310x_tx_empty(struct uart_port *port) 840 { 841 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 842 843 return lvl ? 0 : TIOCSER_TEMT; 844 } 845 846 static unsigned int max310x_get_mctrl(struct uart_port *port) 847 { 848 /* DCD and DSR are not wired and CTS/RTS is handled automatically 849 * so just indicate DSR and CAR asserted 850 */ 851 return TIOCM_DSR | TIOCM_CAR; 852 } 853 854 static void max310x_md_proc(struct work_struct *ws) 855 { 856 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 857 858 max310x_port_update(&one->port, MAX310X_MODE2_REG, 859 MAX310X_MODE2_LOOPBACK_BIT, 860 (one->port.mctrl & TIOCM_LOOP) ? 861 MAX310X_MODE2_LOOPBACK_BIT : 0); 862 } 863 864 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 865 { 866 struct max310x_one *one = container_of(port, struct max310x_one, port); 867 868 schedule_work(&one->md_work); 869 } 870 871 static void max310x_break_ctl(struct uart_port *port, int break_state) 872 { 873 max310x_port_update(port, MAX310X_LCR_REG, 874 MAX310X_LCR_TXBREAK_BIT, 875 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 876 } 877 878 static void max310x_set_termios(struct uart_port *port, 879 struct ktermios *termios, 880 struct ktermios *old) 881 { 882 unsigned int lcr = 0, flow = 0; 883 int baud; 884 885 /* Mask termios capabilities we don't support */ 886 termios->c_cflag &= ~CMSPAR; 887 888 /* Word size */ 889 switch (termios->c_cflag & CSIZE) { 890 case CS5: 891 break; 892 case CS6: 893 lcr = MAX310X_LCR_LENGTH0_BIT; 894 break; 895 case CS7: 896 lcr = MAX310X_LCR_LENGTH1_BIT; 897 break; 898 case CS8: 899 default: 900 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 901 break; 902 } 903 904 /* Parity */ 905 if (termios->c_cflag & PARENB) { 906 lcr |= MAX310X_LCR_PARITY_BIT; 907 if (!(termios->c_cflag & PARODD)) 908 lcr |= MAX310X_LCR_EVENPARITY_BIT; 909 } 910 911 /* Stop bits */ 912 if (termios->c_cflag & CSTOPB) 913 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 914 915 /* Update LCR register */ 916 max310x_port_write(port, MAX310X_LCR_REG, lcr); 917 918 /* Set read status mask */ 919 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 920 if (termios->c_iflag & INPCK) 921 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 922 MAX310X_LSR_FRERR_BIT; 923 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 924 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 925 926 /* Set status ignore mask */ 927 port->ignore_status_mask = 0; 928 if (termios->c_iflag & IGNBRK) 929 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 930 if (!(termios->c_cflag & CREAD)) 931 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 932 MAX310X_LSR_RXOVR_BIT | 933 MAX310X_LSR_FRERR_BIT | 934 MAX310X_LSR_RXBRK_BIT; 935 936 /* Configure flow control */ 937 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 938 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 939 if (termios->c_cflag & CRTSCTS) 940 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 941 MAX310X_FLOWCTRL_AUTORTS_BIT; 942 if (termios->c_iflag & IXON) 943 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 944 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 945 if (termios->c_iflag & IXOFF) 946 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 947 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 948 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 949 950 /* Get baud rate generator configuration */ 951 baud = uart_get_baud_rate(port, termios, old, 952 port->uartclk / 16 / 0xffff, 953 port->uartclk / 4); 954 955 /* Setup baudrate generator */ 956 baud = max310x_set_baud(port, baud); 957 958 /* Update timeout according to new baud rate */ 959 uart_update_timeout(port, termios->c_cflag, baud); 960 } 961 962 static void max310x_rs_proc(struct work_struct *ws) 963 { 964 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 965 unsigned int val; 966 967 val = (one->port.rs485.delay_rts_before_send << 4) | 968 one->port.rs485.delay_rts_after_send; 969 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val); 970 971 if (one->port.rs485.flags & SER_RS485_ENABLED) { 972 max310x_port_update(&one->port, MAX310X_MODE1_REG, 973 MAX310X_MODE1_TRNSCVCTRL_BIT, 974 MAX310X_MODE1_TRNSCVCTRL_BIT); 975 max310x_port_update(&one->port, MAX310X_MODE2_REG, 976 MAX310X_MODE2_ECHOSUPR_BIT, 977 MAX310X_MODE2_ECHOSUPR_BIT); 978 } else { 979 max310x_port_update(&one->port, MAX310X_MODE1_REG, 980 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 981 max310x_port_update(&one->port, MAX310X_MODE2_REG, 982 MAX310X_MODE2_ECHOSUPR_BIT, 0); 983 } 984 } 985 986 static int max310x_rs485_config(struct uart_port *port, 987 struct serial_rs485 *rs485) 988 { 989 struct max310x_one *one = container_of(port, struct max310x_one, port); 990 991 if ((rs485->delay_rts_before_send > 0x0f) || 992 (rs485->delay_rts_after_send > 0x0f)) 993 return -ERANGE; 994 995 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED; 996 memset(rs485->padding, 0, sizeof(rs485->padding)); 997 port->rs485 = *rs485; 998 999 schedule_work(&one->rs_work); 1000 1001 return 0; 1002 } 1003 1004 static int max310x_startup(struct uart_port *port) 1005 { 1006 struct max310x_port *s = dev_get_drvdata(port->dev); 1007 unsigned int val; 1008 1009 s->devtype->power(port, 1); 1010 1011 /* Configure MODE1 register */ 1012 max310x_port_update(port, MAX310X_MODE1_REG, 1013 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1014 1015 /* Configure MODE2 register & Reset FIFOs*/ 1016 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1017 max310x_port_write(port, MAX310X_MODE2_REG, val); 1018 max310x_port_update(port, MAX310X_MODE2_REG, 1019 MAX310X_MODE2_FIFORST_BIT, 0); 1020 1021 /* Configure flow control levels */ 1022 /* Flow control halt level 96, resume level 48 */ 1023 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1024 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1025 1026 /* Clear IRQ status register */ 1027 max310x_port_read(port, MAX310X_IRQSTS_REG); 1028 1029 /* Enable RX, TX, CTS change interrupts */ 1030 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1031 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1032 1033 return 0; 1034 } 1035 1036 static void max310x_shutdown(struct uart_port *port) 1037 { 1038 struct max310x_port *s = dev_get_drvdata(port->dev); 1039 1040 /* Disable all interrupts */ 1041 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1042 1043 s->devtype->power(port, 0); 1044 } 1045 1046 static const char *max310x_type(struct uart_port *port) 1047 { 1048 struct max310x_port *s = dev_get_drvdata(port->dev); 1049 1050 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1051 } 1052 1053 static int max310x_request_port(struct uart_port *port) 1054 { 1055 /* Do nothing */ 1056 return 0; 1057 } 1058 1059 static void max310x_config_port(struct uart_port *port, int flags) 1060 { 1061 if (flags & UART_CONFIG_TYPE) 1062 port->type = PORT_MAX310X; 1063 } 1064 1065 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1066 { 1067 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1068 return -EINVAL; 1069 if (s->irq != port->irq) 1070 return -EINVAL; 1071 1072 return 0; 1073 } 1074 1075 static void max310x_null_void(struct uart_port *port) 1076 { 1077 /* Do nothing */ 1078 } 1079 1080 static const struct uart_ops max310x_ops = { 1081 .tx_empty = max310x_tx_empty, 1082 .set_mctrl = max310x_set_mctrl, 1083 .get_mctrl = max310x_get_mctrl, 1084 .stop_tx = max310x_null_void, 1085 .start_tx = max310x_start_tx, 1086 .stop_rx = max310x_null_void, 1087 .break_ctl = max310x_break_ctl, 1088 .startup = max310x_startup, 1089 .shutdown = max310x_shutdown, 1090 .set_termios = max310x_set_termios, 1091 .type = max310x_type, 1092 .request_port = max310x_request_port, 1093 .release_port = max310x_null_void, 1094 .config_port = max310x_config_port, 1095 .verify_port = max310x_verify_port, 1096 }; 1097 1098 static int __maybe_unused max310x_suspend(struct device *dev) 1099 { 1100 struct max310x_port *s = dev_get_drvdata(dev); 1101 int i; 1102 1103 for (i = 0; i < s->devtype->nr; i++) { 1104 uart_suspend_port(&max310x_uart, &s->p[i].port); 1105 s->devtype->power(&s->p[i].port, 0); 1106 } 1107 1108 return 0; 1109 } 1110 1111 static int __maybe_unused max310x_resume(struct device *dev) 1112 { 1113 struct max310x_port *s = dev_get_drvdata(dev); 1114 int i; 1115 1116 for (i = 0; i < s->devtype->nr; i++) { 1117 s->devtype->power(&s->p[i].port, 1); 1118 uart_resume_port(&max310x_uart, &s->p[i].port); 1119 } 1120 1121 return 0; 1122 } 1123 1124 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1125 1126 #ifdef CONFIG_GPIOLIB 1127 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1128 { 1129 unsigned int val; 1130 struct max310x_port *s = gpiochip_get_data(chip); 1131 struct uart_port *port = &s->p[offset / 4].port; 1132 1133 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1134 1135 return !!((val >> 4) & (1 << (offset % 4))); 1136 } 1137 1138 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1139 { 1140 struct max310x_port *s = gpiochip_get_data(chip); 1141 struct uart_port *port = &s->p[offset / 4].port; 1142 1143 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1144 value ? 1 << (offset % 4) : 0); 1145 } 1146 1147 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1148 { 1149 struct max310x_port *s = gpiochip_get_data(chip); 1150 struct uart_port *port = &s->p[offset / 4].port; 1151 1152 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1153 1154 return 0; 1155 } 1156 1157 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1158 unsigned offset, int value) 1159 { 1160 struct max310x_port *s = gpiochip_get_data(chip); 1161 struct uart_port *port = &s->p[offset / 4].port; 1162 1163 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1164 value ? 1 << (offset % 4) : 0); 1165 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1166 1 << (offset % 4)); 1167 1168 return 0; 1169 } 1170 1171 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1172 unsigned long config) 1173 { 1174 struct max310x_port *s = gpiochip_get_data(chip); 1175 struct uart_port *port = &s->p[offset / 4].port; 1176 1177 switch (pinconf_to_config_param(config)) { 1178 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1179 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1180 1 << ((offset % 4) + 4), 1181 1 << ((offset % 4) + 4)); 1182 return 0; 1183 case PIN_CONFIG_DRIVE_PUSH_PULL: 1184 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1185 1 << ((offset % 4) + 4), 0); 1186 return 0; 1187 default: 1188 return -ENOTSUPP; 1189 } 1190 } 1191 #endif 1192 1193 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, 1194 struct regmap *regmap, int irq) 1195 { 1196 int i, ret, fmin, fmax, freq, uartclk; 1197 struct clk *clk_osc, *clk_xtal; 1198 struct max310x_port *s; 1199 bool xtal = false; 1200 1201 if (IS_ERR(regmap)) 1202 return PTR_ERR(regmap); 1203 1204 /* Alloc port structure */ 1205 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1206 if (!s) { 1207 dev_err(dev, "Error allocating port structure\n"); 1208 return -ENOMEM; 1209 } 1210 1211 clk_osc = devm_clk_get(dev, "osc"); 1212 clk_xtal = devm_clk_get(dev, "xtal"); 1213 if (!IS_ERR(clk_osc)) { 1214 s->clk = clk_osc; 1215 fmin = 500000; 1216 fmax = 35000000; 1217 } else if (!IS_ERR(clk_xtal)) { 1218 s->clk = clk_xtal; 1219 fmin = 1000000; 1220 fmax = 4000000; 1221 xtal = true; 1222 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || 1223 PTR_ERR(clk_xtal) == -EPROBE_DEFER) { 1224 return -EPROBE_DEFER; 1225 } else { 1226 dev_err(dev, "Cannot get clock\n"); 1227 return -EINVAL; 1228 } 1229 1230 ret = clk_prepare_enable(s->clk); 1231 if (ret) 1232 return ret; 1233 1234 freq = clk_get_rate(s->clk); 1235 /* Check frequency limits */ 1236 if (freq < fmin || freq > fmax) { 1237 ret = -ERANGE; 1238 goto out_clk; 1239 } 1240 1241 s->regmap = regmap; 1242 s->devtype = devtype; 1243 dev_set_drvdata(dev, s); 1244 1245 /* Check device to ensure we are talking to what we expect */ 1246 ret = devtype->detect(dev); 1247 if (ret) 1248 goto out_clk; 1249 1250 for (i = 0; i < devtype->nr; i++) { 1251 unsigned int offs = i << 5; 1252 1253 /* Reset port */ 1254 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 1255 MAX310X_MODE2_RST_BIT); 1256 /* Clear port reset */ 1257 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); 1258 1259 /* Wait for port startup */ 1260 do { 1261 regmap_read(s->regmap, 1262 MAX310X_BRGDIVLSB_REG + offs, &ret); 1263 } while (ret != 0x01); 1264 1265 regmap_write(s->regmap, MAX310X_MODE1_REG + offs, 1266 devtype->mode1); 1267 } 1268 1269 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1270 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1271 1272 mutex_init(&s->mutex); 1273 1274 for (i = 0; i < devtype->nr; i++) { 1275 unsigned int line; 1276 1277 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1278 if (line == MAX310X_UART_NRMAX) { 1279 ret = -ERANGE; 1280 goto out_uart; 1281 } 1282 1283 /* Initialize port data */ 1284 s->p[i].port.line = line; 1285 s->p[i].port.dev = dev; 1286 s->p[i].port.irq = irq; 1287 s->p[i].port.type = PORT_MAX310X; 1288 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1289 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1290 s->p[i].port.iotype = UPIO_PORT; 1291 s->p[i].port.iobase = i * 0x20; 1292 s->p[i].port.membase = (void __iomem *)~0; 1293 s->p[i].port.uartclk = uartclk; 1294 s->p[i].port.rs485_config = max310x_rs485_config; 1295 s->p[i].port.ops = &max310x_ops; 1296 /* Disable all interrupts */ 1297 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1298 /* Clear IRQ status register */ 1299 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1300 /* Initialize queue for start TX */ 1301 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc); 1302 /* Initialize queue for changing LOOPBACK mode */ 1303 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1304 /* Initialize queue for changing RS485 mode */ 1305 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1306 1307 /* Register port */ 1308 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1309 if (ret) { 1310 s->p[i].port.dev = NULL; 1311 goto out_uart; 1312 } 1313 set_bit(line, max310x_lines); 1314 1315 /* Go to suspend mode */ 1316 devtype->power(&s->p[i].port, 0); 1317 } 1318 1319 #ifdef CONFIG_GPIOLIB 1320 /* Setup GPIO cotroller */ 1321 s->gpio.owner = THIS_MODULE; 1322 s->gpio.parent = dev; 1323 s->gpio.label = devtype->name; 1324 s->gpio.direction_input = max310x_gpio_direction_input; 1325 s->gpio.get = max310x_gpio_get; 1326 s->gpio.direction_output= max310x_gpio_direction_output; 1327 s->gpio.set = max310x_gpio_set; 1328 s->gpio.set_config = max310x_gpio_set_config; 1329 s->gpio.base = -1; 1330 s->gpio.ngpio = devtype->nr * 4; 1331 s->gpio.can_sleep = 1; 1332 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1333 if (ret) 1334 goto out_uart; 1335 #endif 1336 1337 /* Setup interrupt */ 1338 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1339 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1340 if (!ret) 1341 return 0; 1342 1343 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1344 1345 out_uart: 1346 for (i = 0; i < devtype->nr; i++) { 1347 if (s->p[i].port.dev) { 1348 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1349 clear_bit(s->p[i].port.line, max310x_lines); 1350 } 1351 } 1352 1353 mutex_destroy(&s->mutex); 1354 1355 out_clk: 1356 clk_disable_unprepare(s->clk); 1357 1358 return ret; 1359 } 1360 1361 static int max310x_remove(struct device *dev) 1362 { 1363 struct max310x_port *s = dev_get_drvdata(dev); 1364 int i; 1365 1366 for (i = 0; i < s->devtype->nr; i++) { 1367 cancel_work_sync(&s->p[i].tx_work); 1368 cancel_work_sync(&s->p[i].md_work); 1369 cancel_work_sync(&s->p[i].rs_work); 1370 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1371 clear_bit(s->p[i].port.line, max310x_lines); 1372 s->devtype->power(&s->p[i].port, 0); 1373 } 1374 1375 mutex_destroy(&s->mutex); 1376 clk_disable_unprepare(s->clk); 1377 1378 return 0; 1379 } 1380 1381 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1382 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1383 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1384 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1385 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1386 { } 1387 }; 1388 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1389 1390 static struct regmap_config regcfg = { 1391 .reg_bits = 8, 1392 .val_bits = 8, 1393 .write_flag_mask = MAX310X_WRITE_BIT, 1394 .cache_type = REGCACHE_RBTREE, 1395 .writeable_reg = max310x_reg_writeable, 1396 .volatile_reg = max310x_reg_volatile, 1397 .precious_reg = max310x_reg_precious, 1398 }; 1399 1400 #ifdef CONFIG_SPI_MASTER 1401 static int max310x_spi_probe(struct spi_device *spi) 1402 { 1403 struct max310x_devtype *devtype; 1404 struct regmap *regmap; 1405 int ret; 1406 1407 /* Setup SPI bus */ 1408 spi->bits_per_word = 8; 1409 spi->mode = spi->mode ? : SPI_MODE_0; 1410 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1411 ret = spi_setup(spi); 1412 if (ret) 1413 return ret; 1414 1415 if (spi->dev.of_node) { 1416 const struct of_device_id *of_id = 1417 of_match_device(max310x_dt_ids, &spi->dev); 1418 if (!of_id) 1419 return -ENODEV; 1420 1421 devtype = (struct max310x_devtype *)of_id->data; 1422 } else { 1423 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1424 1425 devtype = (struct max310x_devtype *)id_entry->driver_data; 1426 } 1427 1428 regcfg.max_register = devtype->nr * 0x20 - 1; 1429 regmap = devm_regmap_init_spi(spi, ®cfg); 1430 1431 return max310x_probe(&spi->dev, devtype, regmap, spi->irq); 1432 } 1433 1434 static int max310x_spi_remove(struct spi_device *spi) 1435 { 1436 return max310x_remove(&spi->dev); 1437 } 1438 1439 static const struct spi_device_id max310x_id_table[] = { 1440 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1441 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1442 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1443 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1444 { } 1445 }; 1446 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1447 1448 static struct spi_driver max310x_spi_driver = { 1449 .driver = { 1450 .name = MAX310X_NAME, 1451 .of_match_table = of_match_ptr(max310x_dt_ids), 1452 .pm = &max310x_pm_ops, 1453 }, 1454 .probe = max310x_spi_probe, 1455 .remove = max310x_spi_remove, 1456 .id_table = max310x_id_table, 1457 }; 1458 #endif 1459 1460 static int __init max310x_uart_init(void) 1461 { 1462 int ret; 1463 1464 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1465 1466 ret = uart_register_driver(&max310x_uart); 1467 if (ret) 1468 return ret; 1469 1470 #ifdef CONFIG_SPI_MASTER 1471 ret = spi_register_driver(&max310x_spi_driver); 1472 #endif 1473 1474 return ret; 1475 } 1476 module_init(max310x_uart_init); 1477 1478 static void __exit max310x_uart_exit(void) 1479 { 1480 #ifdef CONFIG_SPI_MASTER 1481 spi_unregister_driver(&max310x_spi_driver); 1482 #endif 1483 1484 uart_unregister_driver(&max310x_uart); 1485 } 1486 module_exit(max310x_uart_exit); 1487 1488 MODULE_LICENSE("GPL"); 1489 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1490 MODULE_DESCRIPTION("MAX310X serial driver"); 1491