1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/regmap.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial.h> 23 #include <linux/tty.h> 24 #include <linux/tty_flip.h> 25 #include <linux/spi/spi.h> 26 #include <linux/uaccess.h> 27 28 #define MAX310X_NAME "max310x" 29 #define MAX310X_MAJOR 204 30 #define MAX310X_MINOR 209 31 #define MAX310X_UART_NRMAX 16 32 33 /* MAX310X register definitions */ 34 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 35 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 36 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 37 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 38 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 39 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 40 #define MAX310X_REG_05 (0x05) 41 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 42 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 43 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 44 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 45 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 46 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 47 #define MAX310X_LCR_REG (0x0b) /* LCR */ 48 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 49 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 50 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 51 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 52 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 53 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 54 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 55 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 56 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 57 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 58 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 59 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 60 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 61 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 62 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 63 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 64 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 65 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 66 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 67 #define MAX310X_REG_1F (0x1f) 68 69 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 70 71 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 72 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 73 74 /* Extended registers */ 75 #define MAX310X_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 76 77 /* IRQ register bits */ 78 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 79 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 80 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 81 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 82 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 83 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 84 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 85 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 86 87 /* LSR register bits */ 88 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 89 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 90 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 91 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 92 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 93 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 94 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 95 96 /* Special character register bits */ 97 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 98 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 99 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 100 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 101 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 102 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 103 104 /* Status register bits */ 105 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 106 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 107 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 108 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 109 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 110 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 111 112 /* MODE1 register bits */ 113 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 114 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 115 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 116 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 117 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 118 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 119 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 120 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 121 122 /* MODE2 register bits */ 123 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 124 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 125 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 126 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 127 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 128 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 129 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 130 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 131 132 /* LCR register bits */ 133 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 134 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 135 * 136 * Word length bits table: 137 * 00 -> 5 bit words 138 * 01 -> 6 bit words 139 * 10 -> 7 bit words 140 * 11 -> 8 bit words 141 */ 142 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 143 * 144 * STOP length bit table: 145 * 0 -> 1 stop bit 146 * 1 -> 1-1.5 stop bits if 147 * word length is 5, 148 * 2 stop bits otherwise 149 */ 150 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 151 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 152 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 153 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 154 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 155 156 /* IRDA register bits */ 157 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 158 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 159 160 /* Flow control trigger level register masks */ 161 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 162 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 163 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 164 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 165 166 /* FIFO interrupt trigger level register masks */ 167 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 168 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 169 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 170 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 171 172 /* Flow control register bits */ 173 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 174 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 175 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 176 * are used in conjunction with 177 * XOFF2 for definition of 178 * special character */ 179 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 180 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 181 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 182 * 183 * SWFLOW bits 1 & 0 table: 184 * 00 -> no transmitter flow 185 * control 186 * 01 -> receiver compares 187 * XON2 and XOFF2 188 * and controls 189 * transmitter 190 * 10 -> receiver compares 191 * XON1 and XOFF1 192 * and controls 193 * transmitter 194 * 11 -> receiver compares 195 * XON1, XON2, XOFF1 and 196 * XOFF2 and controls 197 * transmitter 198 */ 199 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 200 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 201 * 202 * SWFLOW bits 3 & 2 table: 203 * 00 -> no received flow 204 * control 205 * 01 -> transmitter generates 206 * XON2 and XOFF2 207 * 10 -> transmitter generates 208 * XON1 and XOFF1 209 * 11 -> transmitter generates 210 * XON1, XON2, XOFF1 and 211 * XOFF2 212 */ 213 214 /* PLL configuration register masks */ 215 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 216 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 217 218 /* Baud rate generator configuration register bits */ 219 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 220 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 221 222 /* Clock source register bits */ 223 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 224 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 225 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 226 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 227 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 228 229 /* Global commands */ 230 #define MAX310X_EXTREG_ENBL (0xce) 231 #define MAX310X_EXTREG_DSBL (0xcd) 232 233 /* Misc definitions */ 234 #define MAX310X_FIFO_SIZE (128) 235 #define MAX310x_REV_MASK (0xf8) 236 237 /* MAX3107 specific */ 238 #define MAX3107_REV_ID (0xa0) 239 240 /* MAX3109 specific */ 241 #define MAX3109_REV_ID (0xc0) 242 243 /* MAX14830 specific */ 244 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 245 #define MAX14830_REV_ID (0xb0) 246 247 struct max310x_devtype { 248 char name[9]; 249 int nr; 250 int (*detect)(struct device *); 251 void (*power)(struct uart_port *, int); 252 }; 253 254 struct max310x_one { 255 struct uart_port port; 256 struct work_struct tx_work; 257 struct work_struct md_work; 258 struct work_struct rs_work; 259 }; 260 261 struct max310x_port { 262 struct max310x_devtype *devtype; 263 struct regmap *regmap; 264 struct mutex mutex; 265 struct clk *clk; 266 #ifdef CONFIG_GPIOLIB 267 struct gpio_chip gpio; 268 #endif 269 struct max310x_one p[0]; 270 }; 271 272 static struct uart_driver max310x_uart = { 273 .owner = THIS_MODULE, 274 .driver_name = MAX310X_NAME, 275 .dev_name = "ttyMAX", 276 .major = MAX310X_MAJOR, 277 .minor = MAX310X_MINOR, 278 .nr = MAX310X_UART_NRMAX, 279 }; 280 281 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 282 283 static u8 max310x_port_read(struct uart_port *port, u8 reg) 284 { 285 struct max310x_port *s = dev_get_drvdata(port->dev); 286 unsigned int val = 0; 287 288 regmap_read(s->regmap, port->iobase + reg, &val); 289 290 return val; 291 } 292 293 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 294 { 295 struct max310x_port *s = dev_get_drvdata(port->dev); 296 297 regmap_write(s->regmap, port->iobase + reg, val); 298 } 299 300 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 301 { 302 struct max310x_port *s = dev_get_drvdata(port->dev); 303 304 regmap_update_bits(s->regmap, port->iobase + reg, mask, val); 305 } 306 307 static int max3107_detect(struct device *dev) 308 { 309 struct max310x_port *s = dev_get_drvdata(dev); 310 unsigned int val = 0; 311 int ret; 312 313 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 314 if (ret) 315 return ret; 316 317 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 318 dev_err(dev, 319 "%s ID 0x%02x does not match\n", s->devtype->name, val); 320 return -ENODEV; 321 } 322 323 return 0; 324 } 325 326 static int max3108_detect(struct device *dev) 327 { 328 struct max310x_port *s = dev_get_drvdata(dev); 329 unsigned int val = 0; 330 int ret; 331 332 /* MAX3108 have not REV ID register, we just check default value 333 * from clocksource register to make sure everything works. 334 */ 335 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 336 if (ret) 337 return ret; 338 339 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 340 dev_err(dev, "%s not present\n", s->devtype->name); 341 return -ENODEV; 342 } 343 344 return 0; 345 } 346 347 static int max3109_detect(struct device *dev) 348 { 349 struct max310x_port *s = dev_get_drvdata(dev); 350 unsigned int val = 0; 351 int ret; 352 353 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 354 MAX310X_EXTREG_ENBL); 355 if (ret) 356 return ret; 357 358 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 359 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 360 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 361 dev_err(dev, 362 "%s ID 0x%02x does not match\n", s->devtype->name, val); 363 return -ENODEV; 364 } 365 366 return 0; 367 } 368 369 static void max310x_power(struct uart_port *port, int on) 370 { 371 max310x_port_update(port, MAX310X_MODE1_REG, 372 MAX310X_MODE1_FORCESLEEP_BIT, 373 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 374 if (on) 375 msleep(50); 376 } 377 378 static int max14830_detect(struct device *dev) 379 { 380 struct max310x_port *s = dev_get_drvdata(dev); 381 unsigned int val = 0; 382 int ret; 383 384 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 385 MAX310X_EXTREG_ENBL); 386 if (ret) 387 return ret; 388 389 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val); 390 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL); 391 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 392 dev_err(dev, 393 "%s ID 0x%02x does not match\n", s->devtype->name, val); 394 return -ENODEV; 395 } 396 397 return 0; 398 } 399 400 static void max14830_power(struct uart_port *port, int on) 401 { 402 max310x_port_update(port, MAX310X_BRGCFG_REG, 403 MAX14830_BRGCFG_CLKDIS_BIT, 404 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 405 if (on) 406 msleep(50); 407 } 408 409 static const struct max310x_devtype max3107_devtype = { 410 .name = "MAX3107", 411 .nr = 1, 412 .detect = max3107_detect, 413 .power = max310x_power, 414 }; 415 416 static const struct max310x_devtype max3108_devtype = { 417 .name = "MAX3108", 418 .nr = 1, 419 .detect = max3108_detect, 420 .power = max310x_power, 421 }; 422 423 static const struct max310x_devtype max3109_devtype = { 424 .name = "MAX3109", 425 .nr = 2, 426 .detect = max3109_detect, 427 .power = max310x_power, 428 }; 429 430 static const struct max310x_devtype max14830_devtype = { 431 .name = "MAX14830", 432 .nr = 4, 433 .detect = max14830_detect, 434 .power = max14830_power, 435 }; 436 437 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 438 { 439 switch (reg & 0x1f) { 440 case MAX310X_IRQSTS_REG: 441 case MAX310X_LSR_IRQSTS_REG: 442 case MAX310X_SPCHR_IRQSTS_REG: 443 case MAX310X_STS_IRQSTS_REG: 444 case MAX310X_TXFIFOLVL_REG: 445 case MAX310X_RXFIFOLVL_REG: 446 return false; 447 default: 448 break; 449 } 450 451 return true; 452 } 453 454 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 455 { 456 switch (reg & 0x1f) { 457 case MAX310X_RHR_REG: 458 case MAX310X_IRQSTS_REG: 459 case MAX310X_LSR_IRQSTS_REG: 460 case MAX310X_SPCHR_IRQSTS_REG: 461 case MAX310X_STS_IRQSTS_REG: 462 case MAX310X_TXFIFOLVL_REG: 463 case MAX310X_RXFIFOLVL_REG: 464 case MAX310X_GPIODATA_REG: 465 case MAX310X_BRGDIVLSB_REG: 466 case MAX310X_REG_05: 467 case MAX310X_REG_1F: 468 return true; 469 default: 470 break; 471 } 472 473 return false; 474 } 475 476 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 477 { 478 switch (reg & 0x1f) { 479 case MAX310X_RHR_REG: 480 case MAX310X_IRQSTS_REG: 481 case MAX310X_SPCHR_IRQSTS_REG: 482 case MAX310X_STS_IRQSTS_REG: 483 return true; 484 default: 485 break; 486 } 487 488 return false; 489 } 490 491 static int max310x_set_baud(struct uart_port *port, int baud) 492 { 493 unsigned int mode = 0, clk = port->uartclk, div = clk / baud; 494 495 /* Check for minimal value for divider */ 496 if (div < 16) 497 div = 16; 498 499 if (clk % baud && (div / 16) < 0x8000) { 500 /* Mode x2 */ 501 mode = MAX310X_BRGCFG_2XMODE_BIT; 502 clk = port->uartclk * 2; 503 div = clk / baud; 504 505 if (clk % baud && (div / 16) < 0x8000) { 506 /* Mode x4 */ 507 mode = MAX310X_BRGCFG_4XMODE_BIT; 508 clk = port->uartclk * 4; 509 div = clk / baud; 510 } 511 } 512 513 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8); 514 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16); 515 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode); 516 517 return DIV_ROUND_CLOSEST(clk, div); 518 } 519 520 static int max310x_update_best_err(unsigned long f, long *besterr) 521 { 522 /* Use baudrate 115200 for calculate error */ 523 long err = f % (115200 * 16); 524 525 if ((*besterr < 0) || (*besterr > err)) { 526 *besterr = err; 527 return 0; 528 } 529 530 return 1; 531 } 532 533 static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq, 534 bool xtal) 535 { 536 unsigned int div, clksrc, pllcfg = 0; 537 long besterr = -1; 538 unsigned long fdiv, fmul, bestfreq = freq; 539 540 /* First, update error without PLL */ 541 max310x_update_best_err(freq, &besterr); 542 543 /* Try all possible PLL dividers */ 544 for (div = 1; (div <= 63) && besterr; div++) { 545 fdiv = DIV_ROUND_CLOSEST(freq, div); 546 547 /* Try multiplier 6 */ 548 fmul = fdiv * 6; 549 if ((fdiv >= 500000) && (fdiv <= 800000)) 550 if (!max310x_update_best_err(fmul, &besterr)) { 551 pllcfg = (0 << 6) | div; 552 bestfreq = fmul; 553 } 554 /* Try multiplier 48 */ 555 fmul = fdiv * 48; 556 if ((fdiv >= 850000) && (fdiv <= 1200000)) 557 if (!max310x_update_best_err(fmul, &besterr)) { 558 pllcfg = (1 << 6) | div; 559 bestfreq = fmul; 560 } 561 /* Try multiplier 96 */ 562 fmul = fdiv * 96; 563 if ((fdiv >= 425000) && (fdiv <= 1000000)) 564 if (!max310x_update_best_err(fmul, &besterr)) { 565 pllcfg = (2 << 6) | div; 566 bestfreq = fmul; 567 } 568 /* Try multiplier 144 */ 569 fmul = fdiv * 144; 570 if ((fdiv >= 390000) && (fdiv <= 667000)) 571 if (!max310x_update_best_err(fmul, &besterr)) { 572 pllcfg = (3 << 6) | div; 573 bestfreq = fmul; 574 } 575 } 576 577 /* Configure clock source */ 578 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT; 579 580 /* Configure PLL */ 581 if (pllcfg) { 582 clksrc |= MAX310X_CLKSRC_PLL_BIT; 583 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 584 } else 585 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 586 587 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 588 589 /* Wait for crystal */ 590 if (pllcfg && xtal) 591 msleep(10); 592 593 return (int)bestfreq; 594 } 595 596 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 597 { 598 unsigned int sts, ch, flag; 599 600 if (unlikely(rxlen >= port->fifosize)) { 601 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 602 port->icount.buf_overrun++; 603 /* Ensure sanity of RX level */ 604 rxlen = port->fifosize; 605 } 606 607 while (rxlen--) { 608 ch = max310x_port_read(port, MAX310X_RHR_REG); 609 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 610 611 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 612 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 613 614 port->icount.rx++; 615 flag = TTY_NORMAL; 616 617 if (unlikely(sts)) { 618 if (sts & MAX310X_LSR_RXBRK_BIT) { 619 port->icount.brk++; 620 if (uart_handle_break(port)) 621 continue; 622 } else if (sts & MAX310X_LSR_RXPAR_BIT) 623 port->icount.parity++; 624 else if (sts & MAX310X_LSR_FRERR_BIT) 625 port->icount.frame++; 626 else if (sts & MAX310X_LSR_RXOVR_BIT) 627 port->icount.overrun++; 628 629 sts &= port->read_status_mask; 630 if (sts & MAX310X_LSR_RXBRK_BIT) 631 flag = TTY_BREAK; 632 else if (sts & MAX310X_LSR_RXPAR_BIT) 633 flag = TTY_PARITY; 634 else if (sts & MAX310X_LSR_FRERR_BIT) 635 flag = TTY_FRAME; 636 else if (sts & MAX310X_LSR_RXOVR_BIT) 637 flag = TTY_OVERRUN; 638 } 639 640 if (uart_handle_sysrq_char(port, ch)) 641 continue; 642 643 if (sts & port->ignore_status_mask) 644 continue; 645 646 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 647 } 648 649 tty_flip_buffer_push(&port->state->port); 650 } 651 652 static void max310x_handle_tx(struct uart_port *port) 653 { 654 struct circ_buf *xmit = &port->state->xmit; 655 unsigned int txlen, to_send; 656 657 if (unlikely(port->x_char)) { 658 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 659 port->icount.tx++; 660 port->x_char = 0; 661 return; 662 } 663 664 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 665 return; 666 667 /* Get length of data pending in circular buffer */ 668 to_send = uart_circ_chars_pending(xmit); 669 if (likely(to_send)) { 670 /* Limit to size of TX FIFO */ 671 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 672 txlen = port->fifosize - txlen; 673 to_send = (to_send > txlen) ? txlen : to_send; 674 675 /* Add data to send */ 676 port->icount.tx += to_send; 677 while (to_send--) { 678 max310x_port_write(port, MAX310X_THR_REG, 679 xmit->buf[xmit->tail]); 680 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 681 } 682 } 683 684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 685 uart_write_wakeup(port); 686 } 687 688 static void max310x_port_irq(struct max310x_port *s, int portno) 689 { 690 struct uart_port *port = &s->p[portno].port; 691 692 do { 693 unsigned int ists, lsr, rxlen; 694 695 /* Read IRQ status & RX FIFO level */ 696 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 697 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 698 if (!ists && !rxlen) 699 break; 700 701 if (ists & MAX310X_IRQ_CTS_BIT) { 702 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 703 uart_handle_cts_change(port, 704 !!(lsr & MAX310X_LSR_CTS_BIT)); 705 } 706 if (rxlen) 707 max310x_handle_rx(port, rxlen); 708 if (ists & MAX310X_IRQ_TXEMPTY_BIT) { 709 mutex_lock(&s->mutex); 710 max310x_handle_tx(port); 711 mutex_unlock(&s->mutex); 712 } 713 } while (1); 714 } 715 716 static irqreturn_t max310x_ist(int irq, void *dev_id) 717 { 718 struct max310x_port *s = (struct max310x_port *)dev_id; 719 720 if (s->devtype->nr > 1) { 721 do { 722 unsigned int val = ~0; 723 724 WARN_ON_ONCE(regmap_read(s->regmap, 725 MAX310X_GLOBALIRQ_REG, &val)); 726 val = ((1 << s->devtype->nr) - 1) & ~val; 727 if (!val) 728 break; 729 max310x_port_irq(s, fls(val) - 1); 730 } while (1); 731 } else 732 max310x_port_irq(s, 0); 733 734 return IRQ_HANDLED; 735 } 736 737 static void max310x_wq_proc(struct work_struct *ws) 738 { 739 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 740 struct max310x_port *s = dev_get_drvdata(one->port.dev); 741 742 mutex_lock(&s->mutex); 743 max310x_handle_tx(&one->port); 744 mutex_unlock(&s->mutex); 745 } 746 747 static void max310x_start_tx(struct uart_port *port) 748 { 749 struct max310x_one *one = container_of(port, struct max310x_one, port); 750 751 if (!work_pending(&one->tx_work)) 752 schedule_work(&one->tx_work); 753 } 754 755 static unsigned int max310x_tx_empty(struct uart_port *port) 756 { 757 unsigned int lvl, sts; 758 759 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 760 sts = max310x_port_read(port, MAX310X_IRQSTS_REG); 761 762 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0; 763 } 764 765 static unsigned int max310x_get_mctrl(struct uart_port *port) 766 { 767 /* DCD and DSR are not wired and CTS/RTS is handled automatically 768 * so just indicate DSR and CAR asserted 769 */ 770 return TIOCM_DSR | TIOCM_CAR; 771 } 772 773 static void max310x_md_proc(struct work_struct *ws) 774 { 775 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 776 777 max310x_port_update(&one->port, MAX310X_MODE2_REG, 778 MAX310X_MODE2_LOOPBACK_BIT, 779 (one->port.mctrl & TIOCM_LOOP) ? 780 MAX310X_MODE2_LOOPBACK_BIT : 0); 781 } 782 783 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 784 { 785 struct max310x_one *one = container_of(port, struct max310x_one, port); 786 787 schedule_work(&one->md_work); 788 } 789 790 static void max310x_break_ctl(struct uart_port *port, int break_state) 791 { 792 max310x_port_update(port, MAX310X_LCR_REG, 793 MAX310X_LCR_TXBREAK_BIT, 794 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 795 } 796 797 static void max310x_set_termios(struct uart_port *port, 798 struct ktermios *termios, 799 struct ktermios *old) 800 { 801 unsigned int lcr = 0, flow = 0; 802 int baud; 803 804 /* Mask termios capabilities we don't support */ 805 termios->c_cflag &= ~CMSPAR; 806 807 /* Word size */ 808 switch (termios->c_cflag & CSIZE) { 809 case CS5: 810 break; 811 case CS6: 812 lcr = MAX310X_LCR_LENGTH0_BIT; 813 break; 814 case CS7: 815 lcr = MAX310X_LCR_LENGTH1_BIT; 816 break; 817 case CS8: 818 default: 819 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 820 break; 821 } 822 823 /* Parity */ 824 if (termios->c_cflag & PARENB) { 825 lcr |= MAX310X_LCR_PARITY_BIT; 826 if (!(termios->c_cflag & PARODD)) 827 lcr |= MAX310X_LCR_EVENPARITY_BIT; 828 } 829 830 /* Stop bits */ 831 if (termios->c_cflag & CSTOPB) 832 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 833 834 /* Update LCR register */ 835 max310x_port_write(port, MAX310X_LCR_REG, lcr); 836 837 /* Set read status mask */ 838 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 839 if (termios->c_iflag & INPCK) 840 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 841 MAX310X_LSR_FRERR_BIT; 842 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 843 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 844 845 /* Set status ignore mask */ 846 port->ignore_status_mask = 0; 847 if (termios->c_iflag & IGNBRK) 848 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 849 if (!(termios->c_cflag & CREAD)) 850 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 851 MAX310X_LSR_RXOVR_BIT | 852 MAX310X_LSR_FRERR_BIT | 853 MAX310X_LSR_RXBRK_BIT; 854 855 /* Configure flow control */ 856 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 857 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 858 if (termios->c_cflag & CRTSCTS) 859 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 860 MAX310X_FLOWCTRL_AUTORTS_BIT; 861 if (termios->c_iflag & IXON) 862 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 863 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 864 if (termios->c_iflag & IXOFF) 865 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 866 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 867 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 868 869 /* Get baud rate generator configuration */ 870 baud = uart_get_baud_rate(port, termios, old, 871 port->uartclk / 16 / 0xffff, 872 port->uartclk / 4); 873 874 /* Setup baudrate generator */ 875 baud = max310x_set_baud(port, baud); 876 877 /* Update timeout according to new baud rate */ 878 uart_update_timeout(port, termios->c_cflag, baud); 879 } 880 881 static void max310x_rs_proc(struct work_struct *ws) 882 { 883 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 884 unsigned int val; 885 886 val = (one->port.rs485.delay_rts_before_send << 4) | 887 one->port.rs485.delay_rts_after_send; 888 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val); 889 890 if (one->port.rs485.flags & SER_RS485_ENABLED) { 891 max310x_port_update(&one->port, MAX310X_MODE1_REG, 892 MAX310X_MODE1_TRNSCVCTRL_BIT, 893 MAX310X_MODE1_TRNSCVCTRL_BIT); 894 max310x_port_update(&one->port, MAX310X_MODE2_REG, 895 MAX310X_MODE2_ECHOSUPR_BIT, 896 MAX310X_MODE2_ECHOSUPR_BIT); 897 } else { 898 max310x_port_update(&one->port, MAX310X_MODE1_REG, 899 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 900 max310x_port_update(&one->port, MAX310X_MODE2_REG, 901 MAX310X_MODE2_ECHOSUPR_BIT, 0); 902 } 903 } 904 905 static int max310x_rs485_config(struct uart_port *port, 906 struct serial_rs485 *rs485) 907 { 908 struct max310x_one *one = container_of(port, struct max310x_one, port); 909 910 if ((rs485->delay_rts_before_send > 0x0f) || 911 (rs485->delay_rts_after_send > 0x0f)) 912 return -ERANGE; 913 914 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED; 915 memset(rs485->padding, 0, sizeof(rs485->padding)); 916 port->rs485 = *rs485; 917 918 schedule_work(&one->rs_work); 919 920 return 0; 921 } 922 923 static int max310x_startup(struct uart_port *port) 924 { 925 struct max310x_port *s = dev_get_drvdata(port->dev); 926 unsigned int val; 927 928 s->devtype->power(port, 1); 929 930 /* Configure MODE1 register */ 931 max310x_port_update(port, MAX310X_MODE1_REG, 932 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 933 934 /* Configure MODE2 register & Reset FIFOs*/ 935 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 936 max310x_port_write(port, MAX310X_MODE2_REG, val); 937 max310x_port_update(port, MAX310X_MODE2_REG, 938 MAX310X_MODE2_FIFORST_BIT, 0); 939 940 /* Configure flow control levels */ 941 /* Flow control halt level 96, resume level 48 */ 942 max310x_port_write(port, MAX310X_FLOWLVL_REG, 943 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 944 945 /* Clear IRQ status register */ 946 max310x_port_read(port, MAX310X_IRQSTS_REG); 947 948 /* Enable RX, TX, CTS change interrupts */ 949 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 950 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 951 952 return 0; 953 } 954 955 static void max310x_shutdown(struct uart_port *port) 956 { 957 struct max310x_port *s = dev_get_drvdata(port->dev); 958 959 /* Disable all interrupts */ 960 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 961 962 s->devtype->power(port, 0); 963 } 964 965 static const char *max310x_type(struct uart_port *port) 966 { 967 struct max310x_port *s = dev_get_drvdata(port->dev); 968 969 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 970 } 971 972 static int max310x_request_port(struct uart_port *port) 973 { 974 /* Do nothing */ 975 return 0; 976 } 977 978 static void max310x_config_port(struct uart_port *port, int flags) 979 { 980 if (flags & UART_CONFIG_TYPE) 981 port->type = PORT_MAX310X; 982 } 983 984 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 985 { 986 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 987 return -EINVAL; 988 if (s->irq != port->irq) 989 return -EINVAL; 990 991 return 0; 992 } 993 994 static void max310x_null_void(struct uart_port *port) 995 { 996 /* Do nothing */ 997 } 998 999 static const struct uart_ops max310x_ops = { 1000 .tx_empty = max310x_tx_empty, 1001 .set_mctrl = max310x_set_mctrl, 1002 .get_mctrl = max310x_get_mctrl, 1003 .stop_tx = max310x_null_void, 1004 .start_tx = max310x_start_tx, 1005 .stop_rx = max310x_null_void, 1006 .break_ctl = max310x_break_ctl, 1007 .startup = max310x_startup, 1008 .shutdown = max310x_shutdown, 1009 .set_termios = max310x_set_termios, 1010 .type = max310x_type, 1011 .request_port = max310x_request_port, 1012 .release_port = max310x_null_void, 1013 .config_port = max310x_config_port, 1014 .verify_port = max310x_verify_port, 1015 }; 1016 1017 static int __maybe_unused max310x_suspend(struct device *dev) 1018 { 1019 struct max310x_port *s = dev_get_drvdata(dev); 1020 int i; 1021 1022 for (i = 0; i < s->devtype->nr; i++) { 1023 uart_suspend_port(&max310x_uart, &s->p[i].port); 1024 s->devtype->power(&s->p[i].port, 0); 1025 } 1026 1027 return 0; 1028 } 1029 1030 static int __maybe_unused max310x_resume(struct device *dev) 1031 { 1032 struct max310x_port *s = dev_get_drvdata(dev); 1033 int i; 1034 1035 for (i = 0; i < s->devtype->nr; i++) { 1036 s->devtype->power(&s->p[i].port, 1); 1037 uart_resume_port(&max310x_uart, &s->p[i].port); 1038 } 1039 1040 return 0; 1041 } 1042 1043 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1044 1045 #ifdef CONFIG_GPIOLIB 1046 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1047 { 1048 unsigned int val; 1049 struct max310x_port *s = gpiochip_get_data(chip); 1050 struct uart_port *port = &s->p[offset / 4].port; 1051 1052 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1053 1054 return !!((val >> 4) & (1 << (offset % 4))); 1055 } 1056 1057 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1058 { 1059 struct max310x_port *s = gpiochip_get_data(chip); 1060 struct uart_port *port = &s->p[offset / 4].port; 1061 1062 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1063 value ? 1 << (offset % 4) : 0); 1064 } 1065 1066 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1067 { 1068 struct max310x_port *s = gpiochip_get_data(chip); 1069 struct uart_port *port = &s->p[offset / 4].port; 1070 1071 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1072 1073 return 0; 1074 } 1075 1076 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1077 unsigned offset, int value) 1078 { 1079 struct max310x_port *s = gpiochip_get_data(chip); 1080 struct uart_port *port = &s->p[offset / 4].port; 1081 1082 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1083 value ? 1 << (offset % 4) : 0); 1084 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1085 1 << (offset % 4)); 1086 1087 return 0; 1088 } 1089 #endif 1090 1091 static int max310x_probe(struct device *dev, struct max310x_devtype *devtype, 1092 struct regmap *regmap, int irq, unsigned long flags) 1093 { 1094 int i, ret, fmin, fmax, freq, uartclk; 1095 struct clk *clk_osc, *clk_xtal; 1096 struct max310x_port *s; 1097 bool xtal = false; 1098 1099 if (IS_ERR(regmap)) 1100 return PTR_ERR(regmap); 1101 1102 /* Alloc port structure */ 1103 s = devm_kzalloc(dev, sizeof(*s) + 1104 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL); 1105 if (!s) { 1106 dev_err(dev, "Error allocating port structure\n"); 1107 return -ENOMEM; 1108 } 1109 1110 clk_osc = devm_clk_get(dev, "osc"); 1111 clk_xtal = devm_clk_get(dev, "xtal"); 1112 if (!IS_ERR(clk_osc)) { 1113 s->clk = clk_osc; 1114 fmin = 500000; 1115 fmax = 35000000; 1116 } else if (!IS_ERR(clk_xtal)) { 1117 s->clk = clk_xtal; 1118 fmin = 1000000; 1119 fmax = 4000000; 1120 xtal = true; 1121 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER || 1122 PTR_ERR(clk_xtal) == -EPROBE_DEFER) { 1123 return -EPROBE_DEFER; 1124 } else { 1125 dev_err(dev, "Cannot get clock\n"); 1126 return -EINVAL; 1127 } 1128 1129 ret = clk_prepare_enable(s->clk); 1130 if (ret) 1131 return ret; 1132 1133 freq = clk_get_rate(s->clk); 1134 /* Check frequency limits */ 1135 if (freq < fmin || freq > fmax) { 1136 ret = -ERANGE; 1137 goto out_clk; 1138 } 1139 1140 s->regmap = regmap; 1141 s->devtype = devtype; 1142 dev_set_drvdata(dev, s); 1143 1144 /* Check device to ensure we are talking to what we expect */ 1145 ret = devtype->detect(dev); 1146 if (ret) 1147 goto out_clk; 1148 1149 for (i = 0; i < devtype->nr; i++) { 1150 unsigned int offs = i << 5; 1151 1152 /* Reset port */ 1153 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 1154 MAX310X_MODE2_RST_BIT); 1155 /* Clear port reset */ 1156 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0); 1157 1158 /* Wait for port startup */ 1159 do { 1160 regmap_read(s->regmap, 1161 MAX310X_BRGDIVLSB_REG + offs, &ret); 1162 } while (ret != 0x01); 1163 1164 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs, 1165 MAX310X_MODE1_AUTOSLEEP_BIT, 1166 MAX310X_MODE1_AUTOSLEEP_BIT); 1167 } 1168 1169 uartclk = max310x_set_ref_clk(s, freq, xtal); 1170 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1171 1172 #ifdef CONFIG_GPIOLIB 1173 /* Setup GPIO cotroller */ 1174 s->gpio.owner = THIS_MODULE; 1175 s->gpio.parent = dev; 1176 s->gpio.label = dev_name(dev); 1177 s->gpio.direction_input = max310x_gpio_direction_input; 1178 s->gpio.get = max310x_gpio_get; 1179 s->gpio.direction_output= max310x_gpio_direction_output; 1180 s->gpio.set = max310x_gpio_set; 1181 s->gpio.base = -1; 1182 s->gpio.ngpio = devtype->nr * 4; 1183 s->gpio.can_sleep = 1; 1184 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1185 if (ret) 1186 goto out_clk; 1187 #endif 1188 1189 mutex_init(&s->mutex); 1190 1191 for (i = 0; i < devtype->nr; i++) { 1192 unsigned int line; 1193 1194 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1195 if (line == MAX310X_UART_NRMAX) { 1196 ret = -ERANGE; 1197 goto out_uart; 1198 } 1199 1200 /* Initialize port data */ 1201 s->p[i].port.line = line; 1202 s->p[i].port.dev = dev; 1203 s->p[i].port.irq = irq; 1204 s->p[i].port.type = PORT_MAX310X; 1205 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1206 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1207 s->p[i].port.iotype = UPIO_PORT; 1208 s->p[i].port.iobase = i * 0x20; 1209 s->p[i].port.membase = (void __iomem *)~0; 1210 s->p[i].port.uartclk = uartclk; 1211 s->p[i].port.rs485_config = max310x_rs485_config; 1212 s->p[i].port.ops = &max310x_ops; 1213 /* Disable all interrupts */ 1214 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1215 /* Clear IRQ status register */ 1216 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1217 /* Enable IRQ pin */ 1218 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG, 1219 MAX310X_MODE1_IRQSEL_BIT, 1220 MAX310X_MODE1_IRQSEL_BIT); 1221 /* Initialize queue for start TX */ 1222 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc); 1223 /* Initialize queue for changing LOOPBACK mode */ 1224 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1225 /* Initialize queue for changing RS485 mode */ 1226 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1227 1228 /* Register port */ 1229 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1230 if (ret) { 1231 s->p[i].port.dev = NULL; 1232 goto out_uart; 1233 } 1234 set_bit(line, max310x_lines); 1235 1236 /* Go to suspend mode */ 1237 devtype->power(&s->p[i].port, 0); 1238 } 1239 1240 /* Setup interrupt */ 1241 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1242 IRQF_ONESHOT | flags, dev_name(dev), s); 1243 if (!ret) 1244 return 0; 1245 1246 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1247 1248 out_uart: 1249 for (i = 0; i < devtype->nr; i++) { 1250 if (s->p[i].port.dev) { 1251 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1252 clear_bit(s->p[i].port.line, max310x_lines); 1253 } 1254 } 1255 1256 mutex_destroy(&s->mutex); 1257 1258 out_clk: 1259 clk_disable_unprepare(s->clk); 1260 1261 return ret; 1262 } 1263 1264 static int max310x_remove(struct device *dev) 1265 { 1266 struct max310x_port *s = dev_get_drvdata(dev); 1267 int i; 1268 1269 for (i = 0; i < s->devtype->nr; i++) { 1270 cancel_work_sync(&s->p[i].tx_work); 1271 cancel_work_sync(&s->p[i].md_work); 1272 cancel_work_sync(&s->p[i].rs_work); 1273 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1274 clear_bit(s->p[i].port.line, max310x_lines); 1275 s->devtype->power(&s->p[i].port, 0); 1276 } 1277 1278 mutex_destroy(&s->mutex); 1279 clk_disable_unprepare(s->clk); 1280 1281 return 0; 1282 } 1283 1284 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1285 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1286 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1287 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1288 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1289 { } 1290 }; 1291 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1292 1293 static struct regmap_config regcfg = { 1294 .reg_bits = 8, 1295 .val_bits = 8, 1296 .write_flag_mask = 0x80, 1297 .cache_type = REGCACHE_RBTREE, 1298 .writeable_reg = max310x_reg_writeable, 1299 .volatile_reg = max310x_reg_volatile, 1300 .precious_reg = max310x_reg_precious, 1301 }; 1302 1303 #ifdef CONFIG_SPI_MASTER 1304 static int max310x_spi_probe(struct spi_device *spi) 1305 { 1306 struct max310x_devtype *devtype; 1307 unsigned long flags = 0; 1308 struct regmap *regmap; 1309 int ret; 1310 1311 /* Setup SPI bus */ 1312 spi->bits_per_word = 8; 1313 spi->mode = spi->mode ? : SPI_MODE_0; 1314 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1315 ret = spi_setup(spi); 1316 if (ret) 1317 return ret; 1318 1319 if (spi->dev.of_node) { 1320 const struct of_device_id *of_id = 1321 of_match_device(max310x_dt_ids, &spi->dev); 1322 1323 devtype = (struct max310x_devtype *)of_id->data; 1324 } else { 1325 const struct spi_device_id *id_entry = spi_get_device_id(spi); 1326 1327 devtype = (struct max310x_devtype *)id_entry->driver_data; 1328 } 1329 1330 flags = IRQF_TRIGGER_FALLING; 1331 regcfg.max_register = devtype->nr * 0x20 - 1; 1332 regmap = devm_regmap_init_spi(spi, ®cfg); 1333 1334 return max310x_probe(&spi->dev, devtype, regmap, spi->irq, flags); 1335 } 1336 1337 static int max310x_spi_remove(struct spi_device *spi) 1338 { 1339 return max310x_remove(&spi->dev); 1340 } 1341 1342 static const struct spi_device_id max310x_id_table[] = { 1343 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1344 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1345 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1346 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1347 { } 1348 }; 1349 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1350 1351 static struct spi_driver max310x_spi_driver = { 1352 .driver = { 1353 .name = MAX310X_NAME, 1354 .of_match_table = of_match_ptr(max310x_dt_ids), 1355 .pm = &max310x_pm_ops, 1356 }, 1357 .probe = max310x_spi_probe, 1358 .remove = max310x_spi_remove, 1359 .id_table = max310x_id_table, 1360 }; 1361 #endif 1362 1363 static int __init max310x_uart_init(void) 1364 { 1365 int ret; 1366 1367 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1368 1369 ret = uart_register_driver(&max310x_uart); 1370 if (ret) 1371 return ret; 1372 1373 #ifdef CONFIG_SPI_MASTER 1374 spi_register_driver(&max310x_spi_driver); 1375 #endif 1376 1377 return 0; 1378 } 1379 module_init(max310x_uart_init); 1380 1381 static void __exit max310x_uart_exit(void) 1382 { 1383 #ifdef CONFIG_SPI_MASTER 1384 spi_unregister_driver(&max310x_spi_driver); 1385 #endif 1386 1387 uart_unregister_driver(&max310x_uart); 1388 } 1389 module_exit(max310x_uart_exit); 1390 1391 MODULE_LICENSE("GPL"); 1392 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1393 MODULE_DESCRIPTION("MAX310X serial driver"); 1394