1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spi/spi.h> 27 #include <linux/uaccess.h> 28 29 #define MAX310X_NAME "max310x" 30 #define MAX310X_MAJOR 204 31 #define MAX310X_MINOR 209 32 #define MAX310X_UART_NRMAX 16 33 34 /* MAX310X register definitions */ 35 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 36 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 37 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 38 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 39 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 40 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 41 #define MAX310X_REG_05 (0x05) 42 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 43 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 44 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 45 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 46 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 47 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 48 #define MAX310X_LCR_REG (0x0b) /* LCR */ 49 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 50 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 51 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 52 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 53 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 54 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 55 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 56 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 57 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 58 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 59 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 60 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 63 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 64 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 65 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 66 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 67 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 68 #define MAX310X_REG_1F (0x1f) 69 70 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 71 72 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 74 75 /* Extended registers */ 76 #define MAX310X_SPI_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 77 #define MAX310X_I2C_REVID_EXTREG (0x25) /* Revision ID */ 78 79 /* IRQ register bits */ 80 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 81 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 82 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 83 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 84 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 85 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 86 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 87 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 88 89 /* LSR register bits */ 90 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 91 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 92 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 93 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 94 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 95 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 97 98 /* Special character register bits */ 99 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 100 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 101 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 102 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 103 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 105 106 /* Status register bits */ 107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 109 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 110 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 111 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 112 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 113 114 /* MODE1 register bits */ 115 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 116 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 119 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 120 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 122 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 123 124 /* MODE2 register bits */ 125 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 126 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 127 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 128 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 129 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 130 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 132 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 133 134 /* LCR register bits */ 135 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 136 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 137 * 138 * Word length bits table: 139 * 00 -> 5 bit words 140 * 01 -> 6 bit words 141 * 10 -> 7 bit words 142 * 11 -> 8 bit words 143 */ 144 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 145 * 146 * STOP length bit table: 147 * 0 -> 1 stop bit 148 * 1 -> 1-1.5 stop bits if 149 * word length is 5, 150 * 2 stop bits otherwise 151 */ 152 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 153 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 155 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 156 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 157 158 /* IRDA register bits */ 159 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 160 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 161 162 /* Flow control trigger level register masks */ 163 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 164 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 165 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 166 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 167 168 /* FIFO interrupt trigger level register masks */ 169 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 170 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 171 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 172 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 173 174 /* Flow control register bits */ 175 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 176 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 177 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 178 * are used in conjunction with 179 * XOFF2 for definition of 180 * special character */ 181 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 182 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 183 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 184 * 185 * SWFLOW bits 1 & 0 table: 186 * 00 -> no transmitter flow 187 * control 188 * 01 -> receiver compares 189 * XON2 and XOFF2 190 * and controls 191 * transmitter 192 * 10 -> receiver compares 193 * XON1 and XOFF1 194 * and controls 195 * transmitter 196 * 11 -> receiver compares 197 * XON1, XON2, XOFF1 and 198 * XOFF2 and controls 199 * transmitter 200 */ 201 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 202 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 203 * 204 * SWFLOW bits 3 & 2 table: 205 * 00 -> no received flow 206 * control 207 * 01 -> transmitter generates 208 * XON2 and XOFF2 209 * 10 -> transmitter generates 210 * XON1 and XOFF1 211 * 11 -> transmitter generates 212 * XON1, XON2, XOFF1 and 213 * XOFF2 214 */ 215 216 /* PLL configuration register masks */ 217 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 218 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 219 220 /* Baud rate generator configuration register bits */ 221 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 222 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 223 224 /* Clock source register bits */ 225 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 226 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 227 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 228 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 229 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 230 231 /* Global commands */ 232 #define MAX310X_EXTREG_ENBL (0xce) 233 #define MAX310X_EXTREG_DSBL (0xcd) 234 235 /* Misc definitions */ 236 #define MAX310X_FIFO_SIZE (128) 237 #define MAX310x_REV_MASK (0xf8) 238 #define MAX310X_WRITE_BIT 0x80 239 240 /* MAX3107 specific */ 241 #define MAX3107_REV_ID (0xa0) 242 243 /* MAX3109 specific */ 244 #define MAX3109_REV_ID (0xc0) 245 246 /* MAX14830 specific */ 247 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 248 #define MAX14830_REV_ID (0xb0) 249 250 struct max310x_if_cfg { 251 int (*extended_reg_enable)(struct device *dev, bool enable); 252 253 unsigned int rev_id_reg; 254 }; 255 256 struct max310x_devtype { 257 struct { 258 unsigned short min; 259 unsigned short max; 260 } slave_addr; 261 char name[9]; 262 int nr; 263 u8 mode1; 264 int (*detect)(struct device *); 265 void (*power)(struct uart_port *, int); 266 }; 267 268 struct max310x_one { 269 struct uart_port port; 270 struct work_struct tx_work; 271 struct work_struct md_work; 272 struct work_struct rs_work; 273 struct regmap *regmap; 274 275 u8 rx_buf[MAX310X_FIFO_SIZE]; 276 }; 277 #define to_max310x_port(_port) \ 278 container_of(_port, struct max310x_one, port) 279 280 struct max310x_port { 281 const struct max310x_devtype *devtype; 282 const struct max310x_if_cfg *if_cfg; 283 struct regmap *regmap; 284 struct clk *clk; 285 #ifdef CONFIG_GPIOLIB 286 struct gpio_chip gpio; 287 #endif 288 struct max310x_one p[]; 289 }; 290 291 static struct uart_driver max310x_uart = { 292 .owner = THIS_MODULE, 293 .driver_name = MAX310X_NAME, 294 .dev_name = "ttyMAX", 295 .major = MAX310X_MAJOR, 296 .minor = MAX310X_MINOR, 297 .nr = MAX310X_UART_NRMAX, 298 }; 299 300 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 301 302 static u8 max310x_port_read(struct uart_port *port, u8 reg) 303 { 304 struct max310x_one *one = to_max310x_port(port); 305 unsigned int val = 0; 306 307 regmap_read(one->regmap, reg, &val); 308 309 return val; 310 } 311 312 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 313 { 314 struct max310x_one *one = to_max310x_port(port); 315 316 regmap_write(one->regmap, reg, val); 317 } 318 319 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 320 { 321 struct max310x_one *one = to_max310x_port(port); 322 323 regmap_update_bits(one->regmap, reg, mask, val); 324 } 325 326 static int max3107_detect(struct device *dev) 327 { 328 struct max310x_port *s = dev_get_drvdata(dev); 329 unsigned int val = 0; 330 int ret; 331 332 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 333 if (ret) 334 return ret; 335 336 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 337 dev_err(dev, 338 "%s ID 0x%02x does not match\n", s->devtype->name, val); 339 return -ENODEV; 340 } 341 342 return 0; 343 } 344 345 static int max3108_detect(struct device *dev) 346 { 347 struct max310x_port *s = dev_get_drvdata(dev); 348 unsigned int val = 0; 349 int ret; 350 351 /* MAX3108 have not REV ID register, we just check default value 352 * from clocksource register to make sure everything works. 353 */ 354 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 355 if (ret) 356 return ret; 357 358 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 359 dev_err(dev, "%s not present\n", s->devtype->name); 360 return -ENODEV; 361 } 362 363 return 0; 364 } 365 366 static int max3109_detect(struct device *dev) 367 { 368 struct max310x_port *s = dev_get_drvdata(dev); 369 unsigned int val = 0; 370 int ret; 371 372 ret = s->if_cfg->extended_reg_enable(dev, true); 373 if (ret) 374 return ret; 375 376 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 377 s->if_cfg->extended_reg_enable(dev, false); 378 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 379 dev_err(dev, 380 "%s ID 0x%02x does not match\n", s->devtype->name, val); 381 return -ENODEV; 382 } 383 384 return 0; 385 } 386 387 static void max310x_power(struct uart_port *port, int on) 388 { 389 max310x_port_update(port, MAX310X_MODE1_REG, 390 MAX310X_MODE1_FORCESLEEP_BIT, 391 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 392 if (on) 393 msleep(50); 394 } 395 396 static int max14830_detect(struct device *dev) 397 { 398 struct max310x_port *s = dev_get_drvdata(dev); 399 unsigned int val = 0; 400 int ret; 401 402 ret = s->if_cfg->extended_reg_enable(dev, true); 403 if (ret) 404 return ret; 405 406 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 407 s->if_cfg->extended_reg_enable(dev, false); 408 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 409 dev_err(dev, 410 "%s ID 0x%02x does not match\n", s->devtype->name, val); 411 return -ENODEV; 412 } 413 414 return 0; 415 } 416 417 static void max14830_power(struct uart_port *port, int on) 418 { 419 max310x_port_update(port, MAX310X_BRGCFG_REG, 420 MAX14830_BRGCFG_CLKDIS_BIT, 421 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 422 if (on) 423 msleep(50); 424 } 425 426 static const struct max310x_devtype max3107_devtype = { 427 .name = "MAX3107", 428 .nr = 1, 429 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 430 .detect = max3107_detect, 431 .power = max310x_power, 432 .slave_addr = { 433 .min = 0x2c, 434 .max = 0x2f, 435 }, 436 }; 437 438 static const struct max310x_devtype max3108_devtype = { 439 .name = "MAX3108", 440 .nr = 1, 441 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 442 .detect = max3108_detect, 443 .power = max310x_power, 444 .slave_addr = { 445 .min = 0x60, 446 .max = 0x6f, 447 }, 448 }; 449 450 static const struct max310x_devtype max3109_devtype = { 451 .name = "MAX3109", 452 .nr = 2, 453 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 454 .detect = max3109_detect, 455 .power = max310x_power, 456 .slave_addr = { 457 .min = 0x60, 458 .max = 0x6f, 459 }, 460 }; 461 462 static const struct max310x_devtype max14830_devtype = { 463 .name = "MAX14830", 464 .nr = 4, 465 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 466 .detect = max14830_detect, 467 .power = max14830_power, 468 .slave_addr = { 469 .min = 0x60, 470 .max = 0x6f, 471 }, 472 }; 473 474 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 475 { 476 switch (reg) { 477 case MAX310X_IRQSTS_REG: 478 case MAX310X_LSR_IRQSTS_REG: 479 case MAX310X_SPCHR_IRQSTS_REG: 480 case MAX310X_STS_IRQSTS_REG: 481 case MAX310X_TXFIFOLVL_REG: 482 case MAX310X_RXFIFOLVL_REG: 483 return false; 484 default: 485 break; 486 } 487 488 return true; 489 } 490 491 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 492 { 493 switch (reg) { 494 case MAX310X_RHR_REG: 495 case MAX310X_IRQSTS_REG: 496 case MAX310X_LSR_IRQSTS_REG: 497 case MAX310X_SPCHR_IRQSTS_REG: 498 case MAX310X_STS_IRQSTS_REG: 499 case MAX310X_TXFIFOLVL_REG: 500 case MAX310X_RXFIFOLVL_REG: 501 case MAX310X_GPIODATA_REG: 502 case MAX310X_BRGDIVLSB_REG: 503 case MAX310X_REG_05: 504 case MAX310X_REG_1F: 505 return true; 506 default: 507 break; 508 } 509 510 return false; 511 } 512 513 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 514 { 515 switch (reg) { 516 case MAX310X_RHR_REG: 517 case MAX310X_IRQSTS_REG: 518 case MAX310X_SPCHR_IRQSTS_REG: 519 case MAX310X_STS_IRQSTS_REG: 520 return true; 521 default: 522 break; 523 } 524 525 return false; 526 } 527 528 static bool max310x_reg_noinc(struct device *dev, unsigned int reg) 529 { 530 return reg == MAX310X_RHR_REG; 531 } 532 533 static int max310x_set_baud(struct uart_port *port, int baud) 534 { 535 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 536 537 /* 538 * Calculate the integer divisor first. Select a proper mode 539 * in case if the requested baud is too high for the pre-defined 540 * clocks frequency. 541 */ 542 div = port->uartclk / baud; 543 if (div < 8) { 544 /* Mode x4 */ 545 c = 4; 546 mode = MAX310X_BRGCFG_4XMODE_BIT; 547 } else if (div < 16) { 548 /* Mode x2 */ 549 c = 8; 550 mode = MAX310X_BRGCFG_2XMODE_BIT; 551 } else { 552 c = 16; 553 } 554 555 /* Calculate the divisor in accordance with the fraction coefficient */ 556 div /= c; 557 F = c*baud; 558 559 /* Calculate the baud rate fraction */ 560 if (div > 0) 561 frac = (16*(port->uartclk % F)) / F; 562 else 563 div = 1; 564 565 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 566 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 567 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 568 569 /* Return the actual baud rate we just programmed */ 570 return (16*port->uartclk) / (c*(16*div + frac)); 571 } 572 573 static int max310x_update_best_err(unsigned long f, long *besterr) 574 { 575 /* Use baudrate 115200 for calculate error */ 576 long err = f % (460800 * 16); 577 578 if ((*besterr < 0) || (*besterr > err)) { 579 *besterr = err; 580 return 0; 581 } 582 583 return 1; 584 } 585 586 static u32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 587 unsigned long freq, bool xtal) 588 { 589 unsigned int div, clksrc, pllcfg = 0; 590 long besterr = -1; 591 unsigned long fdiv, fmul, bestfreq = freq; 592 593 /* First, update error without PLL */ 594 max310x_update_best_err(freq, &besterr); 595 596 /* Try all possible PLL dividers */ 597 for (div = 1; (div <= 63) && besterr; div++) { 598 fdiv = DIV_ROUND_CLOSEST(freq, div); 599 600 /* Try multiplier 6 */ 601 fmul = fdiv * 6; 602 if ((fdiv >= 500000) && (fdiv <= 800000)) 603 if (!max310x_update_best_err(fmul, &besterr)) { 604 pllcfg = (0 << 6) | div; 605 bestfreq = fmul; 606 } 607 /* Try multiplier 48 */ 608 fmul = fdiv * 48; 609 if ((fdiv >= 850000) && (fdiv <= 1200000)) 610 if (!max310x_update_best_err(fmul, &besterr)) { 611 pllcfg = (1 << 6) | div; 612 bestfreq = fmul; 613 } 614 /* Try multiplier 96 */ 615 fmul = fdiv * 96; 616 if ((fdiv >= 425000) && (fdiv <= 1000000)) 617 if (!max310x_update_best_err(fmul, &besterr)) { 618 pllcfg = (2 << 6) | div; 619 bestfreq = fmul; 620 } 621 /* Try multiplier 144 */ 622 fmul = fdiv * 144; 623 if ((fdiv >= 390000) && (fdiv <= 667000)) 624 if (!max310x_update_best_err(fmul, &besterr)) { 625 pllcfg = (3 << 6) | div; 626 bestfreq = fmul; 627 } 628 } 629 630 /* Configure clock source */ 631 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 632 633 /* Configure PLL */ 634 if (pllcfg) { 635 clksrc |= MAX310X_CLKSRC_PLL_BIT; 636 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 637 } else 638 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 639 640 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 641 642 /* Wait for crystal */ 643 if (xtal) { 644 unsigned int val; 645 msleep(10); 646 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 647 if (!(val & MAX310X_STS_CLKREADY_BIT)) { 648 dev_warn(dev, "clock is not stable yet\n"); 649 } 650 } 651 652 return bestfreq; 653 } 654 655 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 656 { 657 struct max310x_one *one = to_max310x_port(port); 658 659 regmap_noinc_write(one->regmap, MAX310X_THR_REG, txbuf, len); 660 } 661 662 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 663 { 664 struct max310x_one *one = to_max310x_port(port); 665 666 regmap_noinc_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 667 } 668 669 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 670 { 671 struct max310x_one *one = to_max310x_port(port); 672 unsigned int sts, i; 673 u8 ch, flag; 674 675 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 676 /* We are just reading, happily ignoring any error conditions. 677 * Break condition, parity checking, framing errors -- they 678 * are all ignored. That means that we can do a batch-read. 679 * 680 * There is a small opportunity for race if the RX FIFO 681 * overruns while we're reading the buffer; the datasheets says 682 * that the LSR register applies to the "current" character. 683 * That's also the reason why we cannot do batched reads when 684 * asked to check the individual statuses. 685 * */ 686 687 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 688 max310x_batch_read(port, one->rx_buf, rxlen); 689 690 port->icount.rx += rxlen; 691 flag = TTY_NORMAL; 692 sts &= port->read_status_mask; 693 694 if (sts & MAX310X_LSR_RXOVR_BIT) { 695 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 696 port->icount.overrun++; 697 } 698 699 for (i = 0; i < (rxlen - 1); ++i) 700 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 701 702 /* 703 * Handle the overrun case for the last character only, since 704 * the RxFIFO overflow happens after it is pushed to the FIFO 705 * tail. 706 */ 707 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 708 one->rx_buf[rxlen-1], flag); 709 710 } else { 711 if (unlikely(rxlen >= port->fifosize)) { 712 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 713 port->icount.buf_overrun++; 714 /* Ensure sanity of RX level */ 715 rxlen = port->fifosize; 716 } 717 718 while (rxlen--) { 719 ch = max310x_port_read(port, MAX310X_RHR_REG); 720 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 721 722 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 723 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 724 725 port->icount.rx++; 726 flag = TTY_NORMAL; 727 728 if (unlikely(sts)) { 729 if (sts & MAX310X_LSR_RXBRK_BIT) { 730 port->icount.brk++; 731 if (uart_handle_break(port)) 732 continue; 733 } else if (sts & MAX310X_LSR_RXPAR_BIT) 734 port->icount.parity++; 735 else if (sts & MAX310X_LSR_FRERR_BIT) 736 port->icount.frame++; 737 else if (sts & MAX310X_LSR_RXOVR_BIT) 738 port->icount.overrun++; 739 740 sts &= port->read_status_mask; 741 if (sts & MAX310X_LSR_RXBRK_BIT) 742 flag = TTY_BREAK; 743 else if (sts & MAX310X_LSR_RXPAR_BIT) 744 flag = TTY_PARITY; 745 else if (sts & MAX310X_LSR_FRERR_BIT) 746 flag = TTY_FRAME; 747 else if (sts & MAX310X_LSR_RXOVR_BIT) 748 flag = TTY_OVERRUN; 749 } 750 751 if (uart_handle_sysrq_char(port, ch)) 752 continue; 753 754 if (sts & port->ignore_status_mask) 755 continue; 756 757 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 758 } 759 } 760 761 tty_flip_buffer_push(&port->state->port); 762 } 763 764 static void max310x_handle_tx(struct uart_port *port) 765 { 766 struct circ_buf *xmit = &port->state->xmit; 767 unsigned int txlen, to_send, until_end; 768 769 if (unlikely(port->x_char)) { 770 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 771 port->icount.tx++; 772 port->x_char = 0; 773 return; 774 } 775 776 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 777 return; 778 779 /* Get length of data pending in circular buffer */ 780 to_send = uart_circ_chars_pending(xmit); 781 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 782 if (likely(to_send)) { 783 /* Limit to size of TX FIFO */ 784 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 785 txlen = port->fifosize - txlen; 786 to_send = (to_send > txlen) ? txlen : to_send; 787 788 if (until_end < to_send) { 789 /* It's a circ buffer -- wrap around. 790 * We could do that in one SPI transaction, but meh. */ 791 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 792 max310x_batch_write(port, xmit->buf, to_send - until_end); 793 } else { 794 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 795 } 796 uart_xmit_advance(port, to_send); 797 } 798 799 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 800 uart_write_wakeup(port); 801 } 802 803 static void max310x_start_tx(struct uart_port *port) 804 { 805 struct max310x_one *one = to_max310x_port(port); 806 807 schedule_work(&one->tx_work); 808 } 809 810 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 811 { 812 struct uart_port *port = &s->p[portno].port; 813 irqreturn_t res = IRQ_NONE; 814 815 do { 816 unsigned int ists, lsr, rxlen; 817 818 /* Read IRQ status & RX FIFO level */ 819 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 820 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 821 if (!ists && !rxlen) 822 break; 823 824 res = IRQ_HANDLED; 825 826 if (ists & MAX310X_IRQ_CTS_BIT) { 827 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 828 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 829 } 830 if (rxlen) 831 max310x_handle_rx(port, rxlen); 832 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 833 max310x_start_tx(port); 834 } while (1); 835 return res; 836 } 837 838 static irqreturn_t max310x_ist(int irq, void *dev_id) 839 { 840 struct max310x_port *s = (struct max310x_port *)dev_id; 841 bool handled = false; 842 843 if (s->devtype->nr > 1) { 844 do { 845 unsigned int val = ~0; 846 847 WARN_ON_ONCE(regmap_read(s->regmap, 848 MAX310X_GLOBALIRQ_REG, &val)); 849 val = ((1 << s->devtype->nr) - 1) & ~val; 850 if (!val) 851 break; 852 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 853 handled = true; 854 } while (1); 855 } else { 856 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 857 handled = true; 858 } 859 860 return IRQ_RETVAL(handled); 861 } 862 863 static void max310x_tx_proc(struct work_struct *ws) 864 { 865 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 866 867 max310x_handle_tx(&one->port); 868 } 869 870 static unsigned int max310x_tx_empty(struct uart_port *port) 871 { 872 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 873 874 return lvl ? 0 : TIOCSER_TEMT; 875 } 876 877 static unsigned int max310x_get_mctrl(struct uart_port *port) 878 { 879 /* DCD and DSR are not wired and CTS/RTS is handled automatically 880 * so just indicate DSR and CAR asserted 881 */ 882 return TIOCM_DSR | TIOCM_CAR; 883 } 884 885 static void max310x_md_proc(struct work_struct *ws) 886 { 887 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 888 889 max310x_port_update(&one->port, MAX310X_MODE2_REG, 890 MAX310X_MODE2_LOOPBACK_BIT, 891 (one->port.mctrl & TIOCM_LOOP) ? 892 MAX310X_MODE2_LOOPBACK_BIT : 0); 893 } 894 895 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 896 { 897 struct max310x_one *one = to_max310x_port(port); 898 899 schedule_work(&one->md_work); 900 } 901 902 static void max310x_break_ctl(struct uart_port *port, int break_state) 903 { 904 max310x_port_update(port, MAX310X_LCR_REG, 905 MAX310X_LCR_TXBREAK_BIT, 906 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 907 } 908 909 static void max310x_set_termios(struct uart_port *port, 910 struct ktermios *termios, 911 const struct ktermios *old) 912 { 913 unsigned int lcr = 0, flow = 0; 914 int baud; 915 916 /* Mask termios capabilities we don't support */ 917 termios->c_cflag &= ~CMSPAR; 918 919 /* Word size */ 920 switch (termios->c_cflag & CSIZE) { 921 case CS5: 922 break; 923 case CS6: 924 lcr = MAX310X_LCR_LENGTH0_BIT; 925 break; 926 case CS7: 927 lcr = MAX310X_LCR_LENGTH1_BIT; 928 break; 929 case CS8: 930 default: 931 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 932 break; 933 } 934 935 /* Parity */ 936 if (termios->c_cflag & PARENB) { 937 lcr |= MAX310X_LCR_PARITY_BIT; 938 if (!(termios->c_cflag & PARODD)) 939 lcr |= MAX310X_LCR_EVENPARITY_BIT; 940 } 941 942 /* Stop bits */ 943 if (termios->c_cflag & CSTOPB) 944 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 945 946 /* Update LCR register */ 947 max310x_port_write(port, MAX310X_LCR_REG, lcr); 948 949 /* Set read status mask */ 950 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 951 if (termios->c_iflag & INPCK) 952 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 953 MAX310X_LSR_FRERR_BIT; 954 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 955 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 956 957 /* Set status ignore mask */ 958 port->ignore_status_mask = 0; 959 if (termios->c_iflag & IGNBRK) 960 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 961 if (!(termios->c_cflag & CREAD)) 962 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 963 MAX310X_LSR_RXOVR_BIT | 964 MAX310X_LSR_FRERR_BIT | 965 MAX310X_LSR_RXBRK_BIT; 966 967 /* Configure flow control */ 968 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 969 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 970 971 /* Disable transmitter before enabling AutoCTS or auto transmitter 972 * flow control 973 */ 974 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 975 max310x_port_update(port, MAX310X_MODE1_REG, 976 MAX310X_MODE1_TXDIS_BIT, 977 MAX310X_MODE1_TXDIS_BIT); 978 } 979 980 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 981 982 if (termios->c_cflag & CRTSCTS) { 983 /* Enable AUTORTS and AUTOCTS */ 984 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 985 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 986 MAX310X_FLOWCTRL_AUTORTS_BIT; 987 } 988 if (termios->c_iflag & IXON) 989 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 990 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 991 if (termios->c_iflag & IXOFF) { 992 port->status |= UPSTAT_AUTOXOFF; 993 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 994 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 995 } 996 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 997 998 /* Enable transmitter after disabling AutoCTS and auto transmitter 999 * flow control 1000 */ 1001 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 1002 max310x_port_update(port, MAX310X_MODE1_REG, 1003 MAX310X_MODE1_TXDIS_BIT, 1004 0); 1005 } 1006 1007 /* Get baud rate generator configuration */ 1008 baud = uart_get_baud_rate(port, termios, old, 1009 port->uartclk / 16 / 0xffff, 1010 port->uartclk / 4); 1011 1012 /* Setup baudrate generator */ 1013 baud = max310x_set_baud(port, baud); 1014 1015 /* Update timeout according to new baud rate */ 1016 uart_update_timeout(port, termios->c_cflag, baud); 1017 } 1018 1019 static void max310x_rs_proc(struct work_struct *ws) 1020 { 1021 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1022 unsigned int delay, mode1 = 0, mode2 = 0; 1023 1024 delay = (one->port.rs485.delay_rts_before_send << 4) | 1025 one->port.rs485.delay_rts_after_send; 1026 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1027 1028 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1029 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1030 1031 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1032 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1033 } 1034 1035 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1036 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1037 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1038 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1039 } 1040 1041 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1042 struct serial_rs485 *rs485) 1043 { 1044 struct max310x_one *one = to_max310x_port(port); 1045 1046 if ((rs485->delay_rts_before_send > 0x0f) || 1047 (rs485->delay_rts_after_send > 0x0f)) 1048 return -ERANGE; 1049 1050 port->rs485 = *rs485; 1051 1052 schedule_work(&one->rs_work); 1053 1054 return 0; 1055 } 1056 1057 static int max310x_startup(struct uart_port *port) 1058 { 1059 struct max310x_port *s = dev_get_drvdata(port->dev); 1060 unsigned int val; 1061 1062 s->devtype->power(port, 1); 1063 1064 /* Configure MODE1 register */ 1065 max310x_port_update(port, MAX310X_MODE1_REG, 1066 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1067 1068 /* Configure MODE2 register & Reset FIFOs*/ 1069 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1070 max310x_port_write(port, MAX310X_MODE2_REG, val); 1071 max310x_port_update(port, MAX310X_MODE2_REG, 1072 MAX310X_MODE2_FIFORST_BIT, 0); 1073 1074 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1075 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1076 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1077 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1078 1079 if (port->rs485.flags & SER_RS485_ENABLED) { 1080 max310x_port_update(port, MAX310X_MODE1_REG, 1081 MAX310X_MODE1_TRNSCVCTRL_BIT, 1082 MAX310X_MODE1_TRNSCVCTRL_BIT); 1083 1084 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1085 max310x_port_update(port, MAX310X_MODE2_REG, 1086 MAX310X_MODE2_ECHOSUPR_BIT, 1087 MAX310X_MODE2_ECHOSUPR_BIT); 1088 } 1089 1090 /* Configure flow control levels */ 1091 /* Flow control halt level 96, resume level 48 */ 1092 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1093 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1094 1095 /* Clear IRQ status register */ 1096 max310x_port_read(port, MAX310X_IRQSTS_REG); 1097 1098 /* Enable RX, TX, CTS change interrupts */ 1099 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1100 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1101 1102 return 0; 1103 } 1104 1105 static void max310x_shutdown(struct uart_port *port) 1106 { 1107 struct max310x_port *s = dev_get_drvdata(port->dev); 1108 1109 /* Disable all interrupts */ 1110 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1111 1112 s->devtype->power(port, 0); 1113 } 1114 1115 static const char *max310x_type(struct uart_port *port) 1116 { 1117 struct max310x_port *s = dev_get_drvdata(port->dev); 1118 1119 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1120 } 1121 1122 static int max310x_request_port(struct uart_port *port) 1123 { 1124 /* Do nothing */ 1125 return 0; 1126 } 1127 1128 static void max310x_config_port(struct uart_port *port, int flags) 1129 { 1130 if (flags & UART_CONFIG_TYPE) 1131 port->type = PORT_MAX310X; 1132 } 1133 1134 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1135 { 1136 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1137 return -EINVAL; 1138 if (s->irq != port->irq) 1139 return -EINVAL; 1140 1141 return 0; 1142 } 1143 1144 static void max310x_null_void(struct uart_port *port) 1145 { 1146 /* Do nothing */ 1147 } 1148 1149 static const struct uart_ops max310x_ops = { 1150 .tx_empty = max310x_tx_empty, 1151 .set_mctrl = max310x_set_mctrl, 1152 .get_mctrl = max310x_get_mctrl, 1153 .stop_tx = max310x_null_void, 1154 .start_tx = max310x_start_tx, 1155 .stop_rx = max310x_null_void, 1156 .break_ctl = max310x_break_ctl, 1157 .startup = max310x_startup, 1158 .shutdown = max310x_shutdown, 1159 .set_termios = max310x_set_termios, 1160 .type = max310x_type, 1161 .request_port = max310x_request_port, 1162 .release_port = max310x_null_void, 1163 .config_port = max310x_config_port, 1164 .verify_port = max310x_verify_port, 1165 }; 1166 1167 static int __maybe_unused max310x_suspend(struct device *dev) 1168 { 1169 struct max310x_port *s = dev_get_drvdata(dev); 1170 int i; 1171 1172 for (i = 0; i < s->devtype->nr; i++) { 1173 uart_suspend_port(&max310x_uart, &s->p[i].port); 1174 s->devtype->power(&s->p[i].port, 0); 1175 } 1176 1177 return 0; 1178 } 1179 1180 static int __maybe_unused max310x_resume(struct device *dev) 1181 { 1182 struct max310x_port *s = dev_get_drvdata(dev); 1183 int i; 1184 1185 for (i = 0; i < s->devtype->nr; i++) { 1186 s->devtype->power(&s->p[i].port, 1); 1187 uart_resume_port(&max310x_uart, &s->p[i].port); 1188 } 1189 1190 return 0; 1191 } 1192 1193 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1194 1195 #ifdef CONFIG_GPIOLIB 1196 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1197 { 1198 unsigned int val; 1199 struct max310x_port *s = gpiochip_get_data(chip); 1200 struct uart_port *port = &s->p[offset / 4].port; 1201 1202 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1203 1204 return !!((val >> 4) & (1 << (offset % 4))); 1205 } 1206 1207 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1208 { 1209 struct max310x_port *s = gpiochip_get_data(chip); 1210 struct uart_port *port = &s->p[offset / 4].port; 1211 1212 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1213 value ? 1 << (offset % 4) : 0); 1214 } 1215 1216 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1217 { 1218 struct max310x_port *s = gpiochip_get_data(chip); 1219 struct uart_port *port = &s->p[offset / 4].port; 1220 1221 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1222 1223 return 0; 1224 } 1225 1226 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1227 unsigned offset, int value) 1228 { 1229 struct max310x_port *s = gpiochip_get_data(chip); 1230 struct uart_port *port = &s->p[offset / 4].port; 1231 1232 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1233 value ? 1 << (offset % 4) : 0); 1234 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1235 1 << (offset % 4)); 1236 1237 return 0; 1238 } 1239 1240 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1241 unsigned long config) 1242 { 1243 struct max310x_port *s = gpiochip_get_data(chip); 1244 struct uart_port *port = &s->p[offset / 4].port; 1245 1246 switch (pinconf_to_config_param(config)) { 1247 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1248 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1249 1 << ((offset % 4) + 4), 1250 1 << ((offset % 4) + 4)); 1251 return 0; 1252 case PIN_CONFIG_DRIVE_PUSH_PULL: 1253 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1254 1 << ((offset % 4) + 4), 0); 1255 return 0; 1256 default: 1257 return -ENOTSUPP; 1258 } 1259 } 1260 #endif 1261 1262 static const struct serial_rs485 max310x_rs485_supported = { 1263 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1264 .delay_rts_before_send = 1, 1265 .delay_rts_after_send = 1, 1266 }; 1267 1268 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1269 const struct max310x_if_cfg *if_cfg, 1270 struct regmap *regmaps[], int irq) 1271 { 1272 int i, ret, fmin, fmax, freq; 1273 struct max310x_port *s; 1274 u32 uartclk = 0; 1275 bool xtal; 1276 1277 for (i = 0; i < devtype->nr; i++) 1278 if (IS_ERR(regmaps[i])) 1279 return PTR_ERR(regmaps[i]); 1280 1281 /* Alloc port structure */ 1282 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1283 if (!s) { 1284 dev_err(dev, "Error allocating port structure\n"); 1285 return -ENOMEM; 1286 } 1287 1288 /* Always ask for fixed clock rate from a property. */ 1289 device_property_read_u32(dev, "clock-frequency", &uartclk); 1290 1291 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1292 if (xtal) 1293 s->clk = devm_clk_get_optional(dev, "xtal"); 1294 else 1295 s->clk = devm_clk_get_optional(dev, "osc"); 1296 if (IS_ERR(s->clk)) 1297 return PTR_ERR(s->clk); 1298 1299 ret = clk_prepare_enable(s->clk); 1300 if (ret) 1301 return ret; 1302 1303 freq = clk_get_rate(s->clk); 1304 if (freq == 0) 1305 freq = uartclk; 1306 if (freq == 0) { 1307 dev_err(dev, "Cannot get clock rate\n"); 1308 ret = -EINVAL; 1309 goto out_clk; 1310 } 1311 1312 if (xtal) { 1313 fmin = 1000000; 1314 fmax = 4000000; 1315 } else { 1316 fmin = 500000; 1317 fmax = 35000000; 1318 } 1319 1320 /* Check frequency limits */ 1321 if (freq < fmin || freq > fmax) { 1322 ret = -ERANGE; 1323 goto out_clk; 1324 } 1325 1326 s->regmap = regmaps[0]; 1327 s->devtype = devtype; 1328 s->if_cfg = if_cfg; 1329 dev_set_drvdata(dev, s); 1330 1331 /* Check device to ensure we are talking to what we expect */ 1332 ret = devtype->detect(dev); 1333 if (ret) 1334 goto out_clk; 1335 1336 for (i = 0; i < devtype->nr; i++) { 1337 /* Reset port */ 1338 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1339 MAX310X_MODE2_RST_BIT); 1340 /* Clear port reset */ 1341 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1342 1343 /* Wait for port startup */ 1344 do { 1345 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &ret); 1346 } while (ret != 0x01); 1347 1348 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1349 } 1350 1351 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1352 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1353 1354 for (i = 0; i < devtype->nr; i++) { 1355 unsigned int line; 1356 1357 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1358 if (line == MAX310X_UART_NRMAX) { 1359 ret = -ERANGE; 1360 goto out_uart; 1361 } 1362 1363 /* Initialize port data */ 1364 s->p[i].port.line = line; 1365 s->p[i].port.dev = dev; 1366 s->p[i].port.irq = irq; 1367 s->p[i].port.type = PORT_MAX310X; 1368 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1369 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1370 s->p[i].port.iotype = UPIO_PORT; 1371 s->p[i].port.iobase = i; 1372 /* 1373 * Use all ones as membase to make sure uart_configure_port() in 1374 * serial_core.c does not abort for SPI/I2C devices where the 1375 * membase address is not applicable. 1376 */ 1377 s->p[i].port.membase = (void __iomem *)~0; 1378 s->p[i].port.uartclk = uartclk; 1379 s->p[i].port.rs485_config = max310x_rs485_config; 1380 s->p[i].port.rs485_supported = max310x_rs485_supported; 1381 s->p[i].port.ops = &max310x_ops; 1382 s->p[i].regmap = regmaps[i]; 1383 1384 /* Disable all interrupts */ 1385 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1386 /* Clear IRQ status register */ 1387 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1388 /* Initialize queue for start TX */ 1389 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1390 /* Initialize queue for changing LOOPBACK mode */ 1391 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1392 /* Initialize queue for changing RS485 mode */ 1393 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1394 1395 /* Register port */ 1396 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1397 if (ret) { 1398 s->p[i].port.dev = NULL; 1399 goto out_uart; 1400 } 1401 set_bit(line, max310x_lines); 1402 1403 /* Go to suspend mode */ 1404 devtype->power(&s->p[i].port, 0); 1405 } 1406 1407 #ifdef CONFIG_GPIOLIB 1408 /* Setup GPIO controller */ 1409 s->gpio.owner = THIS_MODULE; 1410 s->gpio.parent = dev; 1411 s->gpio.label = devtype->name; 1412 s->gpio.direction_input = max310x_gpio_direction_input; 1413 s->gpio.get = max310x_gpio_get; 1414 s->gpio.direction_output= max310x_gpio_direction_output; 1415 s->gpio.set = max310x_gpio_set; 1416 s->gpio.set_config = max310x_gpio_set_config; 1417 s->gpio.base = -1; 1418 s->gpio.ngpio = devtype->nr * 4; 1419 s->gpio.can_sleep = 1; 1420 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1421 if (ret) 1422 goto out_uart; 1423 #endif 1424 1425 /* Setup interrupt */ 1426 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1427 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1428 if (!ret) 1429 return 0; 1430 1431 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1432 1433 out_uart: 1434 for (i = 0; i < devtype->nr; i++) { 1435 if (s->p[i].port.dev) { 1436 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1437 clear_bit(s->p[i].port.line, max310x_lines); 1438 } 1439 } 1440 1441 out_clk: 1442 clk_disable_unprepare(s->clk); 1443 1444 return ret; 1445 } 1446 1447 static void max310x_remove(struct device *dev) 1448 { 1449 struct max310x_port *s = dev_get_drvdata(dev); 1450 int i; 1451 1452 for (i = 0; i < s->devtype->nr; i++) { 1453 cancel_work_sync(&s->p[i].tx_work); 1454 cancel_work_sync(&s->p[i].md_work); 1455 cancel_work_sync(&s->p[i].rs_work); 1456 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1457 clear_bit(s->p[i].port.line, max310x_lines); 1458 s->devtype->power(&s->p[i].port, 0); 1459 } 1460 1461 clk_disable_unprepare(s->clk); 1462 } 1463 1464 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1465 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1466 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1467 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1468 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1469 { } 1470 }; 1471 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1472 1473 static struct regmap_config regcfg = { 1474 .reg_bits = 8, 1475 .val_bits = 8, 1476 .write_flag_mask = MAX310X_WRITE_BIT, 1477 .cache_type = REGCACHE_RBTREE, 1478 .max_register = MAX310X_REG_1F, 1479 .writeable_reg = max310x_reg_writeable, 1480 .volatile_reg = max310x_reg_volatile, 1481 .precious_reg = max310x_reg_precious, 1482 .writeable_noinc_reg = max310x_reg_noinc, 1483 .readable_noinc_reg = max310x_reg_noinc, 1484 .max_raw_read = MAX310X_FIFO_SIZE, 1485 .max_raw_write = MAX310X_FIFO_SIZE, 1486 }; 1487 1488 #ifdef CONFIG_SPI_MASTER 1489 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1490 { 1491 struct max310x_port *s = dev_get_drvdata(dev); 1492 1493 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1494 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1495 } 1496 1497 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1498 .extended_reg_enable = max310x_spi_extended_reg_enable, 1499 .rev_id_reg = MAX310X_SPI_REVID_EXTREG, 1500 }; 1501 1502 static int max310x_spi_probe(struct spi_device *spi) 1503 { 1504 const struct max310x_devtype *devtype; 1505 struct regmap *regmaps[4]; 1506 unsigned int i; 1507 int ret; 1508 1509 /* Setup SPI bus */ 1510 spi->bits_per_word = 8; 1511 spi->mode = spi->mode ? : SPI_MODE_0; 1512 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1513 ret = spi_setup(spi); 1514 if (ret) 1515 return ret; 1516 1517 devtype = device_get_match_data(&spi->dev); 1518 if (!devtype) 1519 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; 1520 1521 for (i = 0; i < devtype->nr; i++) { 1522 u8 port_mask = i * 0x20; 1523 regcfg.read_flag_mask = port_mask; 1524 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1525 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1526 } 1527 1528 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1529 } 1530 1531 static void max310x_spi_remove(struct spi_device *spi) 1532 { 1533 max310x_remove(&spi->dev); 1534 } 1535 1536 static const struct spi_device_id max310x_id_table[] = { 1537 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1538 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1539 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1540 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1541 { } 1542 }; 1543 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1544 1545 static struct spi_driver max310x_spi_driver = { 1546 .driver = { 1547 .name = MAX310X_NAME, 1548 .of_match_table = max310x_dt_ids, 1549 .pm = &max310x_pm_ops, 1550 }, 1551 .probe = max310x_spi_probe, 1552 .remove = max310x_spi_remove, 1553 .id_table = max310x_id_table, 1554 }; 1555 #endif 1556 1557 #ifdef CONFIG_I2C 1558 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1559 { 1560 return 0; 1561 } 1562 1563 static struct regmap_config regcfg_i2c = { 1564 .reg_bits = 8, 1565 .val_bits = 8, 1566 .cache_type = REGCACHE_RBTREE, 1567 .writeable_reg = max310x_reg_writeable, 1568 .volatile_reg = max310x_reg_volatile, 1569 .precious_reg = max310x_reg_precious, 1570 .max_register = MAX310X_I2C_REVID_EXTREG, 1571 .writeable_noinc_reg = max310x_reg_noinc, 1572 .readable_noinc_reg = max310x_reg_noinc, 1573 .max_raw_read = MAX310X_FIFO_SIZE, 1574 .max_raw_write = MAX310X_FIFO_SIZE, 1575 }; 1576 1577 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1578 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1579 .rev_id_reg = MAX310X_I2C_REVID_EXTREG, 1580 }; 1581 1582 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1583 unsigned int nr) 1584 { 1585 /* 1586 * For MAX14830 and MAX3109, the slave address depends on what the 1587 * A0 and A1 pins are tied to. 1588 * See Table I2C Address Map of the datasheet. 1589 * Based on that table, the following formulas were determined. 1590 * UART1 - UART0 = 0x10 1591 * UART2 - UART1 = 0x20 + 0x10 1592 * UART3 - UART2 = 0x10 1593 */ 1594 1595 addr -= nr * 0x10; 1596 1597 if (nr >= 2) 1598 addr -= 0x20; 1599 1600 return addr; 1601 } 1602 1603 static int max310x_i2c_probe(struct i2c_client *client) 1604 { 1605 const struct max310x_devtype *devtype = 1606 device_get_match_data(&client->dev); 1607 struct i2c_client *port_client; 1608 struct regmap *regmaps[4]; 1609 unsigned int i; 1610 u8 port_addr; 1611 1612 if (client->addr < devtype->slave_addr.min || 1613 client->addr > devtype->slave_addr.max) 1614 return dev_err_probe(&client->dev, -EINVAL, 1615 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1616 client->addr, devtype->slave_addr.min, 1617 devtype->slave_addr.max); 1618 1619 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1620 1621 for (i = 1; i < devtype->nr; i++) { 1622 port_addr = max310x_i2c_slave_addr(client->addr, i); 1623 port_client = devm_i2c_new_dummy_device(&client->dev, 1624 client->adapter, 1625 port_addr); 1626 1627 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1628 } 1629 1630 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1631 regmaps, client->irq); 1632 } 1633 1634 static void max310x_i2c_remove(struct i2c_client *client) 1635 { 1636 max310x_remove(&client->dev); 1637 } 1638 1639 static struct i2c_driver max310x_i2c_driver = { 1640 .driver = { 1641 .name = MAX310X_NAME, 1642 .of_match_table = max310x_dt_ids, 1643 .pm = &max310x_pm_ops, 1644 }, 1645 .probe = max310x_i2c_probe, 1646 .remove = max310x_i2c_remove, 1647 }; 1648 #endif 1649 1650 static int __init max310x_uart_init(void) 1651 { 1652 int ret; 1653 1654 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1655 1656 ret = uart_register_driver(&max310x_uart); 1657 if (ret) 1658 return ret; 1659 1660 #ifdef CONFIG_SPI_MASTER 1661 ret = spi_register_driver(&max310x_spi_driver); 1662 if (ret) 1663 goto err_spi_register; 1664 #endif 1665 1666 #ifdef CONFIG_I2C 1667 ret = i2c_add_driver(&max310x_i2c_driver); 1668 if (ret) 1669 goto err_i2c_register; 1670 #endif 1671 1672 return 0; 1673 1674 #ifdef CONFIG_I2C 1675 err_i2c_register: 1676 spi_unregister_driver(&max310x_spi_driver); 1677 #endif 1678 1679 err_spi_register: 1680 uart_unregister_driver(&max310x_uart); 1681 1682 return ret; 1683 } 1684 module_init(max310x_uart_init); 1685 1686 static void __exit max310x_uart_exit(void) 1687 { 1688 #ifdef CONFIG_I2C 1689 i2c_del_driver(&max310x_i2c_driver); 1690 #endif 1691 1692 #ifdef CONFIG_SPI_MASTER 1693 spi_unregister_driver(&max310x_spi_driver); 1694 #endif 1695 1696 uart_unregister_driver(&max310x_uart); 1697 } 1698 module_exit(max310x_uart_exit); 1699 1700 MODULE_LICENSE("GPL"); 1701 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1702 MODULE_DESCRIPTION("MAX310X serial driver"); 1703