1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Maxim (Dallas) MAX3107/8/9, MAX14830 serial driver 4 * 5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru> 6 * 7 * Based on max3100.c, by Christian Pellegrin <chripell@evolware.org> 8 * Based on max3110.c, by Feng Tang <feng.tang@intel.com> 9 * Based on max3107.c, by Aavamobile 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/gpio/driver.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/mod_devicetable.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/serial_core.h> 23 #include <linux/serial.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/spi/spi.h> 27 #include <linux/uaccess.h> 28 29 #define MAX310X_NAME "max310x" 30 #define MAX310X_MAJOR 204 31 #define MAX310X_MINOR 209 32 #define MAX310X_UART_NRMAX 16 33 34 /* MAX310X register definitions */ 35 #define MAX310X_RHR_REG (0x00) /* RX FIFO */ 36 #define MAX310X_THR_REG (0x00) /* TX FIFO */ 37 #define MAX310X_IRQEN_REG (0x01) /* IRQ enable */ 38 #define MAX310X_IRQSTS_REG (0x02) /* IRQ status */ 39 #define MAX310X_LSR_IRQEN_REG (0x03) /* LSR IRQ enable */ 40 #define MAX310X_LSR_IRQSTS_REG (0x04) /* LSR IRQ status */ 41 #define MAX310X_REG_05 (0x05) 42 #define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05 /* Special char IRQ en */ 43 #define MAX310X_SPCHR_IRQSTS_REG (0x06) /* Special char IRQ status */ 44 #define MAX310X_STS_IRQEN_REG (0x07) /* Status IRQ enable */ 45 #define MAX310X_STS_IRQSTS_REG (0x08) /* Status IRQ status */ 46 #define MAX310X_MODE1_REG (0x09) /* MODE1 */ 47 #define MAX310X_MODE2_REG (0x0a) /* MODE2 */ 48 #define MAX310X_LCR_REG (0x0b) /* LCR */ 49 #define MAX310X_RXTO_REG (0x0c) /* RX timeout */ 50 #define MAX310X_HDPIXDELAY_REG (0x0d) /* Auto transceiver delays */ 51 #define MAX310X_IRDA_REG (0x0e) /* IRDA settings */ 52 #define MAX310X_FLOWLVL_REG (0x0f) /* Flow control levels */ 53 #define MAX310X_FIFOTRIGLVL_REG (0x10) /* FIFO IRQ trigger levels */ 54 #define MAX310X_TXFIFOLVL_REG (0x11) /* TX FIFO level */ 55 #define MAX310X_RXFIFOLVL_REG (0x12) /* RX FIFO level */ 56 #define MAX310X_FLOWCTRL_REG (0x13) /* Flow control */ 57 #define MAX310X_XON1_REG (0x14) /* XON1 character */ 58 #define MAX310X_XON2_REG (0x15) /* XON2 character */ 59 #define MAX310X_XOFF1_REG (0x16) /* XOFF1 character */ 60 #define MAX310X_XOFF2_REG (0x17) /* XOFF2 character */ 61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */ 62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */ 63 #define MAX310X_PLLCFG_REG (0x1a) /* PLL config */ 64 #define MAX310X_BRGCFG_REG (0x1b) /* Baud rate generator conf */ 65 #define MAX310X_BRGDIVLSB_REG (0x1c) /* Baud rate divisor LSB */ 66 #define MAX310X_BRGDIVMSB_REG (0x1d) /* Baud rate divisor MSB */ 67 #define MAX310X_CLKSRC_REG (0x1e) /* Clock source */ 68 #define MAX310X_REG_1F (0x1f) 69 70 #define MAX310X_REVID_REG MAX310X_REG_1F /* Revision ID */ 71 72 #define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F /* Global IRQ (RO) */ 73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */ 74 75 /* Extended registers */ 76 #define MAX310X_SPI_REVID_EXTREG MAX310X_REG_05 /* Revision ID */ 77 #define MAX310X_I2C_REVID_EXTREG (0x25) /* Revision ID */ 78 79 /* IRQ register bits */ 80 #define MAX310X_IRQ_LSR_BIT (1 << 0) /* LSR interrupt */ 81 #define MAX310X_IRQ_SPCHR_BIT (1 << 1) /* Special char interrupt */ 82 #define MAX310X_IRQ_STS_BIT (1 << 2) /* Status interrupt */ 83 #define MAX310X_IRQ_RXFIFO_BIT (1 << 3) /* RX FIFO interrupt */ 84 #define MAX310X_IRQ_TXFIFO_BIT (1 << 4) /* TX FIFO interrupt */ 85 #define MAX310X_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */ 86 #define MAX310X_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */ 87 #define MAX310X_IRQ_CTS_BIT (1 << 7) /* CTS interrupt */ 88 89 /* LSR register bits */ 90 #define MAX310X_LSR_RXTO_BIT (1 << 0) /* RX timeout */ 91 #define MAX310X_LSR_RXOVR_BIT (1 << 1) /* RX overrun */ 92 #define MAX310X_LSR_RXPAR_BIT (1 << 2) /* RX parity error */ 93 #define MAX310X_LSR_FRERR_BIT (1 << 3) /* Frame error */ 94 #define MAX310X_LSR_RXBRK_BIT (1 << 4) /* RX break */ 95 #define MAX310X_LSR_RXNOISE_BIT (1 << 5) /* RX noise */ 96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */ 97 98 /* Special character register bits */ 99 #define MAX310X_SPCHR_XON1_BIT (1 << 0) /* XON1 character */ 100 #define MAX310X_SPCHR_XON2_BIT (1 << 1) /* XON2 character */ 101 #define MAX310X_SPCHR_XOFF1_BIT (1 << 2) /* XOFF1 character */ 102 #define MAX310X_SPCHR_XOFF2_BIT (1 << 3) /* XOFF2 character */ 103 #define MAX310X_SPCHR_BREAK_BIT (1 << 4) /* RX break */ 104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */ 105 106 /* Status register bits */ 107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */ 108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */ 109 #define MAX310X_STS_GPIO2_BIT (1 << 2) /* GPIO 2 interrupt */ 110 #define MAX310X_STS_GPIO3_BIT (1 << 3) /* GPIO 3 interrupt */ 111 #define MAX310X_STS_CLKREADY_BIT (1 << 5) /* Clock ready */ 112 #define MAX310X_STS_SLEEP_BIT (1 << 6) /* Sleep interrupt */ 113 114 /* MODE1 register bits */ 115 #define MAX310X_MODE1_RXDIS_BIT (1 << 0) /* RX disable */ 116 #define MAX310X_MODE1_TXDIS_BIT (1 << 1) /* TX disable */ 117 #define MAX310X_MODE1_TXHIZ_BIT (1 << 2) /* TX pin three-state */ 118 #define MAX310X_MODE1_RTSHIZ_BIT (1 << 3) /* RTS pin three-state */ 119 #define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4) /* Transceiver ctrl enable */ 120 #define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5) /* Force sleep mode */ 121 #define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6) /* Auto sleep enable */ 122 #define MAX310X_MODE1_IRQSEL_BIT (1 << 7) /* IRQ pin enable */ 123 124 /* MODE2 register bits */ 125 #define MAX310X_MODE2_RST_BIT (1 << 0) /* Chip reset */ 126 #define MAX310X_MODE2_FIFORST_BIT (1 << 1) /* FIFO reset */ 127 #define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2) /* RX FIFO INT invert */ 128 #define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3) /* RX FIFO empty INT invert */ 129 #define MAX310X_MODE2_SPCHR_BIT (1 << 4) /* Special chr detect enable */ 130 #define MAX310X_MODE2_LOOPBACK_BIT (1 << 5) /* Internal loopback enable */ 131 #define MAX310X_MODE2_MULTIDROP_BIT (1 << 6) /* 9-bit multidrop enable */ 132 #define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7) /* ECHO suppression enable */ 133 134 /* LCR register bits */ 135 #define MAX310X_LCR_LENGTH0_BIT (1 << 0) /* Word length bit 0 */ 136 #define MAX310X_LCR_LENGTH1_BIT (1 << 1) /* Word length bit 1 137 * 138 * Word length bits table: 139 * 00 -> 5 bit words 140 * 01 -> 6 bit words 141 * 10 -> 7 bit words 142 * 11 -> 8 bit words 143 */ 144 #define MAX310X_LCR_STOPLEN_BIT (1 << 2) /* STOP length bit 145 * 146 * STOP length bit table: 147 * 0 -> 1 stop bit 148 * 1 -> 1-1.5 stop bits if 149 * word length is 5, 150 * 2 stop bits otherwise 151 */ 152 #define MAX310X_LCR_PARITY_BIT (1 << 3) /* Parity bit enable */ 153 #define MAX310X_LCR_EVENPARITY_BIT (1 << 4) /* Even parity bit enable */ 154 #define MAX310X_LCR_FORCEPARITY_BIT (1 << 5) /* 9-bit multidrop parity */ 155 #define MAX310X_LCR_TXBREAK_BIT (1 << 6) /* TX break enable */ 156 #define MAX310X_LCR_RTS_BIT (1 << 7) /* RTS pin control */ 157 158 /* IRDA register bits */ 159 #define MAX310X_IRDA_IRDAEN_BIT (1 << 0) /* IRDA mode enable */ 160 #define MAX310X_IRDA_SIR_BIT (1 << 1) /* SIR mode enable */ 161 162 /* Flow control trigger level register masks */ 163 #define MAX310X_FLOWLVL_HALT_MASK (0x000f) /* Flow control halt level */ 164 #define MAX310X_FLOWLVL_RES_MASK (0x00f0) /* Flow control resume level */ 165 #define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f) 166 #define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4) 167 168 /* FIFO interrupt trigger level register masks */ 169 #define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f) /* TX FIFO trigger level */ 170 #define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0) /* RX FIFO trigger level */ 171 #define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f) 172 #define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4) 173 174 /* Flow control register bits */ 175 #define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0) /* Auto RTS flow ctrl enable */ 176 #define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1) /* Auto CTS flow ctrl enable */ 177 #define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2) /* Enables that GPIO inputs 178 * are used in conjunction with 179 * XOFF2 for definition of 180 * special character */ 181 #define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3) /* Auto SW flow ctrl enable */ 182 #define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4) /* SWFLOW bit 0 */ 183 #define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5) /* SWFLOW bit 1 184 * 185 * SWFLOW bits 1 & 0 table: 186 * 00 -> no transmitter flow 187 * control 188 * 01 -> receiver compares 189 * XON2 and XOFF2 190 * and controls 191 * transmitter 192 * 10 -> receiver compares 193 * XON1 and XOFF1 194 * and controls 195 * transmitter 196 * 11 -> receiver compares 197 * XON1, XON2, XOFF1 and 198 * XOFF2 and controls 199 * transmitter 200 */ 201 #define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6) /* SWFLOW bit 2 */ 202 #define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7) /* SWFLOW bit 3 203 * 204 * SWFLOW bits 3 & 2 table: 205 * 00 -> no received flow 206 * control 207 * 01 -> transmitter generates 208 * XON2 and XOFF2 209 * 10 -> transmitter generates 210 * XON1 and XOFF1 211 * 11 -> transmitter generates 212 * XON1, XON2, XOFF1 and 213 * XOFF2 214 */ 215 216 /* PLL configuration register masks */ 217 #define MAX310X_PLLCFG_PREDIV_MASK (0x3f) /* PLL predivision value */ 218 #define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0) /* PLL multiplication factor */ 219 220 /* Baud rate generator configuration register bits */ 221 #define MAX310X_BRGCFG_2XMODE_BIT (1 << 4) /* Double baud rate */ 222 #define MAX310X_BRGCFG_4XMODE_BIT (1 << 5) /* Quadruple baud rate */ 223 224 /* Clock source register bits */ 225 #define MAX310X_CLKSRC_CRYST_BIT (1 << 1) /* Crystal osc enable */ 226 #define MAX310X_CLKSRC_PLL_BIT (1 << 2) /* PLL enable */ 227 #define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3) /* PLL bypass */ 228 #define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4) /* External clock enable */ 229 #define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7) /* Baud clk to RTS pin */ 230 231 /* Global commands */ 232 #define MAX310X_EXTREG_ENBL (0xce) 233 #define MAX310X_EXTREG_DSBL (0xcd) 234 235 /* Misc definitions */ 236 #define MAX310X_FIFO_SIZE (128) 237 #define MAX310x_REV_MASK (0xf8) 238 #define MAX310X_WRITE_BIT 0x80 239 240 /* MAX3107 specific */ 241 #define MAX3107_REV_ID (0xa0) 242 243 /* MAX3109 specific */ 244 #define MAX3109_REV_ID (0xc0) 245 246 /* MAX14830 specific */ 247 #define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6) /* Clock Disable */ 248 #define MAX14830_REV_ID (0xb0) 249 250 struct max310x_if_cfg { 251 int (*extended_reg_enable)(struct device *dev, bool enable); 252 253 unsigned int rev_id_reg; 254 }; 255 256 struct max310x_devtype { 257 struct { 258 unsigned short min; 259 unsigned short max; 260 } slave_addr; 261 char name[9]; 262 int nr; 263 u8 mode1; 264 int (*detect)(struct device *); 265 void (*power)(struct uart_port *, int); 266 }; 267 268 struct max310x_one { 269 struct uart_port port; 270 struct work_struct tx_work; 271 struct work_struct md_work; 272 struct work_struct rs_work; 273 struct regmap *regmap; 274 275 u8 rx_buf[MAX310X_FIFO_SIZE]; 276 }; 277 #define to_max310x_port(_port) \ 278 container_of(_port, struct max310x_one, port) 279 280 struct max310x_port { 281 const struct max310x_devtype *devtype; 282 const struct max310x_if_cfg *if_cfg; 283 struct regmap *regmap; 284 struct clk *clk; 285 #ifdef CONFIG_GPIOLIB 286 struct gpio_chip gpio; 287 #endif 288 struct max310x_one p[]; 289 }; 290 291 static struct uart_driver max310x_uart = { 292 .owner = THIS_MODULE, 293 .driver_name = MAX310X_NAME, 294 .dev_name = "ttyMAX", 295 .major = MAX310X_MAJOR, 296 .minor = MAX310X_MINOR, 297 .nr = MAX310X_UART_NRMAX, 298 }; 299 300 static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX); 301 302 static u8 max310x_port_read(struct uart_port *port, u8 reg) 303 { 304 struct max310x_one *one = to_max310x_port(port); 305 unsigned int val = 0; 306 307 regmap_read(one->regmap, reg, &val); 308 309 return val; 310 } 311 312 static void max310x_port_write(struct uart_port *port, u8 reg, u8 val) 313 { 314 struct max310x_one *one = to_max310x_port(port); 315 316 regmap_write(one->regmap, reg, val); 317 } 318 319 static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val) 320 { 321 struct max310x_one *one = to_max310x_port(port); 322 323 regmap_update_bits(one->regmap, reg, mask, val); 324 } 325 326 static int max3107_detect(struct device *dev) 327 { 328 struct max310x_port *s = dev_get_drvdata(dev); 329 unsigned int val = 0; 330 int ret; 331 332 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val); 333 if (ret) 334 return ret; 335 336 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) { 337 dev_err(dev, 338 "%s ID 0x%02x does not match\n", s->devtype->name, val); 339 return -ENODEV; 340 } 341 342 return 0; 343 } 344 345 static int max3108_detect(struct device *dev) 346 { 347 struct max310x_port *s = dev_get_drvdata(dev); 348 unsigned int val = 0; 349 int ret; 350 351 /* MAX3108 have not REV ID register, we just check default value 352 * from clocksource register to make sure everything works. 353 */ 354 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val); 355 if (ret) 356 return ret; 357 358 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) { 359 dev_err(dev, "%s not present\n", s->devtype->name); 360 return -ENODEV; 361 } 362 363 return 0; 364 } 365 366 static int max3109_detect(struct device *dev) 367 { 368 struct max310x_port *s = dev_get_drvdata(dev); 369 unsigned int val = 0; 370 int ret; 371 372 ret = s->if_cfg->extended_reg_enable(dev, true); 373 if (ret) 374 return ret; 375 376 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 377 s->if_cfg->extended_reg_enable(dev, false); 378 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) { 379 dev_err(dev, 380 "%s ID 0x%02x does not match\n", s->devtype->name, val); 381 return -ENODEV; 382 } 383 384 return 0; 385 } 386 387 static void max310x_power(struct uart_port *port, int on) 388 { 389 max310x_port_update(port, MAX310X_MODE1_REG, 390 MAX310X_MODE1_FORCESLEEP_BIT, 391 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT); 392 if (on) 393 msleep(50); 394 } 395 396 static int max14830_detect(struct device *dev) 397 { 398 struct max310x_port *s = dev_get_drvdata(dev); 399 unsigned int val = 0; 400 int ret; 401 402 ret = s->if_cfg->extended_reg_enable(dev, true); 403 if (ret) 404 return ret; 405 406 regmap_read(s->regmap, s->if_cfg->rev_id_reg, &val); 407 s->if_cfg->extended_reg_enable(dev, false); 408 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) { 409 dev_err(dev, 410 "%s ID 0x%02x does not match\n", s->devtype->name, val); 411 return -ENODEV; 412 } 413 414 return 0; 415 } 416 417 static void max14830_power(struct uart_port *port, int on) 418 { 419 max310x_port_update(port, MAX310X_BRGCFG_REG, 420 MAX14830_BRGCFG_CLKDIS_BIT, 421 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT); 422 if (on) 423 msleep(50); 424 } 425 426 static const struct max310x_devtype max3107_devtype = { 427 .name = "MAX3107", 428 .nr = 1, 429 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT | MAX310X_MODE1_IRQSEL_BIT, 430 .detect = max3107_detect, 431 .power = max310x_power, 432 .slave_addr = { 433 .min = 0x2c, 434 .max = 0x2f, 435 }, 436 }; 437 438 static const struct max310x_devtype max3108_devtype = { 439 .name = "MAX3108", 440 .nr = 1, 441 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 442 .detect = max3108_detect, 443 .power = max310x_power, 444 .slave_addr = { 445 .min = 0x60, 446 .max = 0x6f, 447 }, 448 }; 449 450 static const struct max310x_devtype max3109_devtype = { 451 .name = "MAX3109", 452 .nr = 2, 453 .mode1 = MAX310X_MODE1_AUTOSLEEP_BIT, 454 .detect = max3109_detect, 455 .power = max310x_power, 456 .slave_addr = { 457 .min = 0x60, 458 .max = 0x6f, 459 }, 460 }; 461 462 static const struct max310x_devtype max14830_devtype = { 463 .name = "MAX14830", 464 .nr = 4, 465 .mode1 = MAX310X_MODE1_IRQSEL_BIT, 466 .detect = max14830_detect, 467 .power = max14830_power, 468 .slave_addr = { 469 .min = 0x60, 470 .max = 0x6f, 471 }, 472 }; 473 474 static bool max310x_reg_writeable(struct device *dev, unsigned int reg) 475 { 476 switch (reg) { 477 case MAX310X_IRQSTS_REG: 478 case MAX310X_LSR_IRQSTS_REG: 479 case MAX310X_SPCHR_IRQSTS_REG: 480 case MAX310X_STS_IRQSTS_REG: 481 case MAX310X_TXFIFOLVL_REG: 482 case MAX310X_RXFIFOLVL_REG: 483 return false; 484 default: 485 break; 486 } 487 488 return true; 489 } 490 491 static bool max310x_reg_volatile(struct device *dev, unsigned int reg) 492 { 493 switch (reg) { 494 case MAX310X_RHR_REG: 495 case MAX310X_IRQSTS_REG: 496 case MAX310X_LSR_IRQSTS_REG: 497 case MAX310X_SPCHR_IRQSTS_REG: 498 case MAX310X_STS_IRQSTS_REG: 499 case MAX310X_TXFIFOLVL_REG: 500 case MAX310X_RXFIFOLVL_REG: 501 case MAX310X_GPIODATA_REG: 502 case MAX310X_BRGDIVLSB_REG: 503 case MAX310X_REG_05: 504 case MAX310X_REG_1F: 505 return true; 506 default: 507 break; 508 } 509 510 return false; 511 } 512 513 static bool max310x_reg_precious(struct device *dev, unsigned int reg) 514 { 515 switch (reg) { 516 case MAX310X_RHR_REG: 517 case MAX310X_IRQSTS_REG: 518 case MAX310X_SPCHR_IRQSTS_REG: 519 case MAX310X_STS_IRQSTS_REG: 520 return true; 521 default: 522 break; 523 } 524 525 return false; 526 } 527 528 static int max310x_set_baud(struct uart_port *port, int baud) 529 { 530 unsigned int mode = 0, div = 0, frac = 0, c = 0, F = 0; 531 532 /* 533 * Calculate the integer divisor first. Select a proper mode 534 * in case if the requested baud is too high for the pre-defined 535 * clocks frequency. 536 */ 537 div = port->uartclk / baud; 538 if (div < 8) { 539 /* Mode x4 */ 540 c = 4; 541 mode = MAX310X_BRGCFG_4XMODE_BIT; 542 } else if (div < 16) { 543 /* Mode x2 */ 544 c = 8; 545 mode = MAX310X_BRGCFG_2XMODE_BIT; 546 } else { 547 c = 16; 548 } 549 550 /* Calculate the divisor in accordance with the fraction coefficient */ 551 div /= c; 552 F = c*baud; 553 554 /* Calculate the baud rate fraction */ 555 if (div > 0) 556 frac = (16*(port->uartclk % F)) / F; 557 else 558 div = 1; 559 560 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, div >> 8); 561 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div); 562 max310x_port_write(port, MAX310X_BRGCFG_REG, frac | mode); 563 564 /* Return the actual baud rate we just programmed */ 565 return (16*port->uartclk) / (c*(16*div + frac)); 566 } 567 568 static int max310x_update_best_err(unsigned long f, long *besterr) 569 { 570 /* Use baudrate 115200 for calculate error */ 571 long err = f % (460800 * 16); 572 573 if ((*besterr < 0) || (*besterr > err)) { 574 *besterr = err; 575 return 0; 576 } 577 578 return 1; 579 } 580 581 static u32 max310x_set_ref_clk(struct device *dev, struct max310x_port *s, 582 unsigned long freq, bool xtal) 583 { 584 unsigned int div, clksrc, pllcfg = 0; 585 long besterr = -1; 586 unsigned long fdiv, fmul, bestfreq = freq; 587 588 /* First, update error without PLL */ 589 max310x_update_best_err(freq, &besterr); 590 591 /* Try all possible PLL dividers */ 592 for (div = 1; (div <= 63) && besterr; div++) { 593 fdiv = DIV_ROUND_CLOSEST(freq, div); 594 595 /* Try multiplier 6 */ 596 fmul = fdiv * 6; 597 if ((fdiv >= 500000) && (fdiv <= 800000)) 598 if (!max310x_update_best_err(fmul, &besterr)) { 599 pllcfg = (0 << 6) | div; 600 bestfreq = fmul; 601 } 602 /* Try multiplier 48 */ 603 fmul = fdiv * 48; 604 if ((fdiv >= 850000) && (fdiv <= 1200000)) 605 if (!max310x_update_best_err(fmul, &besterr)) { 606 pllcfg = (1 << 6) | div; 607 bestfreq = fmul; 608 } 609 /* Try multiplier 96 */ 610 fmul = fdiv * 96; 611 if ((fdiv >= 425000) && (fdiv <= 1000000)) 612 if (!max310x_update_best_err(fmul, &besterr)) { 613 pllcfg = (2 << 6) | div; 614 bestfreq = fmul; 615 } 616 /* Try multiplier 144 */ 617 fmul = fdiv * 144; 618 if ((fdiv >= 390000) && (fdiv <= 667000)) 619 if (!max310x_update_best_err(fmul, &besterr)) { 620 pllcfg = (3 << 6) | div; 621 bestfreq = fmul; 622 } 623 } 624 625 /* Configure clock source */ 626 clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); 627 628 /* Configure PLL */ 629 if (pllcfg) { 630 clksrc |= MAX310X_CLKSRC_PLL_BIT; 631 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg); 632 } else 633 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT; 634 635 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc); 636 637 /* Wait for crystal */ 638 if (xtal) { 639 unsigned int val; 640 msleep(10); 641 regmap_read(s->regmap, MAX310X_STS_IRQSTS_REG, &val); 642 if (!(val & MAX310X_STS_CLKREADY_BIT)) { 643 dev_warn(dev, "clock is not stable yet\n"); 644 } 645 } 646 647 return bestfreq; 648 } 649 650 static void max310x_batch_write(struct uart_port *port, u8 *txbuf, unsigned int len) 651 { 652 struct max310x_one *one = to_max310x_port(port); 653 654 regmap_raw_write(one->regmap, MAX310X_THR_REG, txbuf, len); 655 } 656 657 static void max310x_batch_read(struct uart_port *port, u8 *rxbuf, unsigned int len) 658 { 659 struct max310x_one *one = to_max310x_port(port); 660 661 regmap_raw_read(one->regmap, MAX310X_RHR_REG, rxbuf, len); 662 } 663 664 static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen) 665 { 666 struct max310x_one *one = to_max310x_port(port); 667 unsigned int sts, ch, flag, i; 668 669 if (port->read_status_mask == MAX310X_LSR_RXOVR_BIT) { 670 /* We are just reading, happily ignoring any error conditions. 671 * Break condition, parity checking, framing errors -- they 672 * are all ignored. That means that we can do a batch-read. 673 * 674 * There is a small opportunity for race if the RX FIFO 675 * overruns while we're reading the buffer; the datasheets says 676 * that the LSR register applies to the "current" character. 677 * That's also the reason why we cannot do batched reads when 678 * asked to check the individual statuses. 679 * */ 680 681 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 682 max310x_batch_read(port, one->rx_buf, rxlen); 683 684 port->icount.rx += rxlen; 685 flag = TTY_NORMAL; 686 sts &= port->read_status_mask; 687 688 if (sts & MAX310X_LSR_RXOVR_BIT) { 689 dev_warn_ratelimited(port->dev, "Hardware RX FIFO overrun\n"); 690 port->icount.overrun++; 691 } 692 693 for (i = 0; i < (rxlen - 1); ++i) 694 uart_insert_char(port, sts, 0, one->rx_buf[i], flag); 695 696 /* 697 * Handle the overrun case for the last character only, since 698 * the RxFIFO overflow happens after it is pushed to the FIFO 699 * tail. 700 */ 701 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, 702 one->rx_buf[rxlen-1], flag); 703 704 } else { 705 if (unlikely(rxlen >= port->fifosize)) { 706 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n"); 707 port->icount.buf_overrun++; 708 /* Ensure sanity of RX level */ 709 rxlen = port->fifosize; 710 } 711 712 while (rxlen--) { 713 ch = max310x_port_read(port, MAX310X_RHR_REG); 714 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 715 716 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT | 717 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT; 718 719 port->icount.rx++; 720 flag = TTY_NORMAL; 721 722 if (unlikely(sts)) { 723 if (sts & MAX310X_LSR_RXBRK_BIT) { 724 port->icount.brk++; 725 if (uart_handle_break(port)) 726 continue; 727 } else if (sts & MAX310X_LSR_RXPAR_BIT) 728 port->icount.parity++; 729 else if (sts & MAX310X_LSR_FRERR_BIT) 730 port->icount.frame++; 731 else if (sts & MAX310X_LSR_RXOVR_BIT) 732 port->icount.overrun++; 733 734 sts &= port->read_status_mask; 735 if (sts & MAX310X_LSR_RXBRK_BIT) 736 flag = TTY_BREAK; 737 else if (sts & MAX310X_LSR_RXPAR_BIT) 738 flag = TTY_PARITY; 739 else if (sts & MAX310X_LSR_FRERR_BIT) 740 flag = TTY_FRAME; 741 else if (sts & MAX310X_LSR_RXOVR_BIT) 742 flag = TTY_OVERRUN; 743 } 744 745 if (uart_handle_sysrq_char(port, ch)) 746 continue; 747 748 if (sts & port->ignore_status_mask) 749 continue; 750 751 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag); 752 } 753 } 754 755 tty_flip_buffer_push(&port->state->port); 756 } 757 758 static void max310x_handle_tx(struct uart_port *port) 759 { 760 struct circ_buf *xmit = &port->state->xmit; 761 unsigned int txlen, to_send, until_end; 762 763 if (unlikely(port->x_char)) { 764 max310x_port_write(port, MAX310X_THR_REG, port->x_char); 765 port->icount.tx++; 766 port->x_char = 0; 767 return; 768 } 769 770 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 771 return; 772 773 /* Get length of data pending in circular buffer */ 774 to_send = uart_circ_chars_pending(xmit); 775 until_end = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 776 if (likely(to_send)) { 777 /* Limit to size of TX FIFO */ 778 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 779 txlen = port->fifosize - txlen; 780 to_send = (to_send > txlen) ? txlen : to_send; 781 782 if (until_end < to_send) { 783 /* It's a circ buffer -- wrap around. 784 * We could do that in one SPI transaction, but meh. */ 785 max310x_batch_write(port, xmit->buf + xmit->tail, until_end); 786 max310x_batch_write(port, xmit->buf, to_send - until_end); 787 } else { 788 max310x_batch_write(port, xmit->buf + xmit->tail, to_send); 789 } 790 uart_xmit_advance(port, to_send); 791 } 792 793 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 794 uart_write_wakeup(port); 795 } 796 797 static void max310x_start_tx(struct uart_port *port) 798 { 799 struct max310x_one *one = to_max310x_port(port); 800 801 schedule_work(&one->tx_work); 802 } 803 804 static irqreturn_t max310x_port_irq(struct max310x_port *s, int portno) 805 { 806 struct uart_port *port = &s->p[portno].port; 807 irqreturn_t res = IRQ_NONE; 808 809 do { 810 unsigned int ists, lsr, rxlen; 811 812 /* Read IRQ status & RX FIFO level */ 813 ists = max310x_port_read(port, MAX310X_IRQSTS_REG); 814 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG); 815 if (!ists && !rxlen) 816 break; 817 818 res = IRQ_HANDLED; 819 820 if (ists & MAX310X_IRQ_CTS_BIT) { 821 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG); 822 uart_handle_cts_change(port, lsr & MAX310X_LSR_CTS_BIT); 823 } 824 if (rxlen) 825 max310x_handle_rx(port, rxlen); 826 if (ists & MAX310X_IRQ_TXEMPTY_BIT) 827 max310x_start_tx(port); 828 } while (1); 829 return res; 830 } 831 832 static irqreturn_t max310x_ist(int irq, void *dev_id) 833 { 834 struct max310x_port *s = (struct max310x_port *)dev_id; 835 bool handled = false; 836 837 if (s->devtype->nr > 1) { 838 do { 839 unsigned int val = ~0; 840 841 WARN_ON_ONCE(regmap_read(s->regmap, 842 MAX310X_GLOBALIRQ_REG, &val)); 843 val = ((1 << s->devtype->nr) - 1) & ~val; 844 if (!val) 845 break; 846 if (max310x_port_irq(s, fls(val) - 1) == IRQ_HANDLED) 847 handled = true; 848 } while (1); 849 } else { 850 if (max310x_port_irq(s, 0) == IRQ_HANDLED) 851 handled = true; 852 } 853 854 return IRQ_RETVAL(handled); 855 } 856 857 static void max310x_tx_proc(struct work_struct *ws) 858 { 859 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work); 860 861 max310x_handle_tx(&one->port); 862 } 863 864 static unsigned int max310x_tx_empty(struct uart_port *port) 865 { 866 u8 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG); 867 868 return lvl ? 0 : TIOCSER_TEMT; 869 } 870 871 static unsigned int max310x_get_mctrl(struct uart_port *port) 872 { 873 /* DCD and DSR are not wired and CTS/RTS is handled automatically 874 * so just indicate DSR and CAR asserted 875 */ 876 return TIOCM_DSR | TIOCM_CAR; 877 } 878 879 static void max310x_md_proc(struct work_struct *ws) 880 { 881 struct max310x_one *one = container_of(ws, struct max310x_one, md_work); 882 883 max310x_port_update(&one->port, MAX310X_MODE2_REG, 884 MAX310X_MODE2_LOOPBACK_BIT, 885 (one->port.mctrl & TIOCM_LOOP) ? 886 MAX310X_MODE2_LOOPBACK_BIT : 0); 887 } 888 889 static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl) 890 { 891 struct max310x_one *one = to_max310x_port(port); 892 893 schedule_work(&one->md_work); 894 } 895 896 static void max310x_break_ctl(struct uart_port *port, int break_state) 897 { 898 max310x_port_update(port, MAX310X_LCR_REG, 899 MAX310X_LCR_TXBREAK_BIT, 900 break_state ? MAX310X_LCR_TXBREAK_BIT : 0); 901 } 902 903 static void max310x_set_termios(struct uart_port *port, 904 struct ktermios *termios, 905 const struct ktermios *old) 906 { 907 unsigned int lcr = 0, flow = 0; 908 int baud; 909 910 /* Mask termios capabilities we don't support */ 911 termios->c_cflag &= ~CMSPAR; 912 913 /* Word size */ 914 switch (termios->c_cflag & CSIZE) { 915 case CS5: 916 break; 917 case CS6: 918 lcr = MAX310X_LCR_LENGTH0_BIT; 919 break; 920 case CS7: 921 lcr = MAX310X_LCR_LENGTH1_BIT; 922 break; 923 case CS8: 924 default: 925 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT; 926 break; 927 } 928 929 /* Parity */ 930 if (termios->c_cflag & PARENB) { 931 lcr |= MAX310X_LCR_PARITY_BIT; 932 if (!(termios->c_cflag & PARODD)) 933 lcr |= MAX310X_LCR_EVENPARITY_BIT; 934 } 935 936 /* Stop bits */ 937 if (termios->c_cflag & CSTOPB) 938 lcr |= MAX310X_LCR_STOPLEN_BIT; /* 2 stops */ 939 940 /* Update LCR register */ 941 max310x_port_write(port, MAX310X_LCR_REG, lcr); 942 943 /* Set read status mask */ 944 port->read_status_mask = MAX310X_LSR_RXOVR_BIT; 945 if (termios->c_iflag & INPCK) 946 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT | 947 MAX310X_LSR_FRERR_BIT; 948 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 949 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT; 950 951 /* Set status ignore mask */ 952 port->ignore_status_mask = 0; 953 if (termios->c_iflag & IGNBRK) 954 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT; 955 if (!(termios->c_cflag & CREAD)) 956 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT | 957 MAX310X_LSR_RXOVR_BIT | 958 MAX310X_LSR_FRERR_BIT | 959 MAX310X_LSR_RXBRK_BIT; 960 961 /* Configure flow control */ 962 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]); 963 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]); 964 965 /* Disable transmitter before enabling AutoCTS or auto transmitter 966 * flow control 967 */ 968 if (termios->c_cflag & CRTSCTS || termios->c_iflag & IXOFF) { 969 max310x_port_update(port, MAX310X_MODE1_REG, 970 MAX310X_MODE1_TXDIS_BIT, 971 MAX310X_MODE1_TXDIS_BIT); 972 } 973 974 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF); 975 976 if (termios->c_cflag & CRTSCTS) { 977 /* Enable AUTORTS and AUTOCTS */ 978 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; 979 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT | 980 MAX310X_FLOWCTRL_AUTORTS_BIT; 981 } 982 if (termios->c_iflag & IXON) 983 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT | 984 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 985 if (termios->c_iflag & IXOFF) { 986 port->status |= UPSTAT_AUTOXOFF; 987 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT | 988 MAX310X_FLOWCTRL_SWFLOWEN_BIT; 989 } 990 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow); 991 992 /* Enable transmitter after disabling AutoCTS and auto transmitter 993 * flow control 994 */ 995 if (!(termios->c_cflag & CRTSCTS) && !(termios->c_iflag & IXOFF)) { 996 max310x_port_update(port, MAX310X_MODE1_REG, 997 MAX310X_MODE1_TXDIS_BIT, 998 0); 999 } 1000 1001 /* Get baud rate generator configuration */ 1002 baud = uart_get_baud_rate(port, termios, old, 1003 port->uartclk / 16 / 0xffff, 1004 port->uartclk / 4); 1005 1006 /* Setup baudrate generator */ 1007 baud = max310x_set_baud(port, baud); 1008 1009 /* Update timeout according to new baud rate */ 1010 uart_update_timeout(port, termios->c_cflag, baud); 1011 } 1012 1013 static void max310x_rs_proc(struct work_struct *ws) 1014 { 1015 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work); 1016 unsigned int delay, mode1 = 0, mode2 = 0; 1017 1018 delay = (one->port.rs485.delay_rts_before_send << 4) | 1019 one->port.rs485.delay_rts_after_send; 1020 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, delay); 1021 1022 if (one->port.rs485.flags & SER_RS485_ENABLED) { 1023 mode1 = MAX310X_MODE1_TRNSCVCTRL_BIT; 1024 1025 if (!(one->port.rs485.flags & SER_RS485_RX_DURING_TX)) 1026 mode2 = MAX310X_MODE2_ECHOSUPR_BIT; 1027 } 1028 1029 max310x_port_update(&one->port, MAX310X_MODE1_REG, 1030 MAX310X_MODE1_TRNSCVCTRL_BIT, mode1); 1031 max310x_port_update(&one->port, MAX310X_MODE2_REG, 1032 MAX310X_MODE2_ECHOSUPR_BIT, mode2); 1033 } 1034 1035 static int max310x_rs485_config(struct uart_port *port, struct ktermios *termios, 1036 struct serial_rs485 *rs485) 1037 { 1038 struct max310x_one *one = to_max310x_port(port); 1039 1040 if ((rs485->delay_rts_before_send > 0x0f) || 1041 (rs485->delay_rts_after_send > 0x0f)) 1042 return -ERANGE; 1043 1044 port->rs485 = *rs485; 1045 1046 schedule_work(&one->rs_work); 1047 1048 return 0; 1049 } 1050 1051 static int max310x_startup(struct uart_port *port) 1052 { 1053 struct max310x_port *s = dev_get_drvdata(port->dev); 1054 unsigned int val; 1055 1056 s->devtype->power(port, 1); 1057 1058 /* Configure MODE1 register */ 1059 max310x_port_update(port, MAX310X_MODE1_REG, 1060 MAX310X_MODE1_TRNSCVCTRL_BIT, 0); 1061 1062 /* Configure MODE2 register & Reset FIFOs*/ 1063 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT; 1064 max310x_port_write(port, MAX310X_MODE2_REG, val); 1065 max310x_port_update(port, MAX310X_MODE2_REG, 1066 MAX310X_MODE2_FIFORST_BIT, 0); 1067 1068 /* Configure mode1/mode2 to have rs485/rs232 enabled at startup */ 1069 val = (clamp(port->rs485.delay_rts_before_send, 0U, 15U) << 4) | 1070 clamp(port->rs485.delay_rts_after_send, 0U, 15U); 1071 max310x_port_write(port, MAX310X_HDPIXDELAY_REG, val); 1072 1073 if (port->rs485.flags & SER_RS485_ENABLED) { 1074 max310x_port_update(port, MAX310X_MODE1_REG, 1075 MAX310X_MODE1_TRNSCVCTRL_BIT, 1076 MAX310X_MODE1_TRNSCVCTRL_BIT); 1077 1078 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX)) 1079 max310x_port_update(port, MAX310X_MODE2_REG, 1080 MAX310X_MODE2_ECHOSUPR_BIT, 1081 MAX310X_MODE2_ECHOSUPR_BIT); 1082 } 1083 1084 /* Configure flow control levels */ 1085 /* Flow control halt level 96, resume level 48 */ 1086 max310x_port_write(port, MAX310X_FLOWLVL_REG, 1087 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96)); 1088 1089 /* Clear IRQ status register */ 1090 max310x_port_read(port, MAX310X_IRQSTS_REG); 1091 1092 /* Enable RX, TX, CTS change interrupts */ 1093 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT; 1094 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT); 1095 1096 return 0; 1097 } 1098 1099 static void max310x_shutdown(struct uart_port *port) 1100 { 1101 struct max310x_port *s = dev_get_drvdata(port->dev); 1102 1103 /* Disable all interrupts */ 1104 max310x_port_write(port, MAX310X_IRQEN_REG, 0); 1105 1106 s->devtype->power(port, 0); 1107 } 1108 1109 static const char *max310x_type(struct uart_port *port) 1110 { 1111 struct max310x_port *s = dev_get_drvdata(port->dev); 1112 1113 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL; 1114 } 1115 1116 static int max310x_request_port(struct uart_port *port) 1117 { 1118 /* Do nothing */ 1119 return 0; 1120 } 1121 1122 static void max310x_config_port(struct uart_port *port, int flags) 1123 { 1124 if (flags & UART_CONFIG_TYPE) 1125 port->type = PORT_MAX310X; 1126 } 1127 1128 static int max310x_verify_port(struct uart_port *port, struct serial_struct *s) 1129 { 1130 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X)) 1131 return -EINVAL; 1132 if (s->irq != port->irq) 1133 return -EINVAL; 1134 1135 return 0; 1136 } 1137 1138 static void max310x_null_void(struct uart_port *port) 1139 { 1140 /* Do nothing */ 1141 } 1142 1143 static const struct uart_ops max310x_ops = { 1144 .tx_empty = max310x_tx_empty, 1145 .set_mctrl = max310x_set_mctrl, 1146 .get_mctrl = max310x_get_mctrl, 1147 .stop_tx = max310x_null_void, 1148 .start_tx = max310x_start_tx, 1149 .stop_rx = max310x_null_void, 1150 .break_ctl = max310x_break_ctl, 1151 .startup = max310x_startup, 1152 .shutdown = max310x_shutdown, 1153 .set_termios = max310x_set_termios, 1154 .type = max310x_type, 1155 .request_port = max310x_request_port, 1156 .release_port = max310x_null_void, 1157 .config_port = max310x_config_port, 1158 .verify_port = max310x_verify_port, 1159 }; 1160 1161 static int __maybe_unused max310x_suspend(struct device *dev) 1162 { 1163 struct max310x_port *s = dev_get_drvdata(dev); 1164 int i; 1165 1166 for (i = 0; i < s->devtype->nr; i++) { 1167 uart_suspend_port(&max310x_uart, &s->p[i].port); 1168 s->devtype->power(&s->p[i].port, 0); 1169 } 1170 1171 return 0; 1172 } 1173 1174 static int __maybe_unused max310x_resume(struct device *dev) 1175 { 1176 struct max310x_port *s = dev_get_drvdata(dev); 1177 int i; 1178 1179 for (i = 0; i < s->devtype->nr; i++) { 1180 s->devtype->power(&s->p[i].port, 1); 1181 uart_resume_port(&max310x_uart, &s->p[i].port); 1182 } 1183 1184 return 0; 1185 } 1186 1187 static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume); 1188 1189 #ifdef CONFIG_GPIOLIB 1190 static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset) 1191 { 1192 unsigned int val; 1193 struct max310x_port *s = gpiochip_get_data(chip); 1194 struct uart_port *port = &s->p[offset / 4].port; 1195 1196 val = max310x_port_read(port, MAX310X_GPIODATA_REG); 1197 1198 return !!((val >> 4) & (1 << (offset % 4))); 1199 } 1200 1201 static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1202 { 1203 struct max310x_port *s = gpiochip_get_data(chip); 1204 struct uart_port *port = &s->p[offset / 4].port; 1205 1206 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1207 value ? 1 << (offset % 4) : 0); 1208 } 1209 1210 static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 1211 { 1212 struct max310x_port *s = gpiochip_get_data(chip); 1213 struct uart_port *port = &s->p[offset / 4].port; 1214 1215 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0); 1216 1217 return 0; 1218 } 1219 1220 static int max310x_gpio_direction_output(struct gpio_chip *chip, 1221 unsigned offset, int value) 1222 { 1223 struct max310x_port *s = gpiochip_get_data(chip); 1224 struct uart_port *port = &s->p[offset / 4].port; 1225 1226 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4), 1227 value ? 1 << (offset % 4) : 0); 1228 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 1229 1 << (offset % 4)); 1230 1231 return 0; 1232 } 1233 1234 static int max310x_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 1235 unsigned long config) 1236 { 1237 struct max310x_port *s = gpiochip_get_data(chip); 1238 struct uart_port *port = &s->p[offset / 4].port; 1239 1240 switch (pinconf_to_config_param(config)) { 1241 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1242 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1243 1 << ((offset % 4) + 4), 1244 1 << ((offset % 4) + 4)); 1245 return 0; 1246 case PIN_CONFIG_DRIVE_PUSH_PULL: 1247 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1248 1 << ((offset % 4) + 4), 0); 1249 return 0; 1250 default: 1251 return -ENOTSUPP; 1252 } 1253 } 1254 #endif 1255 1256 static const struct serial_rs485 max310x_rs485_supported = { 1257 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX, 1258 .delay_rts_before_send = 1, 1259 .delay_rts_after_send = 1, 1260 }; 1261 1262 static int max310x_probe(struct device *dev, const struct max310x_devtype *devtype, 1263 const struct max310x_if_cfg *if_cfg, 1264 struct regmap *regmaps[], int irq) 1265 { 1266 int i, ret, fmin, fmax, freq; 1267 struct max310x_port *s; 1268 u32 uartclk = 0; 1269 bool xtal; 1270 1271 for (i = 0; i < devtype->nr; i++) 1272 if (IS_ERR(regmaps[i])) 1273 return PTR_ERR(regmaps[i]); 1274 1275 /* Alloc port structure */ 1276 s = devm_kzalloc(dev, struct_size(s, p, devtype->nr), GFP_KERNEL); 1277 if (!s) { 1278 dev_err(dev, "Error allocating port structure\n"); 1279 return -ENOMEM; 1280 } 1281 1282 /* Always ask for fixed clock rate from a property. */ 1283 device_property_read_u32(dev, "clock-frequency", &uartclk); 1284 1285 xtal = device_property_match_string(dev, "clock-names", "osc") < 0; 1286 if (xtal) 1287 s->clk = devm_clk_get_optional(dev, "xtal"); 1288 else 1289 s->clk = devm_clk_get_optional(dev, "osc"); 1290 if (IS_ERR(s->clk)) 1291 return PTR_ERR(s->clk); 1292 1293 ret = clk_prepare_enable(s->clk); 1294 if (ret) 1295 return ret; 1296 1297 freq = clk_get_rate(s->clk); 1298 if (freq == 0) 1299 freq = uartclk; 1300 if (freq == 0) { 1301 dev_err(dev, "Cannot get clock rate\n"); 1302 ret = -EINVAL; 1303 goto out_clk; 1304 } 1305 1306 if (xtal) { 1307 fmin = 1000000; 1308 fmax = 4000000; 1309 } else { 1310 fmin = 500000; 1311 fmax = 35000000; 1312 } 1313 1314 /* Check frequency limits */ 1315 if (freq < fmin || freq > fmax) { 1316 ret = -ERANGE; 1317 goto out_clk; 1318 } 1319 1320 s->regmap = regmaps[0]; 1321 s->devtype = devtype; 1322 s->if_cfg = if_cfg; 1323 dev_set_drvdata(dev, s); 1324 1325 /* Check device to ensure we are talking to what we expect */ 1326 ret = devtype->detect(dev); 1327 if (ret) 1328 goto out_clk; 1329 1330 for (i = 0; i < devtype->nr; i++) { 1331 /* Reset port */ 1332 regmap_write(regmaps[i], MAX310X_MODE2_REG, 1333 MAX310X_MODE2_RST_BIT); 1334 /* Clear port reset */ 1335 regmap_write(regmaps[i], MAX310X_MODE2_REG, 0); 1336 1337 /* Wait for port startup */ 1338 do { 1339 regmap_read(regmaps[i], MAX310X_BRGDIVLSB_REG, &ret); 1340 } while (ret != 0x01); 1341 1342 regmap_write(regmaps[i], MAX310X_MODE1_REG, devtype->mode1); 1343 } 1344 1345 uartclk = max310x_set_ref_clk(dev, s, freq, xtal); 1346 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk); 1347 1348 for (i = 0; i < devtype->nr; i++) { 1349 unsigned int line; 1350 1351 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX); 1352 if (line == MAX310X_UART_NRMAX) { 1353 ret = -ERANGE; 1354 goto out_uart; 1355 } 1356 1357 /* Initialize port data */ 1358 s->p[i].port.line = line; 1359 s->p[i].port.dev = dev; 1360 s->p[i].port.irq = irq; 1361 s->p[i].port.type = PORT_MAX310X; 1362 s->p[i].port.fifosize = MAX310X_FIFO_SIZE; 1363 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY; 1364 s->p[i].port.iotype = UPIO_PORT; 1365 s->p[i].port.iobase = i; 1366 s->p[i].port.membase = (void __iomem *)~0; 1367 s->p[i].port.uartclk = uartclk; 1368 s->p[i].port.rs485_config = max310x_rs485_config; 1369 s->p[i].port.rs485_supported = max310x_rs485_supported; 1370 s->p[i].port.ops = &max310x_ops; 1371 s->p[i].regmap = regmaps[i]; 1372 1373 /* Disable all interrupts */ 1374 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0); 1375 /* Clear IRQ status register */ 1376 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG); 1377 /* Initialize queue for start TX */ 1378 INIT_WORK(&s->p[i].tx_work, max310x_tx_proc); 1379 /* Initialize queue for changing LOOPBACK mode */ 1380 INIT_WORK(&s->p[i].md_work, max310x_md_proc); 1381 /* Initialize queue for changing RS485 mode */ 1382 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc); 1383 1384 /* Register port */ 1385 ret = uart_add_one_port(&max310x_uart, &s->p[i].port); 1386 if (ret) { 1387 s->p[i].port.dev = NULL; 1388 goto out_uart; 1389 } 1390 set_bit(line, max310x_lines); 1391 1392 /* Go to suspend mode */ 1393 devtype->power(&s->p[i].port, 0); 1394 } 1395 1396 #ifdef CONFIG_GPIOLIB 1397 /* Setup GPIO cotroller */ 1398 s->gpio.owner = THIS_MODULE; 1399 s->gpio.parent = dev; 1400 s->gpio.label = devtype->name; 1401 s->gpio.direction_input = max310x_gpio_direction_input; 1402 s->gpio.get = max310x_gpio_get; 1403 s->gpio.direction_output= max310x_gpio_direction_output; 1404 s->gpio.set = max310x_gpio_set; 1405 s->gpio.set_config = max310x_gpio_set_config; 1406 s->gpio.base = -1; 1407 s->gpio.ngpio = devtype->nr * 4; 1408 s->gpio.can_sleep = 1; 1409 ret = devm_gpiochip_add_data(dev, &s->gpio, s); 1410 if (ret) 1411 goto out_uart; 1412 #endif 1413 1414 /* Setup interrupt */ 1415 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist, 1416 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), s); 1417 if (!ret) 1418 return 0; 1419 1420 dev_err(dev, "Unable to reguest IRQ %i\n", irq); 1421 1422 out_uart: 1423 for (i = 0; i < devtype->nr; i++) { 1424 if (s->p[i].port.dev) { 1425 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1426 clear_bit(s->p[i].port.line, max310x_lines); 1427 } 1428 } 1429 1430 out_clk: 1431 clk_disable_unprepare(s->clk); 1432 1433 return ret; 1434 } 1435 1436 static void max310x_remove(struct device *dev) 1437 { 1438 struct max310x_port *s = dev_get_drvdata(dev); 1439 int i; 1440 1441 for (i = 0; i < s->devtype->nr; i++) { 1442 cancel_work_sync(&s->p[i].tx_work); 1443 cancel_work_sync(&s->p[i].md_work); 1444 cancel_work_sync(&s->p[i].rs_work); 1445 uart_remove_one_port(&max310x_uart, &s->p[i].port); 1446 clear_bit(s->p[i].port.line, max310x_lines); 1447 s->devtype->power(&s->p[i].port, 0); 1448 } 1449 1450 clk_disable_unprepare(s->clk); 1451 } 1452 1453 static const struct of_device_id __maybe_unused max310x_dt_ids[] = { 1454 { .compatible = "maxim,max3107", .data = &max3107_devtype, }, 1455 { .compatible = "maxim,max3108", .data = &max3108_devtype, }, 1456 { .compatible = "maxim,max3109", .data = &max3109_devtype, }, 1457 { .compatible = "maxim,max14830", .data = &max14830_devtype }, 1458 { } 1459 }; 1460 MODULE_DEVICE_TABLE(of, max310x_dt_ids); 1461 1462 static struct regmap_config regcfg = { 1463 .reg_bits = 8, 1464 .val_bits = 8, 1465 .write_flag_mask = MAX310X_WRITE_BIT, 1466 .cache_type = REGCACHE_RBTREE, 1467 .max_register = MAX310X_REG_1F, 1468 .writeable_reg = max310x_reg_writeable, 1469 .volatile_reg = max310x_reg_volatile, 1470 .precious_reg = max310x_reg_precious, 1471 }; 1472 1473 #ifdef CONFIG_SPI_MASTER 1474 static int max310x_spi_extended_reg_enable(struct device *dev, bool enable) 1475 { 1476 struct max310x_port *s = dev_get_drvdata(dev); 1477 1478 return regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, 1479 enable ? MAX310X_EXTREG_ENBL : MAX310X_EXTREG_DSBL); 1480 } 1481 1482 static const struct max310x_if_cfg __maybe_unused max310x_spi_if_cfg = { 1483 .extended_reg_enable = max310x_spi_extended_reg_enable, 1484 .rev_id_reg = MAX310X_SPI_REVID_EXTREG, 1485 }; 1486 1487 static int max310x_spi_probe(struct spi_device *spi) 1488 { 1489 const struct max310x_devtype *devtype; 1490 struct regmap *regmaps[4]; 1491 unsigned int i; 1492 int ret; 1493 1494 /* Setup SPI bus */ 1495 spi->bits_per_word = 8; 1496 spi->mode = spi->mode ? : SPI_MODE_0; 1497 spi->max_speed_hz = spi->max_speed_hz ? : 26000000; 1498 ret = spi_setup(spi); 1499 if (ret) 1500 return ret; 1501 1502 devtype = device_get_match_data(&spi->dev); 1503 if (!devtype) 1504 devtype = (struct max310x_devtype *)spi_get_device_id(spi)->driver_data; 1505 1506 for (i = 0; i < devtype->nr; i++) { 1507 u8 port_mask = i * 0x20; 1508 regcfg.read_flag_mask = port_mask; 1509 regcfg.write_flag_mask = port_mask | MAX310X_WRITE_BIT; 1510 regmaps[i] = devm_regmap_init_spi(spi, ®cfg); 1511 } 1512 1513 return max310x_probe(&spi->dev, devtype, &max310x_spi_if_cfg, regmaps, spi->irq); 1514 } 1515 1516 static void max310x_spi_remove(struct spi_device *spi) 1517 { 1518 max310x_remove(&spi->dev); 1519 } 1520 1521 static const struct spi_device_id max310x_id_table[] = { 1522 { "max3107", (kernel_ulong_t)&max3107_devtype, }, 1523 { "max3108", (kernel_ulong_t)&max3108_devtype, }, 1524 { "max3109", (kernel_ulong_t)&max3109_devtype, }, 1525 { "max14830", (kernel_ulong_t)&max14830_devtype, }, 1526 { } 1527 }; 1528 MODULE_DEVICE_TABLE(spi, max310x_id_table); 1529 1530 static struct spi_driver max310x_spi_driver = { 1531 .driver = { 1532 .name = MAX310X_NAME, 1533 .of_match_table = max310x_dt_ids, 1534 .pm = &max310x_pm_ops, 1535 }, 1536 .probe = max310x_spi_probe, 1537 .remove = max310x_spi_remove, 1538 .id_table = max310x_id_table, 1539 }; 1540 #endif 1541 1542 #ifdef CONFIG_I2C 1543 static int max310x_i2c_extended_reg_enable(struct device *dev, bool enable) 1544 { 1545 return 0; 1546 } 1547 1548 static struct regmap_config regcfg_i2c = { 1549 .reg_bits = 8, 1550 .val_bits = 8, 1551 .cache_type = REGCACHE_RBTREE, 1552 .writeable_reg = max310x_reg_writeable, 1553 .volatile_reg = max310x_reg_volatile, 1554 .precious_reg = max310x_reg_precious, 1555 .max_register = MAX310X_I2C_REVID_EXTREG, 1556 }; 1557 1558 static const struct max310x_if_cfg max310x_i2c_if_cfg = { 1559 .extended_reg_enable = max310x_i2c_extended_reg_enable, 1560 .rev_id_reg = MAX310X_I2C_REVID_EXTREG, 1561 }; 1562 1563 static unsigned short max310x_i2c_slave_addr(unsigned short addr, 1564 unsigned int nr) 1565 { 1566 /* 1567 * For MAX14830 and MAX3109, the slave address depends on what the 1568 * A0 and A1 pins are tied to. 1569 * See Table I2C Address Map of the datasheet. 1570 * Based on that table, the following formulas were determined. 1571 * UART1 - UART0 = 0x10 1572 * UART2 - UART1 = 0x20 + 0x10 1573 * UART3 - UART2 = 0x10 1574 */ 1575 1576 addr -= nr * 0x10; 1577 1578 if (nr >= 2) 1579 addr -= 0x20; 1580 1581 return addr; 1582 } 1583 1584 static int max310x_i2c_probe(struct i2c_client *client) 1585 { 1586 const struct max310x_devtype *devtype = 1587 device_get_match_data(&client->dev); 1588 struct i2c_client *port_client; 1589 struct regmap *regmaps[4]; 1590 unsigned int i; 1591 u8 port_addr; 1592 1593 if (client->addr < devtype->slave_addr.min || 1594 client->addr > devtype->slave_addr.max) 1595 return dev_err_probe(&client->dev, -EINVAL, 1596 "Slave addr 0x%x outside of range [0x%x, 0x%x]\n", 1597 client->addr, devtype->slave_addr.min, 1598 devtype->slave_addr.max); 1599 1600 regmaps[0] = devm_regmap_init_i2c(client, ®cfg_i2c); 1601 1602 for (i = 1; i < devtype->nr; i++) { 1603 port_addr = max310x_i2c_slave_addr(client->addr, i); 1604 port_client = devm_i2c_new_dummy_device(&client->dev, 1605 client->adapter, 1606 port_addr); 1607 1608 regmaps[i] = devm_regmap_init_i2c(port_client, ®cfg_i2c); 1609 } 1610 1611 return max310x_probe(&client->dev, devtype, &max310x_i2c_if_cfg, 1612 regmaps, client->irq); 1613 } 1614 1615 static void max310x_i2c_remove(struct i2c_client *client) 1616 { 1617 max310x_remove(&client->dev); 1618 } 1619 1620 static struct i2c_driver max310x_i2c_driver = { 1621 .driver = { 1622 .name = MAX310X_NAME, 1623 .of_match_table = max310x_dt_ids, 1624 .pm = &max310x_pm_ops, 1625 }, 1626 .probe_new = max310x_i2c_probe, 1627 .remove = max310x_i2c_remove, 1628 }; 1629 #endif 1630 1631 static int __init max310x_uart_init(void) 1632 { 1633 int ret; 1634 1635 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX); 1636 1637 ret = uart_register_driver(&max310x_uart); 1638 if (ret) 1639 return ret; 1640 1641 #ifdef CONFIG_SPI_MASTER 1642 ret = spi_register_driver(&max310x_spi_driver); 1643 if (ret) 1644 goto err_spi_register; 1645 #endif 1646 1647 #ifdef CONFIG_I2C 1648 ret = i2c_add_driver(&max310x_i2c_driver); 1649 if (ret) 1650 goto err_i2c_register; 1651 #endif 1652 1653 return 0; 1654 1655 #ifdef CONFIG_I2C 1656 err_i2c_register: 1657 spi_unregister_driver(&max310x_spi_driver); 1658 #endif 1659 1660 err_spi_register: 1661 uart_unregister_driver(&max310x_uart); 1662 1663 return ret; 1664 } 1665 module_init(max310x_uart_init); 1666 1667 static void __exit max310x_uart_exit(void) 1668 { 1669 #ifdef CONFIG_I2C 1670 i2c_del_driver(&max310x_i2c_driver); 1671 #endif 1672 1673 #ifdef CONFIG_SPI_MASTER 1674 spi_unregister_driver(&max310x_spi_driver); 1675 #endif 1676 1677 uart_unregister_driver(&max310x_uart); 1678 } 1679 module_exit(max310x_uart_exit); 1680 1681 MODULE_LICENSE("GPL"); 1682 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); 1683 MODULE_DESCRIPTION("MAX310X serial driver"); 1684