1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * High Speed Serial Ports on NXP LPC32xx SoC 4 * 5 * Authors: Kevin Wells <kevin.wells@nxp.com> 6 * Roland Stigge <stigge@antcom.de> 7 * 8 * Copyright (C) 2010 NXP Semiconductors 9 * Copyright (C) 2012 Roland Stigge 10 */ 11 12 #include <linux/module.h> 13 #include <linux/ioport.h> 14 #include <linux/init.h> 15 #include <linux/console.h> 16 #include <linux/sysrq.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/platform_device.h> 22 #include <linux/delay.h> 23 #include <linux/nmi.h> 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/of.h> 27 #include <linux/sizes.h> 28 #include <linux/soc/nxp/lpc32xx-misc.h> 29 30 /* 31 * High Speed UART register offsets 32 */ 33 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) 34 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) 35 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08) 36 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) 37 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10) 38 39 #define LPC32XX_HSU_BREAK_DATA (1 << 10) 40 #define LPC32XX_HSU_ERROR_DATA (1 << 9) 41 #define LPC32XX_HSU_RX_EMPTY (1 << 8) 42 43 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) 44 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) 45 46 #define LPC32XX_HSU_TX_INT_SET (1 << 6) 47 #define LPC32XX_HSU_RX_OE_INT (1 << 5) 48 #define LPC32XX_HSU_BRK_INT (1 << 4) 49 #define LPC32XX_HSU_FE_INT (1 << 3) 50 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) 51 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1) 52 #define LPC32XX_HSU_TX_INT (1 << 0) 53 54 #define LPC32XX_HSU_HRTS_INV (1 << 21) 55 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) 56 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) 57 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) 58 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) 59 #define LPC32XX_HSU_HRTS_EN (1 << 18) 60 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) 61 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) 62 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) 63 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) 64 #define LPC32XX_HSU_HCTS_INV (1 << 15) 65 #define LPC32XX_HSU_HCTS_EN (1 << 14) 66 #define LPC32XX_HSU_OFFSET(n) ((n) << 9) 67 #define LPC32XX_HSU_BREAK (1 << 8) 68 #define LPC32XX_HSU_ERR_INT_EN (1 << 7) 69 #define LPC32XX_HSU_RX_INT_EN (1 << 6) 70 #define LPC32XX_HSU_TX_INT_EN (1 << 5) 71 #define LPC32XX_HSU_RX_TL1B (0x0 << 2) 72 #define LPC32XX_HSU_RX_TL4B (0x1 << 2) 73 #define LPC32XX_HSU_RX_TL8B (0x2 << 2) 74 #define LPC32XX_HSU_RX_TL16B (0x3 << 2) 75 #define LPC32XX_HSU_RX_TL32B (0x4 << 2) 76 #define LPC32XX_HSU_RX_TL48B (0x5 << 2) 77 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) 78 #define LPC32XX_HSU_TX_TL0B (0x0 << 0) 79 #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 80 #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 81 #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 82 83 #define LPC32XX_MAIN_OSC_FREQ 13000000 84 85 #define MODNAME "lpc32xx_hsuart" 86 87 struct lpc32xx_hsuart_port { 88 struct uart_port port; 89 }; 90 91 #define FIFO_READ_LIMIT 128 92 #define MAX_PORTS 3 93 #define LPC32XX_TTY_NAME "ttyTX" 94 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; 95 96 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE 97 static void wait_for_xmit_empty(struct uart_port *port) 98 { 99 unsigned int timeout = 10000; 100 101 do { 102 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 103 port->membase))) == 0) 104 break; 105 if (--timeout == 0) 106 break; 107 udelay(1); 108 } while (1); 109 } 110 111 static void wait_for_xmit_ready(struct uart_port *port) 112 { 113 unsigned int timeout = 10000; 114 115 while (1) { 116 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 117 port->membase))) < 32) 118 break; 119 if (--timeout == 0) 120 break; 121 udelay(1); 122 } 123 } 124 125 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, unsigned char ch) 126 { 127 wait_for_xmit_ready(port); 128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 129 } 130 131 static void lpc32xx_hsuart_console_write(struct console *co, const char *s, 132 unsigned int count) 133 { 134 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; 135 unsigned long flags; 136 int locked = 1; 137 138 touch_nmi_watchdog(); 139 local_irq_save(flags); 140 if (up->port.sysrq) 141 locked = 0; 142 else if (oops_in_progress) 143 locked = spin_trylock(&up->port.lock); 144 else 145 spin_lock(&up->port.lock); 146 147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 148 wait_for_xmit_empty(&up->port); 149 150 if (locked) 151 spin_unlock(&up->port.lock); 152 local_irq_restore(flags); 153 } 154 155 static int __init lpc32xx_hsuart_console_setup(struct console *co, 156 char *options) 157 { 158 struct uart_port *port; 159 int baud = 115200; 160 int bits = 8; 161 int parity = 'n'; 162 int flow = 'n'; 163 164 if (co->index >= MAX_PORTS) 165 co->index = 0; 166 167 port = &lpc32xx_hs_ports[co->index].port; 168 if (!port->membase) 169 return -ENODEV; 170 171 if (options) 172 uart_parse_options(options, &baud, &parity, &bits, &flow); 173 174 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 175 176 return uart_set_options(port, co, baud, parity, bits, flow); 177 } 178 179 static struct uart_driver lpc32xx_hsuart_reg; 180 static struct console lpc32xx_hsuart_console = { 181 .name = LPC32XX_TTY_NAME, 182 .write = lpc32xx_hsuart_console_write, 183 .device = uart_console_device, 184 .setup = lpc32xx_hsuart_console_setup, 185 .flags = CON_PRINTBUFFER, 186 .index = -1, 187 .data = &lpc32xx_hsuart_reg, 188 }; 189 190 static int __init lpc32xx_hsuart_console_init(void) 191 { 192 register_console(&lpc32xx_hsuart_console); 193 return 0; 194 } 195 console_initcall(lpc32xx_hsuart_console_init); 196 197 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) 198 #else 199 #define LPC32XX_HSUART_CONSOLE NULL 200 #endif 201 202 static struct uart_driver lpc32xx_hs_reg = { 203 .owner = THIS_MODULE, 204 .driver_name = MODNAME, 205 .dev_name = LPC32XX_TTY_NAME, 206 .nr = MAX_PORTS, 207 .cons = LPC32XX_HSUART_CONSOLE, 208 }; 209 static int uarts_registered; 210 211 static unsigned int __serial_get_clock_div(unsigned long uartclk, 212 unsigned long rate) 213 { 214 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; 215 u32 rate_diff; 216 217 /* Find the closest divider to get the desired clock rate */ 218 div = uartclk / rate; 219 goodrate = hsu_rate = (div / 14) - 1; 220 if (hsu_rate != 0) 221 hsu_rate--; 222 223 /* Tweak divider */ 224 l_hsu_rate = hsu_rate + 3; 225 rate_diff = 0xFFFFFFFF; 226 227 while (hsu_rate < l_hsu_rate) { 228 comprate = uartclk / ((hsu_rate + 1) * 14); 229 if (abs(comprate - rate) < rate_diff) { 230 goodrate = hsu_rate; 231 rate_diff = abs(comprate - rate); 232 } 233 234 hsu_rate++; 235 } 236 if (hsu_rate > 0xFF) 237 hsu_rate = 0xFF; 238 239 return goodrate; 240 } 241 242 static void __serial_uart_flush(struct uart_port *port) 243 { 244 int cnt = 0; 245 246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 247 (cnt++ < FIFO_READ_LIMIT)) 248 readl(LPC32XX_HSUART_FIFO(port->membase)); 249 } 250 251 static void __serial_lpc32xx_rx(struct uart_port *port) 252 { 253 struct tty_port *tport = &port->state->port; 254 unsigned int tmp, flag; 255 256 /* Read data from FIFO and push into terminal */ 257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 258 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { 259 flag = TTY_NORMAL; 260 port->icount.rx++; 261 262 if (tmp & LPC32XX_HSU_ERROR_DATA) { 263 /* Framing error */ 264 writel(LPC32XX_HSU_FE_INT, 265 LPC32XX_HSUART_IIR(port->membase)); 266 port->icount.frame++; 267 flag = TTY_FRAME; 268 tty_insert_flip_char(tport, 0, TTY_FRAME); 269 } 270 271 tty_insert_flip_char(tport, (tmp & 0xFF), flag); 272 273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 274 } 275 276 tty_flip_buffer_push(tport); 277 } 278 279 static bool serial_lpc32xx_tx_ready(struct uart_port *port) 280 { 281 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase)); 282 283 return LPC32XX_HSU_TX_LEV(level) < 64; 284 } 285 286 static void __serial_lpc32xx_tx(struct uart_port *port) 287 { 288 u8 ch; 289 290 uart_port_tx(port, ch, 291 serial_lpc32xx_tx_ready(port), 292 writel(ch, LPC32XX_HSUART_FIFO(port->membase))); 293 } 294 295 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) 296 { 297 struct uart_port *port = dev_id; 298 struct tty_port *tport = &port->state->port; 299 u32 status; 300 301 spin_lock(&port->lock); 302 303 /* Read UART status and clear latched interrupts */ 304 status = readl(LPC32XX_HSUART_IIR(port->membase)); 305 306 if (status & LPC32XX_HSU_BRK_INT) { 307 /* Break received */ 308 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 309 port->icount.brk++; 310 uart_handle_break(port); 311 } 312 313 /* Framing error */ 314 if (status & LPC32XX_HSU_FE_INT) 315 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 316 317 if (status & LPC32XX_HSU_RX_OE_INT) { 318 /* Receive FIFO overrun */ 319 writel(LPC32XX_HSU_RX_OE_INT, 320 LPC32XX_HSUART_IIR(port->membase)); 321 port->icount.overrun++; 322 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 323 tty_flip_buffer_push(tport); 324 } 325 326 /* Data received? */ 327 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) 328 __serial_lpc32xx_rx(port); 329 330 /* Transmit data request? */ 331 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { 332 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 333 __serial_lpc32xx_tx(port); 334 } 335 336 spin_unlock(&port->lock); 337 338 return IRQ_HANDLED; 339 } 340 341 /* port->lock is not held. */ 342 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) 343 { 344 unsigned int ret = 0; 345 346 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) 347 ret = TIOCSER_TEMT; 348 349 return ret; 350 } 351 352 /* port->lock held by caller. */ 353 static void serial_lpc32xx_set_mctrl(struct uart_port *port, 354 unsigned int mctrl) 355 { 356 /* No signals are supported on HS UARTs */ 357 } 358 359 /* port->lock is held by caller and interrupts are disabled. */ 360 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) 361 { 362 /* No signals are supported on HS UARTs */ 363 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 364 } 365 366 /* port->lock held by caller. */ 367 static void serial_lpc32xx_stop_tx(struct uart_port *port) 368 { 369 u32 tmp; 370 371 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 372 tmp &= ~LPC32XX_HSU_TX_INT_EN; 373 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 374 } 375 376 /* port->lock held by caller. */ 377 static void serial_lpc32xx_start_tx(struct uart_port *port) 378 { 379 u32 tmp; 380 381 __serial_lpc32xx_tx(port); 382 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 383 tmp |= LPC32XX_HSU_TX_INT_EN; 384 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 385 } 386 387 /* port->lock held by caller. */ 388 static void serial_lpc32xx_stop_rx(struct uart_port *port) 389 { 390 u32 tmp; 391 392 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 393 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 394 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 395 396 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | 397 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); 398 } 399 400 /* port->lock is not held. */ 401 static void serial_lpc32xx_break_ctl(struct uart_port *port, 402 int break_state) 403 { 404 unsigned long flags; 405 u32 tmp; 406 407 spin_lock_irqsave(&port->lock, flags); 408 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 409 if (break_state != 0) 410 tmp |= LPC32XX_HSU_BREAK; 411 else 412 tmp &= ~LPC32XX_HSU_BREAK; 413 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 414 spin_unlock_irqrestore(&port->lock, flags); 415 } 416 417 /* port->lock is not held. */ 418 static int serial_lpc32xx_startup(struct uart_port *port) 419 { 420 int retval; 421 unsigned long flags; 422 u32 tmp; 423 424 spin_lock_irqsave(&port->lock, flags); 425 426 __serial_uart_flush(port); 427 428 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 429 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 430 LPC32XX_HSUART_IIR(port->membase)); 431 432 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 433 434 /* 435 * Set receiver timeout, HSU offset of 20, no break, no interrupts, 436 * and default FIFO trigger levels 437 */ 438 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 439 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 440 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 441 442 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 443 444 spin_unlock_irqrestore(&port->lock, flags); 445 446 retval = request_irq(port->irq, serial_lpc32xx_interrupt, 447 0, MODNAME, port); 448 if (!retval) 449 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), 450 LPC32XX_HSUART_CTRL(port->membase)); 451 452 return retval; 453 } 454 455 /* port->lock is not held. */ 456 static void serial_lpc32xx_shutdown(struct uart_port *port) 457 { 458 u32 tmp; 459 unsigned long flags; 460 461 spin_lock_irqsave(&port->lock, flags); 462 463 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 464 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 465 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 466 467 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 468 469 spin_unlock_irqrestore(&port->lock, flags); 470 471 free_irq(port->irq, port); 472 } 473 474 /* port->lock is not held. */ 475 static void serial_lpc32xx_set_termios(struct uart_port *port, 476 struct ktermios *termios, 477 const struct ktermios *old) 478 { 479 unsigned long flags; 480 unsigned int baud, quot; 481 u32 tmp; 482 483 /* Always 8-bit, no parity, 1 stop bit */ 484 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 485 termios->c_cflag |= CS8; 486 487 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); 488 489 baud = uart_get_baud_rate(port, termios, old, 0, 490 port->uartclk / 14); 491 492 quot = __serial_get_clock_div(port->uartclk, baud); 493 494 spin_lock_irqsave(&port->lock, flags); 495 496 /* Ignore characters? */ 497 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 498 if ((termios->c_cflag & CREAD) == 0) 499 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 500 else 501 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; 502 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 503 504 writel(quot, LPC32XX_HSUART_RATE(port->membase)); 505 506 uart_update_timeout(port, termios->c_cflag, baud); 507 508 spin_unlock_irqrestore(&port->lock, flags); 509 510 /* Don't rewrite B0 */ 511 if (tty_termios_baud_rate(termios)) 512 tty_termios_encode_baud_rate(termios, baud, baud); 513 } 514 515 static const char *serial_lpc32xx_type(struct uart_port *port) 516 { 517 return MODNAME; 518 } 519 520 static void serial_lpc32xx_release_port(struct uart_port *port) 521 { 522 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 523 if (port->flags & UPF_IOREMAP) { 524 iounmap(port->membase); 525 port->membase = NULL; 526 } 527 528 release_mem_region(port->mapbase, SZ_4K); 529 } 530 } 531 532 static int serial_lpc32xx_request_port(struct uart_port *port) 533 { 534 int ret = -ENODEV; 535 536 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 537 ret = 0; 538 539 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) 540 ret = -EBUSY; 541 else if (port->flags & UPF_IOREMAP) { 542 port->membase = ioremap(port->mapbase, SZ_4K); 543 if (!port->membase) { 544 release_mem_region(port->mapbase, SZ_4K); 545 ret = -ENOMEM; 546 } 547 } 548 } 549 550 return ret; 551 } 552 553 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) 554 { 555 int ret; 556 557 ret = serial_lpc32xx_request_port(port); 558 if (ret < 0) 559 return; 560 port->type = PORT_UART00; 561 port->fifosize = 64; 562 563 __serial_uart_flush(port); 564 565 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 566 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 567 LPC32XX_HSUART_IIR(port->membase)); 568 569 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 570 571 /* Set receiver timeout, HSU offset of 20, no break, no interrupts, 572 and default FIFO trigger levels */ 573 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 574 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, 575 LPC32XX_HSUART_CTRL(port->membase)); 576 } 577 578 static int serial_lpc32xx_verify_port(struct uart_port *port, 579 struct serial_struct *ser) 580 { 581 int ret = 0; 582 583 if (ser->type != PORT_UART00) 584 ret = -EINVAL; 585 586 return ret; 587 } 588 589 static const struct uart_ops serial_lpc32xx_pops = { 590 .tx_empty = serial_lpc32xx_tx_empty, 591 .set_mctrl = serial_lpc32xx_set_mctrl, 592 .get_mctrl = serial_lpc32xx_get_mctrl, 593 .stop_tx = serial_lpc32xx_stop_tx, 594 .start_tx = serial_lpc32xx_start_tx, 595 .stop_rx = serial_lpc32xx_stop_rx, 596 .break_ctl = serial_lpc32xx_break_ctl, 597 .startup = serial_lpc32xx_startup, 598 .shutdown = serial_lpc32xx_shutdown, 599 .set_termios = serial_lpc32xx_set_termios, 600 .type = serial_lpc32xx_type, 601 .release_port = serial_lpc32xx_release_port, 602 .request_port = serial_lpc32xx_request_port, 603 .config_port = serial_lpc32xx_config_port, 604 .verify_port = serial_lpc32xx_verify_port, 605 }; 606 607 /* 608 * Register a set of serial devices attached to a platform device 609 */ 610 static int serial_hs_lpc32xx_probe(struct platform_device *pdev) 611 { 612 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; 613 int ret = 0; 614 struct resource *res; 615 616 if (uarts_registered >= MAX_PORTS) { 617 dev_err(&pdev->dev, 618 "Error: Number of possible ports exceeded (%d)!\n", 619 uarts_registered + 1); 620 return -ENXIO; 621 } 622 623 memset(p, 0, sizeof(*p)); 624 625 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 626 if (!res) { 627 dev_err(&pdev->dev, 628 "Error getting mem resource for HS UART port %d\n", 629 uarts_registered); 630 return -ENXIO; 631 } 632 p->port.mapbase = res->start; 633 p->port.membase = NULL; 634 635 ret = platform_get_irq(pdev, 0); 636 if (ret < 0) 637 return ret; 638 p->port.irq = ret; 639 640 p->port.iotype = UPIO_MEM32; 641 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; 642 p->port.regshift = 2; 643 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; 644 p->port.dev = &pdev->dev; 645 p->port.ops = &serial_lpc32xx_pops; 646 p->port.line = uarts_registered++; 647 spin_lock_init(&p->port.lock); 648 649 /* send port to loopback mode by default */ 650 lpc32xx_loopback_set(p->port.mapbase, 1); 651 652 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); 653 654 platform_set_drvdata(pdev, p); 655 656 return ret; 657 } 658 659 /* 660 * Remove serial ports registered against a platform device. 661 */ 662 static int serial_hs_lpc32xx_remove(struct platform_device *pdev) 663 { 664 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 665 666 uart_remove_one_port(&lpc32xx_hs_reg, &p->port); 667 668 return 0; 669 } 670 671 672 #ifdef CONFIG_PM 673 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, 674 pm_message_t state) 675 { 676 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 677 678 uart_suspend_port(&lpc32xx_hs_reg, &p->port); 679 680 return 0; 681 } 682 683 static int serial_hs_lpc32xx_resume(struct platform_device *pdev) 684 { 685 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 686 687 uart_resume_port(&lpc32xx_hs_reg, &p->port); 688 689 return 0; 690 } 691 #else 692 #define serial_hs_lpc32xx_suspend NULL 693 #define serial_hs_lpc32xx_resume NULL 694 #endif 695 696 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { 697 { .compatible = "nxp,lpc3220-hsuart" }, 698 { /* sentinel */ } 699 }; 700 701 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); 702 703 static struct platform_driver serial_hs_lpc32xx_driver = { 704 .probe = serial_hs_lpc32xx_probe, 705 .remove = serial_hs_lpc32xx_remove, 706 .suspend = serial_hs_lpc32xx_suspend, 707 .resume = serial_hs_lpc32xx_resume, 708 .driver = { 709 .name = MODNAME, 710 .of_match_table = serial_hs_lpc32xx_dt_ids, 711 }, 712 }; 713 714 static int __init lpc32xx_hsuart_init(void) 715 { 716 int ret; 717 718 ret = uart_register_driver(&lpc32xx_hs_reg); 719 if (ret) 720 return ret; 721 722 ret = platform_driver_register(&serial_hs_lpc32xx_driver); 723 if (ret) 724 uart_unregister_driver(&lpc32xx_hs_reg); 725 726 return ret; 727 } 728 729 static void __exit lpc32xx_hsuart_exit(void) 730 { 731 platform_driver_unregister(&serial_hs_lpc32xx_driver); 732 uart_unregister_driver(&lpc32xx_hs_reg); 733 } 734 735 module_init(lpc32xx_hsuart_init); 736 module_exit(lpc32xx_hsuart_exit); 737 738 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 739 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 740 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); 741 MODULE_LICENSE("GPL"); 742