1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * High Speed Serial Ports on NXP LPC32xx SoC 4 * 5 * Authors: Kevin Wells <kevin.wells@nxp.com> 6 * Roland Stigge <stigge@antcom.de> 7 * 8 * Copyright (C) 2010 NXP Semiconductors 9 * Copyright (C) 2012 Roland Stigge 10 */ 11 12 #include <linux/module.h> 13 #include <linux/ioport.h> 14 #include <linux/init.h> 15 #include <linux/console.h> 16 #include <linux/sysrq.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/platform_device.h> 22 #include <linux/delay.h> 23 #include <linux/nmi.h> 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/of.h> 27 #include <linux/sizes.h> 28 #include <linux/soc/nxp/lpc32xx-misc.h> 29 30 /* 31 * High Speed UART register offsets 32 */ 33 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) 34 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) 35 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08) 36 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) 37 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10) 38 39 #define LPC32XX_HSU_BREAK_DATA (1 << 10) 40 #define LPC32XX_HSU_ERROR_DATA (1 << 9) 41 #define LPC32XX_HSU_RX_EMPTY (1 << 8) 42 43 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) 44 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) 45 46 #define LPC32XX_HSU_TX_INT_SET (1 << 6) 47 #define LPC32XX_HSU_RX_OE_INT (1 << 5) 48 #define LPC32XX_HSU_BRK_INT (1 << 4) 49 #define LPC32XX_HSU_FE_INT (1 << 3) 50 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) 51 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1) 52 #define LPC32XX_HSU_TX_INT (1 << 0) 53 54 #define LPC32XX_HSU_HRTS_INV (1 << 21) 55 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) 56 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) 57 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) 58 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) 59 #define LPC32XX_HSU_HRTS_EN (1 << 18) 60 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) 61 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) 62 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) 63 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) 64 #define LPC32XX_HSU_HCTS_INV (1 << 15) 65 #define LPC32XX_HSU_HCTS_EN (1 << 14) 66 #define LPC32XX_HSU_OFFSET(n) ((n) << 9) 67 #define LPC32XX_HSU_BREAK (1 << 8) 68 #define LPC32XX_HSU_ERR_INT_EN (1 << 7) 69 #define LPC32XX_HSU_RX_INT_EN (1 << 6) 70 #define LPC32XX_HSU_TX_INT_EN (1 << 5) 71 #define LPC32XX_HSU_RX_TL1B (0x0 << 2) 72 #define LPC32XX_HSU_RX_TL4B (0x1 << 2) 73 #define LPC32XX_HSU_RX_TL8B (0x2 << 2) 74 #define LPC32XX_HSU_RX_TL16B (0x3 << 2) 75 #define LPC32XX_HSU_RX_TL32B (0x4 << 2) 76 #define LPC32XX_HSU_RX_TL48B (0x5 << 2) 77 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) 78 #define LPC32XX_HSU_TX_TL0B (0x0 << 0) 79 #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 80 #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 81 #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 82 83 #define LPC32XX_MAIN_OSC_FREQ 13000000 84 85 #define MODNAME "lpc32xx_hsuart" 86 87 struct lpc32xx_hsuart_port { 88 struct uart_port port; 89 }; 90 91 #define FIFO_READ_LIMIT 128 92 #define MAX_PORTS 3 93 #define LPC32XX_TTY_NAME "ttyTX" 94 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; 95 96 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE 97 static void wait_for_xmit_empty(struct uart_port *port) 98 { 99 unsigned int timeout = 10000; 100 101 do { 102 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 103 port->membase))) == 0) 104 break; 105 if (--timeout == 0) 106 break; 107 udelay(1); 108 } while (1); 109 } 110 111 static void wait_for_xmit_ready(struct uart_port *port) 112 { 113 unsigned int timeout = 10000; 114 115 while (1) { 116 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 117 port->membase))) < 32) 118 break; 119 if (--timeout == 0) 120 break; 121 udelay(1); 122 } 123 } 124 125 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, unsigned char ch) 126 { 127 wait_for_xmit_ready(port); 128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 129 } 130 131 static void lpc32xx_hsuart_console_write(struct console *co, const char *s, 132 unsigned int count) 133 { 134 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; 135 unsigned long flags; 136 int locked = 1; 137 138 touch_nmi_watchdog(); 139 local_irq_save(flags); 140 if (up->port.sysrq) 141 locked = 0; 142 else if (oops_in_progress) 143 locked = spin_trylock(&up->port.lock); 144 else 145 spin_lock(&up->port.lock); 146 147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 148 wait_for_xmit_empty(&up->port); 149 150 if (locked) 151 spin_unlock(&up->port.lock); 152 local_irq_restore(flags); 153 } 154 155 static int __init lpc32xx_hsuart_console_setup(struct console *co, 156 char *options) 157 { 158 struct uart_port *port; 159 int baud = 115200; 160 int bits = 8; 161 int parity = 'n'; 162 int flow = 'n'; 163 164 if (co->index >= MAX_PORTS) 165 co->index = 0; 166 167 port = &lpc32xx_hs_ports[co->index].port; 168 if (!port->membase) 169 return -ENODEV; 170 171 if (options) 172 uart_parse_options(options, &baud, &parity, &bits, &flow); 173 174 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 175 176 return uart_set_options(port, co, baud, parity, bits, flow); 177 } 178 179 static struct uart_driver lpc32xx_hsuart_reg; 180 static struct console lpc32xx_hsuart_console = { 181 .name = LPC32XX_TTY_NAME, 182 .write = lpc32xx_hsuart_console_write, 183 .device = uart_console_device, 184 .setup = lpc32xx_hsuart_console_setup, 185 .flags = CON_PRINTBUFFER, 186 .index = -1, 187 .data = &lpc32xx_hsuart_reg, 188 }; 189 190 static int __init lpc32xx_hsuart_console_init(void) 191 { 192 register_console(&lpc32xx_hsuart_console); 193 return 0; 194 } 195 console_initcall(lpc32xx_hsuart_console_init); 196 197 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) 198 #else 199 #define LPC32XX_HSUART_CONSOLE NULL 200 #endif 201 202 static struct uart_driver lpc32xx_hs_reg = { 203 .owner = THIS_MODULE, 204 .driver_name = MODNAME, 205 .dev_name = LPC32XX_TTY_NAME, 206 .nr = MAX_PORTS, 207 .cons = LPC32XX_HSUART_CONSOLE, 208 }; 209 static int uarts_registered; 210 211 static unsigned int __serial_get_clock_div(unsigned long uartclk, 212 unsigned long rate) 213 { 214 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; 215 u32 rate_diff; 216 217 /* Find the closest divider to get the desired clock rate */ 218 div = uartclk / rate; 219 goodrate = hsu_rate = (div / 14) - 1; 220 if (hsu_rate != 0) 221 hsu_rate--; 222 223 /* Tweak divider */ 224 l_hsu_rate = hsu_rate + 3; 225 rate_diff = 0xFFFFFFFF; 226 227 while (hsu_rate < l_hsu_rate) { 228 comprate = uartclk / ((hsu_rate + 1) * 14); 229 if (abs(comprate - rate) < rate_diff) { 230 goodrate = hsu_rate; 231 rate_diff = abs(comprate - rate); 232 } 233 234 hsu_rate++; 235 } 236 if (hsu_rate > 0xFF) 237 hsu_rate = 0xFF; 238 239 return goodrate; 240 } 241 242 static void __serial_uart_flush(struct uart_port *port) 243 { 244 int cnt = 0; 245 246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 247 (cnt++ < FIFO_READ_LIMIT)) 248 readl(LPC32XX_HSUART_FIFO(port->membase)); 249 } 250 251 static void __serial_lpc32xx_rx(struct uart_port *port) 252 { 253 struct tty_port *tport = &port->state->port; 254 unsigned int tmp, flag; 255 256 /* Read data from FIFO and push into terminal */ 257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 258 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { 259 flag = TTY_NORMAL; 260 port->icount.rx++; 261 262 if (tmp & LPC32XX_HSU_ERROR_DATA) { 263 /* Framing error */ 264 writel(LPC32XX_HSU_FE_INT, 265 LPC32XX_HSUART_IIR(port->membase)); 266 port->icount.frame++; 267 flag = TTY_FRAME; 268 tty_insert_flip_char(tport, 0, TTY_FRAME); 269 } 270 271 tty_insert_flip_char(tport, (tmp & 0xFF), flag); 272 273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 274 } 275 276 tty_flip_buffer_push(tport); 277 } 278 279 static void serial_lpc32xx_stop_tx(struct uart_port *port); 280 281 static bool serial_lpc32xx_tx_ready(struct uart_port *port) 282 { 283 u32 level = readl(LPC32XX_HSUART_LEVEL(port->membase)); 284 285 return LPC32XX_HSU_TX_LEV(level) < 64; 286 } 287 288 static void __serial_lpc32xx_tx(struct uart_port *port) 289 { 290 struct circ_buf *xmit = &port->state->xmit; 291 292 if (port->x_char) { 293 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 294 port->icount.tx++; 295 port->x_char = 0; 296 return; 297 } 298 299 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 300 goto exit_tx; 301 302 /* Transfer data */ 303 while (serial_lpc32xx_tx_ready(port)) { 304 writel((u32) xmit->buf[xmit->tail], 305 LPC32XX_HSUART_FIFO(port->membase)); 306 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 307 port->icount.tx++; 308 if (uart_circ_empty(xmit)) 309 break; 310 } 311 312 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 313 uart_write_wakeup(port); 314 315 exit_tx: 316 if (uart_circ_empty(xmit)) 317 serial_lpc32xx_stop_tx(port); 318 } 319 320 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) 321 { 322 struct uart_port *port = dev_id; 323 struct tty_port *tport = &port->state->port; 324 u32 status; 325 326 spin_lock(&port->lock); 327 328 /* Read UART status and clear latched interrupts */ 329 status = readl(LPC32XX_HSUART_IIR(port->membase)); 330 331 if (status & LPC32XX_HSU_BRK_INT) { 332 /* Break received */ 333 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 334 port->icount.brk++; 335 uart_handle_break(port); 336 } 337 338 /* Framing error */ 339 if (status & LPC32XX_HSU_FE_INT) 340 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 341 342 if (status & LPC32XX_HSU_RX_OE_INT) { 343 /* Receive FIFO overrun */ 344 writel(LPC32XX_HSU_RX_OE_INT, 345 LPC32XX_HSUART_IIR(port->membase)); 346 port->icount.overrun++; 347 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 348 tty_flip_buffer_push(tport); 349 } 350 351 /* Data received? */ 352 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) 353 __serial_lpc32xx_rx(port); 354 355 /* Transmit data request? */ 356 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { 357 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 358 __serial_lpc32xx_tx(port); 359 } 360 361 spin_unlock(&port->lock); 362 363 return IRQ_HANDLED; 364 } 365 366 /* port->lock is not held. */ 367 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) 368 { 369 unsigned int ret = 0; 370 371 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) 372 ret = TIOCSER_TEMT; 373 374 return ret; 375 } 376 377 /* port->lock held by caller. */ 378 static void serial_lpc32xx_set_mctrl(struct uart_port *port, 379 unsigned int mctrl) 380 { 381 /* No signals are supported on HS UARTs */ 382 } 383 384 /* port->lock is held by caller and interrupts are disabled. */ 385 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) 386 { 387 /* No signals are supported on HS UARTs */ 388 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 389 } 390 391 /* port->lock held by caller. */ 392 static void serial_lpc32xx_stop_tx(struct uart_port *port) 393 { 394 u32 tmp; 395 396 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 397 tmp &= ~LPC32XX_HSU_TX_INT_EN; 398 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 399 } 400 401 /* port->lock held by caller. */ 402 static void serial_lpc32xx_start_tx(struct uart_port *port) 403 { 404 u32 tmp; 405 406 __serial_lpc32xx_tx(port); 407 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 408 tmp |= LPC32XX_HSU_TX_INT_EN; 409 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 410 } 411 412 /* port->lock held by caller. */ 413 static void serial_lpc32xx_stop_rx(struct uart_port *port) 414 { 415 u32 tmp; 416 417 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 418 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 419 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 420 421 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | 422 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); 423 } 424 425 /* port->lock is not held. */ 426 static void serial_lpc32xx_break_ctl(struct uart_port *port, 427 int break_state) 428 { 429 unsigned long flags; 430 u32 tmp; 431 432 spin_lock_irqsave(&port->lock, flags); 433 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 434 if (break_state != 0) 435 tmp |= LPC32XX_HSU_BREAK; 436 else 437 tmp &= ~LPC32XX_HSU_BREAK; 438 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 439 spin_unlock_irqrestore(&port->lock, flags); 440 } 441 442 /* port->lock is not held. */ 443 static int serial_lpc32xx_startup(struct uart_port *port) 444 { 445 int retval; 446 unsigned long flags; 447 u32 tmp; 448 449 spin_lock_irqsave(&port->lock, flags); 450 451 __serial_uart_flush(port); 452 453 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 454 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 455 LPC32XX_HSUART_IIR(port->membase)); 456 457 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 458 459 /* 460 * Set receiver timeout, HSU offset of 20, no break, no interrupts, 461 * and default FIFO trigger levels 462 */ 463 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 464 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 465 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 466 467 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 468 469 spin_unlock_irqrestore(&port->lock, flags); 470 471 retval = request_irq(port->irq, serial_lpc32xx_interrupt, 472 0, MODNAME, port); 473 if (!retval) 474 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), 475 LPC32XX_HSUART_CTRL(port->membase)); 476 477 return retval; 478 } 479 480 /* port->lock is not held. */ 481 static void serial_lpc32xx_shutdown(struct uart_port *port) 482 { 483 u32 tmp; 484 unsigned long flags; 485 486 spin_lock_irqsave(&port->lock, flags); 487 488 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 489 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 490 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 491 492 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 493 494 spin_unlock_irqrestore(&port->lock, flags); 495 496 free_irq(port->irq, port); 497 } 498 499 /* port->lock is not held. */ 500 static void serial_lpc32xx_set_termios(struct uart_port *port, 501 struct ktermios *termios, 502 const struct ktermios *old) 503 { 504 unsigned long flags; 505 unsigned int baud, quot; 506 u32 tmp; 507 508 /* Always 8-bit, no parity, 1 stop bit */ 509 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 510 termios->c_cflag |= CS8; 511 512 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); 513 514 baud = uart_get_baud_rate(port, termios, old, 0, 515 port->uartclk / 14); 516 517 quot = __serial_get_clock_div(port->uartclk, baud); 518 519 spin_lock_irqsave(&port->lock, flags); 520 521 /* Ignore characters? */ 522 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 523 if ((termios->c_cflag & CREAD) == 0) 524 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 525 else 526 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; 527 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 528 529 writel(quot, LPC32XX_HSUART_RATE(port->membase)); 530 531 uart_update_timeout(port, termios->c_cflag, baud); 532 533 spin_unlock_irqrestore(&port->lock, flags); 534 535 /* Don't rewrite B0 */ 536 if (tty_termios_baud_rate(termios)) 537 tty_termios_encode_baud_rate(termios, baud, baud); 538 } 539 540 static const char *serial_lpc32xx_type(struct uart_port *port) 541 { 542 return MODNAME; 543 } 544 545 static void serial_lpc32xx_release_port(struct uart_port *port) 546 { 547 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 548 if (port->flags & UPF_IOREMAP) { 549 iounmap(port->membase); 550 port->membase = NULL; 551 } 552 553 release_mem_region(port->mapbase, SZ_4K); 554 } 555 } 556 557 static int serial_lpc32xx_request_port(struct uart_port *port) 558 { 559 int ret = -ENODEV; 560 561 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 562 ret = 0; 563 564 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) 565 ret = -EBUSY; 566 else if (port->flags & UPF_IOREMAP) { 567 port->membase = ioremap(port->mapbase, SZ_4K); 568 if (!port->membase) { 569 release_mem_region(port->mapbase, SZ_4K); 570 ret = -ENOMEM; 571 } 572 } 573 } 574 575 return ret; 576 } 577 578 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) 579 { 580 int ret; 581 582 ret = serial_lpc32xx_request_port(port); 583 if (ret < 0) 584 return; 585 port->type = PORT_UART00; 586 port->fifosize = 64; 587 588 __serial_uart_flush(port); 589 590 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 591 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 592 LPC32XX_HSUART_IIR(port->membase)); 593 594 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 595 596 /* Set receiver timeout, HSU offset of 20, no break, no interrupts, 597 and default FIFO trigger levels */ 598 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 599 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, 600 LPC32XX_HSUART_CTRL(port->membase)); 601 } 602 603 static int serial_lpc32xx_verify_port(struct uart_port *port, 604 struct serial_struct *ser) 605 { 606 int ret = 0; 607 608 if (ser->type != PORT_UART00) 609 ret = -EINVAL; 610 611 return ret; 612 } 613 614 static const struct uart_ops serial_lpc32xx_pops = { 615 .tx_empty = serial_lpc32xx_tx_empty, 616 .set_mctrl = serial_lpc32xx_set_mctrl, 617 .get_mctrl = serial_lpc32xx_get_mctrl, 618 .stop_tx = serial_lpc32xx_stop_tx, 619 .start_tx = serial_lpc32xx_start_tx, 620 .stop_rx = serial_lpc32xx_stop_rx, 621 .break_ctl = serial_lpc32xx_break_ctl, 622 .startup = serial_lpc32xx_startup, 623 .shutdown = serial_lpc32xx_shutdown, 624 .set_termios = serial_lpc32xx_set_termios, 625 .type = serial_lpc32xx_type, 626 .release_port = serial_lpc32xx_release_port, 627 .request_port = serial_lpc32xx_request_port, 628 .config_port = serial_lpc32xx_config_port, 629 .verify_port = serial_lpc32xx_verify_port, 630 }; 631 632 /* 633 * Register a set of serial devices attached to a platform device 634 */ 635 static int serial_hs_lpc32xx_probe(struct platform_device *pdev) 636 { 637 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; 638 int ret = 0; 639 struct resource *res; 640 641 if (uarts_registered >= MAX_PORTS) { 642 dev_err(&pdev->dev, 643 "Error: Number of possible ports exceeded (%d)!\n", 644 uarts_registered + 1); 645 return -ENXIO; 646 } 647 648 memset(p, 0, sizeof(*p)); 649 650 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 651 if (!res) { 652 dev_err(&pdev->dev, 653 "Error getting mem resource for HS UART port %d\n", 654 uarts_registered); 655 return -ENXIO; 656 } 657 p->port.mapbase = res->start; 658 p->port.membase = NULL; 659 660 ret = platform_get_irq(pdev, 0); 661 if (ret < 0) 662 return ret; 663 p->port.irq = ret; 664 665 p->port.iotype = UPIO_MEM32; 666 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; 667 p->port.regshift = 2; 668 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; 669 p->port.dev = &pdev->dev; 670 p->port.ops = &serial_lpc32xx_pops; 671 p->port.line = uarts_registered++; 672 spin_lock_init(&p->port.lock); 673 674 /* send port to loopback mode by default */ 675 lpc32xx_loopback_set(p->port.mapbase, 1); 676 677 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); 678 679 platform_set_drvdata(pdev, p); 680 681 return ret; 682 } 683 684 /* 685 * Remove serial ports registered against a platform device. 686 */ 687 static int serial_hs_lpc32xx_remove(struct platform_device *pdev) 688 { 689 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 690 691 uart_remove_one_port(&lpc32xx_hs_reg, &p->port); 692 693 return 0; 694 } 695 696 697 #ifdef CONFIG_PM 698 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, 699 pm_message_t state) 700 { 701 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 702 703 uart_suspend_port(&lpc32xx_hs_reg, &p->port); 704 705 return 0; 706 } 707 708 static int serial_hs_lpc32xx_resume(struct platform_device *pdev) 709 { 710 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 711 712 uart_resume_port(&lpc32xx_hs_reg, &p->port); 713 714 return 0; 715 } 716 #else 717 #define serial_hs_lpc32xx_suspend NULL 718 #define serial_hs_lpc32xx_resume NULL 719 #endif 720 721 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { 722 { .compatible = "nxp,lpc3220-hsuart" }, 723 { /* sentinel */ } 724 }; 725 726 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); 727 728 static struct platform_driver serial_hs_lpc32xx_driver = { 729 .probe = serial_hs_lpc32xx_probe, 730 .remove = serial_hs_lpc32xx_remove, 731 .suspend = serial_hs_lpc32xx_suspend, 732 .resume = serial_hs_lpc32xx_resume, 733 .driver = { 734 .name = MODNAME, 735 .of_match_table = serial_hs_lpc32xx_dt_ids, 736 }, 737 }; 738 739 static int __init lpc32xx_hsuart_init(void) 740 { 741 int ret; 742 743 ret = uart_register_driver(&lpc32xx_hs_reg); 744 if (ret) 745 return ret; 746 747 ret = platform_driver_register(&serial_hs_lpc32xx_driver); 748 if (ret) 749 uart_unregister_driver(&lpc32xx_hs_reg); 750 751 return ret; 752 } 753 754 static void __exit lpc32xx_hsuart_exit(void) 755 { 756 platform_driver_unregister(&serial_hs_lpc32xx_driver); 757 uart_unregister_driver(&lpc32xx_hs_reg); 758 } 759 760 module_init(lpc32xx_hsuart_init); 761 module_exit(lpc32xx_hsuart_exit); 762 763 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 764 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 765 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); 766 MODULE_LICENSE("GPL"); 767