1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * High Speed Serial Ports on NXP LPC32xx SoC 4 * 5 * Authors: Kevin Wells <kevin.wells@nxp.com> 6 * Roland Stigge <stigge@antcom.de> 7 * 8 * Copyright (C) 2010 NXP Semiconductors 9 * Copyright (C) 2012 Roland Stigge 10 */ 11 12 #include <linux/module.h> 13 #include <linux/ioport.h> 14 #include <linux/init.h> 15 #include <linux/console.h> 16 #include <linux/sysrq.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/platform_device.h> 22 #include <linux/delay.h> 23 #include <linux/nmi.h> 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/of.h> 27 #include <linux/sizes.h> 28 #include <linux/soc/nxp/lpc32xx-misc.h> 29 30 /* 31 * High Speed UART register offsets 32 */ 33 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) 34 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) 35 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08) 36 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) 37 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10) 38 39 #define LPC32XX_HSU_BREAK_DATA (1 << 10) 40 #define LPC32XX_HSU_ERROR_DATA (1 << 9) 41 #define LPC32XX_HSU_RX_EMPTY (1 << 8) 42 43 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) 44 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) 45 46 #define LPC32XX_HSU_TX_INT_SET (1 << 6) 47 #define LPC32XX_HSU_RX_OE_INT (1 << 5) 48 #define LPC32XX_HSU_BRK_INT (1 << 4) 49 #define LPC32XX_HSU_FE_INT (1 << 3) 50 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) 51 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1) 52 #define LPC32XX_HSU_TX_INT (1 << 0) 53 54 #define LPC32XX_HSU_HRTS_INV (1 << 21) 55 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) 56 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) 57 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) 58 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) 59 #define LPC32XX_HSU_HRTS_EN (1 << 18) 60 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) 61 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) 62 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) 63 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) 64 #define LPC32XX_HSU_HCTS_INV (1 << 15) 65 #define LPC32XX_HSU_HCTS_EN (1 << 14) 66 #define LPC32XX_HSU_OFFSET(n) ((n) << 9) 67 #define LPC32XX_HSU_BREAK (1 << 8) 68 #define LPC32XX_HSU_ERR_INT_EN (1 << 7) 69 #define LPC32XX_HSU_RX_INT_EN (1 << 6) 70 #define LPC32XX_HSU_TX_INT_EN (1 << 5) 71 #define LPC32XX_HSU_RX_TL1B (0x0 << 2) 72 #define LPC32XX_HSU_RX_TL4B (0x1 << 2) 73 #define LPC32XX_HSU_RX_TL8B (0x2 << 2) 74 #define LPC32XX_HSU_RX_TL16B (0x3 << 2) 75 #define LPC32XX_HSU_RX_TL32B (0x4 << 2) 76 #define LPC32XX_HSU_RX_TL48B (0x5 << 2) 77 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) 78 #define LPC32XX_HSU_TX_TL0B (0x0 << 0) 79 #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 80 #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 81 #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 82 83 #define LPC32XX_MAIN_OSC_FREQ 13000000 84 85 #define MODNAME "lpc32xx_hsuart" 86 87 struct lpc32xx_hsuart_port { 88 struct uart_port port; 89 }; 90 91 #define FIFO_READ_LIMIT 128 92 #define MAX_PORTS 3 93 #define LPC32XX_TTY_NAME "ttyTX" 94 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; 95 96 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE 97 static void wait_for_xmit_empty(struct uart_port *port) 98 { 99 unsigned int timeout = 10000; 100 101 do { 102 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 103 port->membase))) == 0) 104 break; 105 if (--timeout == 0) 106 break; 107 udelay(1); 108 } while (1); 109 } 110 111 static void wait_for_xmit_ready(struct uart_port *port) 112 { 113 unsigned int timeout = 10000; 114 115 while (1) { 116 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 117 port->membase))) < 32) 118 break; 119 if (--timeout == 0) 120 break; 121 udelay(1); 122 } 123 } 124 125 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch) 126 { 127 wait_for_xmit_ready(port); 128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 129 } 130 131 static void lpc32xx_hsuart_console_write(struct console *co, const char *s, 132 unsigned int count) 133 { 134 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; 135 unsigned long flags; 136 int locked = 1; 137 138 touch_nmi_watchdog(); 139 local_irq_save(flags); 140 if (up->port.sysrq) 141 locked = 0; 142 else if (oops_in_progress) 143 locked = spin_trylock(&up->port.lock); 144 else 145 spin_lock(&up->port.lock); 146 147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 148 wait_for_xmit_empty(&up->port); 149 150 if (locked) 151 spin_unlock(&up->port.lock); 152 local_irq_restore(flags); 153 } 154 155 static int __init lpc32xx_hsuart_console_setup(struct console *co, 156 char *options) 157 { 158 struct uart_port *port; 159 int baud = 115200; 160 int bits = 8; 161 int parity = 'n'; 162 int flow = 'n'; 163 164 if (co->index >= MAX_PORTS) 165 co->index = 0; 166 167 port = &lpc32xx_hs_ports[co->index].port; 168 if (!port->membase) 169 return -ENODEV; 170 171 if (options) 172 uart_parse_options(options, &baud, &parity, &bits, &flow); 173 174 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 175 176 return uart_set_options(port, co, baud, parity, bits, flow); 177 } 178 179 static struct uart_driver lpc32xx_hsuart_reg; 180 static struct console lpc32xx_hsuart_console = { 181 .name = LPC32XX_TTY_NAME, 182 .write = lpc32xx_hsuart_console_write, 183 .device = uart_console_device, 184 .setup = lpc32xx_hsuart_console_setup, 185 .flags = CON_PRINTBUFFER, 186 .index = -1, 187 .data = &lpc32xx_hsuart_reg, 188 }; 189 190 static int __init lpc32xx_hsuart_console_init(void) 191 { 192 register_console(&lpc32xx_hsuart_console); 193 return 0; 194 } 195 console_initcall(lpc32xx_hsuart_console_init); 196 197 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) 198 #else 199 #define LPC32XX_HSUART_CONSOLE NULL 200 #endif 201 202 static struct uart_driver lpc32xx_hs_reg = { 203 .owner = THIS_MODULE, 204 .driver_name = MODNAME, 205 .dev_name = LPC32XX_TTY_NAME, 206 .nr = MAX_PORTS, 207 .cons = LPC32XX_HSUART_CONSOLE, 208 }; 209 static int uarts_registered; 210 211 static unsigned int __serial_get_clock_div(unsigned long uartclk, 212 unsigned long rate) 213 { 214 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; 215 u32 rate_diff; 216 217 /* Find the closest divider to get the desired clock rate */ 218 div = uartclk / rate; 219 goodrate = hsu_rate = (div / 14) - 1; 220 if (hsu_rate != 0) 221 hsu_rate--; 222 223 /* Tweak divider */ 224 l_hsu_rate = hsu_rate + 3; 225 rate_diff = 0xFFFFFFFF; 226 227 while (hsu_rate < l_hsu_rate) { 228 comprate = uartclk / ((hsu_rate + 1) * 14); 229 if (abs(comprate - rate) < rate_diff) { 230 goodrate = hsu_rate; 231 rate_diff = abs(comprate - rate); 232 } 233 234 hsu_rate++; 235 } 236 if (hsu_rate > 0xFF) 237 hsu_rate = 0xFF; 238 239 return goodrate; 240 } 241 242 static void __serial_uart_flush(struct uart_port *port) 243 { 244 int cnt = 0; 245 246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 247 (cnt++ < FIFO_READ_LIMIT)) 248 readl(LPC32XX_HSUART_FIFO(port->membase)); 249 } 250 251 static void __serial_lpc32xx_rx(struct uart_port *port) 252 { 253 struct tty_port *tport = &port->state->port; 254 unsigned int tmp, flag; 255 256 /* Read data from FIFO and push into terminal */ 257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 258 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { 259 flag = TTY_NORMAL; 260 port->icount.rx++; 261 262 if (tmp & LPC32XX_HSU_ERROR_DATA) { 263 /* Framing error */ 264 writel(LPC32XX_HSU_FE_INT, 265 LPC32XX_HSUART_IIR(port->membase)); 266 port->icount.frame++; 267 flag = TTY_FRAME; 268 tty_insert_flip_char(tport, 0, TTY_FRAME); 269 } 270 271 tty_insert_flip_char(tport, (tmp & 0xFF), flag); 272 273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 274 } 275 276 tty_flip_buffer_push(tport); 277 } 278 279 static void __serial_lpc32xx_tx(struct uart_port *port) 280 { 281 struct circ_buf *xmit = &port->state->xmit; 282 unsigned int tmp; 283 284 if (port->x_char) { 285 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 286 port->icount.tx++; 287 port->x_char = 0; 288 return; 289 } 290 291 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 292 goto exit_tx; 293 294 /* Transfer data */ 295 while (LPC32XX_HSU_TX_LEV(readl( 296 LPC32XX_HSUART_LEVEL(port->membase))) < 64) { 297 writel((u32) xmit->buf[xmit->tail], 298 LPC32XX_HSUART_FIFO(port->membase)); 299 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 300 port->icount.tx++; 301 if (uart_circ_empty(xmit)) 302 break; 303 } 304 305 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 306 uart_write_wakeup(port); 307 308 exit_tx: 309 if (uart_circ_empty(xmit)) { 310 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 311 tmp &= ~LPC32XX_HSU_TX_INT_EN; 312 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 313 } 314 } 315 316 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) 317 { 318 struct uart_port *port = dev_id; 319 struct tty_port *tport = &port->state->port; 320 u32 status; 321 322 spin_lock(&port->lock); 323 324 /* Read UART status and clear latched interrupts */ 325 status = readl(LPC32XX_HSUART_IIR(port->membase)); 326 327 if (status & LPC32XX_HSU_BRK_INT) { 328 /* Break received */ 329 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 330 port->icount.brk++; 331 uart_handle_break(port); 332 } 333 334 /* Framing error */ 335 if (status & LPC32XX_HSU_FE_INT) 336 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 337 338 if (status & LPC32XX_HSU_RX_OE_INT) { 339 /* Receive FIFO overrun */ 340 writel(LPC32XX_HSU_RX_OE_INT, 341 LPC32XX_HSUART_IIR(port->membase)); 342 port->icount.overrun++; 343 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 344 tty_schedule_flip(tport); 345 } 346 347 /* Data received? */ 348 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) 349 __serial_lpc32xx_rx(port); 350 351 /* Transmit data request? */ 352 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { 353 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 354 __serial_lpc32xx_tx(port); 355 } 356 357 spin_unlock(&port->lock); 358 359 return IRQ_HANDLED; 360 } 361 362 /* port->lock is not held. */ 363 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) 364 { 365 unsigned int ret = 0; 366 367 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) 368 ret = TIOCSER_TEMT; 369 370 return ret; 371 } 372 373 /* port->lock held by caller. */ 374 static void serial_lpc32xx_set_mctrl(struct uart_port *port, 375 unsigned int mctrl) 376 { 377 /* No signals are supported on HS UARTs */ 378 } 379 380 /* port->lock is held by caller and interrupts are disabled. */ 381 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) 382 { 383 /* No signals are supported on HS UARTs */ 384 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 385 } 386 387 /* port->lock held by caller. */ 388 static void serial_lpc32xx_stop_tx(struct uart_port *port) 389 { 390 u32 tmp; 391 392 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 393 tmp &= ~LPC32XX_HSU_TX_INT_EN; 394 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 395 } 396 397 /* port->lock held by caller. */ 398 static void serial_lpc32xx_start_tx(struct uart_port *port) 399 { 400 u32 tmp; 401 402 __serial_lpc32xx_tx(port); 403 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 404 tmp |= LPC32XX_HSU_TX_INT_EN; 405 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 406 } 407 408 /* port->lock held by caller. */ 409 static void serial_lpc32xx_stop_rx(struct uart_port *port) 410 { 411 u32 tmp; 412 413 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 414 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 415 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 416 417 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | 418 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); 419 } 420 421 /* port->lock is not held. */ 422 static void serial_lpc32xx_break_ctl(struct uart_port *port, 423 int break_state) 424 { 425 unsigned long flags; 426 u32 tmp; 427 428 spin_lock_irqsave(&port->lock, flags); 429 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 430 if (break_state != 0) 431 tmp |= LPC32XX_HSU_BREAK; 432 else 433 tmp &= ~LPC32XX_HSU_BREAK; 434 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 435 spin_unlock_irqrestore(&port->lock, flags); 436 } 437 438 /* port->lock is not held. */ 439 static int serial_lpc32xx_startup(struct uart_port *port) 440 { 441 int retval; 442 unsigned long flags; 443 u32 tmp; 444 445 spin_lock_irqsave(&port->lock, flags); 446 447 __serial_uart_flush(port); 448 449 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 450 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 451 LPC32XX_HSUART_IIR(port->membase)); 452 453 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 454 455 /* 456 * Set receiver timeout, HSU offset of 20, no break, no interrupts, 457 * and default FIFO trigger levels 458 */ 459 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 460 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 461 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 462 463 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 464 465 spin_unlock_irqrestore(&port->lock, flags); 466 467 retval = request_irq(port->irq, serial_lpc32xx_interrupt, 468 0, MODNAME, port); 469 if (!retval) 470 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), 471 LPC32XX_HSUART_CTRL(port->membase)); 472 473 return retval; 474 } 475 476 /* port->lock is not held. */ 477 static void serial_lpc32xx_shutdown(struct uart_port *port) 478 { 479 u32 tmp; 480 unsigned long flags; 481 482 spin_lock_irqsave(&port->lock, flags); 483 484 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 485 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 486 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 487 488 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 489 490 spin_unlock_irqrestore(&port->lock, flags); 491 492 free_irq(port->irq, port); 493 } 494 495 /* port->lock is not held. */ 496 static void serial_lpc32xx_set_termios(struct uart_port *port, 497 struct ktermios *termios, 498 struct ktermios *old) 499 { 500 unsigned long flags; 501 unsigned int baud, quot; 502 u32 tmp; 503 504 /* Always 8-bit, no parity, 1 stop bit */ 505 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 506 termios->c_cflag |= CS8; 507 508 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); 509 510 baud = uart_get_baud_rate(port, termios, old, 0, 511 port->uartclk / 14); 512 513 quot = __serial_get_clock_div(port->uartclk, baud); 514 515 spin_lock_irqsave(&port->lock, flags); 516 517 /* Ignore characters? */ 518 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 519 if ((termios->c_cflag & CREAD) == 0) 520 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 521 else 522 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; 523 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 524 525 writel(quot, LPC32XX_HSUART_RATE(port->membase)); 526 527 uart_update_timeout(port, termios->c_cflag, baud); 528 529 spin_unlock_irqrestore(&port->lock, flags); 530 531 /* Don't rewrite B0 */ 532 if (tty_termios_baud_rate(termios)) 533 tty_termios_encode_baud_rate(termios, baud, baud); 534 } 535 536 static const char *serial_lpc32xx_type(struct uart_port *port) 537 { 538 return MODNAME; 539 } 540 541 static void serial_lpc32xx_release_port(struct uart_port *port) 542 { 543 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 544 if (port->flags & UPF_IOREMAP) { 545 iounmap(port->membase); 546 port->membase = NULL; 547 } 548 549 release_mem_region(port->mapbase, SZ_4K); 550 } 551 } 552 553 static int serial_lpc32xx_request_port(struct uart_port *port) 554 { 555 int ret = -ENODEV; 556 557 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 558 ret = 0; 559 560 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) 561 ret = -EBUSY; 562 else if (port->flags & UPF_IOREMAP) { 563 port->membase = ioremap(port->mapbase, SZ_4K); 564 if (!port->membase) { 565 release_mem_region(port->mapbase, SZ_4K); 566 ret = -ENOMEM; 567 } 568 } 569 } 570 571 return ret; 572 } 573 574 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) 575 { 576 int ret; 577 578 ret = serial_lpc32xx_request_port(port); 579 if (ret < 0) 580 return; 581 port->type = PORT_UART00; 582 port->fifosize = 64; 583 584 __serial_uart_flush(port); 585 586 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 587 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 588 LPC32XX_HSUART_IIR(port->membase)); 589 590 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 591 592 /* Set receiver timeout, HSU offset of 20, no break, no interrupts, 593 and default FIFO trigger levels */ 594 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 595 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, 596 LPC32XX_HSUART_CTRL(port->membase)); 597 } 598 599 static int serial_lpc32xx_verify_port(struct uart_port *port, 600 struct serial_struct *ser) 601 { 602 int ret = 0; 603 604 if (ser->type != PORT_UART00) 605 ret = -EINVAL; 606 607 return ret; 608 } 609 610 static const struct uart_ops serial_lpc32xx_pops = { 611 .tx_empty = serial_lpc32xx_tx_empty, 612 .set_mctrl = serial_lpc32xx_set_mctrl, 613 .get_mctrl = serial_lpc32xx_get_mctrl, 614 .stop_tx = serial_lpc32xx_stop_tx, 615 .start_tx = serial_lpc32xx_start_tx, 616 .stop_rx = serial_lpc32xx_stop_rx, 617 .break_ctl = serial_lpc32xx_break_ctl, 618 .startup = serial_lpc32xx_startup, 619 .shutdown = serial_lpc32xx_shutdown, 620 .set_termios = serial_lpc32xx_set_termios, 621 .type = serial_lpc32xx_type, 622 .release_port = serial_lpc32xx_release_port, 623 .request_port = serial_lpc32xx_request_port, 624 .config_port = serial_lpc32xx_config_port, 625 .verify_port = serial_lpc32xx_verify_port, 626 }; 627 628 /* 629 * Register a set of serial devices attached to a platform device 630 */ 631 static int serial_hs_lpc32xx_probe(struct platform_device *pdev) 632 { 633 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; 634 int ret = 0; 635 struct resource *res; 636 637 if (uarts_registered >= MAX_PORTS) { 638 dev_err(&pdev->dev, 639 "Error: Number of possible ports exceeded (%d)!\n", 640 uarts_registered + 1); 641 return -ENXIO; 642 } 643 644 memset(p, 0, sizeof(*p)); 645 646 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 647 if (!res) { 648 dev_err(&pdev->dev, 649 "Error getting mem resource for HS UART port %d\n", 650 uarts_registered); 651 return -ENXIO; 652 } 653 p->port.mapbase = res->start; 654 p->port.membase = NULL; 655 656 ret = platform_get_irq(pdev, 0); 657 if (ret < 0) 658 return ret; 659 p->port.irq = ret; 660 661 p->port.iotype = UPIO_MEM32; 662 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; 663 p->port.regshift = 2; 664 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; 665 p->port.dev = &pdev->dev; 666 p->port.ops = &serial_lpc32xx_pops; 667 p->port.line = uarts_registered++; 668 spin_lock_init(&p->port.lock); 669 670 /* send port to loopback mode by default */ 671 lpc32xx_loopback_set(p->port.mapbase, 1); 672 673 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); 674 675 platform_set_drvdata(pdev, p); 676 677 return ret; 678 } 679 680 /* 681 * Remove serial ports registered against a platform device. 682 */ 683 static int serial_hs_lpc32xx_remove(struct platform_device *pdev) 684 { 685 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 686 687 uart_remove_one_port(&lpc32xx_hs_reg, &p->port); 688 689 return 0; 690 } 691 692 693 #ifdef CONFIG_PM 694 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, 695 pm_message_t state) 696 { 697 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 698 699 uart_suspend_port(&lpc32xx_hs_reg, &p->port); 700 701 return 0; 702 } 703 704 static int serial_hs_lpc32xx_resume(struct platform_device *pdev) 705 { 706 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 707 708 uart_resume_port(&lpc32xx_hs_reg, &p->port); 709 710 return 0; 711 } 712 #else 713 #define serial_hs_lpc32xx_suspend NULL 714 #define serial_hs_lpc32xx_resume NULL 715 #endif 716 717 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { 718 { .compatible = "nxp,lpc3220-hsuart" }, 719 { /* sentinel */ } 720 }; 721 722 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); 723 724 static struct platform_driver serial_hs_lpc32xx_driver = { 725 .probe = serial_hs_lpc32xx_probe, 726 .remove = serial_hs_lpc32xx_remove, 727 .suspend = serial_hs_lpc32xx_suspend, 728 .resume = serial_hs_lpc32xx_resume, 729 .driver = { 730 .name = MODNAME, 731 .of_match_table = serial_hs_lpc32xx_dt_ids, 732 }, 733 }; 734 735 static int __init lpc32xx_hsuart_init(void) 736 { 737 int ret; 738 739 ret = uart_register_driver(&lpc32xx_hs_reg); 740 if (ret) 741 return ret; 742 743 ret = platform_driver_register(&serial_hs_lpc32xx_driver); 744 if (ret) 745 uart_unregister_driver(&lpc32xx_hs_reg); 746 747 return ret; 748 } 749 750 static void __exit lpc32xx_hsuart_exit(void) 751 { 752 platform_driver_unregister(&serial_hs_lpc32xx_driver); 753 uart_unregister_driver(&lpc32xx_hs_reg); 754 } 755 756 module_init(lpc32xx_hsuart_init); 757 module_exit(lpc32xx_hsuart_exit); 758 759 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 760 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 761 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); 762 MODULE_LICENSE("GPL"); 763