1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * High Speed Serial Ports on NXP LPC32xx SoC 4 * 5 * Authors: Kevin Wells <kevin.wells@nxp.com> 6 * Roland Stigge <stigge@antcom.de> 7 * 8 * Copyright (C) 2010 NXP Semiconductors 9 * Copyright (C) 2012 Roland Stigge 10 */ 11 12 #include <linux/module.h> 13 #include <linux/ioport.h> 14 #include <linux/init.h> 15 #include <linux/console.h> 16 #include <linux/sysrq.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/platform_device.h> 22 #include <linux/delay.h> 23 #include <linux/nmi.h> 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/of.h> 27 #include <linux/sizes.h> 28 #include <linux/soc/nxp/lpc32xx-misc.h> 29 30 /* 31 * High Speed UART register offsets 32 */ 33 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) 34 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) 35 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08) 36 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) 37 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10) 38 39 #define LPC32XX_HSU_BREAK_DATA (1 << 10) 40 #define LPC32XX_HSU_ERROR_DATA (1 << 9) 41 #define LPC32XX_HSU_RX_EMPTY (1 << 8) 42 43 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) 44 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) 45 46 #define LPC32XX_HSU_TX_INT_SET (1 << 6) 47 #define LPC32XX_HSU_RX_OE_INT (1 << 5) 48 #define LPC32XX_HSU_BRK_INT (1 << 4) 49 #define LPC32XX_HSU_FE_INT (1 << 3) 50 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) 51 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1) 52 #define LPC32XX_HSU_TX_INT (1 << 0) 53 54 #define LPC32XX_HSU_HRTS_INV (1 << 21) 55 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) 56 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) 57 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) 58 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) 59 #define LPC32XX_HSU_HRTS_EN (1 << 18) 60 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) 61 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) 62 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) 63 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) 64 #define LPC32XX_HSU_HCTS_INV (1 << 15) 65 #define LPC32XX_HSU_HCTS_EN (1 << 14) 66 #define LPC32XX_HSU_OFFSET(n) ((n) << 9) 67 #define LPC32XX_HSU_BREAK (1 << 8) 68 #define LPC32XX_HSU_ERR_INT_EN (1 << 7) 69 #define LPC32XX_HSU_RX_INT_EN (1 << 6) 70 #define LPC32XX_HSU_TX_INT_EN (1 << 5) 71 #define LPC32XX_HSU_RX_TL1B (0x0 << 2) 72 #define LPC32XX_HSU_RX_TL4B (0x1 << 2) 73 #define LPC32XX_HSU_RX_TL8B (0x2 << 2) 74 #define LPC32XX_HSU_RX_TL16B (0x3 << 2) 75 #define LPC32XX_HSU_RX_TL32B (0x4 << 2) 76 #define LPC32XX_HSU_RX_TL48B (0x5 << 2) 77 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) 78 #define LPC32XX_HSU_TX_TL0B (0x0 << 0) 79 #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 80 #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 81 #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 82 83 #define LPC32XX_MAIN_OSC_FREQ 13000000 84 85 #define MODNAME "lpc32xx_hsuart" 86 87 struct lpc32xx_hsuart_port { 88 struct uart_port port; 89 }; 90 91 #define FIFO_READ_LIMIT 128 92 #define MAX_PORTS 3 93 #define LPC32XX_TTY_NAME "ttyTX" 94 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; 95 96 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE 97 static void wait_for_xmit_empty(struct uart_port *port) 98 { 99 unsigned int timeout = 10000; 100 101 do { 102 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 103 port->membase))) == 0) 104 break; 105 if (--timeout == 0) 106 break; 107 udelay(1); 108 } while (1); 109 } 110 111 static void wait_for_xmit_ready(struct uart_port *port) 112 { 113 unsigned int timeout = 10000; 114 115 while (1) { 116 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 117 port->membase))) < 32) 118 break; 119 if (--timeout == 0) 120 break; 121 udelay(1); 122 } 123 } 124 125 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, unsigned char ch) 126 { 127 wait_for_xmit_ready(port); 128 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 129 } 130 131 static void lpc32xx_hsuart_console_write(struct console *co, const char *s, 132 unsigned int count) 133 { 134 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; 135 unsigned long flags; 136 int locked = 1; 137 138 touch_nmi_watchdog(); 139 local_irq_save(flags); 140 if (up->port.sysrq) 141 locked = 0; 142 else if (oops_in_progress) 143 locked = spin_trylock(&up->port.lock); 144 else 145 spin_lock(&up->port.lock); 146 147 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 148 wait_for_xmit_empty(&up->port); 149 150 if (locked) 151 spin_unlock(&up->port.lock); 152 local_irq_restore(flags); 153 } 154 155 static int __init lpc32xx_hsuart_console_setup(struct console *co, 156 char *options) 157 { 158 struct uart_port *port; 159 int baud = 115200; 160 int bits = 8; 161 int parity = 'n'; 162 int flow = 'n'; 163 164 if (co->index >= MAX_PORTS) 165 co->index = 0; 166 167 port = &lpc32xx_hs_ports[co->index].port; 168 if (!port->membase) 169 return -ENODEV; 170 171 if (options) 172 uart_parse_options(options, &baud, &parity, &bits, &flow); 173 174 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 175 176 return uart_set_options(port, co, baud, parity, bits, flow); 177 } 178 179 static struct uart_driver lpc32xx_hsuart_reg; 180 static struct console lpc32xx_hsuart_console = { 181 .name = LPC32XX_TTY_NAME, 182 .write = lpc32xx_hsuart_console_write, 183 .device = uart_console_device, 184 .setup = lpc32xx_hsuart_console_setup, 185 .flags = CON_PRINTBUFFER, 186 .index = -1, 187 .data = &lpc32xx_hsuart_reg, 188 }; 189 190 static int __init lpc32xx_hsuart_console_init(void) 191 { 192 register_console(&lpc32xx_hsuart_console); 193 return 0; 194 } 195 console_initcall(lpc32xx_hsuart_console_init); 196 197 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) 198 #else 199 #define LPC32XX_HSUART_CONSOLE NULL 200 #endif 201 202 static struct uart_driver lpc32xx_hs_reg = { 203 .owner = THIS_MODULE, 204 .driver_name = MODNAME, 205 .dev_name = LPC32XX_TTY_NAME, 206 .nr = MAX_PORTS, 207 .cons = LPC32XX_HSUART_CONSOLE, 208 }; 209 static int uarts_registered; 210 211 static unsigned int __serial_get_clock_div(unsigned long uartclk, 212 unsigned long rate) 213 { 214 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; 215 u32 rate_diff; 216 217 /* Find the closest divider to get the desired clock rate */ 218 div = uartclk / rate; 219 goodrate = hsu_rate = (div / 14) - 1; 220 if (hsu_rate != 0) 221 hsu_rate--; 222 223 /* Tweak divider */ 224 l_hsu_rate = hsu_rate + 3; 225 rate_diff = 0xFFFFFFFF; 226 227 while (hsu_rate < l_hsu_rate) { 228 comprate = uartclk / ((hsu_rate + 1) * 14); 229 if (abs(comprate - rate) < rate_diff) { 230 goodrate = hsu_rate; 231 rate_diff = abs(comprate - rate); 232 } 233 234 hsu_rate++; 235 } 236 if (hsu_rate > 0xFF) 237 hsu_rate = 0xFF; 238 239 return goodrate; 240 } 241 242 static void __serial_uart_flush(struct uart_port *port) 243 { 244 int cnt = 0; 245 246 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 247 (cnt++ < FIFO_READ_LIMIT)) 248 readl(LPC32XX_HSUART_FIFO(port->membase)); 249 } 250 251 static void __serial_lpc32xx_rx(struct uart_port *port) 252 { 253 struct tty_port *tport = &port->state->port; 254 unsigned int tmp, flag; 255 256 /* Read data from FIFO and push into terminal */ 257 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 258 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { 259 flag = TTY_NORMAL; 260 port->icount.rx++; 261 262 if (tmp & LPC32XX_HSU_ERROR_DATA) { 263 /* Framing error */ 264 writel(LPC32XX_HSU_FE_INT, 265 LPC32XX_HSUART_IIR(port->membase)); 266 port->icount.frame++; 267 flag = TTY_FRAME; 268 tty_insert_flip_char(tport, 0, TTY_FRAME); 269 } 270 271 tty_insert_flip_char(tport, (tmp & 0xFF), flag); 272 273 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 274 } 275 276 tty_flip_buffer_push(tport); 277 } 278 279 static void serial_lpc32xx_stop_tx(struct uart_port *port); 280 281 static void __serial_lpc32xx_tx(struct uart_port *port) 282 { 283 struct circ_buf *xmit = &port->state->xmit; 284 285 if (port->x_char) { 286 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 287 port->icount.tx++; 288 port->x_char = 0; 289 return; 290 } 291 292 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 293 goto exit_tx; 294 295 /* Transfer data */ 296 while (LPC32XX_HSU_TX_LEV(readl( 297 LPC32XX_HSUART_LEVEL(port->membase))) < 64) { 298 writel((u32) xmit->buf[xmit->tail], 299 LPC32XX_HSUART_FIFO(port->membase)); 300 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 301 port->icount.tx++; 302 if (uart_circ_empty(xmit)) 303 break; 304 } 305 306 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 307 uart_write_wakeup(port); 308 309 exit_tx: 310 if (uart_circ_empty(xmit)) 311 serial_lpc32xx_stop_tx(port); 312 } 313 314 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) 315 { 316 struct uart_port *port = dev_id; 317 struct tty_port *tport = &port->state->port; 318 u32 status; 319 320 spin_lock(&port->lock); 321 322 /* Read UART status and clear latched interrupts */ 323 status = readl(LPC32XX_HSUART_IIR(port->membase)); 324 325 if (status & LPC32XX_HSU_BRK_INT) { 326 /* Break received */ 327 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 328 port->icount.brk++; 329 uart_handle_break(port); 330 } 331 332 /* Framing error */ 333 if (status & LPC32XX_HSU_FE_INT) 334 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 335 336 if (status & LPC32XX_HSU_RX_OE_INT) { 337 /* Receive FIFO overrun */ 338 writel(LPC32XX_HSU_RX_OE_INT, 339 LPC32XX_HSUART_IIR(port->membase)); 340 port->icount.overrun++; 341 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 342 tty_flip_buffer_push(tport); 343 } 344 345 /* Data received? */ 346 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) 347 __serial_lpc32xx_rx(port); 348 349 /* Transmit data request? */ 350 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { 351 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 352 __serial_lpc32xx_tx(port); 353 } 354 355 spin_unlock(&port->lock); 356 357 return IRQ_HANDLED; 358 } 359 360 /* port->lock is not held. */ 361 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) 362 { 363 unsigned int ret = 0; 364 365 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) 366 ret = TIOCSER_TEMT; 367 368 return ret; 369 } 370 371 /* port->lock held by caller. */ 372 static void serial_lpc32xx_set_mctrl(struct uart_port *port, 373 unsigned int mctrl) 374 { 375 /* No signals are supported on HS UARTs */ 376 } 377 378 /* port->lock is held by caller and interrupts are disabled. */ 379 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) 380 { 381 /* No signals are supported on HS UARTs */ 382 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 383 } 384 385 /* port->lock held by caller. */ 386 static void serial_lpc32xx_stop_tx(struct uart_port *port) 387 { 388 u32 tmp; 389 390 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 391 tmp &= ~LPC32XX_HSU_TX_INT_EN; 392 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 393 } 394 395 /* port->lock held by caller. */ 396 static void serial_lpc32xx_start_tx(struct uart_port *port) 397 { 398 u32 tmp; 399 400 __serial_lpc32xx_tx(port); 401 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 402 tmp |= LPC32XX_HSU_TX_INT_EN; 403 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 404 } 405 406 /* port->lock held by caller. */ 407 static void serial_lpc32xx_stop_rx(struct uart_port *port) 408 { 409 u32 tmp; 410 411 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 412 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 413 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 414 415 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | 416 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); 417 } 418 419 /* port->lock is not held. */ 420 static void serial_lpc32xx_break_ctl(struct uart_port *port, 421 int break_state) 422 { 423 unsigned long flags; 424 u32 tmp; 425 426 spin_lock_irqsave(&port->lock, flags); 427 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 428 if (break_state != 0) 429 tmp |= LPC32XX_HSU_BREAK; 430 else 431 tmp &= ~LPC32XX_HSU_BREAK; 432 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 433 spin_unlock_irqrestore(&port->lock, flags); 434 } 435 436 /* port->lock is not held. */ 437 static int serial_lpc32xx_startup(struct uart_port *port) 438 { 439 int retval; 440 unsigned long flags; 441 u32 tmp; 442 443 spin_lock_irqsave(&port->lock, flags); 444 445 __serial_uart_flush(port); 446 447 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 448 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 449 LPC32XX_HSUART_IIR(port->membase)); 450 451 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 452 453 /* 454 * Set receiver timeout, HSU offset of 20, no break, no interrupts, 455 * and default FIFO trigger levels 456 */ 457 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 458 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 459 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 460 461 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 462 463 spin_unlock_irqrestore(&port->lock, flags); 464 465 retval = request_irq(port->irq, serial_lpc32xx_interrupt, 466 0, MODNAME, port); 467 if (!retval) 468 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), 469 LPC32XX_HSUART_CTRL(port->membase)); 470 471 return retval; 472 } 473 474 /* port->lock is not held. */ 475 static void serial_lpc32xx_shutdown(struct uart_port *port) 476 { 477 u32 tmp; 478 unsigned long flags; 479 480 spin_lock_irqsave(&port->lock, flags); 481 482 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 483 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 484 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 485 486 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 487 488 spin_unlock_irqrestore(&port->lock, flags); 489 490 free_irq(port->irq, port); 491 } 492 493 /* port->lock is not held. */ 494 static void serial_lpc32xx_set_termios(struct uart_port *port, 495 struct ktermios *termios, 496 struct ktermios *old) 497 { 498 unsigned long flags; 499 unsigned int baud, quot; 500 u32 tmp; 501 502 /* Always 8-bit, no parity, 1 stop bit */ 503 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 504 termios->c_cflag |= CS8; 505 506 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); 507 508 baud = uart_get_baud_rate(port, termios, old, 0, 509 port->uartclk / 14); 510 511 quot = __serial_get_clock_div(port->uartclk, baud); 512 513 spin_lock_irqsave(&port->lock, flags); 514 515 /* Ignore characters? */ 516 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 517 if ((termios->c_cflag & CREAD) == 0) 518 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 519 else 520 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; 521 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 522 523 writel(quot, LPC32XX_HSUART_RATE(port->membase)); 524 525 uart_update_timeout(port, termios->c_cflag, baud); 526 527 spin_unlock_irqrestore(&port->lock, flags); 528 529 /* Don't rewrite B0 */ 530 if (tty_termios_baud_rate(termios)) 531 tty_termios_encode_baud_rate(termios, baud, baud); 532 } 533 534 static const char *serial_lpc32xx_type(struct uart_port *port) 535 { 536 return MODNAME; 537 } 538 539 static void serial_lpc32xx_release_port(struct uart_port *port) 540 { 541 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 542 if (port->flags & UPF_IOREMAP) { 543 iounmap(port->membase); 544 port->membase = NULL; 545 } 546 547 release_mem_region(port->mapbase, SZ_4K); 548 } 549 } 550 551 static int serial_lpc32xx_request_port(struct uart_port *port) 552 { 553 int ret = -ENODEV; 554 555 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 556 ret = 0; 557 558 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) 559 ret = -EBUSY; 560 else if (port->flags & UPF_IOREMAP) { 561 port->membase = ioremap(port->mapbase, SZ_4K); 562 if (!port->membase) { 563 release_mem_region(port->mapbase, SZ_4K); 564 ret = -ENOMEM; 565 } 566 } 567 } 568 569 return ret; 570 } 571 572 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) 573 { 574 int ret; 575 576 ret = serial_lpc32xx_request_port(port); 577 if (ret < 0) 578 return; 579 port->type = PORT_UART00; 580 port->fifosize = 64; 581 582 __serial_uart_flush(port); 583 584 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 585 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 586 LPC32XX_HSUART_IIR(port->membase)); 587 588 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 589 590 /* Set receiver timeout, HSU offset of 20, no break, no interrupts, 591 and default FIFO trigger levels */ 592 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 593 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, 594 LPC32XX_HSUART_CTRL(port->membase)); 595 } 596 597 static int serial_lpc32xx_verify_port(struct uart_port *port, 598 struct serial_struct *ser) 599 { 600 int ret = 0; 601 602 if (ser->type != PORT_UART00) 603 ret = -EINVAL; 604 605 return ret; 606 } 607 608 static const struct uart_ops serial_lpc32xx_pops = { 609 .tx_empty = serial_lpc32xx_tx_empty, 610 .set_mctrl = serial_lpc32xx_set_mctrl, 611 .get_mctrl = serial_lpc32xx_get_mctrl, 612 .stop_tx = serial_lpc32xx_stop_tx, 613 .start_tx = serial_lpc32xx_start_tx, 614 .stop_rx = serial_lpc32xx_stop_rx, 615 .break_ctl = serial_lpc32xx_break_ctl, 616 .startup = serial_lpc32xx_startup, 617 .shutdown = serial_lpc32xx_shutdown, 618 .set_termios = serial_lpc32xx_set_termios, 619 .type = serial_lpc32xx_type, 620 .release_port = serial_lpc32xx_release_port, 621 .request_port = serial_lpc32xx_request_port, 622 .config_port = serial_lpc32xx_config_port, 623 .verify_port = serial_lpc32xx_verify_port, 624 }; 625 626 /* 627 * Register a set of serial devices attached to a platform device 628 */ 629 static int serial_hs_lpc32xx_probe(struct platform_device *pdev) 630 { 631 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; 632 int ret = 0; 633 struct resource *res; 634 635 if (uarts_registered >= MAX_PORTS) { 636 dev_err(&pdev->dev, 637 "Error: Number of possible ports exceeded (%d)!\n", 638 uarts_registered + 1); 639 return -ENXIO; 640 } 641 642 memset(p, 0, sizeof(*p)); 643 644 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 645 if (!res) { 646 dev_err(&pdev->dev, 647 "Error getting mem resource for HS UART port %d\n", 648 uarts_registered); 649 return -ENXIO; 650 } 651 p->port.mapbase = res->start; 652 p->port.membase = NULL; 653 654 ret = platform_get_irq(pdev, 0); 655 if (ret < 0) 656 return ret; 657 p->port.irq = ret; 658 659 p->port.iotype = UPIO_MEM32; 660 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; 661 p->port.regshift = 2; 662 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; 663 p->port.dev = &pdev->dev; 664 p->port.ops = &serial_lpc32xx_pops; 665 p->port.line = uarts_registered++; 666 spin_lock_init(&p->port.lock); 667 668 /* send port to loopback mode by default */ 669 lpc32xx_loopback_set(p->port.mapbase, 1); 670 671 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); 672 673 platform_set_drvdata(pdev, p); 674 675 return ret; 676 } 677 678 /* 679 * Remove serial ports registered against a platform device. 680 */ 681 static int serial_hs_lpc32xx_remove(struct platform_device *pdev) 682 { 683 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 684 685 uart_remove_one_port(&lpc32xx_hs_reg, &p->port); 686 687 return 0; 688 } 689 690 691 #ifdef CONFIG_PM 692 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, 693 pm_message_t state) 694 { 695 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 696 697 uart_suspend_port(&lpc32xx_hs_reg, &p->port); 698 699 return 0; 700 } 701 702 static int serial_hs_lpc32xx_resume(struct platform_device *pdev) 703 { 704 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 705 706 uart_resume_port(&lpc32xx_hs_reg, &p->port); 707 708 return 0; 709 } 710 #else 711 #define serial_hs_lpc32xx_suspend NULL 712 #define serial_hs_lpc32xx_resume NULL 713 #endif 714 715 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { 716 { .compatible = "nxp,lpc3220-hsuart" }, 717 { /* sentinel */ } 718 }; 719 720 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); 721 722 static struct platform_driver serial_hs_lpc32xx_driver = { 723 .probe = serial_hs_lpc32xx_probe, 724 .remove = serial_hs_lpc32xx_remove, 725 .suspend = serial_hs_lpc32xx_suspend, 726 .resume = serial_hs_lpc32xx_resume, 727 .driver = { 728 .name = MODNAME, 729 .of_match_table = serial_hs_lpc32xx_dt_ids, 730 }, 731 }; 732 733 static int __init lpc32xx_hsuart_init(void) 734 { 735 int ret; 736 737 ret = uart_register_driver(&lpc32xx_hs_reg); 738 if (ret) 739 return ret; 740 741 ret = platform_driver_register(&serial_hs_lpc32xx_driver); 742 if (ret) 743 uart_unregister_driver(&lpc32xx_hs_reg); 744 745 return ret; 746 } 747 748 static void __exit lpc32xx_hsuart_exit(void) 749 { 750 platform_driver_unregister(&serial_hs_lpc32xx_driver); 751 uart_unregister_driver(&lpc32xx_hs_reg); 752 } 753 754 module_init(lpc32xx_hsuart_init); 755 module_exit(lpc32xx_hsuart_exit); 756 757 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 758 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 759 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); 760 MODULE_LICENSE("GPL"); 761