1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * High Speed Serial Ports on NXP LPC32xx SoC 4 * 5 * Authors: Kevin Wells <kevin.wells@nxp.com> 6 * Roland Stigge <stigge@antcom.de> 7 * 8 * Copyright (C) 2010 NXP Semiconductors 9 * Copyright (C) 2012 Roland Stigge 10 */ 11 12 #include <linux/module.h> 13 #include <linux/ioport.h> 14 #include <linux/init.h> 15 #include <linux/console.h> 16 #include <linux/sysrq.h> 17 #include <linux/tty.h> 18 #include <linux/tty_flip.h> 19 #include <linux/serial_core.h> 20 #include <linux/serial.h> 21 #include <linux/platform_device.h> 22 #include <linux/delay.h> 23 #include <linux/nmi.h> 24 #include <linux/io.h> 25 #include <linux/irq.h> 26 #include <linux/gpio.h> 27 #include <linux/of.h> 28 #include <mach/platform.h> 29 #include <mach/hardware.h> 30 31 /* 32 * High Speed UART register offsets 33 */ 34 #define LPC32XX_HSUART_FIFO(x) ((x) + 0x00) 35 #define LPC32XX_HSUART_LEVEL(x) ((x) + 0x04) 36 #define LPC32XX_HSUART_IIR(x) ((x) + 0x08) 37 #define LPC32XX_HSUART_CTRL(x) ((x) + 0x0C) 38 #define LPC32XX_HSUART_RATE(x) ((x) + 0x10) 39 40 #define LPC32XX_HSU_BREAK_DATA (1 << 10) 41 #define LPC32XX_HSU_ERROR_DATA (1 << 9) 42 #define LPC32XX_HSU_RX_EMPTY (1 << 8) 43 44 #define LPC32XX_HSU_TX_LEV(n) (((n) >> 8) & 0xFF) 45 #define LPC32XX_HSU_RX_LEV(n) ((n) & 0xFF) 46 47 #define LPC32XX_HSU_TX_INT_SET (1 << 6) 48 #define LPC32XX_HSU_RX_OE_INT (1 << 5) 49 #define LPC32XX_HSU_BRK_INT (1 << 4) 50 #define LPC32XX_HSU_FE_INT (1 << 3) 51 #define LPC32XX_HSU_RX_TIMEOUT_INT (1 << 2) 52 #define LPC32XX_HSU_RX_TRIG_INT (1 << 1) 53 #define LPC32XX_HSU_TX_INT (1 << 0) 54 55 #define LPC32XX_HSU_HRTS_INV (1 << 21) 56 #define LPC32XX_HSU_HRTS_TRIG_8B (0x0 << 19) 57 #define LPC32XX_HSU_HRTS_TRIG_16B (0x1 << 19) 58 #define LPC32XX_HSU_HRTS_TRIG_32B (0x2 << 19) 59 #define LPC32XX_HSU_HRTS_TRIG_48B (0x3 << 19) 60 #define LPC32XX_HSU_HRTS_EN (1 << 18) 61 #define LPC32XX_HSU_TMO_DISABLED (0x0 << 16) 62 #define LPC32XX_HSU_TMO_INACT_4B (0x1 << 16) 63 #define LPC32XX_HSU_TMO_INACT_8B (0x2 << 16) 64 #define LPC32XX_HSU_TMO_INACT_16B (0x3 << 16) 65 #define LPC32XX_HSU_HCTS_INV (1 << 15) 66 #define LPC32XX_HSU_HCTS_EN (1 << 14) 67 #define LPC32XX_HSU_OFFSET(n) ((n) << 9) 68 #define LPC32XX_HSU_BREAK (1 << 8) 69 #define LPC32XX_HSU_ERR_INT_EN (1 << 7) 70 #define LPC32XX_HSU_RX_INT_EN (1 << 6) 71 #define LPC32XX_HSU_TX_INT_EN (1 << 5) 72 #define LPC32XX_HSU_RX_TL1B (0x0 << 2) 73 #define LPC32XX_HSU_RX_TL4B (0x1 << 2) 74 #define LPC32XX_HSU_RX_TL8B (0x2 << 2) 75 #define LPC32XX_HSU_RX_TL16B (0x3 << 2) 76 #define LPC32XX_HSU_RX_TL32B (0x4 << 2) 77 #define LPC32XX_HSU_RX_TL48B (0x5 << 2) 78 #define LPC32XX_HSU_TX_TLEMPTY (0x0 << 0) 79 #define LPC32XX_HSU_TX_TL0B (0x0 << 0) 80 #define LPC32XX_HSU_TX_TL4B (0x1 << 0) 81 #define LPC32XX_HSU_TX_TL8B (0x2 << 0) 82 #define LPC32XX_HSU_TX_TL16B (0x3 << 0) 83 84 #define MODNAME "lpc32xx_hsuart" 85 86 struct lpc32xx_hsuart_port { 87 struct uart_port port; 88 }; 89 90 #define FIFO_READ_LIMIT 128 91 #define MAX_PORTS 3 92 #define LPC32XX_TTY_NAME "ttyTX" 93 static struct lpc32xx_hsuart_port lpc32xx_hs_ports[MAX_PORTS]; 94 95 #ifdef CONFIG_SERIAL_HS_LPC32XX_CONSOLE 96 static void wait_for_xmit_empty(struct uart_port *port) 97 { 98 unsigned int timeout = 10000; 99 100 do { 101 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 102 port->membase))) == 0) 103 break; 104 if (--timeout == 0) 105 break; 106 udelay(1); 107 } while (1); 108 } 109 110 static void wait_for_xmit_ready(struct uart_port *port) 111 { 112 unsigned int timeout = 10000; 113 114 while (1) { 115 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL( 116 port->membase))) < 32) 117 break; 118 if (--timeout == 0) 119 break; 120 udelay(1); 121 } 122 } 123 124 static void lpc32xx_hsuart_console_putchar(struct uart_port *port, int ch) 125 { 126 wait_for_xmit_ready(port); 127 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); 128 } 129 130 static void lpc32xx_hsuart_console_write(struct console *co, const char *s, 131 unsigned int count) 132 { 133 struct lpc32xx_hsuart_port *up = &lpc32xx_hs_ports[co->index]; 134 unsigned long flags; 135 int locked = 1; 136 137 touch_nmi_watchdog(); 138 local_irq_save(flags); 139 if (up->port.sysrq) 140 locked = 0; 141 else if (oops_in_progress) 142 locked = spin_trylock(&up->port.lock); 143 else 144 spin_lock(&up->port.lock); 145 146 uart_console_write(&up->port, s, count, lpc32xx_hsuart_console_putchar); 147 wait_for_xmit_empty(&up->port); 148 149 if (locked) 150 spin_unlock(&up->port.lock); 151 local_irq_restore(flags); 152 } 153 154 static void lpc32xx_loopback_set(resource_size_t mapbase, int state); 155 156 static int __init lpc32xx_hsuart_console_setup(struct console *co, 157 char *options) 158 { 159 struct uart_port *port; 160 int baud = 115200; 161 int bits = 8; 162 int parity = 'n'; 163 int flow = 'n'; 164 165 if (co->index >= MAX_PORTS) 166 co->index = 0; 167 168 port = &lpc32xx_hs_ports[co->index].port; 169 if (!port->membase) 170 return -ENODEV; 171 172 if (options) 173 uart_parse_options(options, &baud, &parity, &bits, &flow); 174 175 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 176 177 return uart_set_options(port, co, baud, parity, bits, flow); 178 } 179 180 static struct uart_driver lpc32xx_hsuart_reg; 181 static struct console lpc32xx_hsuart_console = { 182 .name = LPC32XX_TTY_NAME, 183 .write = lpc32xx_hsuart_console_write, 184 .device = uart_console_device, 185 .setup = lpc32xx_hsuart_console_setup, 186 .flags = CON_PRINTBUFFER, 187 .index = -1, 188 .data = &lpc32xx_hsuart_reg, 189 }; 190 191 static int __init lpc32xx_hsuart_console_init(void) 192 { 193 register_console(&lpc32xx_hsuart_console); 194 return 0; 195 } 196 console_initcall(lpc32xx_hsuart_console_init); 197 198 #define LPC32XX_HSUART_CONSOLE (&lpc32xx_hsuart_console) 199 #else 200 #define LPC32XX_HSUART_CONSOLE NULL 201 #endif 202 203 static struct uart_driver lpc32xx_hs_reg = { 204 .owner = THIS_MODULE, 205 .driver_name = MODNAME, 206 .dev_name = LPC32XX_TTY_NAME, 207 .nr = MAX_PORTS, 208 .cons = LPC32XX_HSUART_CONSOLE, 209 }; 210 static int uarts_registered; 211 212 static unsigned int __serial_get_clock_div(unsigned long uartclk, 213 unsigned long rate) 214 { 215 u32 div, goodrate, hsu_rate, l_hsu_rate, comprate; 216 u32 rate_diff; 217 218 /* Find the closest divider to get the desired clock rate */ 219 div = uartclk / rate; 220 goodrate = hsu_rate = (div / 14) - 1; 221 if (hsu_rate != 0) 222 hsu_rate--; 223 224 /* Tweak divider */ 225 l_hsu_rate = hsu_rate + 3; 226 rate_diff = 0xFFFFFFFF; 227 228 while (hsu_rate < l_hsu_rate) { 229 comprate = uartclk / ((hsu_rate + 1) * 14); 230 if (abs(comprate - rate) < rate_diff) { 231 goodrate = hsu_rate; 232 rate_diff = abs(comprate - rate); 233 } 234 235 hsu_rate++; 236 } 237 if (hsu_rate > 0xFF) 238 hsu_rate = 0xFF; 239 240 return goodrate; 241 } 242 243 static void __serial_uart_flush(struct uart_port *port) 244 { 245 u32 tmp; 246 int cnt = 0; 247 248 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && 249 (cnt++ < FIFO_READ_LIMIT)) 250 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 251 } 252 253 static void __serial_lpc32xx_rx(struct uart_port *port) 254 { 255 struct tty_port *tport = &port->state->port; 256 unsigned int tmp, flag; 257 258 /* Read data from FIFO and push into terminal */ 259 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 260 while (!(tmp & LPC32XX_HSU_RX_EMPTY)) { 261 flag = TTY_NORMAL; 262 port->icount.rx++; 263 264 if (tmp & LPC32XX_HSU_ERROR_DATA) { 265 /* Framing error */ 266 writel(LPC32XX_HSU_FE_INT, 267 LPC32XX_HSUART_IIR(port->membase)); 268 port->icount.frame++; 269 flag = TTY_FRAME; 270 tty_insert_flip_char(tport, 0, TTY_FRAME); 271 } 272 273 tty_insert_flip_char(tport, (tmp & 0xFF), flag); 274 275 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); 276 } 277 278 spin_unlock(&port->lock); 279 tty_flip_buffer_push(tport); 280 spin_lock(&port->lock); 281 } 282 283 static void __serial_lpc32xx_tx(struct uart_port *port) 284 { 285 struct circ_buf *xmit = &port->state->xmit; 286 unsigned int tmp; 287 288 if (port->x_char) { 289 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); 290 port->icount.tx++; 291 port->x_char = 0; 292 return; 293 } 294 295 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) 296 goto exit_tx; 297 298 /* Transfer data */ 299 while (LPC32XX_HSU_TX_LEV(readl( 300 LPC32XX_HSUART_LEVEL(port->membase))) < 64) { 301 writel((u32) xmit->buf[xmit->tail], 302 LPC32XX_HSUART_FIFO(port->membase)); 303 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 304 port->icount.tx++; 305 if (uart_circ_empty(xmit)) 306 break; 307 } 308 309 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 310 uart_write_wakeup(port); 311 312 exit_tx: 313 if (uart_circ_empty(xmit)) { 314 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 315 tmp &= ~LPC32XX_HSU_TX_INT_EN; 316 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 317 } 318 } 319 320 static irqreturn_t serial_lpc32xx_interrupt(int irq, void *dev_id) 321 { 322 struct uart_port *port = dev_id; 323 struct tty_port *tport = &port->state->port; 324 u32 status; 325 326 spin_lock(&port->lock); 327 328 /* Read UART status and clear latched interrupts */ 329 status = readl(LPC32XX_HSUART_IIR(port->membase)); 330 331 if (status & LPC32XX_HSU_BRK_INT) { 332 /* Break received */ 333 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); 334 port->icount.brk++; 335 uart_handle_break(port); 336 } 337 338 /* Framing error */ 339 if (status & LPC32XX_HSU_FE_INT) 340 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); 341 342 if (status & LPC32XX_HSU_RX_OE_INT) { 343 /* Receive FIFO overrun */ 344 writel(LPC32XX_HSU_RX_OE_INT, 345 LPC32XX_HSUART_IIR(port->membase)); 346 port->icount.overrun++; 347 tty_insert_flip_char(tport, 0, TTY_OVERRUN); 348 tty_schedule_flip(tport); 349 } 350 351 /* Data received? */ 352 if (status & (LPC32XX_HSU_RX_TIMEOUT_INT | LPC32XX_HSU_RX_TRIG_INT)) 353 __serial_lpc32xx_rx(port); 354 355 /* Transmit data request? */ 356 if ((status & LPC32XX_HSU_TX_INT) && (!uart_tx_stopped(port))) { 357 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); 358 __serial_lpc32xx_tx(port); 359 } 360 361 spin_unlock(&port->lock); 362 363 return IRQ_HANDLED; 364 } 365 366 /* port->lock is not held. */ 367 static unsigned int serial_lpc32xx_tx_empty(struct uart_port *port) 368 { 369 unsigned int ret = 0; 370 371 if (LPC32XX_HSU_TX_LEV(readl(LPC32XX_HSUART_LEVEL(port->membase))) == 0) 372 ret = TIOCSER_TEMT; 373 374 return ret; 375 } 376 377 /* port->lock held by caller. */ 378 static void serial_lpc32xx_set_mctrl(struct uart_port *port, 379 unsigned int mctrl) 380 { 381 /* No signals are supported on HS UARTs */ 382 } 383 384 /* port->lock is held by caller and interrupts are disabled. */ 385 static unsigned int serial_lpc32xx_get_mctrl(struct uart_port *port) 386 { 387 /* No signals are supported on HS UARTs */ 388 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; 389 } 390 391 /* port->lock held by caller. */ 392 static void serial_lpc32xx_stop_tx(struct uart_port *port) 393 { 394 u32 tmp; 395 396 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 397 tmp &= ~LPC32XX_HSU_TX_INT_EN; 398 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 399 } 400 401 /* port->lock held by caller. */ 402 static void serial_lpc32xx_start_tx(struct uart_port *port) 403 { 404 u32 tmp; 405 406 __serial_lpc32xx_tx(port); 407 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 408 tmp |= LPC32XX_HSU_TX_INT_EN; 409 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 410 } 411 412 /* port->lock held by caller. */ 413 static void serial_lpc32xx_stop_rx(struct uart_port *port) 414 { 415 u32 tmp; 416 417 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 418 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 419 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 420 421 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | 422 LPC32XX_HSU_FE_INT), LPC32XX_HSUART_IIR(port->membase)); 423 } 424 425 /* port->lock is not held. */ 426 static void serial_lpc32xx_break_ctl(struct uart_port *port, 427 int break_state) 428 { 429 unsigned long flags; 430 u32 tmp; 431 432 spin_lock_irqsave(&port->lock, flags); 433 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 434 if (break_state != 0) 435 tmp |= LPC32XX_HSU_BREAK; 436 else 437 tmp &= ~LPC32XX_HSU_BREAK; 438 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 439 spin_unlock_irqrestore(&port->lock, flags); 440 } 441 442 /* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */ 443 static void lpc32xx_loopback_set(resource_size_t mapbase, int state) 444 { 445 int bit; 446 u32 tmp; 447 448 switch (mapbase) { 449 case LPC32XX_HS_UART1_BASE: 450 bit = 0; 451 break; 452 case LPC32XX_HS_UART2_BASE: 453 bit = 1; 454 break; 455 case LPC32XX_HS_UART7_BASE: 456 bit = 6; 457 break; 458 default: 459 WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase); 460 return; 461 } 462 463 tmp = readl(LPC32XX_UARTCTL_CLOOP); 464 if (state) 465 tmp |= (1 << bit); 466 else 467 tmp &= ~(1 << bit); 468 writel(tmp, LPC32XX_UARTCTL_CLOOP); 469 } 470 471 /* port->lock is not held. */ 472 static int serial_lpc32xx_startup(struct uart_port *port) 473 { 474 int retval; 475 unsigned long flags; 476 u32 tmp; 477 478 spin_lock_irqsave(&port->lock, flags); 479 480 __serial_uart_flush(port); 481 482 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 483 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 484 LPC32XX_HSUART_IIR(port->membase)); 485 486 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 487 488 /* 489 * Set receiver timeout, HSU offset of 20, no break, no interrupts, 490 * and default FIFO trigger levels 491 */ 492 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 493 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 494 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 495 496 lpc32xx_loopback_set(port->mapbase, 0); /* get out of loopback mode */ 497 498 spin_unlock_irqrestore(&port->lock, flags); 499 500 retval = request_irq(port->irq, serial_lpc32xx_interrupt, 501 0, MODNAME, port); 502 if (!retval) 503 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), 504 LPC32XX_HSUART_CTRL(port->membase)); 505 506 return retval; 507 } 508 509 /* port->lock is not held. */ 510 static void serial_lpc32xx_shutdown(struct uart_port *port) 511 { 512 u32 tmp; 513 unsigned long flags; 514 515 spin_lock_irqsave(&port->lock, flags); 516 517 tmp = LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 518 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B; 519 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 520 521 lpc32xx_loopback_set(port->mapbase, 1); /* go to loopback mode */ 522 523 spin_unlock_irqrestore(&port->lock, flags); 524 525 free_irq(port->irq, port); 526 } 527 528 /* port->lock is not held. */ 529 static void serial_lpc32xx_set_termios(struct uart_port *port, 530 struct ktermios *termios, 531 struct ktermios *old) 532 { 533 unsigned long flags; 534 unsigned int baud, quot; 535 u32 tmp; 536 537 /* Always 8-bit, no parity, 1 stop bit */ 538 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD); 539 termios->c_cflag |= CS8; 540 541 termios->c_cflag &= ~(HUPCL | CMSPAR | CLOCAL | CRTSCTS); 542 543 baud = uart_get_baud_rate(port, termios, old, 0, 544 port->uartclk / 14); 545 546 quot = __serial_get_clock_div(port->uartclk, baud); 547 548 spin_lock_irqsave(&port->lock, flags); 549 550 /* Ignore characters? */ 551 tmp = readl(LPC32XX_HSUART_CTRL(port->membase)); 552 if ((termios->c_cflag & CREAD) == 0) 553 tmp &= ~(LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN); 554 else 555 tmp |= LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN; 556 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); 557 558 writel(quot, LPC32XX_HSUART_RATE(port->membase)); 559 560 uart_update_timeout(port, termios->c_cflag, baud); 561 562 spin_unlock_irqrestore(&port->lock, flags); 563 564 /* Don't rewrite B0 */ 565 if (tty_termios_baud_rate(termios)) 566 tty_termios_encode_baud_rate(termios, baud, baud); 567 } 568 569 static const char *serial_lpc32xx_type(struct uart_port *port) 570 { 571 return MODNAME; 572 } 573 574 static void serial_lpc32xx_release_port(struct uart_port *port) 575 { 576 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 577 if (port->flags & UPF_IOREMAP) { 578 iounmap(port->membase); 579 port->membase = NULL; 580 } 581 582 release_mem_region(port->mapbase, SZ_4K); 583 } 584 } 585 586 static int serial_lpc32xx_request_port(struct uart_port *port) 587 { 588 int ret = -ENODEV; 589 590 if ((port->iotype == UPIO_MEM32) && (port->mapbase)) { 591 ret = 0; 592 593 if (!request_mem_region(port->mapbase, SZ_4K, MODNAME)) 594 ret = -EBUSY; 595 else if (port->flags & UPF_IOREMAP) { 596 port->membase = ioremap(port->mapbase, SZ_4K); 597 if (!port->membase) { 598 release_mem_region(port->mapbase, SZ_4K); 599 ret = -ENOMEM; 600 } 601 } 602 } 603 604 return ret; 605 } 606 607 static void serial_lpc32xx_config_port(struct uart_port *port, int uflags) 608 { 609 int ret; 610 611 ret = serial_lpc32xx_request_port(port); 612 if (ret < 0) 613 return; 614 port->type = PORT_UART00; 615 port->fifosize = 64; 616 617 __serial_uart_flush(port); 618 619 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | 620 LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT), 621 LPC32XX_HSUART_IIR(port->membase)); 622 623 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); 624 625 /* Set receiver timeout, HSU offset of 20, no break, no interrupts, 626 and default FIFO trigger levels */ 627 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | 628 LPC32XX_HSU_OFFSET(20) | LPC32XX_HSU_TMO_INACT_4B, 629 LPC32XX_HSUART_CTRL(port->membase)); 630 } 631 632 static int serial_lpc32xx_verify_port(struct uart_port *port, 633 struct serial_struct *ser) 634 { 635 int ret = 0; 636 637 if (ser->type != PORT_UART00) 638 ret = -EINVAL; 639 640 return ret; 641 } 642 643 static const struct uart_ops serial_lpc32xx_pops = { 644 .tx_empty = serial_lpc32xx_tx_empty, 645 .set_mctrl = serial_lpc32xx_set_mctrl, 646 .get_mctrl = serial_lpc32xx_get_mctrl, 647 .stop_tx = serial_lpc32xx_stop_tx, 648 .start_tx = serial_lpc32xx_start_tx, 649 .stop_rx = serial_lpc32xx_stop_rx, 650 .break_ctl = serial_lpc32xx_break_ctl, 651 .startup = serial_lpc32xx_startup, 652 .shutdown = serial_lpc32xx_shutdown, 653 .set_termios = serial_lpc32xx_set_termios, 654 .type = serial_lpc32xx_type, 655 .release_port = serial_lpc32xx_release_port, 656 .request_port = serial_lpc32xx_request_port, 657 .config_port = serial_lpc32xx_config_port, 658 .verify_port = serial_lpc32xx_verify_port, 659 }; 660 661 /* 662 * Register a set of serial devices attached to a platform device 663 */ 664 static int serial_hs_lpc32xx_probe(struct platform_device *pdev) 665 { 666 struct lpc32xx_hsuart_port *p = &lpc32xx_hs_ports[uarts_registered]; 667 int ret = 0; 668 struct resource *res; 669 670 if (uarts_registered >= MAX_PORTS) { 671 dev_err(&pdev->dev, 672 "Error: Number of possible ports exceeded (%d)!\n", 673 uarts_registered + 1); 674 return -ENXIO; 675 } 676 677 memset(p, 0, sizeof(*p)); 678 679 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 680 if (!res) { 681 dev_err(&pdev->dev, 682 "Error getting mem resource for HS UART port %d\n", 683 uarts_registered); 684 return -ENXIO; 685 } 686 p->port.mapbase = res->start; 687 p->port.membase = NULL; 688 689 ret = platform_get_irq(pdev, 0); 690 if (ret < 0) { 691 dev_err(&pdev->dev, "Error getting irq for HS UART port %d\n", 692 uarts_registered); 693 return ret; 694 } 695 p->port.irq = ret; 696 697 p->port.iotype = UPIO_MEM32; 698 p->port.uartclk = LPC32XX_MAIN_OSC_FREQ; 699 p->port.regshift = 2; 700 p->port.flags = UPF_BOOT_AUTOCONF | UPF_FIXED_PORT | UPF_IOREMAP; 701 p->port.dev = &pdev->dev; 702 p->port.ops = &serial_lpc32xx_pops; 703 p->port.line = uarts_registered++; 704 spin_lock_init(&p->port.lock); 705 706 /* send port to loopback mode by default */ 707 lpc32xx_loopback_set(p->port.mapbase, 1); 708 709 ret = uart_add_one_port(&lpc32xx_hs_reg, &p->port); 710 711 platform_set_drvdata(pdev, p); 712 713 return ret; 714 } 715 716 /* 717 * Remove serial ports registered against a platform device. 718 */ 719 static int serial_hs_lpc32xx_remove(struct platform_device *pdev) 720 { 721 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 722 723 uart_remove_one_port(&lpc32xx_hs_reg, &p->port); 724 725 return 0; 726 } 727 728 729 #ifdef CONFIG_PM 730 static int serial_hs_lpc32xx_suspend(struct platform_device *pdev, 731 pm_message_t state) 732 { 733 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 734 735 uart_suspend_port(&lpc32xx_hs_reg, &p->port); 736 737 return 0; 738 } 739 740 static int serial_hs_lpc32xx_resume(struct platform_device *pdev) 741 { 742 struct lpc32xx_hsuart_port *p = platform_get_drvdata(pdev); 743 744 uart_resume_port(&lpc32xx_hs_reg, &p->port); 745 746 return 0; 747 } 748 #else 749 #define serial_hs_lpc32xx_suspend NULL 750 #define serial_hs_lpc32xx_resume NULL 751 #endif 752 753 static const struct of_device_id serial_hs_lpc32xx_dt_ids[] = { 754 { .compatible = "nxp,lpc3220-hsuart" }, 755 { /* sentinel */ } 756 }; 757 758 MODULE_DEVICE_TABLE(of, serial_hs_lpc32xx_dt_ids); 759 760 static struct platform_driver serial_hs_lpc32xx_driver = { 761 .probe = serial_hs_lpc32xx_probe, 762 .remove = serial_hs_lpc32xx_remove, 763 .suspend = serial_hs_lpc32xx_suspend, 764 .resume = serial_hs_lpc32xx_resume, 765 .driver = { 766 .name = MODNAME, 767 .of_match_table = serial_hs_lpc32xx_dt_ids, 768 }, 769 }; 770 771 static int __init lpc32xx_hsuart_init(void) 772 { 773 int ret; 774 775 ret = uart_register_driver(&lpc32xx_hs_reg); 776 if (ret) 777 return ret; 778 779 ret = platform_driver_register(&serial_hs_lpc32xx_driver); 780 if (ret) 781 uart_unregister_driver(&lpc32xx_hs_reg); 782 783 return ret; 784 } 785 786 static void __exit lpc32xx_hsuart_exit(void) 787 { 788 platform_driver_unregister(&serial_hs_lpc32xx_driver); 789 uart_unregister_driver(&lpc32xx_hs_reg); 790 } 791 792 module_init(lpc32xx_hsuart_init); 793 module_exit(lpc32xx_hsuart_exit); 794 795 MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); 796 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 797 MODULE_DESCRIPTION("NXP LPC32XX High Speed UART driver"); 798 MODULE_LICENSE("GPL"); 799